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arm64: dts: rockchip: assign default rates for core rk3399 clocks
[linux-block.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
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f048b9a4
JX		 1/*
2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3399-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h>
48
49/ {
50 compatible = "rockchip,rk3399";
51
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
55
56 aliases {
57 serial0 = &uart0;
58 serial1 = &uart1;
59 serial2 = &uart2;
60 serial3 = &uart3;
61 serial4 = &uart4;
62 };
63
64 cpus {
65 #address-cells = <2>;
66 #size-cells = <0>;
67
68 cpu-map {
69 cluster0 {
70 core0 {
71 cpu = <&cpu_l0>;
72 };
73 core1 {
74 cpu = <&cpu_l1>;
75 };
76 core2 {
77 cpu = <&cpu_l2>;
78 };
79 core3 {
80 cpu = <&cpu_l3>;
81 };
82 };
83
84 cluster1 {
85 core0 {
86 cpu = <&cpu_b0>;
87 };
88 core1 {
89 cpu = <&cpu_b1>;
90 };
91 };
92 };
93
94 cpu_l0: cpu@0 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a53", "arm,armv8";
97 reg = <0x0 0x0>;
98 enable-method = "psci";
99 #cooling-cells = <2>; /* min followed by max */
100 clocks = <&cru ARMCLKL>;
101 };
102
103 cpu_l1: cpu@1 {
104 device_type = "cpu";
105 compatible = "arm,cortex-a53", "arm,armv8";
106 reg = <0x0 0x1>;
107 enable-method = "psci";
108 clocks = <&cru ARMCLKL>;
109 };
110
111 cpu_l2: cpu@2 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a53", "arm,armv8";
114 reg = <0x0 0x2>;
115 enable-method = "psci";
116 clocks = <&cru ARMCLKL>;
117 };
118
119 cpu_l3: cpu@3 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a53", "arm,armv8";
122 reg = <0x0 0x3>;
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 };
126
127 cpu_b0: cpu@100 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a72", "arm,armv8";
130 reg = <0x0 0x100>;
131 enable-method = "psci";
132 #cooling-cells = <2>; /* min followed by max */
133 clocks = <&cru ARMCLKB>;
134 };
135
136 cpu_b1: cpu@101 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a72", "arm,armv8";
139 reg = <0x0 0x101>;
140 enable-method = "psci";
141 clocks = <&cru ARMCLKB>;
142 };
143 };
144
145 psci {
146 compatible = "arm,psci-1.0";
147 method = "smc";
148 };
149
150 timer {
151 compatible = "arm,armv8-timer";
152 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
153 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
154 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
155 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
156 };
157
158 xin24m: xin24m {
159 compatible = "fixed-clock";
160 clock-frequency = <24000000>;
161 clock-output-names = "xin24m";
162 #clock-cells = <0>;
163 };
164
165 amba {
166 compatible = "arm,amba-bus";
167 #address-cells = <2>;
168 #size-cells = <2>;
169 ranges;
170
171 dmac_bus: dma-controller@ff6d0000 {
172 compatible = "arm,pl330", "arm,primecell";
173 reg = <0x0 0xff6d0000 0x0 0x4000>;
174 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
176 #dma-cells = <1>;
177 clocks = <&cru ACLK_DMAC0_PERILP>;
178 clock-names = "apb_pclk";
179 };
180
181 dmac_peri: dma-controller@ff6e0000 {
182 compatible = "arm,pl330", "arm,primecell";
183 reg = <0x0 0xff6e0000 0x0 0x4000>;
184 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
186 #dma-cells = <1>;
187 clocks = <&cru ACLK_DMAC1_PERILP>;
188 clock-names = "apb_pclk";
189 };
190 };
191
192 sdio0: dwmmc@fe310000 {
193 compatible = "rockchip,rk3399-dw-mshc",
194 "rockchip,rk3288-dw-mshc";
195 reg = <0x0 0xfe310000 0x0 0x4000>;
196 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
197 clock-freq-min-max = <400000 150000000>;
198 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
199 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
200 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
201 fifo-depth = <0x100>;
202 status = "disabled";
203 };
204
205 sdmmc: dwmmc@fe320000 {
206 compatible = "rockchip,rk3399-dw-mshc",
207 "rockchip,rk3288-dw-mshc";
208 reg = <0x0 0xfe320000 0x0 0x4000>;
209 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
210 clock-freq-min-max = <400000 150000000>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
215 status = "disabled";
216 };
217
218 usb_host0_ehci: usb@fe380000 {
219 compatible = "generic-ehci";
220 reg = <0x0 0xfe380000 0x0 0x20000>;
221 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
223 clock-names = "hclk_host0", "hclk_host0_arb";
224 status = "disabled";
225 };
226
227 usb_host0_ohci: usb@fe3a0000 {
228 compatible = "generic-ohci";
229 reg = <0x0 0xfe3a0000 0x0 0x20000>;
230 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
232 clock-names = "hclk_host0", "hclk_host0_arb";
233 status = "disabled";
234 };
235
236 usb_host1_ehci: usb@fe3c0000 {
237 compatible = "generic-ehci";
238 reg = <0x0 0xfe3c0000 0x0 0x20000>;
239 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
241 clock-names = "hclk_host1", "hclk_host1_arb";
242 status = "disabled";
243 };
244
245 usb_host1_ohci: usb@fe3e0000 {
246 compatible = "generic-ohci";
247 reg = <0x0 0xfe3e0000 0x0 0x20000>;
248 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
250 clock-names = "hclk_host1", "hclk_host1_arb";
251 status = "disabled";
252 };
253
254 gic: interrupt-controller@fee00000 {
255 compatible = "arm,gic-v3";
256 #interrupt-cells = <3>;
257 #address-cells = <2>;
258 #size-cells = <2>;
259 ranges;
260 interrupt-controller;
261
262 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
263 <0x0 0xfef00000 0 0xc0000>, /* GICR */
264 <0x0 0xfff00000 0 0x10000>, /* GICC */
265 <0x0 0xfff10000 0 0x10000>, /* GICH */
266 <0x0 0xfff20000 0 0x10000>; /* GICV */
267 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
268 its: interrupt-controller@fee20000 {
269 compatible = "arm,gic-v3-its";
270 msi-controller;
271 reg = <0x0 0xfee20000 0x0 0x20000>;
272 };
273 };
274
275 uart0: serial@ff180000 {
276 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
277 reg = <0x0 0xff180000 0x0 0x100>;
278 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
279 clock-names = "baudclk", "apb_pclk";
280 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
281 reg-shift = <2>;
282 reg-io-width = <4>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&uart0_xfer>;
285 status = "disabled";
286 };
287
288 uart1: serial@ff190000 {
289 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
290 reg = <0x0 0xff190000 0x0 0x100>;
291 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
292 clock-names = "baudclk", "apb_pclk";
293 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
294 reg-shift = <2>;
295 reg-io-width = <4>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart1_xfer>;
298 status = "disabled";
299 };
300
301 uart2: serial@ff1a0000 {
302 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
303 reg = <0x0 0xff1a0000 0x0 0x100>;
304 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
305 clock-names = "baudclk", "apb_pclk";
306 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart2c_xfer>;
311 status = "disabled";
312 };
313
314 uart3: serial@ff1b0000 {
315 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff1b0000 0x0 0x100>;
317 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
318 clock-names = "baudclk", "apb_pclk";
319 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
320 reg-shift = <2>;
321 reg-io-width = <4>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart3_xfer>;
324 status = "disabled";
325 };
326
327 spi0: spi@ff1c0000 {
328 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
329 reg = <0x0 0xff1c0000 0x0 0x1000>;
330 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
331 clock-names = "spiclk", "apb_pclk";
332 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
339
340 spi1: spi@ff1d0000 {
341 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
342 reg = <0x0 0xff1d0000 0x0 0x1000>;
343 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
344 clock-names = "spiclk", "apb_pclk";
345 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 status = "disabled";
351 };
352
353 spi2: spi@ff1e0000 {
354 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
355 reg = <0x0 0xff1e0000 0x0 0x1000>;
356 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
357 clock-names = "spiclk", "apb_pclk";
358 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 status = "disabled";
364 };
365
366 spi4: spi@ff1f0000 {
367 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
368 reg = <0x0 0xff1f0000 0x0 0x1000>;
369 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
370 clock-names = "spiclk", "apb_pclk";
371 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 status = "disabled";
377 };
378
379 spi5: spi@ff200000 {
380 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
381 reg = <0x0 0xff200000 0x0 0x1000>;
382 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
383 clock-names = "spiclk", "apb_pclk";
384 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 status = "disabled";
390 };
391
392 pmugrf: syscon@ff320000 {
393 compatible = "rockchip,rk3399-pmugrf", "syscon";
394 reg = <0x0 0xff320000 0x0 0x1000>;
395 };
396
397 spi3: spi@ff350000 {
398 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
399 reg = <0x0 0xff350000 0x0 0x1000>;
400 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
401 clock-names = "spiclk", "apb_pclk";
402 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
405 #address-cells = <1>;
406 #size-cells = <0>;
407 status = "disabled";
408 };
409
410 uart4: serial@ff370000 {
411 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
412 reg = <0x0 0xff370000 0x0 0x100>;
413 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
414 clock-names = "baudclk", "apb_pclk";
415 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
416 reg-shift = <2>;
417 reg-io-width = <4>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&uart4_xfer>;
420 status = "disabled";
421 };
422
423 pwm0: pwm@ff420000 {
424 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
425 reg = <0x0 0xff420000 0x0 0x10>;
426 #pwm-cells = <3>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pwm0_pin>;
429 clocks = <&pmucru PCLK_RKPWM_PMU>;
430 clock-names = "pwm";
431 status = "disabled";
432 };
433
434 pwm1: pwm@ff420010 {
435 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
436 reg = <0x0 0xff420010 0x0 0x10>;
437 #pwm-cells = <3>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pwm1_pin>;
440 clocks = <&pmucru PCLK_RKPWM_PMU>;
441 clock-names = "pwm";
442 status = "disabled";
443 };
444
445 pwm2: pwm@ff420020 {
446 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
447 reg = <0x0 0xff420020 0x0 0x10>;
448 #pwm-cells = <3>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pwm2_pin>;
451 clocks = <&pmucru PCLK_RKPWM_PMU>;
452 clock-names = "pwm";
453 status = "disabled";
454 };
455
456 pwm3: pwm@ff420030 {
457 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
458 reg = <0x0 0xff420030 0x0 0x10>;
459 #pwm-cells = <3>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pwm3a_pin>;
462 clocks = <&pmucru PCLK_RKPWM_PMU>;
463 clock-names = "pwm";
464 status = "disabled";
465 };
466
467 pmucru: pmu-clock-controller@ff750000 {
468 compatible = "rockchip,rk3399-pmucru";
469 reg = <0x0 0xff750000 0x0 0x1000>;
470 #clock-cells = <1>;
471 #reset-cells = <1>;
472 assigned-clocks = <&pmucru PLL_PPLL>;
473 assigned-clock-rates = <676000000>;
474 };
475
476 cru: clock-controller@ff760000 {
477 compatible = "rockchip,rk3399-cru";
478 reg = <0x0 0xff760000 0x0 0x1000>;
479 #clock-cells = <1>;
480 #reset-cells = <1>;
a09906cd
XZ		 481 assigned-clocks =
482 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
483 <&cru PLL_NPLL>,
484 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
485 <&cru PCLK_PERIHP>,
486 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
487 <&cru PCLK_PERILP0>,
488 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
489 assigned-clock-rates =
490 <594000000>, <800000000>,
491 <1000000000>,
492 <150000000>, <75000000>,
493 <37500000>,
494 <100000000>, <100000000>,
495 <50000000>,
496 <100000000>, <50000000>;
f048b9a4
JX		 497 };
498
499 grf: syscon@ff770000 {
500 compatible = "rockchip,rk3399-grf", "syscon";
501 reg = <0x0 0xff770000 0x0 0x10000>;
502 };
503
504 watchdog@ff840000 {
505 compatible = "snps,dw-wdt";
506 reg = <0x0 0xff840000 0x0 0x100>;
507 clocks = <&cru PCLK_WDT>;
508 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
509 };
510
511 spdif: spdif@ff870000 {
512 compatible = "rockchip,rk3399-spdif";
513 reg = <0x0 0xff870000 0x0 0x1000>;
514 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
515 dmas = <&dmac_bus 7>;
516 dma-names = "tx";
517 clock-names = "mclk", "hclk";
518 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&spdif_bus>;
521 status = "disabled";
522 };
523
524 i2s0: i2s@ff880000 {
525 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
526 reg = <0x0 0xff880000 0x0 0x1000>;
527 rockchip,grf = <&grf>;
528 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
529 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
530 dma-names = "tx", "rx";
531 clock-names = "i2s_clk", "i2s_hclk";
532 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2s0_8ch_bus>;
535 status = "disabled";
536 };
537
538 i2s1: i2s@ff890000 {
539 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
540 reg = <0x0 0xff890000 0x0 0x1000>;
541 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
542 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
543 dma-names = "tx", "rx";
544 clock-names = "i2s_clk", "i2s_hclk";
545 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2s1_2ch_bus>;
548 status = "disabled";
549 };
550
551 i2s2: i2s@ff8a0000 {
552 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
553 reg = <0x0 0xff8a0000 0x0 0x1000>;
554 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
555 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
556 dma-names = "tx", "rx";
557 clock-names = "i2s_clk", "i2s_hclk";
558 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
559 status = "disabled";
560 };
561
562 pinctrl: pinctrl {
563 compatible = "rockchip,rk3399-pinctrl";
564 rockchip,grf = <&grf>;
565 rockchip,pmu = <&pmugrf>;
566 #address-cells = <2>;
567 #size-cells = <2>;
568 ranges;
569
570 gpio0: gpio0@ff720000 {
571 compatible = "rockchip,gpio-bank";
572 reg = <0x0 0xff720000 0x0 0x100>;
573 clocks = <&pmucru PCLK_GPIO0_PMU>;
574 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
575
576 gpio-controller;
577 #gpio-cells = <0x2>;
578
579 interrupt-controller;
580 #interrupt-cells = <0x2>;
581 };
582
583 gpio1: gpio1@ff730000 {
584 compatible = "rockchip,gpio-bank";
585 reg = <0x0 0xff730000 0x0 0x100>;
586 clocks = <&pmucru PCLK_GPIO1_PMU>;
587 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
588
589 gpio-controller;
590 #gpio-cells = <0x2>;
591
592 interrupt-controller;
593 #interrupt-cells = <0x2>;
594 };
595
596 gpio2: gpio2@ff780000 {
597 compatible = "rockchip,gpio-bank";
598 reg = <0x0 0xff780000 0x0 0x100>;
599 clocks = <&cru PCLK_GPIO2>;
600 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
601
602 gpio-controller;
603 #gpio-cells = <0x2>;
604
605 interrupt-controller;
606 #interrupt-cells = <0x2>;
607 };
608
609 gpio3: gpio3@ff788000 {
610 compatible = "rockchip,gpio-bank";
611 reg = <0x0 0xff788000 0x0 0x100>;
612 clocks = <&cru PCLK_GPIO3>;
613 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
614
615 gpio-controller;
616 #gpio-cells = <0x2>;
617
618 interrupt-controller;
619 #interrupt-cells = <0x2>;
620 };
621
622 gpio4: gpio4@ff790000 {
623 compatible = "rockchip,gpio-bank";
624 reg = <0x0 0xff790000 0x0 0x100>;
625 clocks = <&cru PCLK_GPIO4>;
626 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
627
628 gpio-controller;
629 #gpio-cells = <0x2>;
630
631 interrupt-controller;
632 #interrupt-cells = <0x2>;
633 };
634
635 pcfg_pull_up: pcfg-pull-up {
636 bias-pull-up;
637 };
638
639 pcfg_pull_down: pcfg-pull-down {
640 bias-pull-down;
641 };
642
643 pcfg_pull_none: pcfg-pull-none {
644 bias-disable;
645 };
646
647 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
648 bias-disable;
649 drive-strength = <12>;
650 };
651
652 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
653 bias-pull-up;
654 drive-strength = <8>;
655 };
656
657 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
658 bias-pull-down;
659 drive-strength = <4>;
660 };
661
662 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
663 bias-pull-up;
664 drive-strength = <2>;
665 };
666
667 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
668 bias-pull-down;
669 drive-strength = <12>;
670 };
671
672 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
673 bias-disable;
674 drive-strength = <13>;
675 };
676
677 i2c0 {
678 i2c0_xfer: i2c0-xfer {
679 rockchip,pins =
680 <1 15 RK_FUNC_2 &pcfg_pull_none>,
681 <1 16 RK_FUNC_2 &pcfg_pull_none>;
682 };
683 };
684
685 i2c1 {
686 i2c1_xfer: i2c1-xfer {
687 rockchip,pins =
688 <4 2 RK_FUNC_1 &pcfg_pull_none>,
689 <4 1 RK_FUNC_1 &pcfg_pull_none>;
690 };
691 };
692
693 i2c2 {
694 i2c2_xfer: i2c2-xfer {
695 rockchip,pins =
696 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
697 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
698 };
699 };
700
701 i2c3 {
702 i2c3_xfer: i2c3-xfer {
703 rockchip,pins =
704 <4 17 RK_FUNC_1 &pcfg_pull_none>,
705 <4 16 RK_FUNC_1 &pcfg_pull_none>;
706 };
707 };
708
709 i2c4 {
710 i2c4_xfer: i2c4-xfer {
711 rockchip,pins =
712 <1 12 RK_FUNC_1 &pcfg_pull_none>,
713 <1 11 RK_FUNC_1 &pcfg_pull_none>;
714 };
715 };
716
717 i2c5 {
718 i2c5_xfer: i2c5-xfer {
719 rockchip,pins =
720 <3 11 RK_FUNC_2 &pcfg_pull_none>,
721 <3 10 RK_FUNC_2 &pcfg_pull_none>;
722 };
723 };
724
725 i2c6 {
726 i2c6_xfer: i2c6-xfer {
727 rockchip,pins =
728 <2 10 RK_FUNC_2 &pcfg_pull_none>,
729 <2 9 RK_FUNC_2 &pcfg_pull_none>;
730 };
731 };
732
733 i2c7 {
734 i2c7_xfer: i2c7-xfer {
735 rockchip,pins =
736 <2 8 RK_FUNC_2 &pcfg_pull_none>,
737 <2 7 RK_FUNC_2 &pcfg_pull_none>;
738 };
739 };
740
741 i2c8 {
742 i2c8_xfer: i2c8-xfer {
743 rockchip,pins =
744 <1 21 RK_FUNC_1 &pcfg_pull_none>,
745 <1 20 RK_FUNC_1 &pcfg_pull_none>;
746 };
747 };
748
749 i2s0 {
750 i2s0_8ch_bus: i2s0-8ch-bus {
751 rockchip,pins =
752 <3 24 RK_FUNC_1 &pcfg_pull_none>,
753 <3 25 RK_FUNC_1 &pcfg_pull_none>,
754 <3 26 RK_FUNC_1 &pcfg_pull_none>,
755 <3 27 RK_FUNC_1 &pcfg_pull_none>,
756 <3 28 RK_FUNC_1 &pcfg_pull_none>,
757 <3 29 RK_FUNC_1 &pcfg_pull_none>,
758 <3 30 RK_FUNC_1 &pcfg_pull_none>,
759 <3 31 RK_FUNC_1 &pcfg_pull_none>,
760 <4 0 RK_FUNC_1 &pcfg_pull_none>;
761 };
762 };
763
764 i2s1 {
765 i2s1_2ch_bus: i2s1-2ch-bus {
766 rockchip,pins =
767 <4 3 RK_FUNC_1 &pcfg_pull_none>,
768 <4 4 RK_FUNC_1 &pcfg_pull_none>,
769 <4 5 RK_FUNC_1 &pcfg_pull_none>,
770 <4 6 RK_FUNC_1 &pcfg_pull_none>,
771 <4 7 RK_FUNC_1 &pcfg_pull_none>;
772 };
773 };
774
775 spdif {
776 spdif_bus: spdif-bus {
777 rockchip,pins =
778 <4 21 RK_FUNC_1 &pcfg_pull_none>;
779 };
780 };
781
782 spi0 {
783 spi0_clk: spi0-clk {
784 rockchip,pins =
785 <3 6 RK_FUNC_2 &pcfg_pull_up>;
786 };
787 spi0_cs0: spi0-cs0 {
788 rockchip,pins =
789 <3 7 RK_FUNC_2 &pcfg_pull_up>;
790 };
791 spi0_cs1: spi0-cs1 {
792 rockchip,pins =
793 <3 8 RK_FUNC_2 &pcfg_pull_up>;
794 };
795 spi0_tx: spi0-tx {
796 rockchip,pins =
797 <3 5 RK_FUNC_2 &pcfg_pull_up>;
798 };
799 spi0_rx: spi0-rx {
800 rockchip,pins =
801 <3 4 RK_FUNC_2 &pcfg_pull_up>;
802 };
803 };
804
805 spi1 {
806 spi1_clk: spi1-clk {
807 rockchip,pins =
808 <1 9 RK_FUNC_2 &pcfg_pull_up>;
809 };
810 spi1_cs0: spi1-cs0 {
811 rockchip,pins =
812 <1 10 RK_FUNC_2 &pcfg_pull_up>;
813 };
814 spi1_rx: spi1-rx {
815 rockchip,pins =
816 <1 7 RK_FUNC_2 &pcfg_pull_up>;
817 };
818 spi1_tx: spi1-tx {
819 rockchip,pins =
820 <1 8 RK_FUNC_2 &pcfg_pull_up>;
821 };
822 };
823
824 spi2 {
825 spi2_clk: spi2-clk {
826 rockchip,pins =
827 <2 11 RK_FUNC_1 &pcfg_pull_up>;
828 };
829 spi2_cs0: spi2-cs0 {
830 rockchip,pins =
831 <2 12 RK_FUNC_1 &pcfg_pull_up>;
832 };
833 spi2_rx: spi2-rx {
834 rockchip,pins =
835 <2 9 RK_FUNC_1 &pcfg_pull_up>;
836 };
837 spi2_tx: spi2-tx {
838 rockchip,pins =
839 <2 10 RK_FUNC_1 &pcfg_pull_up>;
840 };
841 };
842
843 spi3 {
844 spi3_clk: spi3-clk {
845 rockchip,pins =
846 <1 17 RK_FUNC_1 &pcfg_pull_up>;
847 };
848 spi3_cs0: spi3-cs0 {
849 rockchip,pins =
850 <1 18 RK_FUNC_1 &pcfg_pull_up>;
851 };
852 spi3_rx: spi3-rx {
853 rockchip,pins =
854 <1 15 RK_FUNC_1 &pcfg_pull_up>;
855 };
856 spi3_tx: spi3-tx {
857 rockchip,pins =
858 <1 16 RK_FUNC_1 &pcfg_pull_up>;
859 };
860 };
861
862 spi4 {
863 spi4_clk: spi4-clk {
864 rockchip,pins =
865 <3 2 RK_FUNC_2 &pcfg_pull_up>;
866 };
867 spi4_cs0: spi4-cs0 {
868 rockchip,pins =
869 <3 3 RK_FUNC_2 &pcfg_pull_up>;
870 };
871 spi4_rx: spi4-rx {
872 rockchip,pins =
873 <3 0 RK_FUNC_2 &pcfg_pull_up>;
874 };
875 spi4_tx: spi4-tx {
876 rockchip,pins =
877 <3 1 RK_FUNC_2 &pcfg_pull_up>;
878 };
879 };
880
881 spi5 {
882 spi5_clk: spi5-clk {
883 rockchip,pins =
884 <2 22 RK_FUNC_2 &pcfg_pull_up>;
885 };
886 spi5_cs0: spi5-cs0 {
887 rockchip,pins =
888 <2 23 RK_FUNC_2 &pcfg_pull_up>;
889 };
890 spi5_rx: spi5-rx {
891 rockchip,pins =
892 <2 20 RK_FUNC_2 &pcfg_pull_up>;
893 };
894 spi5_tx: spi5-tx {
895 rockchip,pins =
896 <2 21 RK_FUNC_2 &pcfg_pull_up>;
897 };
898 };
899
900 uart0 {
901 uart0_xfer: uart0-xfer {
902 rockchip,pins =
903 <2 16 RK_FUNC_1 &pcfg_pull_up>,
904 <2 17 RK_FUNC_1 &pcfg_pull_none>;
905 };
906
907 uart0_cts: uart0-cts {
908 rockchip,pins =
909 <2 18 RK_FUNC_1 &pcfg_pull_none>;
910 };
911
912 uart0_rts: uart0-rts {
913 rockchip,pins =
914 <2 19 RK_FUNC_1 &pcfg_pull_none>;
915 };
916 };
917
918 uart1 {
919 uart1_xfer: uart1-xfer {
920 rockchip,pins =
921 <3 12 RK_FUNC_2 &pcfg_pull_up>,
922 <3 13 RK_FUNC_2 &pcfg_pull_none>;
923 };
924 };
925
926 uart2a {
927 uart2a_xfer: uart2a-xfer {
928 rockchip,pins =
929 <4 8 RK_FUNC_2 &pcfg_pull_up>,
930 <4 9 RK_FUNC_2 &pcfg_pull_none>;
931 };
932 };
933
934 uart2b {
935 uart2b_xfer: uart2b-xfer {
936 rockchip,pins =
937 <4 16 RK_FUNC_2 &pcfg_pull_up>,
938 <4 17 RK_FUNC_2 &pcfg_pull_none>;
939 };
940 };
941
942 uart2c {
943 uart2c_xfer: uart2c-xfer {
944 rockchip,pins =
945 <4 19 RK_FUNC_1 &pcfg_pull_up>,
946 <4 20 RK_FUNC_1 &pcfg_pull_none>;
947 };
948 };
949
950 uart3 {
951 uart3_xfer: uart3-xfer {
952 rockchip,pins =
953 <3 14 RK_FUNC_2 &pcfg_pull_up>,
954 <3 15 RK_FUNC_2 &pcfg_pull_none>;
955 };
956
957 uart3_cts: uart3-cts {
958 rockchip,pins =
959 <3 18 RK_FUNC_2 &pcfg_pull_none>;
960 };
961
962 uart3_rts: uart3-rts {
963 rockchip,pins =
964 <3 19 RK_FUNC_2 &pcfg_pull_none>;
965 };
966 };
967
968 uart4 {
969 uart4_xfer: uart4-xfer {
970 rockchip,pins =
971 <1 7 RK_FUNC_1 &pcfg_pull_up>,
972 <1 8 RK_FUNC_1 &pcfg_pull_none>;
973 };
974 };
975
976 uarthdcp {
977 uarthdcp_xfer: uarthdcp-xfer {
978 rockchip,pins =
979 <4 21 RK_FUNC_2 &pcfg_pull_up>,
980 <4 22 RK_FUNC_2 &pcfg_pull_none>;
981 };
982 };
983
984 pwm0 {
985 pwm0_pin: pwm0-pin {
986 rockchip,pins =
987 <4 18 RK_FUNC_1 &pcfg_pull_none>;
988 };
989
990 vop0_pwm_pin: vop0-pwm-pin {
991 rockchip,pins =
992 <4 18 RK_FUNC_2 &pcfg_pull_none>;
993 };
994 };
995
996 pwm1 {
997 pwm1_pin: pwm1-pin {
998 rockchip,pins =
999 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1000 };
1001
1002 vop1_pwm_pin: vop1-pwm-pin {
1003 rockchip,pins =
1004 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1005 };
1006 };
1007
1008 pwm2 {
1009 pwm2_pin: pwm2-pin {
1010 rockchip,pins =
1011 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1012 };
1013 };
1014
1015 pwm3a {
1016 pwm3a_pin: pwm3a-pin {
1017 rockchip,pins =
1018 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1019 };
1020 };
1021
1022 pwm3b {
1023 pwm3b_pin: pwm3b-pin {
1024 rockchip,pins =
1025 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1026 };
1027 };
1028 };
1029};
Linux 6.x block layer and io_uring tree(s)