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arm64: dts: rockchip: add missing rockchip,grf property to rk356x
[linux-block.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
CommitLineData
4ee99ceb 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
f048b9a4
JX		 2/*
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
f048b9a4
JX		 4 */
5
6#include <dt-bindings/clock/rk3399-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
807a2371 11#include <dt-bindings/power/rk3399-power.h>
95c27ba7 12#include <dt-bindings/thermal/thermal.h>
f048b9a4
JX		 13
14/ {
15 compatible = "rockchip,rk3399";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
2eca8411 22 ethernet0 = &gmac;
69e5a8fe
DW		 23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
f048b9a4
JX		 32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
38
39 cpus {
40 #address-cells = <2>;
41 #size-cells = <0>;
42
43 cpu-map {
44 cluster0 {
45 core0 {
46 cpu = <&cpu_l0>;
47 };
48 core1 {
49 cpu = <&cpu_l1>;
50 };
51 core2 {
52 cpu = <&cpu_l2>;
53 };
54 core3 {
55 cpu = <&cpu_l3>;
56 };
57 };
58
59 cluster1 {
60 core0 {
61 cpu = <&cpu_b0>;
62 };
63 core1 {
64 cpu = <&cpu_b1>;
65 };
66 };
67 };
68
69 cpu_l0: cpu@0 {
70 device_type = "cpu";
31af04cd 71 compatible = "arm,cortex-a53";
f048b9a4
JX		 72 reg = <0x0 0x0>;
73 enable-method = "psci";
97df3aa7 74 capacity-dmips-mhz = <485>;
f048b9a4 75 clocks = <&cru ARMCLKL>;
cc9b0918 76 #cooling-cells = <2>; /* min followed by max */
f4697bd7 77 dynamic-power-coefficient = <100>;
f888da16 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 79 };
80
81 cpu_l1: cpu@1 {
82 device_type = "cpu";
31af04cd 83 compatible = "arm,cortex-a53";
f048b9a4
JX		 84 reg = <0x0 0x1>;
85 enable-method = "psci";
97df3aa7 86 capacity-dmips-mhz = <485>;
f048b9a4 87 clocks = <&cru ARMCLKL>;
cc9b0918 88 #cooling-cells = <2>; /* min followed by max */
f4697bd7 89 dynamic-power-coefficient = <100>;
f888da16 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 91 };
92
93 cpu_l2: cpu@2 {
94 device_type = "cpu";
31af04cd 95 compatible = "arm,cortex-a53";
f048b9a4
JX		 96 reg = <0x0 0x2>;
97 enable-method = "psci";
97df3aa7 98 capacity-dmips-mhz = <485>;
f048b9a4 99 clocks = <&cru ARMCLKL>;
cc9b0918 100 #cooling-cells = <2>; /* min followed by max */
f4697bd7 101 dynamic-power-coefficient = <100>;
f888da16 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 103 };
104
105 cpu_l3: cpu@3 {
106 device_type = "cpu";
31af04cd 107 compatible = "arm,cortex-a53";
f048b9a4
JX		 108 reg = <0x0 0x3>;
109 enable-method = "psci";
97df3aa7 110 capacity-dmips-mhz = <485>;
f048b9a4 111 clocks = <&cru ARMCLKL>;
cc9b0918 112 #cooling-cells = <2>; /* min followed by max */
f4697bd7 113 dynamic-power-coefficient = <100>;
f888da16 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 115 };
116
117 cpu_b0: cpu@100 {
118 device_type = "cpu";
31af04cd 119 compatible = "arm,cortex-a72";
f048b9a4
JX		 120 reg = <0x0 0x100>;
121 enable-method = "psci";
97df3aa7 122 capacity-dmips-mhz = <1024>;
f048b9a4 123 clocks = <&cru ARMCLKB>;
cc9b0918 124 #cooling-cells = <2>; /* min followed by max */
45a995c0 125 dynamic-power-coefficient = <436>;
f888da16 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 127 };
128
129 cpu_b1: cpu@101 {
130 device_type = "cpu";
31af04cd 131 compatible = "arm,cortex-a72";
f048b9a4
JX		 132 reg = <0x0 0x101>;
133 enable-method = "psci";
97df3aa7 134 capacity-dmips-mhz = <1024>;
f048b9a4 135 clocks = <&cru ARMCLKB>;
cc9b0918 136 #cooling-cells = <2>; /* min followed by max */
45a995c0 137 dynamic-power-coefficient = <436>;
f888da16
TX		 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
139 };
140
141 idle-states {
142 entry-method = "psci";
143
144 CPU_SLEEP: cpu-sleep {
145 compatible = "arm,idle-state";
146 local-timer-stop;
147 arm,psci-suspend-param = <0x0010000>;
148 entry-latency-us = <120>;
149 exit-latency-us = <250>;
150 min-residency-us = <900>;
151 };
152
153 CLUSTER_SLEEP: cluster-sleep {
154 compatible = "arm,idle-state";
155 local-timer-stop;
156 arm,psci-suspend-param = <0x1010000>;
157 entry-latency-us = <400>;
158 exit-latency-us = <500>;
159 min-residency-us = <2000>;
160 };
f048b9a4
JX		 161 };
162 };
163
fbd4cc0e
MY		 164 display-subsystem {
165 compatible = "rockchip,display-subsystem";
166 ports = <&vopl_out>, <&vopb_out>;
167 };
168
6840eb0d
CW		 169 pmu_a53 {
170 compatible = "arm,cortex-a53-pmu";
171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
172 };
173
174 pmu_a72 {
175 compatible = "arm,cortex-a72-pmu";
176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
177 };
178
f048b9a4
JX		 179 psci {
180 compatible = "arm,psci-1.0";
181 method = "smc";
182 };
183
184 timer {
185 compatible = "arm,armv8-timer";
210bbd38
CW		 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
e6186820 190 arm,no-tick-in-suspend;
f048b9a4
JX		 191 };
192
193 xin24m: xin24m {
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
197 #clock-cells = <0>;
198 };
199
66aef3cb
BN		 200 pcie0: pcie@f8000000 {
201 compatible = "rockchip,rk3399-pcie";
202 reg = <0x0 0xf8000000 0x0 0x2000000>,
203 <0x0 0xfd000000 0x0 0x1000000>;
204 reg-names = "axi-base", "apb-base";
43f20b1c 205 device_type = "pci";
66aef3cb
BN		 206 #address-cells = <3>;
207 #size-cells = <2>;
208 #interrupt-cells = <1>;
209 aspm-no-l0s;
d633becc 210 bus-range = <0x0 0x1f>;
66aef3cb
BN		 211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
213 clock-names = "aclk", "aclk-perf",
214 "hclk", "pm";
215 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
218 interrupt-names = "sys", "legacy", "client";
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
221 <0 0 0 2 &pcie0_intc 1>,
222 <0 0 0 3 &pcie0_intc 2>,
223 <0 0 0 4 &pcie0_intc 3>;
224 max-link-speed = <1>;
225 msi-map = <0x0 &its 0x0 0x1000>;
e9a60cac
SL		 226 phys = <&pcie_phy 0>, <&pcie_phy 1>,
227 <&pcie_phy 2>, <&pcie_phy 3>;
228 phy-names = "pcie-phy-0", "pcie-phy-1",
229 "pcie-phy-2", "pcie-phy-3";
8efe01b4 230 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
5b931210 231 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
66aef3cb
BN		 232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
233 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
234 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
235 <&cru SRST_A_PCIE>;
236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
237 "pm", "pclk", "aclk";
238 status = "disabled";
239
240 pcie0_intc: interrupt-controller {
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <1>;
244 };
245 };
246
eb3a6a6a
RC		 247 gmac: ethernet@fe300000 {
248 compatible = "rockchip,rk3399-gmac";
249 reg = <0x0 0xfe300000 0x0 0x10000>;
250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
251 interrupt-names = "macirq";
252 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
253 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
254 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
255 <&cru PCLK_GMAC>;
256 clock-names = "stmmaceth", "mac_clk_rx",
257 "mac_clk_tx", "clk_mac_ref",
258 "clk_mac_refout", "aclk_mac",
259 "pclk_mac";
260 power-domains = <&power RK3399_PD_GMAC>;
261 resets = <&cru SRST_A_GMAC>;
262 reset-names = "stmmaceth";
263 rockchip,grf = <&grf>;
8a469ee3 264 snps,txpbl = <0x4>;
eb3a6a6a
RC		 265 status = "disabled";
266 };
267
3ef7c255 268 sdio0: mmc@fe310000 {
f048b9a4
JX		 269 compatible = "rockchip,rk3399-dw-mshc",
270 "rockchip,rk3288-dw-mshc";
271 reg = <0x0 0xfe310000 0x0 0x4000>;
210bbd38 272 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 273 max-frequency = <150000000>;
f048b9a4
JX		 274 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
275 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
277 fifo-depth = <0x100>;
b0f2110a 278 power-domains = <&power RK3399_PD_SDIOAUDIO>;
04dc7f62
HS		 279 resets = <&cru SRST_SDIO0>;
280 reset-names = "reset";
f048b9a4
JX		 281 status = "disabled";
282 };
283
3ef7c255 284 sdmmc: mmc@fe320000 {
f048b9a4
JX		 285 compatible = "rockchip,rk3399-dw-mshc",
286 "rockchip,rk3288-dw-mshc";
287 reg = <0x0 0xfe320000 0x0 0x4000>;
210bbd38 288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 289 max-frequency = <150000000>;
e702e13f
LH		 290 assigned-clocks = <&cru HCLK_SD>;
291 assigned-clock-rates = <200000000>;
f048b9a4
JX		 292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
295 fifo-depth = <0x100>;
1bc60bee 296 power-domains = <&power RK3399_PD_SD>;
04dc7f62
HS		 297 resets = <&cru SRST_SDMMC>;
298 reset-names = "reset";
f048b9a4
JX		 299 status = "disabled";
300 };
301
9a9f6427 302 sdhci: mmc@fe330000 {
b4e87c09
BN		 303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
304 reg = <0x0 0xfe330000 0x0 0x10000>;
210bbd38 305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
64e3481c 306 arasan,soc-ctl-syscon = <&grf>;
b4e87c09
BN		 307 assigned-clocks = <&cru SCLK_EMMC>;
308 assigned-clock-rates = <200000000>;
309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
310 clock-names = "clk_xin", "clk_ahb";
ed388cdd
DA		 311 clock-output-names = "emmc_cardclock";
312 #clock-cells = <0>;
b4e87c09
BN		 313 phys = <&emmc_phy>;
314 phy-names = "phy_arasan";
a1907df2 315 power-domains = <&power RK3399_PD_EMMC>;
a3eec13b 316 disable-cqe-dcmd;
b4e87c09
BN		 317 status = "disabled";
318 };
319
f048b9a4
JX		 320 usb_host0_ehci: usb@fe380000 {
321 compatible = "generic-ehci";
322 reg = <0x0 0xfe380000 0x0 0x20000>;
210bbd38 323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
325 <&u2phy0>;
103e9f85
FW		 326 phys = <&u2phy0_host>;
327 phy-names = "usb";
f048b9a4
JX		 328 status = "disabled";
329 };
330
331 usb_host0_ohci: usb@fe3a0000 {
332 compatible = "generic-ohci";
333 reg = <0x0 0xfe3a0000 0x0 0x20000>;
210bbd38 334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
336 <&u2phy0>;
b5d1c572
W		 337 phys = <&u2phy0_host>;
338 phy-names = "usb";
f048b9a4
JX		 339 status = "disabled";
340 };
341
342 usb_host1_ehci: usb@fe3c0000 {
343 compatible = "generic-ehci";
344 reg = <0x0 0xfe3c0000 0x0 0x20000>;
210bbd38 345 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 346 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
347 <&u2phy1>;
103e9f85
FW		 348 phys = <&u2phy1_host>;
349 phy-names = "usb";
f048b9a4
JX		 350 status = "disabled";
351 };
352
353 usb_host1_ohci: usb@fe3e0000 {
354 compatible = "generic-ohci";
355 reg = <0x0 0xfe3e0000 0x0 0x20000>;
210bbd38 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
358 <&u2phy1>;
b5d1c572
W		 359 phys = <&u2phy1_host>;
360 phy-names = "usb";
f048b9a4
JX		 361 status = "disabled";
362 };
363
7144224f
BN		 364 usbdrd3_0: usb@fe800000 {
365 compatible = "rockchip,rk3399-dwc3";
366 #address-cells = <2>;
367 #size-cells = <2>;
368 ranges;
369 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
9df8a2d9
EBS		 370 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
371 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 372 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 373 "bus_clk", "aclk_usb3_rksoc_axi_perf",
374 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 375 resets = <&cru SRST_A_USB3_OTG0>;
376 reset-names = "usb3-otg";
7144224f
BN		 377 status = "disabled";
378
190c7f6f 379 usbdrd_dwc3_0: usb@fe800000 {
7144224f
BN		 380 compatible = "snps,dwc3";
381 reg = <0x0 0xfe800000 0x0 0x100000>;
382 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
e6d237fd
EBS		 383 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
384 <&cru SCLK_USB3OTG0_SUSPEND>;
385 clock-names = "ref", "bus_early", "suspend";
7144224f 386 dr_mode = "otg";
bfdca173
EBS		 387 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
388 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 389 phy_type = "utmi_wide";
390 snps,dis_enblslpm_quirk;
391 snps,dis-u2-freeclk-exists-quirk;
392 snps,dis_u2_susphy_quirk;
393 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 394 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 395 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 396 status = "disabled";
397 };
398 };
399
400 usbdrd3_1: usb@fe900000 {
401 compatible = "rockchip,rk3399-dwc3";
402 #address-cells = <2>;
403 #size-cells = <2>;
404 ranges;
405 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
9df8a2d9
EBS		 406 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
407 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 408 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 409 "bus_clk", "aclk_usb3_rksoc_axi_perf",
410 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 411 resets = <&cru SRST_A_USB3_OTG1>;
412 reset-names = "usb3-otg";
7144224f
BN		 413 status = "disabled";
414
190c7f6f 415 usbdrd_dwc3_1: usb@fe900000 {
7144224f
BN		 416 compatible = "snps,dwc3";
417 reg = <0x0 0xfe900000 0x0 0x100000>;
418 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
e6d237fd
EBS		 419 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
420 <&cru SCLK_USB3OTG1_SUSPEND>;
421 clock-names = "ref", "bus_early", "suspend";
7144224f 422 dr_mode = "otg";
bfdca173
EBS		 423 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
424 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 425 phy_type = "utmi_wide";
426 snps,dis_enblslpm_quirk;
427 snps,dis-u2-freeclk-exists-quirk;
428 snps,dis_u2_susphy_quirk;
429 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 430 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 431 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 432 status = "disabled";
433 };
434 };
435
2d3c2d56
CZ		 436 cdn_dp: dp@fec00000 {
437 compatible = "rockchip,rk3399-cdn-dp";
438 reg = <0x0 0xfec00000 0x0 0x100000>;
439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
e702e13f
LH		 440 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
441 assigned-clock-rates = <100000000>, <200000000>;
2d3c2d56
CZ		 442 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
443 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
444 clock-names = "core-clk", "pclk", "spdif", "grf";
445 phys = <&tcphy0_dp>, <&tcphy1_dp>;
446 power-domains = <&power RK3399_PD_HDCP>;
447 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
448 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
449 reset-names = "spdif", "dptx", "apb", "core";
450 rockchip,grf = <&grf>;
451 #sound-dai-cells = <1>;
452 status = "disabled";
453
454 ports {
455 dp_in: port {
456 #address-cells = <1>;
457 #size-cells = <0>;
458
459 dp_in_vopb: endpoint@0 {
460 reg = <0>;
461 remote-endpoint = <&vopb_out_dp>;
462 };
463
464 dp_in_vopl: endpoint@1 {
465 reg = <1>;
466 remote-endpoint = <&vopl_out_dp>;
467 };
468 };
469 };
470 };
471
f048b9a4
JX		 472 gic: interrupt-controller@fee00000 {
473 compatible = "arm,gic-v3";
210bbd38 474 #interrupt-cells = <4>;
f048b9a4
JX		 475 #address-cells = <2>;
476 #size-cells = <2>;
477 ranges;
478 interrupt-controller;
479
480 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
481 <0x0 0xfef00000 0 0xc0000>, /* GICR */
482 <0x0 0xfff00000 0 0x10000>, /* GICC */
483 <0x0 0xfff10000 0 0x10000>, /* GICH */
484 <0x0 0xfff20000 0 0x10000>; /* GICV */
210bbd38 485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 486 its: interrupt-controller@fee20000 {
487 compatible = "arm,gic-v3-its";
488 msi-controller;
85dd7638 489 #msi-cells = <1>;
f048b9a4
JX		 490 reg = <0x0 0xfee20000 0x0 0x20000>;
491 };
6840eb0d
CW		 492
493 ppi-partitions {
494 ppi_cluster0: interrupt-partition-0 {
495 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
496 };
497
498 ppi_cluster1: interrupt-partition-1 {
499 affinity = <&cpu_b0 &cpu_b1>;
500 };
501 };
f048b9a4
JX		 502 };
503
fe996215
CW		 504 saradc: saradc@ff100000 {
505 compatible = "rockchip,rk3399-saradc";
506 reg = <0x0 0xff100000 0x0 0x100>;
210bbd38 507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
fe996215
CW		 508 #io-channel-cells = <1>;
509 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
510 clock-names = "saradc", "apb_pclk";
511 resets = <&cru SRST_P_SARADC>;
512 reset-names = "saradc-apb";
513 status = "disabled";
514 };
515
69e5a8fe
DW		 516 i2c1: i2c@ff110000 {
517 compatible = "rockchip,rk3399-i2c";
518 reg = <0x0 0xff110000 0x0 0x1000>;
519 assigned-clocks = <&cru SCLK_I2C1>;
520 assigned-clock-rates = <200000000>;
521 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
522 clock-names = "i2c", "pclk";
210bbd38 523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c1_xfer>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 status = "disabled";
529 };
530
531 i2c2: i2c@ff120000 {
532 compatible = "rockchip,rk3399-i2c";
533 reg = <0x0 0xff120000 0x0 0x1000>;
534 assigned-clocks = <&cru SCLK_I2C2>;
535 assigned-clock-rates = <200000000>;
536 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
537 clock-names = "i2c", "pclk";
210bbd38 538 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c2_xfer>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
545
546 i2c3: i2c@ff130000 {
547 compatible = "rockchip,rk3399-i2c";
548 reg = <0x0 0xff130000 0x0 0x1000>;
549 assigned-clocks = <&cru SCLK_I2C3>;
550 assigned-clock-rates = <200000000>;
551 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
552 clock-names = "i2c", "pclk";
210bbd38 553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c3_xfer>;
556 #address-cells = <1>;
557 #size-cells = <0>;
558 status = "disabled";
559 };
560
561 i2c5: i2c@ff140000 {
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff140000 0x0 0x1000>;
564 assigned-clocks = <&cru SCLK_I2C5>;
565 assigned-clock-rates = <200000000>;
566 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
567 clock-names = "i2c", "pclk";
210bbd38 568 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c5_xfer>;
571 #address-cells = <1>;
572 #size-cells = <0>;
573 status = "disabled";
574 };
575
576 i2c6: i2c@ff150000 {
577 compatible = "rockchip,rk3399-i2c";
578 reg = <0x0 0xff150000 0x0 0x1000>;
579 assigned-clocks = <&cru SCLK_I2C6>;
580 assigned-clock-rates = <200000000>;
581 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
582 clock-names = "i2c", "pclk";
210bbd38 583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c6_xfer>;
586 #address-cells = <1>;
587 #size-cells = <0>;
588 status = "disabled";
589 };
590
591 i2c7: i2c@ff160000 {
592 compatible = "rockchip,rk3399-i2c";
593 reg = <0x0 0xff160000 0x0 0x1000>;
594 assigned-clocks = <&cru SCLK_I2C7>;
595 assigned-clock-rates = <200000000>;
596 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
597 clock-names = "i2c", "pclk";
210bbd38 598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c7_xfer>;
601 #address-cells = <1>;
602 #size-cells = <0>;
603 status = "disabled";
604 };
605
f048b9a4
JX		 606 uart0: serial@ff180000 {
607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
608 reg = <0x0 0xff180000 0x0 0x100>;
609 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
610 clock-names = "baudclk", "apb_pclk";
210bbd38 611 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 612 reg-shift = <2>;
613 reg-io-width = <4>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&uart0_xfer>;
616 status = "disabled";
617 };
618
619 uart1: serial@ff190000 {
620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
621 reg = <0x0 0xff190000 0x0 0x100>;
622 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
623 clock-names = "baudclk", "apb_pclk";
210bbd38 624 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 625 reg-shift = <2>;
626 reg-io-width = <4>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&uart1_xfer>;
629 status = "disabled";
630 };
631
632 uart2: serial@ff1a0000 {
633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
634 reg = <0x0 0xff1a0000 0x0 0x100>;
635 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
636 clock-names = "baudclk", "apb_pclk";
210bbd38 637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 638 reg-shift = <2>;
639 reg-io-width = <4>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&uart2c_xfer>;
642 status = "disabled";
643 };
644
645 uart3: serial@ff1b0000 {
646 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
647 reg = <0x0 0xff1b0000 0x0 0x100>;
648 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
649 clock-names = "baudclk", "apb_pclk";
210bbd38 650 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 651 reg-shift = <2>;
652 reg-io-width = <4>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&uart3_xfer>;
655 status = "disabled";
656 };
657
658 spi0: spi@ff1c0000 {
659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
660 reg = <0x0 0xff1c0000 0x0 0x1000>;
661 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
662 clock-names = "spiclk", "apb_pclk";
210bbd38 663 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 664 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
665 dma-names = "tx", "rx";
f048b9a4
JX		 666 pinctrl-names = "default";
667 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
668 #address-cells = <1>;
669 #size-cells = <0>;
670 status = "disabled";
671 };
672
673 spi1: spi@ff1d0000 {
674 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
675 reg = <0x0 0xff1d0000 0x0 0x1000>;
676 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
677 clock-names = "spiclk", "apb_pclk";
210bbd38 678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 679 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
680 dma-names = "tx", "rx";
f048b9a4
JX		 681 pinctrl-names = "default";
682 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
683 #address-cells = <1>;
684 #size-cells = <0>;
685 status = "disabled";
686 };
687
688 spi2: spi@ff1e0000 {
689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
690 reg = <0x0 0xff1e0000 0x0 0x1000>;
691 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
692 clock-names = "spiclk", "apb_pclk";
210bbd38 693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 694 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
695 dma-names = "tx", "rx";
f048b9a4
JX		 696 pinctrl-names = "default";
697 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
698 #address-cells = <1>;
699 #size-cells = <0>;
700 status = "disabled";
701 };
702
703 spi4: spi@ff1f0000 {
704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
705 reg = <0x0 0xff1f0000 0x0 0x1000>;
706 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
707 clock-names = "spiclk", "apb_pclk";
210bbd38 708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 709 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
710 dma-names = "tx", "rx";
f048b9a4
JX		 711 pinctrl-names = "default";
712 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
713 #address-cells = <1>;
714 #size-cells = <0>;
715 status = "disabled";
716 };
717
718 spi5: spi@ff200000 {
719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
720 reg = <0x0 0xff200000 0x0 0x1000>;
721 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
722 clock-names = "spiclk", "apb_pclk";
210bbd38 723 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 724 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
725 dma-names = "tx", "rx";
f048b9a4
JX		 726 pinctrl-names = "default";
727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
b0f2110a 728 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 729 #address-cells = <1>;
730 #size-cells = <0>;
731 status = "disabled";
732 };
733
647cea2e 734 thermal_zones: thermal-zones {
e58061b5 735 cpu_thermal: cpu-thermal {
95c27ba7
CW		 736 polling-delay-passive = <100>;
737 polling-delay = <1000>;
738
739 thermal-sensors = <&tsadc 0>;
740
741 trips {
742 cpu_alert0: cpu_alert0 {
743 temperature = <70000>;
744 hysteresis = <2000>;
745 type = "passive";
746 };
747 cpu_alert1: cpu_alert1 {
748 temperature = <75000>;
749 hysteresis = <2000>;
750 type = "passive";
751 };
752 cpu_crit: cpu_crit {
753 temperature = <95000>;
754 hysteresis = <2000>;
755 type = "critical";
756 };
757 };
758
759 cooling-maps {
760 map0 {
761 trip = <&cpu_alert0>;
762 cooling-device =
cdd46460
VK		 763 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
764 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
95c27ba7
CW		 765 };
766 map1 {
767 trip = <&cpu_alert1>;
768 cooling-device =
769 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cdd46460
VK		 770 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
771 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
772 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
773 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
774 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
95c27ba7
CW		 775 };
776 };
777 };
778
e58061b5 779 gpu_thermal: gpu-thermal {
95c27ba7
CW		 780 polling-delay-passive = <100>;
781 polling-delay = <1000>;
782
783 thermal-sensors = <&tsadc 1>;
784
785 trips {
786 gpu_alert0: gpu_alert0 {
787 temperature = <75000>;
788 hysteresis = <2000>;
789 type = "passive";
790 };
791 gpu_crit: gpu_crit {
792 temperature = <95000>;
793 hysteresis = <2000>;
794 type = "critical";
795 };
796 };
36be9111
RM		 797
798 cooling-maps {
799 map0 {
800 trip = <&gpu_alert0>;
801 cooling-device =
802 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
803 };
804 };
95c27ba7
CW		 805 };
806 };
807
808 tsadc: tsadc@ff260000 {
809 compatible = "rockchip,rk3399-tsadc";
810 reg = <0x0 0xff260000 0x0 0x100>;
210bbd38 811 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
95c27ba7
CW		 812 assigned-clocks = <&cru SCLK_TSADC>;
813 assigned-clock-rates = <750000>;
814 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
815 clock-names = "tsadc", "apb_pclk";
816 resets = <&cru SRST_TSADC>;
817 reset-names = "tsadc-apb";
818 rockchip,grf = <&grf>;
819 rockchip,hw-tshut-temp = <95000>;
820 pinctrl-names = "init", "default", "sleep";
2bc65fef 821 pinctrl-0 = <&otp_pin>;
95c27ba7 822 pinctrl-1 = <&otp_out>;
2bc65fef 823 pinctrl-2 = <&otp_pin>;
95c27ba7
CW		 824 #thermal-sensor-cells = <1>;
825 status = "disabled";
826 };
827
a1907df2 828 qos_emmc: qos@ffa58000 {
bd3fd049 829 compatible = "rockchip,rk3399-qos", "syscon";
a1907df2
EZ		 830 reg = <0x0 0xffa58000 0x0 0x20>;
831 };
832
d43c97a5 833 qos_gmac: qos@ffa5c000 {
bd3fd049 834 compatible = "rockchip,rk3399-qos", "syscon";
d43c97a5
CW		 835 reg = <0x0 0xffa5c000 0x0 0x20>;
836 };
837
65f1e902 838 qos_pcie: qos@ffa60080 {
bd3fd049 839 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 840 reg = <0x0 0xffa60080 0x0 0x20>;
841 };
842
843 qos_usb_host0: qos@ffa60100 {
bd3fd049 844 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 845 reg = <0x0 0xffa60100 0x0 0x20>;
846 };
847
848 qos_usb_host1: qos@ffa60180 {
bd3fd049 849 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 850 reg = <0x0 0xffa60180 0x0 0x20>;
851 };
852
853 qos_usb_otg0: qos@ffa70000 {
bd3fd049 854 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 855 reg = <0x0 0xffa70000 0x0 0x20>;
856 };
857
858 qos_usb_otg1: qos@ffa70080 {
bd3fd049 859 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 860 reg = <0x0 0xffa70080 0x0 0x20>;
861 };
862
863 qos_sd: qos@ffa74000 {
bd3fd049 864 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 865 reg = <0x0 0xffa74000 0x0 0x20>;
866 };
867
868 qos_sdioaudio: qos@ffa76000 {
bd3fd049 869 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 870 reg = <0x0 0xffa76000 0x0 0x20>;
871 };
872
807a2371 873 qos_hdcp: qos@ffa90000 {
bd3fd049 874 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 875 reg = <0x0 0xffa90000 0x0 0x20>;
876 };
877
878 qos_iep: qos@ffa98000 {
bd3fd049 879 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 880 reg = <0x0 0xffa98000 0x0 0x20>;
881 };
882
883 qos_isp0_m0: qos@ffaa0000 {
bd3fd049 884 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 885 reg = <0x0 0xffaa0000 0x0 0x20>;
886 };
887
888 qos_isp0_m1: qos@ffaa0080 {
bd3fd049 889 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 890 reg = <0x0 0xffaa0080 0x0 0x20>;
891 };
892
893 qos_isp1_m0: qos@ffaa8000 {
bd3fd049 894 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 895 reg = <0x0 0xffaa8000 0x0 0x20>;
896 };
897
898 qos_isp1_m1: qos@ffaa8080 {
bd3fd049 899 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 900 reg = <0x0 0xffaa8080 0x0 0x20>;
901 };
902
903 qos_rga_r: qos@ffab0000 {
bd3fd049 904 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 905 reg = <0x0 0xffab0000 0x0 0x20>;
906 };
907
908 qos_rga_w: qos@ffab0080 {
bd3fd049 909 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 910 reg = <0x0 0xffab0080 0x0 0x20>;
911 };
912
913 qos_video_m0: qos@ffab8000 {
bd3fd049 914 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 915 reg = <0x0 0xffab8000 0x0 0x20>;
916 };
917
918 qos_video_m1_r: qos@ffac0000 {
bd3fd049 919 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 920 reg = <0x0 0xffac0000 0x0 0x20>;
921 };
922
923 qos_video_m1_w: qos@ffac0080 {
bd3fd049 924 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 925 reg = <0x0 0xffac0080 0x0 0x20>;
926 };
927
928 qos_vop_big_r: qos@ffac8000 {
bd3fd049 929 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 930 reg = <0x0 0xffac8000 0x0 0x20>;
931 };
932
933 qos_vop_big_w: qos@ffac8080 {
bd3fd049 934 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 935 reg = <0x0 0xffac8080 0x0 0x20>;
936 };
937
938 qos_vop_little: qos@ffad0000 {
bd3fd049 939 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 940 reg = <0x0 0xffad0000 0x0 0x20>;
941 };
942
65f1e902 943 qos_perihp: qos@ffad8080 {
bd3fd049 944 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 945 reg = <0x0 0xffad8080 0x0 0x20>;
946 };
947
807a2371 948 qos_gpu: qos@ffae0000 {
bd3fd049 949 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 950 reg = <0x0 0xffae0000 0x0 0x20>;
951 };
952
953 pmu: power-management@ff310000 {
954 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
955 reg = <0x0 0xff310000 0x0 0x1000>;
956
957 /*
958 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
959 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
960 * Some of the power domains are grouped together for every
961 * voltage domain.
962 * The detail contents as below.
963 */
964 power: power-controller {
965 compatible = "rockchip,rk3399-power-controller";
966 #power-domain-cells = <1>;
967 #address-cells = <1>;
968 #size-cells = <0>;
969
970 /* These power domains are grouped by VD_CENTER */
148bbe29 971 power-domain@RK3399_PD_IEP {
807a2371
EZ		 972 reg = <RK3399_PD_IEP>;
973 clocks = <&cru ACLK_IEP>,
974 <&cru HCLK_IEP>;
975 pm_qos = <&qos_iep>;
837188d4 976 #power-domain-cells = <0>;
807a2371 977 };
148bbe29 978 power-domain@RK3399_PD_RGA {
807a2371
EZ		 979 reg = <RK3399_PD_RGA>;
980 clocks = <&cru ACLK_RGA>,
981 <&cru HCLK_RGA>;
982 pm_qos = <&qos_rga_r>,
983 <&qos_rga_w>;
837188d4 984 #power-domain-cells = <0>;
807a2371 985 };
148bbe29 986 power-domain@RK3399_PD_VCODEC {
807a2371
EZ		 987 reg = <RK3399_PD_VCODEC>;
988 clocks = <&cru ACLK_VCODEC>,
989 <&cru HCLK_VCODEC>;
990 pm_qos = <&qos_video_m0>;
837188d4 991 #power-domain-cells = <0>;
807a2371 992 };
148bbe29 993 power-domain@RK3399_PD_VDU {
807a2371
EZ		 994 reg = <RK3399_PD_VDU>;
995 clocks = <&cru ACLK_VDU>,
996 <&cru HCLK_VDU>;
997 pm_qos = <&qos_video_m1_r>,
998 <&qos_video_m1_w>;
837188d4 999 #power-domain-cells = <0>;
807a2371
EZ		 1000 };
1001
1002 /* These power domains are grouped by VD_GPU */
148bbe29 1003 power-domain@RK3399_PD_GPU {
807a2371
EZ		 1004 reg = <RK3399_PD_GPU>;
1005 clocks = <&cru ACLK_GPU>;
1006 pm_qos = <&qos_gpu>;
837188d4 1007 #power-domain-cells = <0>;
807a2371
EZ		 1008 };
1009
1010 /* These power domains are grouped by VD_LOGIC */
148bbe29 1011 power-domain@RK3399_PD_EDP {
3cf04a4e
EZ		 1012 reg = <RK3399_PD_EDP>;
1013 clocks = <&cru PCLK_EDP_CTRL>;
837188d4 1014 #power-domain-cells = <0>;
3cf04a4e 1015 };
148bbe29 1016 power-domain@RK3399_PD_EMMC {
a1907df2
EZ		 1017 reg = <RK3399_PD_EMMC>;
1018 clocks = <&cru ACLK_EMMC>;
1019 pm_qos = <&qos_emmc>;
837188d4 1020 #power-domain-cells = <0>;
a1907df2 1021 };
148bbe29 1022 power-domain@RK3399_PD_GMAC {
d43c97a5 1023 reg = <RK3399_PD_GMAC>;
2afc1db0
JC		 1024 clocks = <&cru ACLK_GMAC>,
1025 <&cru PCLK_GMAC>;
d43c97a5 1026 pm_qos = <&qos_gmac>;
837188d4 1027 #power-domain-cells = <0>;
d43c97a5 1028 };
148bbe29 1029 power-domain@RK3399_PD_SD {
1bc60bee
EZ		 1030 reg = <RK3399_PD_SD>;
1031 clocks = <&cru HCLK_SDMMC>,
1032 <&cru SCLK_SDMMC>;
1033 pm_qos = <&qos_sd>;
837188d4 1034 #power-domain-cells = <0>;
1bc60bee 1035 };
148bbe29 1036 power-domain@RK3399_PD_SDIOAUDIO {
b0f2110a
CW		 1037 reg = <RK3399_PD_SDIOAUDIO>;
1038 clocks = <&cru HCLK_SDIO>;
1039 pm_qos = <&qos_sdioaudio>;
837188d4 1040 #power-domain-cells = <0>;
b0f2110a 1041 };
148bbe29 1042 power-domain@RK3399_PD_TCPD0 {
2b99e619
JJ		 1043 reg = <RK3399_PD_TCPD0>;
1044 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1045 <&cru SCLK_UPHY0_TCPDPHY_REF>;
837188d4 1046 #power-domain-cells = <0>;
2b99e619 1047 };
148bbe29 1048 power-domain@RK3399_PD_TCPD1 {
2b99e619
JJ		 1049 reg = <RK3399_PD_TCPD1>;
1050 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1051 <&cru SCLK_UPHY1_TCPDPHY_REF>;
837188d4 1052 #power-domain-cells = <0>;
2b99e619 1053 };
148bbe29 1054 power-domain@RK3399_PD_USB3 {
a1bbaaa4
EBS		 1055 reg = <RK3399_PD_USB3>;
1056 clocks = <&cru ACLK_USB3>;
1057 pm_qos = <&qos_usb_otg0>,
1058 <&qos_usb_otg1>;
837188d4 1059 #power-domain-cells = <0>;
a1bbaaa4 1060 };
148bbe29 1061 power-domain@RK3399_PD_VIO {
807a2371 1062 reg = <RK3399_PD_VIO>;
837188d4 1063 #power-domain-cells = <1>;
807a2371
EZ		 1064 #address-cells = <1>;
1065 #size-cells = <0>;
1066
148bbe29 1067 power-domain@RK3399_PD_HDCP {
807a2371
EZ		 1068 reg = <RK3399_PD_HDCP>;
1069 clocks = <&cru ACLK_HDCP>,
1070 <&cru HCLK_HDCP>,
1071 <&cru PCLK_HDCP>;
1072 pm_qos = <&qos_hdcp>;
837188d4 1073 #power-domain-cells = <0>;
807a2371 1074 };
148bbe29 1075 power-domain@RK3399_PD_ISP0 {
807a2371
EZ		 1076 reg = <RK3399_PD_ISP0>;
1077 clocks = <&cru ACLK_ISP0>,
1078 <&cru HCLK_ISP0>;
1079 pm_qos = <&qos_isp0_m0>,
1080 <&qos_isp0_m1>;
837188d4 1081 #power-domain-cells = <0>;
807a2371 1082 };
148bbe29 1083 power-domain@RK3399_PD_ISP1 {
807a2371
EZ		 1084 reg = <RK3399_PD_ISP1>;
1085 clocks = <&cru ACLK_ISP1>,
1086 <&cru HCLK_ISP1>;
1087 pm_qos = <&qos_isp1_m0>,
1088 <&qos_isp1_m1>;
837188d4 1089 #power-domain-cells = <0>;
807a2371 1090 };
148bbe29 1091 power-domain@RK3399_PD_VO {
807a2371 1092 reg = <RK3399_PD_VO>;
837188d4 1093 #power-domain-cells = <1>;
807a2371
EZ		 1094 #address-cells = <1>;
1095 #size-cells = <0>;
1096
148bbe29 1097 power-domain@RK3399_PD_VOPB {
807a2371
EZ		 1098 reg = <RK3399_PD_VOPB>;
1099 clocks = <&cru ACLK_VOP0>,
1100 <&cru HCLK_VOP0>;
1101 pm_qos = <&qos_vop_big_r>,
1102 <&qos_vop_big_w>;
837188d4 1103 #power-domain-cells = <0>;
807a2371 1104 };
148bbe29 1105 power-domain@RK3399_PD_VOPL {
807a2371
EZ		 1106 reg = <RK3399_PD_VOPL>;
1107 clocks = <&cru ACLK_VOP1>,
1108 <&cru HCLK_VOP1>;
1109 pm_qos = <&qos_vop_little>;
837188d4 1110 #power-domain-cells = <0>;
807a2371
EZ		 1111 };
1112 };
1113 };
1114 };
1115 };
1116
f048b9a4 1117 pmugrf: syscon@ff320000 {
16759262 1118 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
f048b9a4 1119 reg = <0x0 0xff320000 0x0 0x1000>;
6d0e3a45
HS		 1120
1121 pmu_io_domains: io-domains {
1122 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1123 status = "disabled";
1124 };
f048b9a4
JX		 1125 };
1126
1127 spi3: spi@ff350000 {
1128 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1129 reg = <0x0 0xff350000 0x0 0x1000>;
1130 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1131 clock-names = "spiclk", "apb_pclk";
210bbd38 1132 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1133 pinctrl-names = "default";
1134 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 status = "disabled";
1138 };
1139
1140 uart4: serial@ff370000 {
1141 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1142 reg = <0x0 0xff370000 0x0 0x100>;
1143 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1144 clock-names = "baudclk", "apb_pclk";
210bbd38 1145 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1146 reg-shift = <2>;
1147 reg-io-width = <4>;
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&uart4_xfer>;
1150 status = "disabled";
1151 };
1152
69e5a8fe
DW		 1153 i2c0: i2c@ff3c0000 {
1154 compatible = "rockchip,rk3399-i2c";
1155 reg = <0x0 0xff3c0000 0x0 0x1000>;
1156 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1157 assigned-clock-rates = <200000000>;
1158 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1159 clock-names = "i2c", "pclk";
210bbd38 1160 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1161 pinctrl-names = "default";
1162 pinctrl-0 = <&i2c0_xfer>;
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1165 status = "disabled";
1166 };
1167
1168 i2c4: i2c@ff3d0000 {
1169 compatible = "rockchip,rk3399-i2c";
1170 reg = <0x0 0xff3d0000 0x0 0x1000>;
1171 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1172 assigned-clock-rates = <200000000>;
1173 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1174 clock-names = "i2c", "pclk";
210bbd38 1175 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1176 pinctrl-names = "default";
1177 pinctrl-0 = <&i2c4_xfer>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180 status = "disabled";
1181 };
1182
1183 i2c8: i2c@ff3e0000 {
1184 compatible = "rockchip,rk3399-i2c";
1185 reg = <0x0 0xff3e0000 0x0 0x1000>;
1186 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1187 assigned-clock-rates = <200000000>;
1188 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1189 clock-names = "i2c", "pclk";
210bbd38 1190 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1191 pinctrl-names = "default";
1192 pinctrl-0 = <&i2c8_xfer>;
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1195 status = "disabled";
f048b9a4
JX		 1196 };
1197
1198 pwm0: pwm@ff420000 {
1199 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1200 reg = <0x0 0xff420000 0x0 0x10>;
1201 #pwm-cells = <3>;
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&pwm0_pin>;
1204 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1205 status = "disabled";
1206 };
1207
1208 pwm1: pwm@ff420010 {
1209 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1210 reg = <0x0 0xff420010 0x0 0x10>;
1211 #pwm-cells = <3>;
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&pwm1_pin>;
1214 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1215 status = "disabled";
1216 };
1217
1218 pwm2: pwm@ff420020 {
1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1220 reg = <0x0 0xff420020 0x0 0x10>;
1221 #pwm-cells = <3>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&pwm2_pin>;
1224 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1225 status = "disabled";
1226 };
1227
1228 pwm3: pwm@ff420030 {
1229 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1230 reg = <0x0 0xff420030 0x0 0x10>;
1231 #pwm-cells = <3>;
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&pwm3a_pin>;
1234 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1235 status = "disabled";
1236 };
1237
5cd4c31a
EG		 1238 vpu: video-codec@ff650000 {
1239 compatible = "rockchip,rk3399-vpu";
1240 reg = <0x0 0xff650000 0x0 0x800>;
1241 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1242 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
5cd4c31a
EG		 1243 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1244 clock-names = "aclk", "hclk";
1245 iommus = <&vpu_mmu>;
1246 power-domains = <&power RK3399_PD_VCODEC>;
1247 };
1248
ae4fdcca
SX		 1249 vpu_mmu: iommu@ff650800 {
1250 compatible = "rockchip,iommu";
1251 reg = <0x0 0xff650800 0x0 0x40>;
1252 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
df3bcde7
JC		 1253 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1254 clock-names = "aclk", "iface";
ae4fdcca 1255 #iommu-cells = <0>;
5cd4c31a 1256 power-domains = <&power RK3399_PD_VCODEC>;
ae4fdcca
SX		 1257 };
1258
cbd72144
BB		 1259 vdec: video-codec@ff660000 {
1260 compatible = "rockchip,rk3399-vdec";
1261 reg = <0x0 0xff660000 0x0 0x400>;
1262 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
cbd72144
BB		 1263 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1264 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1265 clock-names = "axi", "ahb", "cabac", "core";
1266 iommus = <&vdec_mmu>;
1267 power-domains = <&power RK3399_PD_VDU>;
1268 };
1269
ae4fdcca
SX		 1270 vdec_mmu: iommu@ff660480 {
1271 compatible = "rockchip,iommu";
1272 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1273 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
df3bcde7
JC		 1274 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1275 clock-names = "aclk", "iface";
cbd72144 1276 power-domains = <&power RK3399_PD_VDU>;
ae4fdcca 1277 #iommu-cells = <0>;
ae4fdcca
SX		 1278 };
1279
1280 iep_mmu: iommu@ff670800 {
1281 compatible = "rockchip,iommu";
1282 reg = <0x0 0xff670800 0x0 0x40>;
1283 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
df3bcde7
JC		 1284 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1285 clock-names = "aclk", "iface";
ae4fdcca
SX		 1286 #iommu-cells = <0>;
1287 status = "disabled";
1288 };
1289
ec5ccfd7
JC		 1290 rga: rga@ff680000 {
1291 compatible = "rockchip,rk3399-rga";
1292 reg = <0x0 0xff680000 0x0 0x10000>;
1293 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1294 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1295 clock-names = "aclk", "hclk", "sclk";
1296 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1297 reset-names = "core", "axi", "ahb";
1298 power-domains = <&power RK3399_PD_RGA>;
1299 };
1300
b7ee3b27
FX		 1301 efuse0: efuse@ff690000 {
1302 compatible = "rockchip,rk3399-efuse";
1303 reg = <0x0 0xff690000 0x0 0x80>;
1304 #address-cells = <1>;
1305 #size-cells = <1>;
1306 clocks = <&cru PCLK_EFUSE1024NS>;
1307 clock-names = "pclk_efuse";
1308
1309 /* Data cells */
0d326927
ZX		 1310 cpu_id: cpu-id@7 {
1311 reg = <0x07 0x10>;
1312 };
b7ee3b27
FX		 1313 cpub_leakage: cpu-leakage@17 {
1314 reg = <0x17 0x1>;
1315 };
1316 gpu_leakage: gpu-leakage@18 {
1317 reg = <0x18 0x1>;
1318 };
1319 center_leakage: center-leakage@19 {
1320 reg = <0x19 0x1>;
1321 };
1322 cpul_leakage: cpu-leakage@1a {
1323 reg = <0x1a 0x1>;
1324 };
1325 logic_leakage: logic-leakage@1b {
1326 reg = <0x1b 0x1>;
1327 };
1328 wafer_info: wafer-info@1c {
1329 reg = <0x1c 0x1>;
1330 };
1331 };
1332
9e824449
RM		 1333 dmac_bus: dma-controller@ff6d0000 {
1334 compatible = "arm,pl330", "arm,primecell";
1335 reg = <0x0 0xff6d0000 0x0 0x4000>;
1336 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1337 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1338 #dma-cells = <1>;
1339 arm,pl330-periph-burst;
1340 clocks = <&cru ACLK_DMAC0_PERILP>;
1341 clock-names = "apb_pclk";
1342 };
1343
1344 dmac_peri: dma-controller@ff6e0000 {
1345 compatible = "arm,pl330", "arm,primecell";
1346 reg = <0x0 0xff6e0000 0x0 0x4000>;
1347 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1348 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1349 #dma-cells = <1>;
1350 arm,pl330-periph-burst;
1351 clocks = <&cru ACLK_DMAC1_PERILP>;
1352 clock-names = "apb_pclk";
1353 };
1354
f048b9a4
JX		 1355 pmucru: pmu-clock-controller@ff750000 {
1356 compatible = "rockchip,rk3399-pmucru";
1357 reg = <0x0 0xff750000 0x0 0x1000>;
8cbb59af 1358 rockchip,grf = <&pmugrf>;
f048b9a4
JX		 1359 #clock-cells = <1>;
1360 #reset-cells = <1>;
1361 assigned-clocks = <&pmucru PLL_PPLL>;
1362 assigned-clock-rates = <676000000>;
1363 };
1364
1365 cru: clock-controller@ff760000 {
1366 compatible = "rockchip,rk3399-cru";
1367 reg = <0x0 0xff760000 0x0 0x1000>;
8cbb59af 1368 rockchip,grf = <&grf>;
f048b9a4
JX		 1369 #clock-cells = <1>;
1370 #reset-cells = <1>;
a09906cd
XZ		 1371 assigned-clocks =
1372 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1373 <&cru PLL_NPLL>,
1374 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1375 <&cru PCLK_PERIHP>,
1376 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
bb4b6201 1377 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
3f7f3b0f 1378 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
e702e13f
LH		 1379 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1380 <&cru ACLK_GIC_PRE>,
1381 <&cru PCLK_DDR>;
a09906cd
XZ		 1382 assigned-clock-rates =
1383 <594000000>, <800000000>,
1384 <1000000000>,
1385 <150000000>, <75000000>,
1386 <37500000>,
1387 <100000000>, <100000000>,
bb4b6201 1388 <50000000>, <600000000>,
3f7f3b0f 1389 <100000000>, <50000000>,
e702e13f
LH		 1390 <400000000>, <400000000>,
1391 <200000000>,
1392 <200000000>;
f048b9a4
JX		 1393 };
1394
1395 grf: syscon@ff770000 {
16759262 1396 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
f048b9a4 1397 reg = <0x0 0xff770000 0x0 0x10000>;
16759262
BN		 1398 #address-cells = <1>;
1399 #size-cells = <1>;
b4e87c09 1400
6d0e3a45
HS		 1401 io_domains: io-domains {
1402 compatible = "rockchip,rk3399-io-voltage-domain";
1403 status = "disabled";
1404 };
1405
e4bfde13
SZ		 1406 mipi_dphy_rx0: mipi-dphy-rx0 {
1407 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1408 clocks = <&cru SCLK_MIPIDPHY_REF>,
1409 <&cru SCLK_DPHY_RX0_CFG>,
1410 <&cru PCLK_VIO_GRF>;
1411 clock-names = "dphy-ref", "dphy-cfg", "grf";
1412 power-domains = <&power RK3399_PD_VIO>;
1413 #phy-cells = <0>;
1414 status = "disabled";
1415 };
1416
8c3d6425 1417 u2phy0: usb2phy@e450 {
103e9f85
FW		 1418 compatible = "rockchip,rk3399-usb2phy";
1419 reg = <0xe450 0x10>;
1420 clocks = <&cru SCLK_USB2PHY0_REF>;
1421 clock-names = "phyclk";
1422 #clock-cells = <0>;
1423 clock-output-names = "clk_usbphy0_480m";
1424 status = "disabled";
1425
1426 u2phy0_host: host-port {
1427 #phy-cells = <0>;
210bbd38 1428 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1429 interrupt-names = "linestate";
1430 status = "disabled";
1431 };
fe7f2de1
WW		 1432
1433 u2phy0_otg: otg-port {
1434 #phy-cells = <0>;
1435 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1436 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1437 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1438 interrupt-names = "otg-bvalid", "otg-id",
1439 "linestate";
1440 status = "disabled";
1441 };
103e9f85
FW		 1442 };
1443
8c3d6425 1444 u2phy1: usb2phy@e460 {
103e9f85
FW		 1445 compatible = "rockchip,rk3399-usb2phy";
1446 reg = <0xe460 0x10>;
1447 clocks = <&cru SCLK_USB2PHY1_REF>;
1448 clock-names = "phyclk";
1449 #clock-cells = <0>;
1450 clock-output-names = "clk_usbphy1_480m";
1451 status = "disabled";
1452
1453 u2phy1_host: host-port {
1454 #phy-cells = <0>;
210bbd38 1455 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1456 interrupt-names = "linestate";
1457 status = "disabled";
1458 };
fe7f2de1
WW		 1459
1460 u2phy1_otg: otg-port {
1461 #phy-cells = <0>;
1462 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1463 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1464 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1465 interrupt-names = "otg-bvalid", "otg-id",
1466 "linestate";
1467 status = "disabled";
1468 };
103e9f85
FW		 1469 };
1470
b4e87c09
BN		 1471 emmc_phy: phy@f780 {
1472 compatible = "rockchip,rk3399-emmc-phy";
1473 reg = <0xf780 0x24>;
ed388cdd
DA		 1474 clocks = <&sdhci>;
1475 clock-names = "emmcclk";
b4e87c09
BN		 1476 #phy-cells = <0>;
1477 status = "disabled";
1478 };
29a0be1c
SL		 1479
1480 pcie_phy: pcie-phy {
1481 compatible = "rockchip,rk3399-pcie-phy";
1482 clocks = <&cru SCLK_PCIEPHY_REF>;
1483 clock-names = "refclk";
e9a60cac 1484 #phy-cells = <1>;
29a0be1c 1485 resets = <&cru SRST_PCIEPHY>;
fb8b7460 1486 drive-impedance-ohm = <50>;
29a0be1c
SL		 1487 reset-names = "phy";
1488 status = "disabled";
1489 };
f048b9a4
JX		 1490 };
1491
f606193a
CZ		 1492 tcphy0: phy@ff7c0000 {
1493 compatible = "rockchip,rk3399-typec-phy";
1494 reg = <0x0 0xff7c0000 0x0 0x40000>;
1495 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1496 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1497 clock-names = "tcpdcore", "tcpdphy-ref";
1498 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1499 assigned-clock-rates = <50000000>;
06ad4b2f 1500 power-domains = <&power RK3399_PD_TCPD0>;
f606193a
CZ		 1501 resets = <&cru SRST_UPHY0>,
1502 <&cru SRST_UPHY0_PIPE_L00>,
1503 <&cru SRST_P_UPHY0_TCPHY>;
1504 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1505 rockchip,grf = <&grf>;
f606193a
CZ		 1506 status = "disabled";
1507
1508 tcphy0_dp: dp-port {
1509 #phy-cells = <0>;
1510 };
1511
1512 tcphy0_usb3: usb3-port {
1513 #phy-cells = <0>;
1514 };
1515 };
1516
1517 tcphy1: phy@ff800000 {
1518 compatible = "rockchip,rk3399-typec-phy";
1519 reg = <0x0 0xff800000 0x0 0x40000>;
1520 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1521 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1522 clock-names = "tcpdcore", "tcpdphy-ref";
1523 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1524 assigned-clock-rates = <50000000>;
06ad4b2f 1525 power-domains = <&power RK3399_PD_TCPD1>;
f606193a
CZ		 1526 resets = <&cru SRST_UPHY1>,
1527 <&cru SRST_UPHY1_PIPE_L00>,
1528 <&cru SRST_P_UPHY1_TCPHY>;
1529 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1530 rockchip,grf = <&grf>;
f606193a
CZ		 1531 status = "disabled";
1532
1533 tcphy1_dp: dp-port {
1534 #phy-cells = <0>;
1535 };
1536
1537 tcphy1_usb3: usb3-port {
1538 #phy-cells = <0>;
1539 };
1540 };
1541
0895b3a8 1542 watchdog@ff848000 {
6b5c5086 1543 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
0895b3a8 1544 reg = <0x0 0xff848000 0x0 0x100>;
f048b9a4 1545 clocks = <&cru PCLK_WDT>;
210bbd38 1546 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1547 };
1548
1e8567d5
HT		 1549 rktimer: rktimer@ff850000 {
1550 compatible = "rockchip,rk3399-timer";
1551 reg = <0x0 0xff850000 0x0 0x1000>;
210bbd38 1552 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1e8567d5
HT		 1553 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1554 clock-names = "pclk", "timer";
1555 };
1556
f048b9a4
JX		 1557 spdif: spdif@ff870000 {
1558 compatible = "rockchip,rk3399-spdif";
1559 reg = <0x0 0xff870000 0x0 0x1000>;
210bbd38 1560 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1561 dmas = <&dmac_bus 7>;
1562 dma-names = "tx";
1563 clock-names = "mclk", "hclk";
1564 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&spdif_bus>;
b0f2110a 1567 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1568 #sound-dai-cells = <0>;
f048b9a4
JX		 1569 status = "disabled";
1570 };
1571
1572 i2s0: i2s@ff880000 {
1573 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1574 reg = <0x0 0xff880000 0x0 0x1000>;
1575 rockchip,grf = <&grf>;
210bbd38 1576 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1577 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1578 dma-names = "tx", "rx";
1579 clock-names = "i2s_clk", "i2s_hclk";
1580 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1581 pinctrl-names = "default";
1582 pinctrl-0 = <&i2s0_8ch_bus>;
b0f2110a 1583 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1584 #sound-dai-cells = <0>;
f048b9a4
JX		 1585 status = "disabled";
1586 };
1587
1588 i2s1: i2s@ff890000 {
1589 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1590 reg = <0x0 0xff890000 0x0 0x1000>;
210bbd38 1591 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1592 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1593 dma-names = "tx", "rx";
1594 clock-names = "i2s_clk", "i2s_hclk";
1595 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1596 pinctrl-names = "default";
1597 pinctrl-0 = <&i2s1_2ch_bus>;
b0f2110a 1598 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1599 #sound-dai-cells = <0>;
f048b9a4
JX		 1600 status = "disabled";
1601 };
1602
1603 i2s2: i2s@ff8a0000 {
1604 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1605 reg = <0x0 0xff8a0000 0x0 0x1000>;
210bbd38 1606 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1607 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1608 dma-names = "tx", "rx";
1609 clock-names = "i2s_clk", "i2s_hclk";
1610 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
b0f2110a 1611 power-domains = <&power RK3399_PD_SDIOAUDIO>;
0d60d48c 1612 #sound-dai-cells = <0>;
f048b9a4
JX		 1613 status = "disabled";
1614 };
1615
fbd4cc0e
MY		 1616 vopl: vop@ff8f0000 {
1617 compatible = "rockchip,rk3399-vop-lit";
1618 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1619 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1620 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1621 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1622 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1623 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1624 iommus = <&vopl_mmu>;
1625 power-domains = <&power RK3399_PD_VOPL>;
1626 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1627 reset-names = "axi", "ahb", "dclk";
1628 status = "disabled";
1629
1630 vopl_out: port {
1631 #address-cells = <1>;
1632 #size-cells = <0>;
f7a29e30 1633
d3f51f49
JC		 1634 vopl_out_mipi: endpoint@0 {
1635 reg = <0>;
1636 remote-endpoint = <&mipi_in_vopl>;
1637 };
1638
f7a29e30
YY		 1639 vopl_out_edp: endpoint@1 {
1640 reg = <1>;
1641 remote-endpoint = <&edp_in_vopl>;
1642 };
1643
81e923dd
JC		 1644 vopl_out_hdmi: endpoint@2 {
1645 reg = <2>;
1646 remote-endpoint = <&hdmi_in_vopl>;
1647 };
1df5d2ab
NY		 1648
1649 vopl_out_mipi1: endpoint@3 {
1650 reg = <3>;
1651 remote-endpoint = <&mipi1_in_vopl>;
1652 };
2d3c2d56
CZ		 1653
1654 vopl_out_dp: endpoint@4 {
1655 reg = <4>;
1656 remote-endpoint = <&dp_in_vopl>;
1657 };
fbd4cc0e
MY		 1658 };
1659 };
1660
1661 vopl_mmu: iommu@ff8f3f00 {
1662 compatible = "rockchip,iommu";
1663 reg = <0x0 0xff8f3f00 0x0 0x100>;
1664 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
fbd4cc0e 1665 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
df3bcde7 1666 clock-names = "aclk", "iface";
fbd4cc0e
MY		 1667 power-domains = <&power RK3399_PD_VOPL>;
1668 #iommu-cells = <0>;
1669 status = "disabled";
1670 };
1671
1672 vopb: vop@ff900000 {
1673 compatible = "rockchip,rk3399-vop-big";
1674 reg = <0x0 0xff900000 0x0 0x3efc>;
1675 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1676 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1677 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1678 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1679 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1680 iommus = <&vopb_mmu>;
1681 power-domains = <&power RK3399_PD_VOPB>;
1682 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1683 reset-names = "axi", "ahb", "dclk";
1684 status = "disabled";
1685
1686 vopb_out: port {
1687 #address-cells = <1>;
1688 #size-cells = <0>;
f7a29e30
YY		 1689
1690 vopb_out_edp: endpoint@0 {
1691 reg = <0>;
1692 remote-endpoint = <&edp_in_vopb>;
1693 };
1694
d3f51f49
JC		 1695 vopb_out_mipi: endpoint@1 {
1696 reg = <1>;
1697 remote-endpoint = <&mipi_in_vopb>;
1698 };
1699
81e923dd
JC		 1700 vopb_out_hdmi: endpoint@2 {
1701 reg = <2>;
1702 remote-endpoint = <&hdmi_in_vopb>;
1703 };
1df5d2ab
NY		 1704
1705 vopb_out_mipi1: endpoint@3 {
1706 reg = <3>;
1707 remote-endpoint = <&mipi1_in_vopb>;
1708 };
2d3c2d56
CZ		 1709
1710 vopb_out_dp: endpoint@4 {
1711 reg = <4>;
1712 remote-endpoint = <&dp_in_vopb>;
1713 };
fbd4cc0e
MY		 1714 };
1715 };
1716
1717 vopb_mmu: iommu@ff903f00 {
1718 compatible = "rockchip,iommu";
1719 reg = <0x0 0xff903f00 0x0 0x100>;
1720 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
fbd4cc0e 1721 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
df3bcde7 1722 clock-names = "aclk", "iface";
fbd4cc0e
MY		 1723 power-domains = <&power RK3399_PD_VOPB>;
1724 #iommu-cells = <0>;
1725 status = "disabled";
1726 };
1727
97a0115c
SZ		 1728 isp0: isp0@ff910000 {
1729 compatible = "rockchip,rk3399-cif-isp";
1730 reg = <0x0 0xff910000 0x0 0x4000>;
1731 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1732 clocks = <&cru SCLK_ISP0>,
1733 <&cru ACLK_ISP0_WRAPPER>,
1734 <&cru HCLK_ISP0_WRAPPER>;
1735 clock-names = "isp", "aclk", "hclk";
1736 iommus = <&isp0_mmu>;
1737 phys = <&mipi_dphy_rx0>;
1738 phy-names = "dphy";
1739 power-domains = <&power RK3399_PD_ISP0>;
1740 status = "disabled";
1741
1742 ports {
1743 #address-cells = <1>;
1744 #size-cells = <0>;
1745
1746 port@0 {
1747 reg = <0>;
1748 #address-cells = <1>;
1749 #size-cells = <0>;
1750 };
1751 };
1752 };
1753
ae4fdcca
SX		 1754 isp0_mmu: iommu@ff914000 {
1755 compatible = "rockchip,iommu";
1756 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1757 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
c432a29d 1758 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
df3bcde7 1759 clock-names = "aclk", "iface";
ae4fdcca 1760 #iommu-cells = <0>;
c432a29d 1761 power-domains = <&power RK3399_PD_ISP0>;
ae4fdcca 1762 rockchip,disable-mmu-reset;
ae4fdcca
SX		 1763 };
1764
c349ae38
HS		 1765 isp1: isp1@ff920000 {
1766 compatible = "rockchip,rk3399-cif-isp";
1767 reg = <0x0 0xff920000 0x0 0x4000>;
1768 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1769 clocks = <&cru SCLK_ISP1>,
1770 <&cru ACLK_ISP1_WRAPPER>,
1771 <&cru HCLK_ISP1_WRAPPER>;
1772 clock-names = "isp", "aclk", "hclk";
1773 iommus = <&isp1_mmu>;
1774 phys = <&mipi_dsi1>;
1775 phy-names = "dphy";
1776 power-domains = <&power RK3399_PD_ISP1>;
1777 status = "disabled";
1778
1779 ports {
1780 #address-cells = <1>;
1781 #size-cells = <0>;
1782
1783 port@0 {
1784 reg = <0>;
1785 #address-cells = <1>;
1786 #size-cells = <0>;
1787 };
1788 };
1789 };
1790
ae4fdcca
SX		 1791 isp1_mmu: iommu@ff924000 {
1792 compatible = "rockchip,iommu";
1793 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1794 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
c432a29d 1795 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
df3bcde7 1796 clock-names = "aclk", "iface";
ae4fdcca 1797 #iommu-cells = <0>;
c432a29d 1798 power-domains = <&power RK3399_PD_ISP1>;
ae4fdcca 1799 rockchip,disable-mmu-reset;
ae4fdcca
SX		 1800 };
1801
0d60d48c
VB		 1802 hdmi_sound: hdmi-sound {
1803 compatible = "simple-audio-card";
1804 simple-audio-card,format = "i2s";
1805 simple-audio-card,mclk-fs = <256>;
1806 simple-audio-card,name = "hdmi-sound";
1807 status = "disabled";
1808
1809 simple-audio-card,cpu {
1810 sound-dai = <&i2s2>;
1811 };
1812 simple-audio-card,codec {
1813 sound-dai = <&hdmi>;
1814 };
1815 };
1816
81e923dd
JC		 1817 hdmi: hdmi@ff940000 {
1818 compatible = "rockchip,rk3399-dw-hdmi";
1819 reg = <0x0 0xff940000 0x0 0x20000>;
1820 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
db2fd26d
PHH		 1821 clocks = <&cru PCLK_HDMI_CTRL>,
1822 <&cru SCLK_HDMI_SFR>,
1823 <&cru PLL_VPLL>,
1824 <&cru PCLK_VIO_GRF>,
1825 <&cru SCLK_HDMI_CEC>;
1826 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
81e923dd
JC		 1827 power-domains = <&power RK3399_PD_HDCP>;
1828 reg-io-width = <4>;
1829 rockchip,grf = <&grf>;
0d60d48c 1830 #sound-dai-cells = <0>;
81e923dd
JC		 1831 status = "disabled";
1832
1833 ports {
1834 hdmi_in: port {
1835 #address-cells = <1>;
1836 #size-cells = <0>;
1837
1838 hdmi_in_vopb: endpoint@0 {
1839 reg = <0>;
1840 remote-endpoint = <&vopb_out_hdmi>;
1841 };
1842 hdmi_in_vopl: endpoint@1 {
1843 reg = <1>;
1844 remote-endpoint = <&vopl_out_hdmi>;
1845 };
1846 };
1847 };
1848 };
1849
d3f51f49
JC		 1850 mipi_dsi: mipi@ff960000 {
1851 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1852 reg = <0x0 0xff960000 0x0 0x8000>;
1853 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
bb4e6ff0 1854 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
0bc15d85
NY		 1855 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1856 clock-names = "ref", "pclk", "phy_cfg", "grf";
d3f51f49 1857 power-domains = <&power RK3399_PD_VIO>;
3813a10a
BN		 1858 resets = <&cru SRST_P_MIPI_DSI0>;
1859 reset-names = "apb";
d3f51f49 1860 rockchip,grf = <&grf>;
91e75bde
HS		 1861 #address-cells = <1>;
1862 #size-cells = <0>;
d3f51f49
JC		 1863 status = "disabled";
1864
1865 ports {
c856cb5d
NY		 1866 #address-cells = <1>;
1867 #size-cells = <0>;
1868
1869 mipi_in: port@0 {
1870 reg = <0>;
d3f51f49
JC		 1871 #address-cells = <1>;
1872 #size-cells = <0>;
1873
1874 mipi_in_vopb: endpoint@0 {
1875 reg = <0>;
1876 remote-endpoint = <&vopb_out_mipi>;
1877 };
1878 mipi_in_vopl: endpoint@1 {
1879 reg = <1>;
1880 remote-endpoint = <&vopl_out_mipi>;
1881 };
1882 };
1883 };
1884 };
1885
1df5d2ab
NY		 1886 mipi_dsi1: mipi@ff968000 {
1887 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1888 reg = <0x0 0xff968000 0x0 0x8000>;
1889 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1890 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1891 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1892 clock-names = "ref", "pclk", "phy_cfg", "grf";
1893 power-domains = <&power RK3399_PD_VIO>;
1894 resets = <&cru SRST_P_MIPI_DSI1>;
1895 reset-names = "apb";
1896 rockchip,grf = <&grf>;
91e75bde
HS		 1897 #address-cells = <1>;
1898 #size-cells = <0>;
8d47d12e 1899 #phy-cells = <0>;
1df5d2ab
NY		 1900 status = "disabled";
1901
1902 ports {
1903 #address-cells = <1>;
1904 #size-cells = <0>;
1905
1906 mipi1_in: port@0 {
1907 reg = <0>;
1908 #address-cells = <1>;
1909 #size-cells = <0>;
1910
1911 mipi1_in_vopb: endpoint@0 {
1912 reg = <0>;
1913 remote-endpoint = <&vopb_out_mipi1>;
1914 };
1915
1916 mipi1_in_vopl: endpoint@1 {
1917 reg = <1>;
1918 remote-endpoint = <&vopl_out_mipi1>;
1919 };
1920 };
1921 };
1922 };
1923
f7a29e30
YY		 1924 edp: edp@ff970000 {
1925 compatible = "rockchip,rk3399-edp";
1926 reg = <0x0 0xff970000 0x0 0x8000>;
1927 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
7b0390ea
YY		 1928 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1929 clock-names = "dp", "pclk", "grf";
f7a29e30
YY		 1930 pinctrl-names = "default";
1931 pinctrl-0 = <&edp_hpd>;
1932 power-domains = <&power RK3399_PD_EDP>;
1933 resets = <&cru SRST_P_EDP_CTRL>;
1934 reset-names = "dp";
1935 rockchip,grf = <&grf>;
1936 status = "disabled";
1937
1938 ports {
1939 #address-cells = <1>;
1940 #size-cells = <0>;
1941 edp_in: port@0 {
1942 reg = <0>;
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1945
1946 edp_in_vopb: endpoint@0 {
1947 reg = <0>;
1948 remote-endpoint = <&vopb_out_edp>;
1949 };
1950
1951 edp_in_vopl: endpoint@1 {
1952 reg = <1>;
1953 remote-endpoint = <&vopl_out_edp>;
1954 };
1955 };
1956 };
1957 };
1958
68d19331
CW		 1959 gpu: gpu@ff9a0000 {
1960 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1961 reg = <0x0 0xff9a0000 0x0 0x10000>;
c604fd81
JJ		 1962 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1963 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1964 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1965 interrupt-names = "job", "mmu", "gpu";
68d19331 1966 clocks = <&cru ACLK_GPU>;
36be9111 1967 #cooling-cells = <2>;
68d19331 1968 power-domains = <&power RK3399_PD_GPU>;
f048b9a4
JX		 1969 status = "disabled";
1970 };
1971
1972 pinctrl: pinctrl {
1973 compatible = "rockchip,rk3399-pinctrl";
1974 rockchip,grf = <&grf>;
1975 rockchip,pmu = <&pmugrf>;
1976 #address-cells = <2>;
1977 #size-cells = <2>;
1978 ranges;
1979
1980 gpio0: gpio0@ff720000 {
1981 compatible = "rockchip,gpio-bank";
1982 reg = <0x0 0xff720000 0x0 0x100>;
1983 clocks = <&pmucru PCLK_GPIO0_PMU>;
210bbd38 1984 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1985
1986 gpio-controller;
1987 #gpio-cells = <0x2>;
1988
1989 interrupt-controller;
1990 #interrupt-cells = <0x2>;
1991 };
1992
1993 gpio1: gpio1@ff730000 {
1994 compatible = "rockchip,gpio-bank";
1995 reg = <0x0 0xff730000 0x0 0x100>;
1996 clocks = <&pmucru PCLK_GPIO1_PMU>;
210bbd38 1997 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1998
1999 gpio-controller;
2000 #gpio-cells = <0x2>;
2001
2002 interrupt-controller;
2003 #interrupt-cells = <0x2>;
2004 };
2005
2006 gpio2: gpio2@ff780000 {
2007 compatible = "rockchip,gpio-bank";
2008 reg = <0x0 0xff780000 0x0 0x100>;
2009 clocks = <&cru PCLK_GPIO2>;
210bbd38 2010 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2011
2012 gpio-controller;
2013 #gpio-cells = <0x2>;
2014
2015 interrupt-controller;
2016 #interrupt-cells = <0x2>;
2017 };
2018
2019 gpio3: gpio3@ff788000 {
2020 compatible = "rockchip,gpio-bank";
2021 reg = <0x0 0xff788000 0x0 0x100>;
2022 clocks = <&cru PCLK_GPIO3>;
210bbd38 2023 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2024
2025 gpio-controller;
2026 #gpio-cells = <0x2>;
2027
2028 interrupt-controller;
2029 #interrupt-cells = <0x2>;
2030 };
2031
2032 gpio4: gpio4@ff790000 {
2033 compatible = "rockchip,gpio-bank";
2034 reg = <0x0 0xff790000 0x0 0x100>;
2035 clocks = <&cru PCLK_GPIO4>;
210bbd38 2036 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2037
2038 gpio-controller;
2039 #gpio-cells = <0x2>;
2040
2041 interrupt-controller;
2042 #interrupt-cells = <0x2>;
2043 };
2044
2045 pcfg_pull_up: pcfg-pull-up {
2046 bias-pull-up;
2047 };
2048
2049 pcfg_pull_down: pcfg-pull-down {
2050 bias-pull-down;
2051 };
2052
2053 pcfg_pull_none: pcfg-pull-none {
2054 bias-disable;
2055 };
2056
2057 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2058 bias-disable;
2059 drive-strength = <12>;
2060 };
2061
b4102328
RL		 2062 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2063 bias-disable;
2064 drive-strength = <13>;
2065 };
2066
2067 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2068 bias-disable;
2069 drive-strength = <18>;
2070 };
2071
2072 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2073 bias-disable;
2074 drive-strength = <20>;
2075 };
2076
2077 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2078 bias-pull-up;
2079 drive-strength = <2>;
2080 };
2081
f048b9a4
JX		 2082 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2083 bias-pull-up;
2084 drive-strength = <8>;
2085 };
2086
b4102328
RL		 2087 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2088 bias-pull-up;
2089 drive-strength = <18>;
2090 };
2091
2092 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2093 bias-pull-up;
2094 drive-strength = <20>;
2095 };
2096
f048b9a4
JX		 2097 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2098 bias-pull-down;
2099 drive-strength = <4>;
2100 };
2101
b4102328
RL		 2102 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2103 bias-pull-down;
2104 drive-strength = <8>;
f048b9a4
JX		 2105 };
2106
2107 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2108 bias-pull-down;
2109 drive-strength = <12>;
2110 };
2111
b4102328
RL		 2112 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2113 bias-pull-down;
2114 drive-strength = <18>;
2115 };
2116
2117 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2118 bias-pull-down;
2119 drive-strength = <20>;
2120 };
2121
2122 pcfg_output_high: pcfg-output-high {
2123 output-high;
2124 };
2125
2126 pcfg_output_low: pcfg-output-low {
2127 output-low;
f048b9a4
JX		 2128 };
2129
a8bcaea7
DA		 2130 clock {
2131 clk_32k: clk-32k {
d64420e8 2132 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
a8bcaea7
DA		 2133 };
2134 };
2135
f1400702
HS		 2136 cif {
2137 cif_clkin: cif-clkin {
2138 rockchip,pins =
2139 <2 RK_PB2 3 &pcfg_pull_none>;
2140 };
2141
2142 cif_clkouta: cif-clkouta {
2143 rockchip,pins =
2144 <2 RK_PB3 3 &pcfg_pull_none>;
2145 };
2146 };
2147
8742466a
BN		 2148 edp {
2149 edp_hpd: edp-hpd {
2150 rockchip,pins =
d64420e8 2151 <4 RK_PC7 2 &pcfg_pull_none>;
8742466a
BN		 2152 };
2153 };
2154
eb3a6a6a
RC		 2155 gmac {
2156 rgmii_pins: rgmii-pins {
2157 rockchip,pins =
2158 /* mac_txclk */
d64420e8 2159 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2160 /* mac_rxclk */
d64420e8 2161 <3 RK_PB6 1 &pcfg_pull_none>,
eb3a6a6a 2162 /* mac_mdio */
d64420e8 2163 <3 RK_PB5 1 &pcfg_pull_none>,
eb3a6a6a 2164 /* mac_txen */
d64420e8 2165 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2166 /* mac_clk */
d64420e8 2167 <3 RK_PB3 1 &pcfg_pull_none>,
eb3a6a6a 2168 /* mac_rxdv */
d64420e8 2169 <3 RK_PB1 1 &pcfg_pull_none>,
eb3a6a6a 2170 /* mac_mdc */
d64420e8 2171 <3 RK_PB0 1 &pcfg_pull_none>,
eb3a6a6a 2172 /* mac_rxd1 */
d64420e8 2173 <3 RK_PA7 1 &pcfg_pull_none>,
eb3a6a6a 2174 /* mac_rxd0 */
d64420e8 2175 <3 RK_PA6 1 &pcfg_pull_none>,
eb3a6a6a 2176 /* mac_txd1 */
d64420e8 2177 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2178 /* mac_txd0 */
d64420e8 2179 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2180 /* mac_rxd3 */
d64420e8 2181 <3 RK_PA3 1 &pcfg_pull_none>,
eb3a6a6a 2182 /* mac_rxd2 */
d64420e8 2183 <3 RK_PA2 1 &pcfg_pull_none>,
eb3a6a6a 2184 /* mac_txd3 */
d64420e8 2185 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2186 /* mac_txd2 */
d64420e8 2187 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
eb3a6a6a
RC		 2188 };
2189
2190 rmii_pins: rmii-pins {
2191 rockchip,pins =
2192 /* mac_mdio */
d64420e8 2193 <3 RK_PB5 1 &pcfg_pull_none>,
eb3a6a6a 2194 /* mac_txen */
d64420e8 2195 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2196 /* mac_clk */
d64420e8 2197 <3 RK_PB3 1 &pcfg_pull_none>,
eb3a6a6a 2198 /* mac_rxer */
d64420e8 2199 <3 RK_PB2 1 &pcfg_pull_none>,
eb3a6a6a 2200 /* mac_rxdv */
d64420e8 2201 <3 RK_PB1 1 &pcfg_pull_none>,
eb3a6a6a 2202 /* mac_mdc */
d64420e8 2203 <3 RK_PB0 1 &pcfg_pull_none>,
eb3a6a6a 2204 /* mac_rxd1 */
d64420e8 2205 <3 RK_PA7 1 &pcfg_pull_none>,
eb3a6a6a 2206 /* mac_rxd0 */
d64420e8 2207 <3 RK_PA6 1 &pcfg_pull_none>,
eb3a6a6a 2208 /* mac_txd1 */
d64420e8 2209 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2210 /* mac_txd0 */
d64420e8 2211 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
eb3a6a6a
RC		 2212 };
2213 };
2214
f048b9a4
JX		 2215 i2c0 {
2216 i2c0_xfer: i2c0-xfer {
2217 rockchip,pins =
d64420e8
HS		 2218 <1 RK_PB7 2 &pcfg_pull_none>,
2219 <1 RK_PC0 2 &pcfg_pull_none>;
f048b9a4
JX		 2220 };
2221 };
2222
2223 i2c1 {
2224 i2c1_xfer: i2c1-xfer {
2225 rockchip,pins =
d64420e8
HS		 2226 <4 RK_PA2 1 &pcfg_pull_none>,
2227 <4 RK_PA1 1 &pcfg_pull_none>;
f048b9a4
JX		 2228 };
2229 };
2230
2231 i2c2 {
2232 i2c2_xfer: i2c2-xfer {
2233 rockchip,pins =
d64420e8
HS		 2234 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2235 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
f048b9a4
JX		 2236 };
2237 };
2238
2239 i2c3 {
2240 i2c3_xfer: i2c3-xfer {
2241 rockchip,pins =
d64420e8
HS		 2242 <4 RK_PC1 1 &pcfg_pull_none>,
2243 <4 RK_PC0 1 &pcfg_pull_none>;
f048b9a4
JX		 2244 };
2245 };
2246
2247 i2c4 {
2248 i2c4_xfer: i2c4-xfer {
2249 rockchip,pins =
d64420e8
HS		 2250 <1 RK_PB4 1 &pcfg_pull_none>,
2251 <1 RK_PB3 1 &pcfg_pull_none>;
f048b9a4
JX		 2252 };
2253 };
2254
2255 i2c5 {
2256 i2c5_xfer: i2c5-xfer {
2257 rockchip,pins =
d64420e8
HS		 2258 <3 RK_PB3 2 &pcfg_pull_none>,
2259 <3 RK_PB2 2 &pcfg_pull_none>;
f048b9a4
JX		 2260 };
2261 };
2262
2263 i2c6 {
2264 i2c6_xfer: i2c6-xfer {
2265 rockchip,pins =
d64420e8
HS		 2266 <2 RK_PB2 2 &pcfg_pull_none>,
2267 <2 RK_PB1 2 &pcfg_pull_none>;
f048b9a4
JX		 2268 };
2269 };
2270
2271 i2c7 {
2272 i2c7_xfer: i2c7-xfer {
2273 rockchip,pins =
d64420e8
HS		 2274 <2 RK_PB0 2 &pcfg_pull_none>,
2275 <2 RK_PA7 2 &pcfg_pull_none>;
f048b9a4
JX		 2276 };
2277 };
2278
2279 i2c8 {
2280 i2c8_xfer: i2c8-xfer {
2281 rockchip,pins =
d64420e8
HS		 2282 <1 RK_PC5 1 &pcfg_pull_none>,
2283 <1 RK_PC4 1 &pcfg_pull_none>;
f048b9a4
JX		 2284 };
2285 };
2286
2287 i2s0 {
0efaf807
KG		 2288 i2s0_2ch_bus: i2s0-2ch-bus {
2289 rockchip,pins =
d64420e8
HS		 2290 <3 RK_PD0 1 &pcfg_pull_none>,
2291 <3 RK_PD1 1 &pcfg_pull_none>,
2292 <3 RK_PD2 1 &pcfg_pull_none>,
2293 <3 RK_PD3 1 &pcfg_pull_none>,
2294 <3 RK_PD7 1 &pcfg_pull_none>,
2295 <4 RK_PA0 1 &pcfg_pull_none>;
0efaf807
KG		 2296 };
2297
f048b9a4
JX		 2298 i2s0_8ch_bus: i2s0-8ch-bus {
2299 rockchip,pins =
d64420e8
HS		 2300 <3 RK_PD0 1 &pcfg_pull_none>,
2301 <3 RK_PD1 1 &pcfg_pull_none>,
2302 <3 RK_PD2 1 &pcfg_pull_none>,
2303 <3 RK_PD3 1 &pcfg_pull_none>,
2304 <3 RK_PD4 1 &pcfg_pull_none>,
2305 <3 RK_PD5 1 &pcfg_pull_none>,
2306 <3 RK_PD6 1 &pcfg_pull_none>,
2307 <3 RK_PD7 1 &pcfg_pull_none>,
2308 <4 RK_PA0 1 &pcfg_pull_none>;
f048b9a4
JX		 2309 };
2310 };
2311
2312 i2s1 {
2313 i2s1_2ch_bus: i2s1-2ch-bus {
2314 rockchip,pins =
d64420e8
HS		 2315 <4 RK_PA3 1 &pcfg_pull_none>,
2316 <4 RK_PA4 1 &pcfg_pull_none>,
2317 <4 RK_PA5 1 &pcfg_pull_none>,
2318 <4 RK_PA6 1 &pcfg_pull_none>,
2319 <4 RK_PA7 1 &pcfg_pull_none>;
f048b9a4
JX		 2320 };
2321 };
2322
b74a2e98
KY		 2323 sdio0 {
2324 sdio0_bus1: sdio0-bus1 {
2325 rockchip,pins =
d64420e8 2326 <2 RK_PC4 1 &pcfg_pull_up>;
b74a2e98
KY		 2327 };
2328
2329 sdio0_bus4: sdio0-bus4 {
2330 rockchip,pins =
d64420e8
HS		 2331 <2 RK_PC4 1 &pcfg_pull_up>,
2332 <2 RK_PC5 1 &pcfg_pull_up>,
2333 <2 RK_PC6 1 &pcfg_pull_up>,
2334 <2 RK_PC7 1 &pcfg_pull_up>;
b74a2e98
KY		 2335 };
2336
2337 sdio0_cmd: sdio0-cmd {
2338 rockchip,pins =
d64420e8 2339 <2 RK_PD0 1 &pcfg_pull_up>;
b74a2e98
KY		 2340 };
2341
2342 sdio0_clk: sdio0-clk {
2343 rockchip,pins =
d64420e8 2344 <2 RK_PD1 1 &pcfg_pull_none>;
b74a2e98
KY		 2345 };
2346
2347 sdio0_cd: sdio0-cd {
2348 rockchip,pins =
d64420e8 2349 <2 RK_PD2 1 &pcfg_pull_up>;
b74a2e98
KY		 2350 };
2351
2352 sdio0_pwr: sdio0-pwr {
2353 rockchip,pins =
d64420e8 2354 <2 RK_PD3 1 &pcfg_pull_up>;
b74a2e98
KY		 2355 };
2356
2357 sdio0_bkpwr: sdio0-bkpwr {
2358 rockchip,pins =
d64420e8 2359 <2 RK_PD4 1 &pcfg_pull_up>;
b74a2e98
KY		 2360 };
2361
2362 sdio0_wp: sdio0-wp {
2363 rockchip,pins =
d64420e8 2364 <0 RK_PA3 1 &pcfg_pull_up>;
b74a2e98
KY		 2365 };
2366
2367 sdio0_int: sdio0-int {
2368 rockchip,pins =
d64420e8 2369 <0 RK_PA4 1 &pcfg_pull_up>;
b74a2e98
KY		 2370 };
2371 };
2372
2373 sdmmc {
2374 sdmmc_bus1: sdmmc-bus1 {
2375 rockchip,pins =
d64420e8 2376 <4 RK_PB0 1 &pcfg_pull_up>;
b74a2e98
KY		 2377 };
2378
2379 sdmmc_bus4: sdmmc-bus4 {
2380 rockchip,pins =
d64420e8
HS		 2381 <4 RK_PB0 1 &pcfg_pull_up>,
2382 <4 RK_PB1 1 &pcfg_pull_up>,
2383 <4 RK_PB2 1 &pcfg_pull_up>,
2384 <4 RK_PB3 1 &pcfg_pull_up>;
b74a2e98
KY		 2385 };
2386
2387 sdmmc_clk: sdmmc-clk {
2388 rockchip,pins =
d64420e8 2389 <4 RK_PB4 1 &pcfg_pull_none>;
b74a2e98
KY		 2390 };
2391
2392 sdmmc_cmd: sdmmc-cmd {
2393 rockchip,pins =
d64420e8 2394 <4 RK_PB5 1 &pcfg_pull_up>;
b74a2e98
KY		 2395 };
2396
6122308e 2397 sdmmc_cd: sdmmc-cd {
b74a2e98 2398 rockchip,pins =
d64420e8 2399 <0 RK_PA7 1 &pcfg_pull_up>;
b74a2e98
KY		 2400 };
2401
2402 sdmmc_wp: sdmmc-wp {
2403 rockchip,pins =
d64420e8 2404 <0 RK_PB0 1 &pcfg_pull_up>;
b74a2e98
KY		 2405 };
2406 };
2407
a7ecfad4 2408 suspend {
5d26ad9c 2409 ap_pwroff: ap-pwroff {
d64420e8 2410 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
5d26ad9c
DA		 2411 };
2412
2413 ddrio_pwroff: ddrio-pwroff {
d64420e8 2414 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
5d26ad9c
DA		 2415 };
2416 };
2417
f048b9a4
JX		 2418 spdif {
2419 spdif_bus: spdif-bus {
2420 rockchip,pins =
d64420e8 2421 <4 RK_PC5 1 &pcfg_pull_none>;
f048b9a4 2422 };
b74a2e98
KY		 2423
2424 spdif_bus_1: spdif-bus-1 {
2425 rockchip,pins =
d64420e8 2426 <3 RK_PC0 3 &pcfg_pull_none>;
b74a2e98 2427 };
f048b9a4
JX		 2428 };
2429
2430 spi0 {
2431 spi0_clk: spi0-clk {
2432 rockchip,pins =
d64420e8 2433 <3 RK_PA6 2 &pcfg_pull_up>;
f048b9a4
JX		 2434 };
2435 spi0_cs0: spi0-cs0 {
2436 rockchip,pins =
d64420e8 2437 <3 RK_PA7 2 &pcfg_pull_up>;
f048b9a4
JX		 2438 };
2439 spi0_cs1: spi0-cs1 {
2440 rockchip,pins =
d64420e8 2441 <3 RK_PB0 2 &pcfg_pull_up>;
f048b9a4
JX		 2442 };
2443 spi0_tx: spi0-tx {
2444 rockchip,pins =
d64420e8 2445 <3 RK_PA5 2 &pcfg_pull_up>;
f048b9a4
JX		 2446 };
2447 spi0_rx: spi0-rx {
2448 rockchip,pins =
d64420e8 2449 <3 RK_PA4 2 &pcfg_pull_up>;
f048b9a4
JX		 2450 };
2451 };
2452
2453 spi1 {
2454 spi1_clk: spi1-clk {
2455 rockchip,pins =
d64420e8 2456 <1 RK_PB1 2 &pcfg_pull_up>;
f048b9a4
JX		 2457 };
2458 spi1_cs0: spi1-cs0 {
2459 rockchip,pins =
d64420e8 2460 <1 RK_PB2 2 &pcfg_pull_up>;
f048b9a4
JX		 2461 };
2462 spi1_rx: spi1-rx {
2463 rockchip,pins =
d64420e8 2464 <1 RK_PA7 2 &pcfg_pull_up>;
f048b9a4
JX		 2465 };
2466 spi1_tx: spi1-tx {
2467 rockchip,pins =
d64420e8 2468 <1 RK_PB0 2 &pcfg_pull_up>;
f048b9a4
JX		 2469 };
2470 };
2471
2472 spi2 {
2473 spi2_clk: spi2-clk {
2474 rockchip,pins =
d64420e8 2475 <2 RK_PB3 1 &pcfg_pull_up>;
f048b9a4
JX		 2476 };
2477 spi2_cs0: spi2-cs0 {
2478 rockchip,pins =
d64420e8 2479 <2 RK_PB4 1 &pcfg_pull_up>;
f048b9a4
JX		 2480 };
2481 spi2_rx: spi2-rx {
2482 rockchip,pins =
d64420e8 2483 <2 RK_PB1 1 &pcfg_pull_up>;
f048b9a4
JX		 2484 };
2485 spi2_tx: spi2-tx {
2486 rockchip,pins =
d64420e8 2487 <2 RK_PB2 1 &pcfg_pull_up>;
f048b9a4
JX		 2488 };
2489 };
2490
2491 spi3 {
2492 spi3_clk: spi3-clk {
2493 rockchip,pins =
d64420e8 2494 <1 RK_PC1 1 &pcfg_pull_up>;
f048b9a4
JX		 2495 };
2496 spi3_cs0: spi3-cs0 {
2497 rockchip,pins =
d64420e8 2498 <1 RK_PC2 1 &pcfg_pull_up>;
f048b9a4
JX		 2499 };
2500 spi3_rx: spi3-rx {
2501 rockchip,pins =
d64420e8 2502 <1 RK_PB7 1 &pcfg_pull_up>;
f048b9a4
JX		 2503 };
2504 spi3_tx: spi3-tx {
2505 rockchip,pins =
d64420e8 2506 <1 RK_PC0 1 &pcfg_pull_up>;
f048b9a4
JX		 2507 };
2508 };
2509
2510 spi4 {
2511 spi4_clk: spi4-clk {
2512 rockchip,pins =
d64420e8 2513 <3 RK_PA2 2 &pcfg_pull_up>;
f048b9a4
JX		 2514 };
2515 spi4_cs0: spi4-cs0 {
2516 rockchip,pins =
d64420e8 2517 <3 RK_PA3 2 &pcfg_pull_up>;
f048b9a4
JX		 2518 };
2519 spi4_rx: spi4-rx {
2520 rockchip,pins =
d64420e8 2521 <3 RK_PA0 2 &pcfg_pull_up>;
f048b9a4
JX		 2522 };
2523 spi4_tx: spi4-tx {
2524 rockchip,pins =
d64420e8 2525 <3 RK_PA1 2 &pcfg_pull_up>;
f048b9a4
JX		 2526 };
2527 };
2528
2529 spi5 {
2530 spi5_clk: spi5-clk {
2531 rockchip,pins =
d64420e8 2532 <2 RK_PC6 2 &pcfg_pull_up>;
f048b9a4
JX		 2533 };
2534 spi5_cs0: spi5-cs0 {
2535 rockchip,pins =
d64420e8 2536 <2 RK_PC7 2 &pcfg_pull_up>;
f048b9a4
JX		 2537 };
2538 spi5_rx: spi5-rx {
2539 rockchip,pins =
d64420e8 2540 <2 RK_PC4 2 &pcfg_pull_up>;
f048b9a4
JX		 2541 };
2542 spi5_tx: spi5-tx {
2543 rockchip,pins =
d64420e8 2544 <2 RK_PC5 2 &pcfg_pull_up>;
f048b9a4
JX		 2545 };
2546 };
2547
ba2b043e
SZ		 2548 testclk {
2549 test_clkout0: test-clkout0 {
2550 rockchip,pins =
d64420e8 2551 <0 RK_PA0 1 &pcfg_pull_none>;
ba2b043e
SZ		 2552 };
2553
2554 test_clkout1: test-clkout1 {
2555 rockchip,pins =
d64420e8 2556 <2 RK_PD1 2 &pcfg_pull_none>;
ba2b043e
SZ		 2557 };
2558
2559 test_clkout2: test-clkout2 {
2560 rockchip,pins =
d64420e8 2561 <0 RK_PB0 3 &pcfg_pull_none>;
ba2b043e
SZ		 2562 };
2563 };
2564
95c27ba7 2565 tsadc {
2bc65fef 2566 otp_pin: otp-pin {
d64420e8 2567 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
95c27ba7
CW		 2568 };
2569
2570 otp_out: otp-out {
d64420e8 2571 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
95c27ba7
CW		 2572 };
2573 };
2574
f048b9a4
JX		 2575 uart0 {
2576 uart0_xfer: uart0-xfer {
2577 rockchip,pins =
d64420e8
HS		 2578 <2 RK_PC0 1 &pcfg_pull_up>,
2579 <2 RK_PC1 1 &pcfg_pull_none>;
f048b9a4
JX		 2580 };
2581
2582 uart0_cts: uart0-cts {
2583 rockchip,pins =
d64420e8 2584 <2 RK_PC2 1 &pcfg_pull_none>;
f048b9a4
JX		 2585 };
2586
2587 uart0_rts: uart0-rts {
2588 rockchip,pins =
d64420e8 2589 <2 RK_PC3 1 &pcfg_pull_none>;
f048b9a4
JX		 2590 };
2591 };
2592
2593 uart1 {
2594 uart1_xfer: uart1-xfer {
2595 rockchip,pins =
d64420e8
HS		 2596 <3 RK_PB4 2 &pcfg_pull_up>,
2597 <3 RK_PB5 2 &pcfg_pull_none>;
f048b9a4
JX		 2598 };
2599 };
2600
2601 uart2a {
2602 uart2a_xfer: uart2a-xfer {
2603 rockchip,pins =
d64420e8
HS		 2604 <4 RK_PB0 2 &pcfg_pull_up>,
2605 <4 RK_PB1 2 &pcfg_pull_none>;
f048b9a4
JX		 2606 };
2607 };
2608
2609 uart2b {
2610 uart2b_xfer: uart2b-xfer {
2611 rockchip,pins =
d64420e8
HS		 2612 <4 RK_PC0 2 &pcfg_pull_up>,
2613 <4 RK_PC1 2 &pcfg_pull_none>;
f048b9a4
JX		 2614 };
2615 };
2616
2617 uart2c {
2618 uart2c_xfer: uart2c-xfer {
2619 rockchip,pins =
d64420e8
HS		 2620 <4 RK_PC3 1 &pcfg_pull_up>,
2621 <4 RK_PC4 1 &pcfg_pull_none>;
f048b9a4
JX		 2622 };
2623 };
2624
2625 uart3 {
2626 uart3_xfer: uart3-xfer {
2627 rockchip,pins =
d64420e8
HS		 2628 <3 RK_PB6 2 &pcfg_pull_up>,
2629 <3 RK_PB7 2 &pcfg_pull_none>;
f048b9a4
JX		 2630 };
2631
2632 uart3_cts: uart3-cts {
2633 rockchip,pins =
40a0dd42 2634 <3 RK_PC0 2 &pcfg_pull_none>;
f048b9a4
JX		 2635 };
2636
2637 uart3_rts: uart3-rts {
2638 rockchip,pins =
40a0dd42 2639 <3 RK_PC1 2 &pcfg_pull_none>;
f048b9a4
JX		 2640 };
2641 };
2642
2643 uart4 {
2644 uart4_xfer: uart4-xfer {
2645 rockchip,pins =
d64420e8
HS		 2646 <1 RK_PA7 1 &pcfg_pull_up>,
2647 <1 RK_PB0 1 &pcfg_pull_none>;
f048b9a4
JX		 2648 };
2649 };
2650
2651 uarthdcp {
2652 uarthdcp_xfer: uarthdcp-xfer {
2653 rockchip,pins =
d64420e8
HS		 2654 <4 RK_PC5 2 &pcfg_pull_up>,
2655 <4 RK_PC6 2 &pcfg_pull_none>;
f048b9a4
JX		 2656 };
2657 };
2658
2659 pwm0 {
2660 pwm0_pin: pwm0-pin {
2661 rockchip,pins =
d64420e8 2662 <4 RK_PC2 1 &pcfg_pull_none>;
b4102328
RL		 2663 };
2664
2665 pwm0_pin_pull_down: pwm0-pin-pull-down {
2666 rockchip,pins =
d64420e8 2667 <4 RK_PC2 1 &pcfg_pull_down>;
f048b9a4
JX		 2668 };
2669
2670 vop0_pwm_pin: vop0-pwm-pin {
2671 rockchip,pins =
d64420e8 2672 <4 RK_PC2 2 &pcfg_pull_none>;
b4102328
RL		 2673 };
2674
2675 vop1_pwm_pin: vop1-pwm-pin {
2676 rockchip,pins =
d64420e8 2677 <4 RK_PC2 3 &pcfg_pull_none>;
f048b9a4
JX		 2678 };
2679 };
2680
2681 pwm1 {
2682 pwm1_pin: pwm1-pin {
2683 rockchip,pins =
d64420e8 2684 <4 RK_PC6 1 &pcfg_pull_none>;
f048b9a4
JX		 2685 };
2686
b4102328 2687 pwm1_pin_pull_down: pwm1-pin-pull-down {
f048b9a4 2688 rockchip,pins =
d64420e8 2689 <4 RK_PC6 1 &pcfg_pull_down>;
f048b9a4
JX		 2690 };
2691 };
2692
2693 pwm2 {
2694 pwm2_pin: pwm2-pin {
2695 rockchip,pins =
d64420e8 2696 <1 RK_PC3 1 &pcfg_pull_none>;
b4102328
RL		 2697 };
2698
2699 pwm2_pin_pull_down: pwm2-pin-pull-down {
2700 rockchip,pins =
d64420e8 2701 <1 RK_PC3 1 &pcfg_pull_down>;
f048b9a4
JX		 2702 };
2703 };
2704
2705 pwm3a {
2706 pwm3a_pin: pwm3a-pin {
2707 rockchip,pins =
d64420e8 2708 <0 RK_PA6 1 &pcfg_pull_none>;
f048b9a4
JX		 2709 };
2710 };
2711
2712 pwm3b {
2713 pwm3b_pin: pwm3b-pin {
2714 rockchip,pins =
d64420e8 2715 <1 RK_PB6 1 &pcfg_pull_none>;
f048b9a4
JX		 2716 };
2717 };
85aaa574 2718
b74a2e98
KY		 2719 hdmi {
2720 hdmi_i2c_xfer: hdmi-i2c-xfer {
2721 rockchip,pins =
d64420e8
HS		 2722 <4 RK_PC1 3 &pcfg_pull_none>,
2723 <4 RK_PC0 3 &pcfg_pull_none>;
b74a2e98
KY		 2724 };
2725
2726 hdmi_cec: hdmi-cec {
2727 rockchip,pins =
d64420e8 2728 <4 RK_PC7 1 &pcfg_pull_none>;
b74a2e98
KY		 2729 };
2730 };
2731
85aaa574 2732 pcie {
b74a2e98
KY		 2733 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2734 rockchip,pins =
2735 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2736 };
2737
2738 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2739 rockchip,pins =
2740 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2741 };
85aaa574
SL		 2742 };
2743
f048b9a4
JX		 2744 };
2745};
Linux 6.x block layer and io_uring tree(s)