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arm64: dts: rockchip: rename thermal subnodes for rk3368
[linux-block.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
CommitLineData
4ee99ceb 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
f048b9a4
JX		 2/*
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
f048b9a4
JX		 4 */
5
6#include <dt-bindings/clock/rk3399-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
807a2371 11#include <dt-bindings/power/rk3399-power.h>
95c27ba7 12#include <dt-bindings/thermal/thermal.h>
f048b9a4
JX		 13
14/ {
15 compatible = "rockchip,rk3399";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
2eca8411 22 ethernet0 = &gmac;
69e5a8fe
DW		 23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
0011c6d1
MR		 32 mmc0 = &sdio0;
33 mmc1 = &sdmmc;
34 mmc2 = &sdhci;
f048b9a4
JX		 35 serial0 = &uart0;
36 serial1 = &uart1;
37 serial2 = &uart2;
38 serial3 = &uart3;
39 serial4 = &uart4;
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 cpu-map {
47 cluster0 {
48 core0 {
49 cpu = <&cpu_l0>;
50 };
51 core1 {
52 cpu = <&cpu_l1>;
53 };
54 core2 {
55 cpu = <&cpu_l2>;
56 };
57 core3 {
58 cpu = <&cpu_l3>;
59 };
60 };
61
62 cluster1 {
63 core0 {
64 cpu = <&cpu_b0>;
65 };
66 core1 {
67 cpu = <&cpu_b1>;
68 };
69 };
70 };
71
72 cpu_l0: cpu@0 {
73 device_type = "cpu";
31af04cd 74 compatible = "arm,cortex-a53";
f048b9a4
JX		 75 reg = <0x0 0x0>;
76 enable-method = "psci";
97df3aa7 77 capacity-dmips-mhz = <485>;
f048b9a4 78 clocks = <&cru ARMCLKL>;
cc9b0918 79 #cooling-cells = <2>; /* min followed by max */
f4697bd7 80 dynamic-power-coefficient = <100>;
f888da16 81 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 82 };
83
84 cpu_l1: cpu@1 {
85 device_type = "cpu";
31af04cd 86 compatible = "arm,cortex-a53";
f048b9a4
JX		 87 reg = <0x0 0x1>;
88 enable-method = "psci";
97df3aa7 89 capacity-dmips-mhz = <485>;
f048b9a4 90 clocks = <&cru ARMCLKL>;
cc9b0918 91 #cooling-cells = <2>; /* min followed by max */
f4697bd7 92 dynamic-power-coefficient = <100>;
f888da16 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 94 };
95
96 cpu_l2: cpu@2 {
97 device_type = "cpu";
31af04cd 98 compatible = "arm,cortex-a53";
f048b9a4
JX		 99 reg = <0x0 0x2>;
100 enable-method = "psci";
97df3aa7 101 capacity-dmips-mhz = <485>;
f048b9a4 102 clocks = <&cru ARMCLKL>;
cc9b0918 103 #cooling-cells = <2>; /* min followed by max */
f4697bd7 104 dynamic-power-coefficient = <100>;
f888da16 105 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 106 };
107
108 cpu_l3: cpu@3 {
109 device_type = "cpu";
31af04cd 110 compatible = "arm,cortex-a53";
f048b9a4
JX		 111 reg = <0x0 0x3>;
112 enable-method = "psci";
97df3aa7 113 capacity-dmips-mhz = <485>;
f048b9a4 114 clocks = <&cru ARMCLKL>;
cc9b0918 115 #cooling-cells = <2>; /* min followed by max */
f4697bd7 116 dynamic-power-coefficient = <100>;
f888da16 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 118 };
119
120 cpu_b0: cpu@100 {
121 device_type = "cpu";
31af04cd 122 compatible = "arm,cortex-a72";
f048b9a4
JX		 123 reg = <0x0 0x100>;
124 enable-method = "psci";
97df3aa7 125 capacity-dmips-mhz = <1024>;
f048b9a4 126 clocks = <&cru ARMCLKB>;
cc9b0918 127 #cooling-cells = <2>; /* min followed by max */
45a995c0 128 dynamic-power-coefficient = <436>;
f888da16 129 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 130 };
131
132 cpu_b1: cpu@101 {
133 device_type = "cpu";
31af04cd 134 compatible = "arm,cortex-a72";
f048b9a4
JX		 135 reg = <0x0 0x101>;
136 enable-method = "psci";
97df3aa7 137 capacity-dmips-mhz = <1024>;
f048b9a4 138 clocks = <&cru ARMCLKB>;
cc9b0918 139 #cooling-cells = <2>; /* min followed by max */
45a995c0 140 dynamic-power-coefficient = <436>;
f888da16
TX		 141 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
142 };
143
144 idle-states {
145 entry-method = "psci";
146
147 CPU_SLEEP: cpu-sleep {
148 compatible = "arm,idle-state";
149 local-timer-stop;
150 arm,psci-suspend-param = <0x0010000>;
151 entry-latency-us = <120>;
152 exit-latency-us = <250>;
153 min-residency-us = <900>;
154 };
155
156 CLUSTER_SLEEP: cluster-sleep {
157 compatible = "arm,idle-state";
158 local-timer-stop;
159 arm,psci-suspend-param = <0x1010000>;
160 entry-latency-us = <400>;
161 exit-latency-us = <500>;
162 min-residency-us = <2000>;
163 };
f048b9a4
JX		 164 };
165 };
166
fbd4cc0e
MY		 167 display-subsystem {
168 compatible = "rockchip,display-subsystem";
169 ports = <&vopl_out>, <&vopb_out>;
170 };
171
6840eb0d
CW		 172 pmu_a53 {
173 compatible = "arm,cortex-a53-pmu";
174 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
175 };
176
177 pmu_a72 {
178 compatible = "arm,cortex-a72-pmu";
179 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
180 };
181
f048b9a4
JX		 182 psci {
183 compatible = "arm,psci-1.0";
184 method = "smc";
185 };
186
187 timer {
188 compatible = "arm,armv8-timer";
210bbd38
CW		 189 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
190 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
191 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
192 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
e6186820 193 arm,no-tick-in-suspend;
f048b9a4
JX		 194 };
195
196 xin24m: xin24m {
197 compatible = "fixed-clock";
198 clock-frequency = <24000000>;
199 clock-output-names = "xin24m";
200 #clock-cells = <0>;
201 };
202
b2411bef 203 amba: bus {
15b7cc78 204 compatible = "simple-bus";
f048b9a4
JX		 205 #address-cells = <2>;
206 #size-cells = <2>;
207 ranges;
208
209 dmac_bus: dma-controller@ff6d0000 {
210 compatible = "arm,pl330", "arm,primecell";
211 reg = <0x0 0xff6d0000 0x0 0x4000>;
210bbd38
CW		 212 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
213 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4 214 #dma-cells = <1>;
505af918 215 arm,pl330-periph-burst;
f048b9a4
JX		 216 clocks = <&cru ACLK_DMAC0_PERILP>;
217 clock-names = "apb_pclk";
218 };
219
220 dmac_peri: dma-controller@ff6e0000 {
221 compatible = "arm,pl330", "arm,primecell";
222 reg = <0x0 0xff6e0000 0x0 0x4000>;
210bbd38
CW		 223 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
224 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4 225 #dma-cells = <1>;
505af918 226 arm,pl330-periph-burst;
f048b9a4
JX		 227 clocks = <&cru ACLK_DMAC1_PERILP>;
228 clock-names = "apb_pclk";
229 };
230 };
231
66aef3cb
BN		 232 pcie0: pcie@f8000000 {
233 compatible = "rockchip,rk3399-pcie";
234 reg = <0x0 0xf8000000 0x0 0x2000000>,
235 <0x0 0xfd000000 0x0 0x1000000>;
236 reg-names = "axi-base", "apb-base";
237 #address-cells = <3>;
238 #size-cells = <2>;
239 #interrupt-cells = <1>;
240 aspm-no-l0s;
d633becc 241 bus-range = <0x0 0x1f>;
66aef3cb
BN		 242 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
243 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
244 clock-names = "aclk", "aclk-perf",
245 "hclk", "pm";
246 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
247 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
248 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
249 interrupt-names = "sys", "legacy", "client";
250 interrupt-map-mask = <0 0 0 7>;
251 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
252 <0 0 0 2 &pcie0_intc 1>,
253 <0 0 0 3 &pcie0_intc 2>,
254 <0 0 0 4 &pcie0_intc 3>;
41b464ef 255 linux,pci-domain = <0>;
66aef3cb
BN		 256 max-link-speed = <1>;
257 msi-map = <0x0 &its 0x0 0x1000>;
e9a60cac
SL		 258 phys = <&pcie_phy 0>, <&pcie_phy 1>,
259 <&pcie_phy 2>, <&pcie_phy 3>;
260 phy-names = "pcie-phy-0", "pcie-phy-1",
261 "pcie-phy-2", "pcie-phy-3";
81f66606
SL		 262 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
263 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
66aef3cb
BN		 264 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
265 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
266 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
267 <&cru SRST_A_PCIE>;
268 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
269 "pm", "pclk", "aclk";
270 status = "disabled";
271
272 pcie0_intc: interrupt-controller {
273 interrupt-controller;
274 #address-cells = <0>;
275 #interrupt-cells = <1>;
276 };
277 };
278
eb3a6a6a
RC		 279 gmac: ethernet@fe300000 {
280 compatible = "rockchip,rk3399-gmac";
281 reg = <0x0 0xfe300000 0x0 0x10000>;
282 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
283 interrupt-names = "macirq";
284 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
285 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
286 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
287 <&cru PCLK_GMAC>;
288 clock-names = "stmmaceth", "mac_clk_rx",
289 "mac_clk_tx", "clk_mac_ref",
290 "clk_mac_refout", "aclk_mac",
291 "pclk_mac";
292 power-domains = <&power RK3399_PD_GMAC>;
293 resets = <&cru SRST_A_GMAC>;
294 reset-names = "stmmaceth";
295 rockchip,grf = <&grf>;
8a469ee3 296 snps,txpbl = <0x4>;
eb3a6a6a
RC		 297 status = "disabled";
298 };
299
3ef7c255 300 sdio0: mmc@fe310000 {
f048b9a4
JX		 301 compatible = "rockchip,rk3399-dw-mshc",
302 "rockchip,rk3288-dw-mshc";
303 reg = <0x0 0xfe310000 0x0 0x4000>;
210bbd38 304 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 305 max-frequency = <150000000>;
f048b9a4
JX		 306 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
307 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
308 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
309 fifo-depth = <0x100>;
b0f2110a 310 power-domains = <&power RK3399_PD_SDIOAUDIO>;
04dc7f62
HS		 311 resets = <&cru SRST_SDIO0>;
312 reset-names = "reset";
f048b9a4
JX		 313 status = "disabled";
314 };
315
3ef7c255 316 sdmmc: mmc@fe320000 {
f048b9a4
JX		 317 compatible = "rockchip,rk3399-dw-mshc",
318 "rockchip,rk3288-dw-mshc";
319 reg = <0x0 0xfe320000 0x0 0x4000>;
210bbd38 320 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 321 max-frequency = <150000000>;
e702e13f
LH		 322 assigned-clocks = <&cru HCLK_SD>;
323 assigned-clock-rates = <200000000>;
f048b9a4
JX		 324 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
325 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
326 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
327 fifo-depth = <0x100>;
1bc60bee 328 power-domains = <&power RK3399_PD_SD>;
04dc7f62
HS		 329 resets = <&cru SRST_SDMMC>;
330 reset-names = "reset";
f048b9a4
JX		 331 status = "disabled";
332 };
333
9a9f6427 334 sdhci: mmc@fe330000 {
b4e87c09
BN		 335 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
336 reg = <0x0 0xfe330000 0x0 0x10000>;
210bbd38 337 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
64e3481c 338 arasan,soc-ctl-syscon = <&grf>;
b4e87c09
BN		 339 assigned-clocks = <&cru SCLK_EMMC>;
340 assigned-clock-rates = <200000000>;
341 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
342 clock-names = "clk_xin", "clk_ahb";
ed388cdd
DA		 343 clock-output-names = "emmc_cardclock";
344 #clock-cells = <0>;
b4e87c09
BN		 345 phys = <&emmc_phy>;
346 phy-names = "phy_arasan";
a1907df2 347 power-domains = <&power RK3399_PD_EMMC>;
a3eec13b 348 disable-cqe-dcmd;
b4e87c09
BN		 349 status = "disabled";
350 };
351
f048b9a4
JX		 352 usb_host0_ehci: usb@fe380000 {
353 compatible = "generic-ehci";
354 reg = <0x0 0xfe380000 0x0 0x20000>;
210bbd38 355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
357 <&u2phy0>;
103e9f85
FW		 358 phys = <&u2phy0_host>;
359 phy-names = "usb";
f048b9a4
JX		 360 status = "disabled";
361 };
362
363 usb_host0_ohci: usb@fe3a0000 {
364 compatible = "generic-ohci";
365 reg = <0x0 0xfe3a0000 0x0 0x20000>;
210bbd38 366 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 367 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
368 <&u2phy0>;
b5d1c572
W		 369 phys = <&u2phy0_host>;
370 phy-names = "usb";
f048b9a4
JX		 371 status = "disabled";
372 };
373
374 usb_host1_ehci: usb@fe3c0000 {
375 compatible = "generic-ehci";
376 reg = <0x0 0xfe3c0000 0x0 0x20000>;
210bbd38 377 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 378 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
379 <&u2phy1>;
103e9f85
FW		 380 phys = <&u2phy1_host>;
381 phy-names = "usb";
f048b9a4
JX		 382 status = "disabled";
383 };
384
385 usb_host1_ohci: usb@fe3e0000 {
386 compatible = "generic-ohci";
387 reg = <0x0 0xfe3e0000 0x0 0x20000>;
210bbd38 388 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 389 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
390 <&u2phy1>;
b5d1c572
W		 391 phys = <&u2phy1_host>;
392 phy-names = "usb";
f048b9a4
JX		 393 status = "disabled";
394 };
395
7144224f
BN		 396 usbdrd3_0: usb@fe800000 {
397 compatible = "rockchip,rk3399-dwc3";
398 #address-cells = <2>;
399 #size-cells = <2>;
400 ranges;
401 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
9df8a2d9
EBS		 402 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
403 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 404 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 405 "bus_clk", "aclk_usb3_rksoc_axi_perf",
406 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 407 resets = <&cru SRST_A_USB3_OTG0>;
408 reset-names = "usb3-otg";
7144224f
BN		 409 status = "disabled";
410
190c7f6f 411 usbdrd_dwc3_0: usb@fe800000 {
7144224f
BN		 412 compatible = "snps,dwc3";
413 reg = <0x0 0xfe800000 0x0 0x100000>;
414 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
e6d237fd
EBS		 415 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
416 <&cru SCLK_USB3OTG0_SUSPEND>;
417 clock-names = "ref", "bus_early", "suspend";
7144224f 418 dr_mode = "otg";
bfdca173
EBS		 419 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
420 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 421 phy_type = "utmi_wide";
422 snps,dis_enblslpm_quirk;
423 snps,dis-u2-freeclk-exists-quirk;
424 snps,dis_u2_susphy_quirk;
425 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 426 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 427 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 428 status = "disabled";
429 };
430 };
431
432 usbdrd3_1: usb@fe900000 {
433 compatible = "rockchip,rk3399-dwc3";
434 #address-cells = <2>;
435 #size-cells = <2>;
436 ranges;
437 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
9df8a2d9
EBS		 438 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
439 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 440 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 441 "bus_clk", "aclk_usb3_rksoc_axi_perf",
442 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 443 resets = <&cru SRST_A_USB3_OTG1>;
444 reset-names = "usb3-otg";
7144224f
BN		 445 status = "disabled";
446
190c7f6f 447 usbdrd_dwc3_1: usb@fe900000 {
7144224f
BN		 448 compatible = "snps,dwc3";
449 reg = <0x0 0xfe900000 0x0 0x100000>;
450 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
e6d237fd
EBS		 451 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
452 <&cru SCLK_USB3OTG1_SUSPEND>;
453 clock-names = "ref", "bus_early", "suspend";
7144224f 454 dr_mode = "otg";
bfdca173
EBS		 455 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
456 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 457 phy_type = "utmi_wide";
458 snps,dis_enblslpm_quirk;
459 snps,dis-u2-freeclk-exists-quirk;
460 snps,dis_u2_susphy_quirk;
461 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 462 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 463 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 464 status = "disabled";
465 };
466 };
467
2d3c2d56
CZ		 468 cdn_dp: dp@fec00000 {
469 compatible = "rockchip,rk3399-cdn-dp";
470 reg = <0x0 0xfec00000 0x0 0x100000>;
471 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
e702e13f
LH		 472 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
473 assigned-clock-rates = <100000000>, <200000000>;
2d3c2d56
CZ		 474 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
475 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
476 clock-names = "core-clk", "pclk", "spdif", "grf";
477 phys = <&tcphy0_dp>, <&tcphy1_dp>;
478 power-domains = <&power RK3399_PD_HDCP>;
479 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
480 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
481 reset-names = "spdif", "dptx", "apb", "core";
482 rockchip,grf = <&grf>;
483 #sound-dai-cells = <1>;
484 status = "disabled";
485
486 ports {
487 dp_in: port {
488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 dp_in_vopb: endpoint@0 {
492 reg = <0>;
493 remote-endpoint = <&vopb_out_dp>;
494 };
495
496 dp_in_vopl: endpoint@1 {
497 reg = <1>;
498 remote-endpoint = <&vopl_out_dp>;
499 };
500 };
501 };
502 };
503
f048b9a4
JX		 504 gic: interrupt-controller@fee00000 {
505 compatible = "arm,gic-v3";
210bbd38 506 #interrupt-cells = <4>;
f048b9a4
JX		 507 #address-cells = <2>;
508 #size-cells = <2>;
509 ranges;
510 interrupt-controller;
511
512 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
513 <0x0 0xfef00000 0 0xc0000>, /* GICR */
514 <0x0 0xfff00000 0 0x10000>, /* GICC */
515 <0x0 0xfff10000 0 0x10000>, /* GICH */
516 <0x0 0xfff20000 0 0x10000>; /* GICV */
210bbd38 517 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 518 its: interrupt-controller@fee20000 {
519 compatible = "arm,gic-v3-its";
520 msi-controller;
85dd7638 521 #msi-cells = <1>;
f048b9a4
JX		 522 reg = <0x0 0xfee20000 0x0 0x20000>;
523 };
6840eb0d
CW		 524
525 ppi-partitions {
526 ppi_cluster0: interrupt-partition-0 {
527 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
528 };
529
530 ppi_cluster1: interrupt-partition-1 {
531 affinity = <&cpu_b0 &cpu_b1>;
532 };
533 };
f048b9a4
JX		 534 };
535
fe996215
CW		 536 saradc: saradc@ff100000 {
537 compatible = "rockchip,rk3399-saradc";
538 reg = <0x0 0xff100000 0x0 0x100>;
210bbd38 539 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
fe996215
CW		 540 #io-channel-cells = <1>;
541 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
542 clock-names = "saradc", "apb_pclk";
543 resets = <&cru SRST_P_SARADC>;
544 reset-names = "saradc-apb";
545 status = "disabled";
546 };
547
69e5a8fe
DW		 548 i2c1: i2c@ff110000 {
549 compatible = "rockchip,rk3399-i2c";
550 reg = <0x0 0xff110000 0x0 0x1000>;
551 assigned-clocks = <&cru SCLK_I2C1>;
552 assigned-clock-rates = <200000000>;
553 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
554 clock-names = "i2c", "pclk";
210bbd38 555 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c1_xfer>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 status = "disabled";
561 };
562
563 i2c2: i2c@ff120000 {
564 compatible = "rockchip,rk3399-i2c";
565 reg = <0x0 0xff120000 0x0 0x1000>;
566 assigned-clocks = <&cru SCLK_I2C2>;
567 assigned-clock-rates = <200000000>;
568 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
569 clock-names = "i2c", "pclk";
210bbd38 570 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c2_xfer>;
573 #address-cells = <1>;
574 #size-cells = <0>;
575 status = "disabled";
576 };
577
578 i2c3: i2c@ff130000 {
579 compatible = "rockchip,rk3399-i2c";
580 reg = <0x0 0xff130000 0x0 0x1000>;
581 assigned-clocks = <&cru SCLK_I2C3>;
582 assigned-clock-rates = <200000000>;
583 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
584 clock-names = "i2c", "pclk";
210bbd38 585 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c3_xfer>;
588 #address-cells = <1>;
589 #size-cells = <0>;
590 status = "disabled";
591 };
592
593 i2c5: i2c@ff140000 {
594 compatible = "rockchip,rk3399-i2c";
595 reg = <0x0 0xff140000 0x0 0x1000>;
596 assigned-clocks = <&cru SCLK_I2C5>;
597 assigned-clock-rates = <200000000>;
598 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
599 clock-names = "i2c", "pclk";
210bbd38 600 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 601 pinctrl-names = "default";
602 pinctrl-0 = <&i2c5_xfer>;
603 #address-cells = <1>;
604 #size-cells = <0>;
605 status = "disabled";
606 };
607
608 i2c6: i2c@ff150000 {
609 compatible = "rockchip,rk3399-i2c";
610 reg = <0x0 0xff150000 0x0 0x1000>;
611 assigned-clocks = <&cru SCLK_I2C6>;
612 assigned-clock-rates = <200000000>;
613 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
614 clock-names = "i2c", "pclk";
210bbd38 615 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 616 pinctrl-names = "default";
617 pinctrl-0 = <&i2c6_xfer>;
618 #address-cells = <1>;
619 #size-cells = <0>;
620 status = "disabled";
621 };
622
623 i2c7: i2c@ff160000 {
624 compatible = "rockchip,rk3399-i2c";
625 reg = <0x0 0xff160000 0x0 0x1000>;
626 assigned-clocks = <&cru SCLK_I2C7>;
627 assigned-clock-rates = <200000000>;
628 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
629 clock-names = "i2c", "pclk";
210bbd38 630 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 631 pinctrl-names = "default";
632 pinctrl-0 = <&i2c7_xfer>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 status = "disabled";
636 };
637
f048b9a4
JX		 638 uart0: serial@ff180000 {
639 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
640 reg = <0x0 0xff180000 0x0 0x100>;
641 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
642 clock-names = "baudclk", "apb_pclk";
210bbd38 643 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 644 reg-shift = <2>;
645 reg-io-width = <4>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&uart0_xfer>;
648 status = "disabled";
649 };
650
651 uart1: serial@ff190000 {
652 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
653 reg = <0x0 0xff190000 0x0 0x100>;
654 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
655 clock-names = "baudclk", "apb_pclk";
210bbd38 656 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 657 reg-shift = <2>;
658 reg-io-width = <4>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&uart1_xfer>;
661 status = "disabled";
662 };
663
664 uart2: serial@ff1a0000 {
665 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
666 reg = <0x0 0xff1a0000 0x0 0x100>;
667 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
668 clock-names = "baudclk", "apb_pclk";
210bbd38 669 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 670 reg-shift = <2>;
671 reg-io-width = <4>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&uart2c_xfer>;
674 status = "disabled";
675 };
676
677 uart3: serial@ff1b0000 {
678 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
679 reg = <0x0 0xff1b0000 0x0 0x100>;
680 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
681 clock-names = "baudclk", "apb_pclk";
210bbd38 682 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 683 reg-shift = <2>;
684 reg-io-width = <4>;
685 pinctrl-names = "default";
686 pinctrl-0 = <&uart3_xfer>;
687 status = "disabled";
688 };
689
690 spi0: spi@ff1c0000 {
691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
692 reg = <0x0 0xff1c0000 0x0 0x1000>;
693 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
694 clock-names = "spiclk", "apb_pclk";
210bbd38 695 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 696 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
697 dma-names = "tx", "rx";
f048b9a4
JX		 698 pinctrl-names = "default";
699 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
700 #address-cells = <1>;
701 #size-cells = <0>;
702 status = "disabled";
703 };
704
705 spi1: spi@ff1d0000 {
706 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
707 reg = <0x0 0xff1d0000 0x0 0x1000>;
708 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
709 clock-names = "spiclk", "apb_pclk";
210bbd38 710 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 711 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
712 dma-names = "tx", "rx";
f048b9a4
JX		 713 pinctrl-names = "default";
714 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
715 #address-cells = <1>;
716 #size-cells = <0>;
717 status = "disabled";
718 };
719
720 spi2: spi@ff1e0000 {
721 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
722 reg = <0x0 0xff1e0000 0x0 0x1000>;
723 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
724 clock-names = "spiclk", "apb_pclk";
210bbd38 725 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 726 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
727 dma-names = "tx", "rx";
f048b9a4
JX		 728 pinctrl-names = "default";
729 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
730 #address-cells = <1>;
731 #size-cells = <0>;
732 status = "disabled";
733 };
734
735 spi4: spi@ff1f0000 {
736 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
737 reg = <0x0 0xff1f0000 0x0 0x1000>;
738 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
739 clock-names = "spiclk", "apb_pclk";
210bbd38 740 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 741 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
742 dma-names = "tx", "rx";
f048b9a4
JX		 743 pinctrl-names = "default";
744 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
745 #address-cells = <1>;
746 #size-cells = <0>;
747 status = "disabled";
748 };
749
750 spi5: spi@ff200000 {
751 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
752 reg = <0x0 0xff200000 0x0 0x1000>;
753 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
754 clock-names = "spiclk", "apb_pclk";
210bbd38 755 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 756 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
757 dma-names = "tx", "rx";
f048b9a4
JX		 758 pinctrl-names = "default";
759 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
b0f2110a 760 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 761 #address-cells = <1>;
762 #size-cells = <0>;
763 status = "disabled";
764 };
765
647cea2e 766 thermal_zones: thermal-zones {
95c27ba7
CW		 767 cpu_thermal: cpu {
768 polling-delay-passive = <100>;
769 polling-delay = <1000>;
770
771 thermal-sensors = <&tsadc 0>;
772
773 trips {
774 cpu_alert0: cpu_alert0 {
775 temperature = <70000>;
776 hysteresis = <2000>;
777 type = "passive";
778 };
779 cpu_alert1: cpu_alert1 {
780 temperature = <75000>;
781 hysteresis = <2000>;
782 type = "passive";
783 };
784 cpu_crit: cpu_crit {
785 temperature = <95000>;
786 hysteresis = <2000>;
787 type = "critical";
788 };
789 };
790
791 cooling-maps {
792 map0 {
793 trip = <&cpu_alert0>;
794 cooling-device =
cdd46460
VK		 795 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
796 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
95c27ba7
CW		 797 };
798 map1 {
799 trip = <&cpu_alert1>;
800 cooling-device =
801 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cdd46460
VK		 802 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
803 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
804 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
805 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
806 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
95c27ba7
CW		 807 };
808 };
809 };
810
811 gpu_thermal: gpu {
812 polling-delay-passive = <100>;
813 polling-delay = <1000>;
814
815 thermal-sensors = <&tsadc 1>;
816
817 trips {
818 gpu_alert0: gpu_alert0 {
819 temperature = <75000>;
820 hysteresis = <2000>;
821 type = "passive";
822 };
823 gpu_crit: gpu_crit {
824 temperature = <95000>;
825 hysteresis = <2000>;
826 type = "critical";
827 };
828 };
36be9111
RM		 829
830 cooling-maps {
831 map0 {
832 trip = <&gpu_alert0>;
833 cooling-device =
834 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
835 };
836 };
95c27ba7
CW		 837 };
838 };
839
840 tsadc: tsadc@ff260000 {
841 compatible = "rockchip,rk3399-tsadc";
842 reg = <0x0 0xff260000 0x0 0x100>;
210bbd38 843 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
95c27ba7
CW		 844 assigned-clocks = <&cru SCLK_TSADC>;
845 assigned-clock-rates = <750000>;
846 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
847 clock-names = "tsadc", "apb_pclk";
848 resets = <&cru SRST_TSADC>;
849 reset-names = "tsadc-apb";
850 rockchip,grf = <&grf>;
851 rockchip,hw-tshut-temp = <95000>;
852 pinctrl-names = "init", "default", "sleep";
2bc65fef 853 pinctrl-0 = <&otp_pin>;
95c27ba7 854 pinctrl-1 = <&otp_out>;
2bc65fef 855 pinctrl-2 = <&otp_pin>;
95c27ba7
CW		 856 #thermal-sensor-cells = <1>;
857 status = "disabled";
858 };
859
a1907df2 860 qos_emmc: qos@ffa58000 {
bd3fd049 861 compatible = "rockchip,rk3399-qos", "syscon";
a1907df2
EZ		 862 reg = <0x0 0xffa58000 0x0 0x20>;
863 };
864
d43c97a5 865 qos_gmac: qos@ffa5c000 {
bd3fd049 866 compatible = "rockchip,rk3399-qos", "syscon";
d43c97a5
CW		 867 reg = <0x0 0xffa5c000 0x0 0x20>;
868 };
869
65f1e902 870 qos_pcie: qos@ffa60080 {
bd3fd049 871 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 872 reg = <0x0 0xffa60080 0x0 0x20>;
873 };
874
875 qos_usb_host0: qos@ffa60100 {
bd3fd049 876 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 877 reg = <0x0 0xffa60100 0x0 0x20>;
878 };
879
880 qos_usb_host1: qos@ffa60180 {
bd3fd049 881 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 882 reg = <0x0 0xffa60180 0x0 0x20>;
883 };
884
885 qos_usb_otg0: qos@ffa70000 {
bd3fd049 886 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 887 reg = <0x0 0xffa70000 0x0 0x20>;
888 };
889
890 qos_usb_otg1: qos@ffa70080 {
bd3fd049 891 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 892 reg = <0x0 0xffa70080 0x0 0x20>;
893 };
894
895 qos_sd: qos@ffa74000 {
bd3fd049 896 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 897 reg = <0x0 0xffa74000 0x0 0x20>;
898 };
899
900 qos_sdioaudio: qos@ffa76000 {
bd3fd049 901 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 902 reg = <0x0 0xffa76000 0x0 0x20>;
903 };
904
807a2371 905 qos_hdcp: qos@ffa90000 {
bd3fd049 906 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 907 reg = <0x0 0xffa90000 0x0 0x20>;
908 };
909
910 qos_iep: qos@ffa98000 {
bd3fd049 911 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 912 reg = <0x0 0xffa98000 0x0 0x20>;
913 };
914
915 qos_isp0_m0: qos@ffaa0000 {
bd3fd049 916 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 917 reg = <0x0 0xffaa0000 0x0 0x20>;
918 };
919
920 qos_isp0_m1: qos@ffaa0080 {
bd3fd049 921 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 922 reg = <0x0 0xffaa0080 0x0 0x20>;
923 };
924
925 qos_isp1_m0: qos@ffaa8000 {
bd3fd049 926 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 927 reg = <0x0 0xffaa8000 0x0 0x20>;
928 };
929
930 qos_isp1_m1: qos@ffaa8080 {
bd3fd049 931 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 932 reg = <0x0 0xffaa8080 0x0 0x20>;
933 };
934
935 qos_rga_r: qos@ffab0000 {
bd3fd049 936 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 937 reg = <0x0 0xffab0000 0x0 0x20>;
938 };
939
940 qos_rga_w: qos@ffab0080 {
bd3fd049 941 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 942 reg = <0x0 0xffab0080 0x0 0x20>;
943 };
944
945 qos_video_m0: qos@ffab8000 {
bd3fd049 946 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 947 reg = <0x0 0xffab8000 0x0 0x20>;
948 };
949
950 qos_video_m1_r: qos@ffac0000 {
bd3fd049 951 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 952 reg = <0x0 0xffac0000 0x0 0x20>;
953 };
954
955 qos_video_m1_w: qos@ffac0080 {
bd3fd049 956 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 957 reg = <0x0 0xffac0080 0x0 0x20>;
958 };
959
960 qos_vop_big_r: qos@ffac8000 {
bd3fd049 961 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 962 reg = <0x0 0xffac8000 0x0 0x20>;
963 };
964
965 qos_vop_big_w: qos@ffac8080 {
bd3fd049 966 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 967 reg = <0x0 0xffac8080 0x0 0x20>;
968 };
969
970 qos_vop_little: qos@ffad0000 {
bd3fd049 971 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 972 reg = <0x0 0xffad0000 0x0 0x20>;
973 };
974
65f1e902 975 qos_perihp: qos@ffad8080 {
bd3fd049 976 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 977 reg = <0x0 0xffad8080 0x0 0x20>;
978 };
979
807a2371 980 qos_gpu: qos@ffae0000 {
bd3fd049 981 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 982 reg = <0x0 0xffae0000 0x0 0x20>;
983 };
984
985 pmu: power-management@ff310000 {
986 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
987 reg = <0x0 0xff310000 0x0 0x1000>;
988
989 /*
990 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
991 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
992 * Some of the power domains are grouped together for every
993 * voltage domain.
994 * The detail contents as below.
995 */
996 power: power-controller {
997 compatible = "rockchip,rk3399-power-controller";
998 #power-domain-cells = <1>;
999 #address-cells = <1>;
1000 #size-cells = <0>;
1001
1002 /* These power domains are grouped by VD_CENTER */
1003 pd_iep@RK3399_PD_IEP {
1004 reg = <RK3399_PD_IEP>;
1005 clocks = <&cru ACLK_IEP>,
1006 <&cru HCLK_IEP>;
1007 pm_qos = <&qos_iep>;
1008 };
1009 pd_rga@RK3399_PD_RGA {
1010 reg = <RK3399_PD_RGA>;
1011 clocks = <&cru ACLK_RGA>,
1012 <&cru HCLK_RGA>;
1013 pm_qos = <&qos_rga_r>,
1014 <&qos_rga_w>;
1015 };
1016 pd_vcodec@RK3399_PD_VCODEC {
1017 reg = <RK3399_PD_VCODEC>;
1018 clocks = <&cru ACLK_VCODEC>,
1019 <&cru HCLK_VCODEC>;
1020 pm_qos = <&qos_video_m0>;
1021 };
1022 pd_vdu@RK3399_PD_VDU {
1023 reg = <RK3399_PD_VDU>;
1024 clocks = <&cru ACLK_VDU>,
1025 <&cru HCLK_VDU>;
1026 pm_qos = <&qos_video_m1_r>,
1027 <&qos_video_m1_w>;
1028 };
1029
1030 /* These power domains are grouped by VD_GPU */
1031 pd_gpu@RK3399_PD_GPU {
1032 reg = <RK3399_PD_GPU>;
1033 clocks = <&cru ACLK_GPU>;
1034 pm_qos = <&qos_gpu>;
1035 };
1036
1037 /* These power domains are grouped by VD_LOGIC */
3cf04a4e
EZ		 1038 pd_edp@RK3399_PD_EDP {
1039 reg = <RK3399_PD_EDP>;
1040 clocks = <&cru PCLK_EDP_CTRL>;
1041 };
a1907df2
EZ		 1042 pd_emmc@RK3399_PD_EMMC {
1043 reg = <RK3399_PD_EMMC>;
1044 clocks = <&cru ACLK_EMMC>;
1045 pm_qos = <&qos_emmc>;
1046 };
d43c97a5
CW		 1047 pd_gmac@RK3399_PD_GMAC {
1048 reg = <RK3399_PD_GMAC>;
2afc1db0
JC		 1049 clocks = <&cru ACLK_GMAC>,
1050 <&cru PCLK_GMAC>;
d43c97a5
CW		 1051 pm_qos = <&qos_gmac>;
1052 };
1bc60bee
EZ		 1053 pd_sd@RK3399_PD_SD {
1054 reg = <RK3399_PD_SD>;
1055 clocks = <&cru HCLK_SDMMC>,
1056 <&cru SCLK_SDMMC>;
1057 pm_qos = <&qos_sd>;
1058 };
b0f2110a
CW		 1059 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1060 reg = <RK3399_PD_SDIOAUDIO>;
1061 clocks = <&cru HCLK_SDIO>;
1062 pm_qos = <&qos_sdioaudio>;
1063 };
2b99e619
JJ		 1064 pd_tcpc0@RK3399_PD_TCPD0 {
1065 reg = <RK3399_PD_TCPD0>;
1066 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1067 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1068 };
1069 pd_tcpc1@RK3399_PD_TCPD1 {
1070 reg = <RK3399_PD_TCPD1>;
1071 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1072 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1073 };
a1bbaaa4
EBS		 1074 pd_usb3@RK3399_PD_USB3 {
1075 reg = <RK3399_PD_USB3>;
1076 clocks = <&cru ACLK_USB3>;
1077 pm_qos = <&qos_usb_otg0>,
1078 <&qos_usb_otg1>;
1079 };
807a2371
EZ		 1080 pd_vio@RK3399_PD_VIO {
1081 reg = <RK3399_PD_VIO>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084
1085 pd_hdcp@RK3399_PD_HDCP {
1086 reg = <RK3399_PD_HDCP>;
1087 clocks = <&cru ACLK_HDCP>,
1088 <&cru HCLK_HDCP>,
1089 <&cru PCLK_HDCP>;
1090 pm_qos = <&qos_hdcp>;
1091 };
1092 pd_isp0@RK3399_PD_ISP0 {
1093 reg = <RK3399_PD_ISP0>;
1094 clocks = <&cru ACLK_ISP0>,
1095 <&cru HCLK_ISP0>;
1096 pm_qos = <&qos_isp0_m0>,
1097 <&qos_isp0_m1>;
1098 };
1099 pd_isp1@RK3399_PD_ISP1 {
1100 reg = <RK3399_PD_ISP1>;
1101 clocks = <&cru ACLK_ISP1>,
1102 <&cru HCLK_ISP1>;
1103 pm_qos = <&qos_isp1_m0>,
1104 <&qos_isp1_m1>;
1105 };
1106 pd_vo@RK3399_PD_VO {
1107 reg = <RK3399_PD_VO>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110
1111 pd_vopb@RK3399_PD_VOPB {
1112 reg = <RK3399_PD_VOPB>;
1113 clocks = <&cru ACLK_VOP0>,
1114 <&cru HCLK_VOP0>;
1115 pm_qos = <&qos_vop_big_r>,
1116 <&qos_vop_big_w>;
1117 };
1118 pd_vopl@RK3399_PD_VOPL {
1119 reg = <RK3399_PD_VOPL>;
1120 clocks = <&cru ACLK_VOP1>,
1121 <&cru HCLK_VOP1>;
1122 pm_qos = <&qos_vop_little>;
1123 };
1124 };
1125 };
1126 };
1127 };
1128
f048b9a4 1129 pmugrf: syscon@ff320000 {
16759262 1130 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
f048b9a4 1131 reg = <0x0 0xff320000 0x0 0x1000>;
6d0e3a45
HS		 1132
1133 pmu_io_domains: io-domains {
1134 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1135 status = "disabled";
1136 };
f048b9a4
JX		 1137 };
1138
1139 spi3: spi@ff350000 {
1140 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1141 reg = <0x0 0xff350000 0x0 0x1000>;
1142 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1143 clock-names = "spiclk", "apb_pclk";
210bbd38 1144 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1145 pinctrl-names = "default";
1146 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149 status = "disabled";
1150 };
1151
1152 uart4: serial@ff370000 {
1153 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1154 reg = <0x0 0xff370000 0x0 0x100>;
1155 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1156 clock-names = "baudclk", "apb_pclk";
210bbd38 1157 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1158 reg-shift = <2>;
1159 reg-io-width = <4>;
1160 pinctrl-names = "default";
1161 pinctrl-0 = <&uart4_xfer>;
1162 status = "disabled";
1163 };
1164
69e5a8fe
DW		 1165 i2c0: i2c@ff3c0000 {
1166 compatible = "rockchip,rk3399-i2c";
1167 reg = <0x0 0xff3c0000 0x0 0x1000>;
1168 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1169 assigned-clock-rates = <200000000>;
1170 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1171 clock-names = "i2c", "pclk";
210bbd38 1172 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1173 pinctrl-names = "default";
1174 pinctrl-0 = <&i2c0_xfer>;
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 status = "disabled";
1178 };
1179
1180 i2c4: i2c@ff3d0000 {
1181 compatible = "rockchip,rk3399-i2c";
1182 reg = <0x0 0xff3d0000 0x0 0x1000>;
1183 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1184 assigned-clock-rates = <200000000>;
1185 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1186 clock-names = "i2c", "pclk";
210bbd38 1187 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1188 pinctrl-names = "default";
1189 pinctrl-0 = <&i2c4_xfer>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 status = "disabled";
1193 };
1194
1195 i2c8: i2c@ff3e0000 {
1196 compatible = "rockchip,rk3399-i2c";
1197 reg = <0x0 0xff3e0000 0x0 0x1000>;
1198 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1199 assigned-clock-rates = <200000000>;
1200 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1201 clock-names = "i2c", "pclk";
210bbd38 1202 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1203 pinctrl-names = "default";
1204 pinctrl-0 = <&i2c8_xfer>;
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1207 status = "disabled";
f048b9a4
JX		 1208 };
1209
1210 pwm0: pwm@ff420000 {
1211 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1212 reg = <0x0 0xff420000 0x0 0x10>;
1213 #pwm-cells = <3>;
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&pwm0_pin>;
1216 clocks = <&pmucru PCLK_RKPWM_PMU>;
1217 clock-names = "pwm";
1218 status = "disabled";
1219 };
1220
1221 pwm1: pwm@ff420010 {
1222 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1223 reg = <0x0 0xff420010 0x0 0x10>;
1224 #pwm-cells = <3>;
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&pwm1_pin>;
1227 clocks = <&pmucru PCLK_RKPWM_PMU>;
1228 clock-names = "pwm";
1229 status = "disabled";
1230 };
1231
1232 pwm2: pwm@ff420020 {
1233 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1234 reg = <0x0 0xff420020 0x0 0x10>;
1235 #pwm-cells = <3>;
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&pwm2_pin>;
1238 clocks = <&pmucru PCLK_RKPWM_PMU>;
1239 clock-names = "pwm";
1240 status = "disabled";
1241 };
1242
1243 pwm3: pwm@ff420030 {
1244 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1245 reg = <0x0 0xff420030 0x0 0x10>;
1246 #pwm-cells = <3>;
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&pwm3a_pin>;
1249 clocks = <&pmucru PCLK_RKPWM_PMU>;
1250 clock-names = "pwm";
1251 status = "disabled";
1252 };
1253
5cd4c31a
EG		 1254 vpu: video-codec@ff650000 {
1255 compatible = "rockchip,rk3399-vpu";
1256 reg = <0x0 0xff650000 0x0 0x800>;
1257 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1258 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1259 interrupt-names = "vepu", "vdpu";
1260 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1261 clock-names = "aclk", "hclk";
1262 iommus = <&vpu_mmu>;
1263 power-domains = <&power RK3399_PD_VCODEC>;
1264 };
1265
ae4fdcca
SX		 1266 vpu_mmu: iommu@ff650800 {
1267 compatible = "rockchip,iommu";
1268 reg = <0x0 0xff650800 0x0 0x40>;
1269 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1270 interrupt-names = "vpu_mmu";
df3bcde7
JC		 1271 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1272 clock-names = "aclk", "iface";
ae4fdcca 1273 #iommu-cells = <0>;
5cd4c31a 1274 power-domains = <&power RK3399_PD_VCODEC>;
ae4fdcca
SX		 1275 };
1276
cbd72144
BB		 1277 vdec: video-codec@ff660000 {
1278 compatible = "rockchip,rk3399-vdec";
1279 reg = <0x0 0xff660000 0x0 0x400>;
1280 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1281 interrupt-names = "vdpu";
1282 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1283 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1284 clock-names = "axi", "ahb", "cabac", "core";
1285 iommus = <&vdec_mmu>;
1286 power-domains = <&power RK3399_PD_VDU>;
1287 };
1288
ae4fdcca
SX		 1289 vdec_mmu: iommu@ff660480 {
1290 compatible = "rockchip,iommu";
1291 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1292 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1293 interrupt-names = "vdec_mmu";
df3bcde7
JC		 1294 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1295 clock-names = "aclk", "iface";
cbd72144 1296 power-domains = <&power RK3399_PD_VDU>;
ae4fdcca 1297 #iommu-cells = <0>;
ae4fdcca
SX		 1298 };
1299
1300 iep_mmu: iommu@ff670800 {
1301 compatible = "rockchip,iommu";
1302 reg = <0x0 0xff670800 0x0 0x40>;
1303 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1304 interrupt-names = "iep_mmu";
df3bcde7
JC		 1305 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1306 clock-names = "aclk", "iface";
ae4fdcca
SX		 1307 #iommu-cells = <0>;
1308 status = "disabled";
1309 };
1310
ec5ccfd7
JC		 1311 rga: rga@ff680000 {
1312 compatible = "rockchip,rk3399-rga";
1313 reg = <0x0 0xff680000 0x0 0x10000>;
1314 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1315 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1316 clock-names = "aclk", "hclk", "sclk";
1317 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1318 reset-names = "core", "axi", "ahb";
1319 power-domains = <&power RK3399_PD_RGA>;
1320 };
1321
b7ee3b27
FX		 1322 efuse0: efuse@ff690000 {
1323 compatible = "rockchip,rk3399-efuse";
1324 reg = <0x0 0xff690000 0x0 0x80>;
1325 #address-cells = <1>;
1326 #size-cells = <1>;
1327 clocks = <&cru PCLK_EFUSE1024NS>;
1328 clock-names = "pclk_efuse";
1329
1330 /* Data cells */
0d326927
ZX		 1331 cpu_id: cpu-id@7 {
1332 reg = <0x07 0x10>;
1333 };
b7ee3b27
FX		 1334 cpub_leakage: cpu-leakage@17 {
1335 reg = <0x17 0x1>;
1336 };
1337 gpu_leakage: gpu-leakage@18 {
1338 reg = <0x18 0x1>;
1339 };
1340 center_leakage: center-leakage@19 {
1341 reg = <0x19 0x1>;
1342 };
1343 cpul_leakage: cpu-leakage@1a {
1344 reg = <0x1a 0x1>;
1345 };
1346 logic_leakage: logic-leakage@1b {
1347 reg = <0x1b 0x1>;
1348 };
1349 wafer_info: wafer-info@1c {
1350 reg = <0x1c 0x1>;
1351 };
1352 };
1353
f048b9a4
JX		 1354 pmucru: pmu-clock-controller@ff750000 {
1355 compatible = "rockchip,rk3399-pmucru";
1356 reg = <0x0 0xff750000 0x0 0x1000>;
8cbb59af 1357 rockchip,grf = <&pmugrf>;
f048b9a4
JX		 1358 #clock-cells = <1>;
1359 #reset-cells = <1>;
1360 assigned-clocks = <&pmucru PLL_PPLL>;
1361 assigned-clock-rates = <676000000>;
1362 };
1363
1364 cru: clock-controller@ff760000 {
1365 compatible = "rockchip,rk3399-cru";
1366 reg = <0x0 0xff760000 0x0 0x1000>;
8cbb59af 1367 rockchip,grf = <&grf>;
f048b9a4
JX		 1368 #clock-cells = <1>;
1369 #reset-cells = <1>;
a09906cd
XZ		 1370 assigned-clocks =
1371 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1372 <&cru PLL_NPLL>,
1373 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1374 <&cru PCLK_PERIHP>,
1375 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
bb4b6201 1376 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
3f7f3b0f 1377 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
e702e13f
LH		 1378 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1379 <&cru ACLK_GIC_PRE>,
1380 <&cru PCLK_DDR>;
a09906cd
XZ		 1381 assigned-clock-rates =
1382 <594000000>, <800000000>,
1383 <1000000000>,
1384 <150000000>, <75000000>,
1385 <37500000>,
1386 <100000000>, <100000000>,
bb4b6201 1387 <50000000>, <600000000>,
3f7f3b0f 1388 <100000000>, <50000000>,
e702e13f
LH		 1389 <400000000>, <400000000>,
1390 <200000000>,
1391 <200000000>;
f048b9a4
JX		 1392 };
1393
1394 grf: syscon@ff770000 {
16759262 1395 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
f048b9a4 1396 reg = <0x0 0xff770000 0x0 0x10000>;
16759262
BN		 1397 #address-cells = <1>;
1398 #size-cells = <1>;
b4e87c09 1399
6d0e3a45
HS		 1400 io_domains: io-domains {
1401 compatible = "rockchip,rk3399-io-voltage-domain";
1402 status = "disabled";
1403 };
1404
e4bfde13
SZ		 1405 mipi_dphy_rx0: mipi-dphy-rx0 {
1406 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1407 clocks = <&cru SCLK_MIPIDPHY_REF>,
1408 <&cru SCLK_DPHY_RX0_CFG>,
1409 <&cru PCLK_VIO_GRF>;
1410 clock-names = "dphy-ref", "dphy-cfg", "grf";
1411 power-domains = <&power RK3399_PD_VIO>;
1412 #phy-cells = <0>;
1413 status = "disabled";
1414 };
1415
103e9f85
FW		 1416 u2phy0: usb2-phy@e450 {
1417 compatible = "rockchip,rk3399-usb2phy";
1418 reg = <0xe450 0x10>;
1419 clocks = <&cru SCLK_USB2PHY0_REF>;
1420 clock-names = "phyclk";
1421 #clock-cells = <0>;
1422 clock-output-names = "clk_usbphy0_480m";
1423 status = "disabled";
1424
1425 u2phy0_host: host-port {
1426 #phy-cells = <0>;
210bbd38 1427 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1428 interrupt-names = "linestate";
1429 status = "disabled";
1430 };
fe7f2de1
WW		 1431
1432 u2phy0_otg: otg-port {
1433 #phy-cells = <0>;
1434 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1435 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1436 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1437 interrupt-names = "otg-bvalid", "otg-id",
1438 "linestate";
1439 status = "disabled";
1440 };
103e9f85
FW		 1441 };
1442
1443 u2phy1: usb2-phy@e460 {
1444 compatible = "rockchip,rk3399-usb2phy";
1445 reg = <0xe460 0x10>;
1446 clocks = <&cru SCLK_USB2PHY1_REF>;
1447 clock-names = "phyclk";
1448 #clock-cells = <0>;
1449 clock-output-names = "clk_usbphy1_480m";
1450 status = "disabled";
1451
1452 u2phy1_host: host-port {
1453 #phy-cells = <0>;
210bbd38 1454 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1455 interrupt-names = "linestate";
1456 status = "disabled";
1457 };
fe7f2de1
WW		 1458
1459 u2phy1_otg: otg-port {
1460 #phy-cells = <0>;
1461 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1462 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1463 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1464 interrupt-names = "otg-bvalid", "otg-id",
1465 "linestate";
1466 status = "disabled";
1467 };
103e9f85
FW		 1468 };
1469
b4e87c09
BN		 1470 emmc_phy: phy@f780 {
1471 compatible = "rockchip,rk3399-emmc-phy";
1472 reg = <0xf780 0x24>;
ed388cdd
DA		 1473 clocks = <&sdhci>;
1474 clock-names = "emmcclk";
b4e87c09
BN		 1475 #phy-cells = <0>;
1476 status = "disabled";
1477 };
29a0be1c
SL		 1478
1479 pcie_phy: pcie-phy {
1480 compatible = "rockchip,rk3399-pcie-phy";
1481 clocks = <&cru SCLK_PCIEPHY_REF>;
1482 clock-names = "refclk";
e9a60cac 1483 #phy-cells = <1>;
29a0be1c 1484 resets = <&cru SRST_PCIEPHY>;
fb8b7460 1485 drive-impedance-ohm = <50>;
29a0be1c
SL		 1486 reset-names = "phy";
1487 status = "disabled";
1488 };
f048b9a4
JX		 1489 };
1490
f606193a
CZ		 1491 tcphy0: phy@ff7c0000 {
1492 compatible = "rockchip,rk3399-typec-phy";
1493 reg = <0x0 0xff7c0000 0x0 0x40000>;
1494 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1495 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1496 clock-names = "tcpdcore", "tcpdphy-ref";
1497 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1498 assigned-clock-rates = <50000000>;
06ad4b2f 1499 power-domains = <&power RK3399_PD_TCPD0>;
f606193a
CZ		 1500 resets = <&cru SRST_UPHY0>,
1501 <&cru SRST_UPHY0_PIPE_L00>,
1502 <&cru SRST_P_UPHY0_TCPHY>;
1503 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1504 rockchip,grf = <&grf>;
f606193a
CZ		 1505 status = "disabled";
1506
1507 tcphy0_dp: dp-port {
1508 #phy-cells = <0>;
1509 };
1510
1511 tcphy0_usb3: usb3-port {
1512 #phy-cells = <0>;
1513 };
1514 };
1515
1516 tcphy1: phy@ff800000 {
1517 compatible = "rockchip,rk3399-typec-phy";
1518 reg = <0x0 0xff800000 0x0 0x40000>;
1519 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1520 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1521 clock-names = "tcpdcore", "tcpdphy-ref";
1522 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1523 assigned-clock-rates = <50000000>;
06ad4b2f 1524 power-domains = <&power RK3399_PD_TCPD1>;
f606193a
CZ		 1525 resets = <&cru SRST_UPHY1>,
1526 <&cru SRST_UPHY1_PIPE_L00>,
1527 <&cru SRST_P_UPHY1_TCPHY>;
1528 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1529 rockchip,grf = <&grf>;
f606193a
CZ		 1530 status = "disabled";
1531
1532 tcphy1_dp: dp-port {
1533 #phy-cells = <0>;
1534 };
1535
1536 tcphy1_usb3: usb3-port {
1537 #phy-cells = <0>;
1538 };
1539 };
1540
0895b3a8 1541 watchdog@ff848000 {
f048b9a4 1542 compatible = "snps,dw-wdt";
0895b3a8 1543 reg = <0x0 0xff848000 0x0 0x100>;
f048b9a4 1544 clocks = <&cru PCLK_WDT>;
210bbd38 1545 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1546 };
1547
1e8567d5
HT		 1548 rktimer: rktimer@ff850000 {
1549 compatible = "rockchip,rk3399-timer";
1550 reg = <0x0 0xff850000 0x0 0x1000>;
210bbd38 1551 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1e8567d5
HT		 1552 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1553 clock-names = "pclk", "timer";
1554 };
1555
f048b9a4
JX		 1556 spdif: spdif@ff870000 {
1557 compatible = "rockchip,rk3399-spdif";
1558 reg = <0x0 0xff870000 0x0 0x1000>;
210bbd38 1559 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1560 dmas = <&dmac_bus 7>;
1561 dma-names = "tx";
1562 clock-names = "mclk", "hclk";
1563 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&spdif_bus>;
b0f2110a 1566 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1567 #sound-dai-cells = <0>;
f048b9a4
JX		 1568 status = "disabled";
1569 };
1570
1571 i2s0: i2s@ff880000 {
1572 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1573 reg = <0x0 0xff880000 0x0 0x1000>;
1574 rockchip,grf = <&grf>;
210bbd38 1575 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1576 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1577 dma-names = "tx", "rx";
1578 clock-names = "i2s_clk", "i2s_hclk";
1579 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1580 pinctrl-names = "default";
1581 pinctrl-0 = <&i2s0_8ch_bus>;
b0f2110a 1582 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1583 #sound-dai-cells = <0>;
f048b9a4
JX		 1584 status = "disabled";
1585 };
1586
1587 i2s1: i2s@ff890000 {
1588 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1589 reg = <0x0 0xff890000 0x0 0x1000>;
210bbd38 1590 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1591 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1592 dma-names = "tx", "rx";
1593 clock-names = "i2s_clk", "i2s_hclk";
1594 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1595 pinctrl-names = "default";
1596 pinctrl-0 = <&i2s1_2ch_bus>;
b0f2110a 1597 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1598 #sound-dai-cells = <0>;
f048b9a4
JX		 1599 status = "disabled";
1600 };
1601
1602 i2s2: i2s@ff8a0000 {
1603 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1604 reg = <0x0 0xff8a0000 0x0 0x1000>;
210bbd38 1605 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1606 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1607 dma-names = "tx", "rx";
1608 clock-names = "i2s_clk", "i2s_hclk";
1609 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
b0f2110a 1610 power-domains = <&power RK3399_PD_SDIOAUDIO>;
0d60d48c 1611 #sound-dai-cells = <0>;
f048b9a4
JX		 1612 status = "disabled";
1613 };
1614
fbd4cc0e
MY		 1615 vopl: vop@ff8f0000 {
1616 compatible = "rockchip,rk3399-vop-lit";
1617 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1618 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1619 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1620 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1621 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1622 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1623 iommus = <&vopl_mmu>;
1624 power-domains = <&power RK3399_PD_VOPL>;
1625 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1626 reset-names = "axi", "ahb", "dclk";
1627 status = "disabled";
1628
1629 vopl_out: port {
1630 #address-cells = <1>;
1631 #size-cells = <0>;
f7a29e30 1632
d3f51f49
JC		 1633 vopl_out_mipi: endpoint@0 {
1634 reg = <0>;
1635 remote-endpoint = <&mipi_in_vopl>;
1636 };
1637
f7a29e30
YY		 1638 vopl_out_edp: endpoint@1 {
1639 reg = <1>;
1640 remote-endpoint = <&edp_in_vopl>;
1641 };
1642
81e923dd
JC		 1643 vopl_out_hdmi: endpoint@2 {
1644 reg = <2>;
1645 remote-endpoint = <&hdmi_in_vopl>;
1646 };
1df5d2ab
NY		 1647
1648 vopl_out_mipi1: endpoint@3 {
1649 reg = <3>;
1650 remote-endpoint = <&mipi1_in_vopl>;
1651 };
2d3c2d56
CZ		 1652
1653 vopl_out_dp: endpoint@4 {
1654 reg = <4>;
1655 remote-endpoint = <&dp_in_vopl>;
1656 };
fbd4cc0e
MY		 1657 };
1658 };
1659
1660 vopl_mmu: iommu@ff8f3f00 {
1661 compatible = "rockchip,iommu";
1662 reg = <0x0 0xff8f3f00 0x0 0x100>;
1663 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1664 interrupt-names = "vopl_mmu";
1665 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
df3bcde7 1666 clock-names = "aclk", "iface";
fbd4cc0e
MY		 1667 power-domains = <&power RK3399_PD_VOPL>;
1668 #iommu-cells = <0>;
1669 status = "disabled";
1670 };
1671
1672 vopb: vop@ff900000 {
1673 compatible = "rockchip,rk3399-vop-big";
1674 reg = <0x0 0xff900000 0x0 0x3efc>;
1675 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1676 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1677 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1678 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1679 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1680 iommus = <&vopb_mmu>;
1681 power-domains = <&power RK3399_PD_VOPB>;
1682 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1683 reset-names = "axi", "ahb", "dclk";
1684 status = "disabled";
1685
1686 vopb_out: port {
1687 #address-cells = <1>;
1688 #size-cells = <0>;
f7a29e30
YY		 1689
1690 vopb_out_edp: endpoint@0 {
1691 reg = <0>;
1692 remote-endpoint = <&edp_in_vopb>;
1693 };
1694
d3f51f49
JC		 1695 vopb_out_mipi: endpoint@1 {
1696 reg = <1>;
1697 remote-endpoint = <&mipi_in_vopb>;
1698 };
1699
81e923dd
JC		 1700 vopb_out_hdmi: endpoint@2 {
1701 reg = <2>;
1702 remote-endpoint = <&hdmi_in_vopb>;
1703 };
1df5d2ab
NY		 1704
1705 vopb_out_mipi1: endpoint@3 {
1706 reg = <3>;
1707 remote-endpoint = <&mipi1_in_vopb>;
1708 };
2d3c2d56
CZ		 1709
1710 vopb_out_dp: endpoint@4 {
1711 reg = <4>;
1712 remote-endpoint = <&dp_in_vopb>;
1713 };
fbd4cc0e
MY		 1714 };
1715 };
1716
1717 vopb_mmu: iommu@ff903f00 {
1718 compatible = "rockchip,iommu";
1719 reg = <0x0 0xff903f00 0x0 0x100>;
1720 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1721 interrupt-names = "vopb_mmu";
1722 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
df3bcde7 1723 clock-names = "aclk", "iface";
fbd4cc0e
MY		 1724 power-domains = <&power RK3399_PD_VOPB>;
1725 #iommu-cells = <0>;
1726 status = "disabled";
1727 };
1728
97a0115c
SZ		 1729 isp0: isp0@ff910000 {
1730 compatible = "rockchip,rk3399-cif-isp";
1731 reg = <0x0 0xff910000 0x0 0x4000>;
1732 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1733 clocks = <&cru SCLK_ISP0>,
1734 <&cru ACLK_ISP0_WRAPPER>,
1735 <&cru HCLK_ISP0_WRAPPER>;
1736 clock-names = "isp", "aclk", "hclk";
1737 iommus = <&isp0_mmu>;
1738 phys = <&mipi_dphy_rx0>;
1739 phy-names = "dphy";
1740 power-domains = <&power RK3399_PD_ISP0>;
1741 status = "disabled";
1742
1743 ports {
1744 #address-cells = <1>;
1745 #size-cells = <0>;
1746
1747 port@0 {
1748 reg = <0>;
1749 #address-cells = <1>;
1750 #size-cells = <0>;
1751 };
1752 };
1753 };
1754
ae4fdcca
SX		 1755 isp0_mmu: iommu@ff914000 {
1756 compatible = "rockchip,iommu";
1757 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1758 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1759 interrupt-names = "isp0_mmu";
c432a29d 1760 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
df3bcde7 1761 clock-names = "aclk", "iface";
ae4fdcca 1762 #iommu-cells = <0>;
c432a29d 1763 power-domains = <&power RK3399_PD_ISP0>;
ae4fdcca 1764 rockchip,disable-mmu-reset;
ae4fdcca
SX		 1765 };
1766
1767 isp1_mmu: iommu@ff924000 {
1768 compatible = "rockchip,iommu";
1769 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1770 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1771 interrupt-names = "isp1_mmu";
c432a29d 1772 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
df3bcde7 1773 clock-names = "aclk", "iface";
ae4fdcca 1774 #iommu-cells = <0>;
c432a29d 1775 power-domains = <&power RK3399_PD_ISP1>;
ae4fdcca 1776 rockchip,disable-mmu-reset;
ae4fdcca
SX		 1777 };
1778
0d60d48c
VB		 1779 hdmi_sound: hdmi-sound {
1780 compatible = "simple-audio-card";
1781 simple-audio-card,format = "i2s";
1782 simple-audio-card,mclk-fs = <256>;
1783 simple-audio-card,name = "hdmi-sound";
1784 status = "disabled";
1785
1786 simple-audio-card,cpu {
1787 sound-dai = <&i2s2>;
1788 };
1789 simple-audio-card,codec {
1790 sound-dai = <&hdmi>;
1791 };
1792 };
1793
81e923dd
JC		 1794 hdmi: hdmi@ff940000 {
1795 compatible = "rockchip,rk3399-dw-hdmi";
1796 reg = <0x0 0xff940000 0x0 0x20000>;
1797 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
db2fd26d
PHH		 1798 clocks = <&cru PCLK_HDMI_CTRL>,
1799 <&cru SCLK_HDMI_SFR>,
1800 <&cru PLL_VPLL>,
1801 <&cru PCLK_VIO_GRF>,
1802 <&cru SCLK_HDMI_CEC>;
1803 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
81e923dd
JC		 1804 power-domains = <&power RK3399_PD_HDCP>;
1805 reg-io-width = <4>;
1806 rockchip,grf = <&grf>;
0d60d48c 1807 #sound-dai-cells = <0>;
81e923dd
JC		 1808 status = "disabled";
1809
1810 ports {
1811 hdmi_in: port {
1812 #address-cells = <1>;
1813 #size-cells = <0>;
1814
1815 hdmi_in_vopb: endpoint@0 {
1816 reg = <0>;
1817 remote-endpoint = <&vopb_out_hdmi>;
1818 };
1819 hdmi_in_vopl: endpoint@1 {
1820 reg = <1>;
1821 remote-endpoint = <&vopl_out_hdmi>;
1822 };
1823 };
1824 };
1825 };
1826
d3f51f49
JC		 1827 mipi_dsi: mipi@ff960000 {
1828 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1829 reg = <0x0 0xff960000 0x0 0x8000>;
1830 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
bb4e6ff0 1831 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
0bc15d85
NY		 1832 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1833 clock-names = "ref", "pclk", "phy_cfg", "grf";
d3f51f49 1834 power-domains = <&power RK3399_PD_VIO>;
3813a10a
BN		 1835 resets = <&cru SRST_P_MIPI_DSI0>;
1836 reset-names = "apb";
d3f51f49 1837 rockchip,grf = <&grf>;
91e75bde
HS		 1838 #address-cells = <1>;
1839 #size-cells = <0>;
d3f51f49
JC		 1840 status = "disabled";
1841
1842 ports {
c856cb5d
NY		 1843 #address-cells = <1>;
1844 #size-cells = <0>;
1845
1846 mipi_in: port@0 {
1847 reg = <0>;
d3f51f49
JC		 1848 #address-cells = <1>;
1849 #size-cells = <0>;
1850
1851 mipi_in_vopb: endpoint@0 {
1852 reg = <0>;
1853 remote-endpoint = <&vopb_out_mipi>;
1854 };
1855 mipi_in_vopl: endpoint@1 {
1856 reg = <1>;
1857 remote-endpoint = <&vopl_out_mipi>;
1858 };
1859 };
1860 };
1861 };
1862
1df5d2ab
NY		 1863 mipi_dsi1: mipi@ff968000 {
1864 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1865 reg = <0x0 0xff968000 0x0 0x8000>;
1866 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1867 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1868 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1869 clock-names = "ref", "pclk", "phy_cfg", "grf";
1870 power-domains = <&power RK3399_PD_VIO>;
1871 resets = <&cru SRST_P_MIPI_DSI1>;
1872 reset-names = "apb";
1873 rockchip,grf = <&grf>;
91e75bde
HS		 1874 #address-cells = <1>;
1875 #size-cells = <0>;
1df5d2ab
NY		 1876 status = "disabled";
1877
1878 ports {
1879 #address-cells = <1>;
1880 #size-cells = <0>;
1881
1882 mipi1_in: port@0 {
1883 reg = <0>;
1884 #address-cells = <1>;
1885 #size-cells = <0>;
1886
1887 mipi1_in_vopb: endpoint@0 {
1888 reg = <0>;
1889 remote-endpoint = <&vopb_out_mipi1>;
1890 };
1891
1892 mipi1_in_vopl: endpoint@1 {
1893 reg = <1>;
1894 remote-endpoint = <&vopl_out_mipi1>;
1895 };
1896 };
1897 };
1898 };
1899
f7a29e30
YY		 1900 edp: edp@ff970000 {
1901 compatible = "rockchip,rk3399-edp";
1902 reg = <0x0 0xff970000 0x0 0x8000>;
1903 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
7b0390ea
YY		 1904 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1905 clock-names = "dp", "pclk", "grf";
f7a29e30
YY		 1906 pinctrl-names = "default";
1907 pinctrl-0 = <&edp_hpd>;
1908 power-domains = <&power RK3399_PD_EDP>;
1909 resets = <&cru SRST_P_EDP_CTRL>;
1910 reset-names = "dp";
1911 rockchip,grf = <&grf>;
1912 status = "disabled";
1913
1914 ports {
1915 #address-cells = <1>;
1916 #size-cells = <0>;
1917 edp_in: port@0 {
1918 reg = <0>;
1919 #address-cells = <1>;
1920 #size-cells = <0>;
1921
1922 edp_in_vopb: endpoint@0 {
1923 reg = <0>;
1924 remote-endpoint = <&vopb_out_edp>;
1925 };
1926
1927 edp_in_vopl: endpoint@1 {
1928 reg = <1>;
1929 remote-endpoint = <&vopl_out_edp>;
1930 };
1931 };
1932 };
1933 };
1934
68d19331
CW		 1935 gpu: gpu@ff9a0000 {
1936 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1937 reg = <0x0 0xff9a0000 0x0 0x10000>;
c604fd81
JJ		 1938 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1939 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1940 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1941 interrupt-names = "job", "mmu", "gpu";
68d19331 1942 clocks = <&cru ACLK_GPU>;
36be9111 1943 #cooling-cells = <2>;
68d19331 1944 power-domains = <&power RK3399_PD_GPU>;
f048b9a4
JX		 1945 status = "disabled";
1946 };
1947
1948 pinctrl: pinctrl {
1949 compatible = "rockchip,rk3399-pinctrl";
1950 rockchip,grf = <&grf>;
1951 rockchip,pmu = <&pmugrf>;
1952 #address-cells = <2>;
1953 #size-cells = <2>;
1954 ranges;
1955
1956 gpio0: gpio0@ff720000 {
1957 compatible = "rockchip,gpio-bank";
1958 reg = <0x0 0xff720000 0x0 0x100>;
1959 clocks = <&pmucru PCLK_GPIO0_PMU>;
210bbd38 1960 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1961
1962 gpio-controller;
1963 #gpio-cells = <0x2>;
1964
1965 interrupt-controller;
1966 #interrupt-cells = <0x2>;
1967 };
1968
1969 gpio1: gpio1@ff730000 {
1970 compatible = "rockchip,gpio-bank";
1971 reg = <0x0 0xff730000 0x0 0x100>;
1972 clocks = <&pmucru PCLK_GPIO1_PMU>;
210bbd38 1973 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1974
1975 gpio-controller;
1976 #gpio-cells = <0x2>;
1977
1978 interrupt-controller;
1979 #interrupt-cells = <0x2>;
1980 };
1981
1982 gpio2: gpio2@ff780000 {
1983 compatible = "rockchip,gpio-bank";
1984 reg = <0x0 0xff780000 0x0 0x100>;
1985 clocks = <&cru PCLK_GPIO2>;
210bbd38 1986 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1987
1988 gpio-controller;
1989 #gpio-cells = <0x2>;
1990
1991 interrupt-controller;
1992 #interrupt-cells = <0x2>;
1993 };
1994
1995 gpio3: gpio3@ff788000 {
1996 compatible = "rockchip,gpio-bank";
1997 reg = <0x0 0xff788000 0x0 0x100>;
1998 clocks = <&cru PCLK_GPIO3>;
210bbd38 1999 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2000
2001 gpio-controller;
2002 #gpio-cells = <0x2>;
2003
2004 interrupt-controller;
2005 #interrupt-cells = <0x2>;
2006 };
2007
2008 gpio4: gpio4@ff790000 {
2009 compatible = "rockchip,gpio-bank";
2010 reg = <0x0 0xff790000 0x0 0x100>;
2011 clocks = <&cru PCLK_GPIO4>;
210bbd38 2012 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2013
2014 gpio-controller;
2015 #gpio-cells = <0x2>;
2016
2017 interrupt-controller;
2018 #interrupt-cells = <0x2>;
2019 };
2020
2021 pcfg_pull_up: pcfg-pull-up {
2022 bias-pull-up;
2023 };
2024
2025 pcfg_pull_down: pcfg-pull-down {
2026 bias-pull-down;
2027 };
2028
2029 pcfg_pull_none: pcfg-pull-none {
2030 bias-disable;
2031 };
2032
2033 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2034 bias-disable;
2035 drive-strength = <12>;
2036 };
2037
b4102328
RL		 2038 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2039 bias-disable;
2040 drive-strength = <13>;
2041 };
2042
2043 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2044 bias-disable;
2045 drive-strength = <18>;
2046 };
2047
2048 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2049 bias-disable;
2050 drive-strength = <20>;
2051 };
2052
2053 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2054 bias-pull-up;
2055 drive-strength = <2>;
2056 };
2057
f048b9a4
JX		 2058 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2059 bias-pull-up;
2060 drive-strength = <8>;
2061 };
2062
b4102328
RL		 2063 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2064 bias-pull-up;
2065 drive-strength = <18>;
2066 };
2067
2068 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2069 bias-pull-up;
2070 drive-strength = <20>;
2071 };
2072
f048b9a4
JX		 2073 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2074 bias-pull-down;
2075 drive-strength = <4>;
2076 };
2077
b4102328
RL		 2078 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2079 bias-pull-down;
2080 drive-strength = <8>;
f048b9a4
JX		 2081 };
2082
2083 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2084 bias-pull-down;
2085 drive-strength = <12>;
2086 };
2087
b4102328
RL		 2088 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2089 bias-pull-down;
2090 drive-strength = <18>;
2091 };
2092
2093 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2094 bias-pull-down;
2095 drive-strength = <20>;
2096 };
2097
2098 pcfg_output_high: pcfg-output-high {
2099 output-high;
2100 };
2101
2102 pcfg_output_low: pcfg-output-low {
2103 output-low;
f048b9a4
JX		 2104 };
2105
a8bcaea7
DA		 2106 clock {
2107 clk_32k: clk-32k {
d64420e8 2108 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
a8bcaea7
DA		 2109 };
2110 };
2111
8742466a
BN		 2112 edp {
2113 edp_hpd: edp-hpd {
2114 rockchip,pins =
d64420e8 2115 <4 RK_PC7 2 &pcfg_pull_none>;
8742466a
BN		 2116 };
2117 };
2118
eb3a6a6a
RC		 2119 gmac {
2120 rgmii_pins: rgmii-pins {
2121 rockchip,pins =
2122 /* mac_txclk */
d64420e8 2123 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2124 /* mac_rxclk */
d64420e8 2125 <3 RK_PB6 1 &pcfg_pull_none>,
eb3a6a6a 2126 /* mac_mdio */
d64420e8 2127 <3 RK_PB5 1 &pcfg_pull_none>,
eb3a6a6a 2128 /* mac_txen */
d64420e8 2129 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2130 /* mac_clk */
d64420e8 2131 <3 RK_PB3 1 &pcfg_pull_none>,
eb3a6a6a 2132 /* mac_rxdv */
d64420e8 2133 <3 RK_PB1 1 &pcfg_pull_none>,
eb3a6a6a 2134 /* mac_mdc */
d64420e8 2135 <3 RK_PB0 1 &pcfg_pull_none>,
eb3a6a6a 2136 /* mac_rxd1 */
d64420e8 2137 <3 RK_PA7 1 &pcfg_pull_none>,
eb3a6a6a 2138 /* mac_rxd0 */
d64420e8 2139 <3 RK_PA6 1 &pcfg_pull_none>,
eb3a6a6a 2140 /* mac_txd1 */
d64420e8 2141 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2142 /* mac_txd0 */
d64420e8 2143 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2144 /* mac_rxd3 */
d64420e8 2145 <3 RK_PA3 1 &pcfg_pull_none>,
eb3a6a6a 2146 /* mac_rxd2 */
d64420e8 2147 <3 RK_PA2 1 &pcfg_pull_none>,
eb3a6a6a 2148 /* mac_txd3 */
d64420e8 2149 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2150 /* mac_txd2 */
d64420e8 2151 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
eb3a6a6a
RC		 2152 };
2153
2154 rmii_pins: rmii-pins {
2155 rockchip,pins =
2156 /* mac_mdio */
d64420e8 2157 <3 RK_PB5 1 &pcfg_pull_none>,
eb3a6a6a 2158 /* mac_txen */
d64420e8 2159 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2160 /* mac_clk */
d64420e8 2161 <3 RK_PB3 1 &pcfg_pull_none>,
eb3a6a6a 2162 /* mac_rxer */
d64420e8 2163 <3 RK_PB2 1 &pcfg_pull_none>,
eb3a6a6a 2164 /* mac_rxdv */
d64420e8 2165 <3 RK_PB1 1 &pcfg_pull_none>,
eb3a6a6a 2166 /* mac_mdc */
d64420e8 2167 <3 RK_PB0 1 &pcfg_pull_none>,
eb3a6a6a 2168 /* mac_rxd1 */
d64420e8 2169 <3 RK_PA7 1 &pcfg_pull_none>,
eb3a6a6a 2170 /* mac_rxd0 */
d64420e8 2171 <3 RK_PA6 1 &pcfg_pull_none>,
eb3a6a6a 2172 /* mac_txd1 */
d64420e8 2173 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2174 /* mac_txd0 */
d64420e8 2175 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
eb3a6a6a
RC		 2176 };
2177 };
2178
f048b9a4
JX		 2179 i2c0 {
2180 i2c0_xfer: i2c0-xfer {
2181 rockchip,pins =
d64420e8
HS		 2182 <1 RK_PB7 2 &pcfg_pull_none>,
2183 <1 RK_PC0 2 &pcfg_pull_none>;
f048b9a4
JX		 2184 };
2185 };
2186
2187 i2c1 {
2188 i2c1_xfer: i2c1-xfer {
2189 rockchip,pins =
d64420e8
HS		 2190 <4 RK_PA2 1 &pcfg_pull_none>,
2191 <4 RK_PA1 1 &pcfg_pull_none>;
f048b9a4
JX		 2192 };
2193 };
2194
2195 i2c2 {
2196 i2c2_xfer: i2c2-xfer {
2197 rockchip,pins =
d64420e8
HS		 2198 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2199 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
f048b9a4
JX		 2200 };
2201 };
2202
2203 i2c3 {
2204 i2c3_xfer: i2c3-xfer {
2205 rockchip,pins =
d64420e8
HS		 2206 <4 RK_PC1 1 &pcfg_pull_none>,
2207 <4 RK_PC0 1 &pcfg_pull_none>;
f048b9a4
JX		 2208 };
2209 };
2210
2211 i2c4 {
2212 i2c4_xfer: i2c4-xfer {
2213 rockchip,pins =
d64420e8
HS		 2214 <1 RK_PB4 1 &pcfg_pull_none>,
2215 <1 RK_PB3 1 &pcfg_pull_none>;
f048b9a4
JX		 2216 };
2217 };
2218
2219 i2c5 {
2220 i2c5_xfer: i2c5-xfer {
2221 rockchip,pins =
d64420e8
HS		 2222 <3 RK_PB3 2 &pcfg_pull_none>,
2223 <3 RK_PB2 2 &pcfg_pull_none>;
f048b9a4
JX		 2224 };
2225 };
2226
2227 i2c6 {
2228 i2c6_xfer: i2c6-xfer {
2229 rockchip,pins =
d64420e8
HS		 2230 <2 RK_PB2 2 &pcfg_pull_none>,
2231 <2 RK_PB1 2 &pcfg_pull_none>;
f048b9a4
JX		 2232 };
2233 };
2234
2235 i2c7 {
2236 i2c7_xfer: i2c7-xfer {
2237 rockchip,pins =
d64420e8
HS		 2238 <2 RK_PB0 2 &pcfg_pull_none>,
2239 <2 RK_PA7 2 &pcfg_pull_none>;
f048b9a4
JX		 2240 };
2241 };
2242
2243 i2c8 {
2244 i2c8_xfer: i2c8-xfer {
2245 rockchip,pins =
d64420e8
HS		 2246 <1 RK_PC5 1 &pcfg_pull_none>,
2247 <1 RK_PC4 1 &pcfg_pull_none>;
f048b9a4
JX		 2248 };
2249 };
2250
2251 i2s0 {
0efaf807
KG		 2252 i2s0_2ch_bus: i2s0-2ch-bus {
2253 rockchip,pins =
d64420e8
HS		 2254 <3 RK_PD0 1 &pcfg_pull_none>,
2255 <3 RK_PD1 1 &pcfg_pull_none>,
2256 <3 RK_PD2 1 &pcfg_pull_none>,
2257 <3 RK_PD3 1 &pcfg_pull_none>,
2258 <3 RK_PD7 1 &pcfg_pull_none>,
2259 <4 RK_PA0 1 &pcfg_pull_none>;
0efaf807
KG		 2260 };
2261
f048b9a4
JX		 2262 i2s0_8ch_bus: i2s0-8ch-bus {
2263 rockchip,pins =
d64420e8
HS		 2264 <3 RK_PD0 1 &pcfg_pull_none>,
2265 <3 RK_PD1 1 &pcfg_pull_none>,
2266 <3 RK_PD2 1 &pcfg_pull_none>,
2267 <3 RK_PD3 1 &pcfg_pull_none>,
2268 <3 RK_PD4 1 &pcfg_pull_none>,
2269 <3 RK_PD5 1 &pcfg_pull_none>,
2270 <3 RK_PD6 1 &pcfg_pull_none>,
2271 <3 RK_PD7 1 &pcfg_pull_none>,
2272 <4 RK_PA0 1 &pcfg_pull_none>;
f048b9a4
JX		 2273 };
2274 };
2275
2276 i2s1 {
2277 i2s1_2ch_bus: i2s1-2ch-bus {
2278 rockchip,pins =
d64420e8
HS		 2279 <4 RK_PA3 1 &pcfg_pull_none>,
2280 <4 RK_PA4 1 &pcfg_pull_none>,
2281 <4 RK_PA5 1 &pcfg_pull_none>,
2282 <4 RK_PA6 1 &pcfg_pull_none>,
2283 <4 RK_PA7 1 &pcfg_pull_none>;
f048b9a4
JX		 2284 };
2285 };
2286
b74a2e98
KY		 2287 sdio0 {
2288 sdio0_bus1: sdio0-bus1 {
2289 rockchip,pins =
d64420e8 2290 <2 RK_PC4 1 &pcfg_pull_up>;
b74a2e98
KY		 2291 };
2292
2293 sdio0_bus4: sdio0-bus4 {
2294 rockchip,pins =
d64420e8
HS		 2295 <2 RK_PC4 1 &pcfg_pull_up>,
2296 <2 RK_PC5 1 &pcfg_pull_up>,
2297 <2 RK_PC6 1 &pcfg_pull_up>,
2298 <2 RK_PC7 1 &pcfg_pull_up>;
b74a2e98
KY		 2299 };
2300
2301 sdio0_cmd: sdio0-cmd {
2302 rockchip,pins =
d64420e8 2303 <2 RK_PD0 1 &pcfg_pull_up>;
b74a2e98
KY		 2304 };
2305
2306 sdio0_clk: sdio0-clk {
2307 rockchip,pins =
d64420e8 2308 <2 RK_PD1 1 &pcfg_pull_none>;
b74a2e98
KY		 2309 };
2310
2311 sdio0_cd: sdio0-cd {
2312 rockchip,pins =
d64420e8 2313 <2 RK_PD2 1 &pcfg_pull_up>;
b74a2e98
KY		 2314 };
2315
2316 sdio0_pwr: sdio0-pwr {
2317 rockchip,pins =
d64420e8 2318 <2 RK_PD3 1 &pcfg_pull_up>;
b74a2e98
KY		 2319 };
2320
2321 sdio0_bkpwr: sdio0-bkpwr {
2322 rockchip,pins =
d64420e8 2323 <2 RK_PD4 1 &pcfg_pull_up>;
b74a2e98
KY		 2324 };
2325
2326 sdio0_wp: sdio0-wp {
2327 rockchip,pins =
d64420e8 2328 <0 RK_PA3 1 &pcfg_pull_up>;
b74a2e98
KY		 2329 };
2330
2331 sdio0_int: sdio0-int {
2332 rockchip,pins =
d64420e8 2333 <0 RK_PA4 1 &pcfg_pull_up>;
b74a2e98
KY		 2334 };
2335 };
2336
2337 sdmmc {
2338 sdmmc_bus1: sdmmc-bus1 {
2339 rockchip,pins =
d64420e8 2340 <4 RK_PB0 1 &pcfg_pull_up>;
b74a2e98
KY		 2341 };
2342
2343 sdmmc_bus4: sdmmc-bus4 {
2344 rockchip,pins =
d64420e8
HS		 2345 <4 RK_PB0 1 &pcfg_pull_up>,
2346 <4 RK_PB1 1 &pcfg_pull_up>,
2347 <4 RK_PB2 1 &pcfg_pull_up>,
2348 <4 RK_PB3 1 &pcfg_pull_up>;
b74a2e98
KY		 2349 };
2350
2351 sdmmc_clk: sdmmc-clk {
2352 rockchip,pins =
d64420e8 2353 <4 RK_PB4 1 &pcfg_pull_none>;
b74a2e98
KY		 2354 };
2355
2356 sdmmc_cmd: sdmmc-cmd {
2357 rockchip,pins =
d64420e8 2358 <4 RK_PB5 1 &pcfg_pull_up>;
b74a2e98
KY		 2359 };
2360
6122308e 2361 sdmmc_cd: sdmmc-cd {
b74a2e98 2362 rockchip,pins =
d64420e8 2363 <0 RK_PA7 1 &pcfg_pull_up>;
b74a2e98
KY		 2364 };
2365
2366 sdmmc_wp: sdmmc-wp {
2367 rockchip,pins =
d64420e8 2368 <0 RK_PB0 1 &pcfg_pull_up>;
b74a2e98
KY		 2369 };
2370 };
2371
5d26ad9c
DA		 2372 sleep {
2373 ap_pwroff: ap-pwroff {
d64420e8 2374 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
5d26ad9c
DA		 2375 };
2376
2377 ddrio_pwroff: ddrio-pwroff {
d64420e8 2378 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
5d26ad9c
DA		 2379 };
2380 };
2381
f048b9a4
JX		 2382 spdif {
2383 spdif_bus: spdif-bus {
2384 rockchip,pins =
d64420e8 2385 <4 RK_PC5 1 &pcfg_pull_none>;
f048b9a4 2386 };
b74a2e98
KY		 2387
2388 spdif_bus_1: spdif-bus-1 {
2389 rockchip,pins =
d64420e8 2390 <3 RK_PC0 3 &pcfg_pull_none>;
b74a2e98 2391 };
f048b9a4
JX		 2392 };
2393
2394 spi0 {
2395 spi0_clk: spi0-clk {
2396 rockchip,pins =
d64420e8 2397 <3 RK_PA6 2 &pcfg_pull_up>;
f048b9a4
JX		 2398 };
2399 spi0_cs0: spi0-cs0 {
2400 rockchip,pins =
d64420e8 2401 <3 RK_PA7 2 &pcfg_pull_up>;
f048b9a4
JX		 2402 };
2403 spi0_cs1: spi0-cs1 {
2404 rockchip,pins =
d64420e8 2405 <3 RK_PB0 2 &pcfg_pull_up>;
f048b9a4
JX		 2406 };
2407 spi0_tx: spi0-tx {
2408 rockchip,pins =
d64420e8 2409 <3 RK_PA5 2 &pcfg_pull_up>;
f048b9a4
JX		 2410 };
2411 spi0_rx: spi0-rx {
2412 rockchip,pins =
d64420e8 2413 <3 RK_PA4 2 &pcfg_pull_up>;
f048b9a4
JX		 2414 };
2415 };
2416
2417 spi1 {
2418 spi1_clk: spi1-clk {
2419 rockchip,pins =
d64420e8 2420 <1 RK_PB1 2 &pcfg_pull_up>;
f048b9a4
JX		 2421 };
2422 spi1_cs0: spi1-cs0 {
2423 rockchip,pins =
d64420e8 2424 <1 RK_PB2 2 &pcfg_pull_up>;
f048b9a4
JX		 2425 };
2426 spi1_rx: spi1-rx {
2427 rockchip,pins =
d64420e8 2428 <1 RK_PA7 2 &pcfg_pull_up>;
f048b9a4
JX		 2429 };
2430 spi1_tx: spi1-tx {
2431 rockchip,pins =
d64420e8 2432 <1 RK_PB0 2 &pcfg_pull_up>;
f048b9a4
JX		 2433 };
2434 };
2435
2436 spi2 {
2437 spi2_clk: spi2-clk {
2438 rockchip,pins =
d64420e8 2439 <2 RK_PB3 1 &pcfg_pull_up>;
f048b9a4
JX		 2440 };
2441 spi2_cs0: spi2-cs0 {
2442 rockchip,pins =
d64420e8 2443 <2 RK_PB4 1 &pcfg_pull_up>;
f048b9a4
JX		 2444 };
2445 spi2_rx: spi2-rx {
2446 rockchip,pins =
d64420e8 2447 <2 RK_PB1 1 &pcfg_pull_up>;
f048b9a4
JX		 2448 };
2449 spi2_tx: spi2-tx {
2450 rockchip,pins =
d64420e8 2451 <2 RK_PB2 1 &pcfg_pull_up>;
f048b9a4
JX		 2452 };
2453 };
2454
2455 spi3 {
2456 spi3_clk: spi3-clk {
2457 rockchip,pins =
d64420e8 2458 <1 RK_PC1 1 &pcfg_pull_up>;
f048b9a4
JX		 2459 };
2460 spi3_cs0: spi3-cs0 {
2461 rockchip,pins =
d64420e8 2462 <1 RK_PC2 1 &pcfg_pull_up>;
f048b9a4
JX		 2463 };
2464 spi3_rx: spi3-rx {
2465 rockchip,pins =
d64420e8 2466 <1 RK_PB7 1 &pcfg_pull_up>;
f048b9a4
JX		 2467 };
2468 spi3_tx: spi3-tx {
2469 rockchip,pins =
d64420e8 2470 <1 RK_PC0 1 &pcfg_pull_up>;
f048b9a4
JX		 2471 };
2472 };
2473
2474 spi4 {
2475 spi4_clk: spi4-clk {
2476 rockchip,pins =
d64420e8 2477 <3 RK_PA2 2 &pcfg_pull_up>;
f048b9a4
JX		 2478 };
2479 spi4_cs0: spi4-cs0 {
2480 rockchip,pins =
d64420e8 2481 <3 RK_PA3 2 &pcfg_pull_up>;
f048b9a4
JX		 2482 };
2483 spi4_rx: spi4-rx {
2484 rockchip,pins =
d64420e8 2485 <3 RK_PA0 2 &pcfg_pull_up>;
f048b9a4
JX		 2486 };
2487 spi4_tx: spi4-tx {
2488 rockchip,pins =
d64420e8 2489 <3 RK_PA1 2 &pcfg_pull_up>;
f048b9a4
JX		 2490 };
2491 };
2492
2493 spi5 {
2494 spi5_clk: spi5-clk {
2495 rockchip,pins =
d64420e8 2496 <2 RK_PC6 2 &pcfg_pull_up>;
f048b9a4
JX		 2497 };
2498 spi5_cs0: spi5-cs0 {
2499 rockchip,pins =
d64420e8 2500 <2 RK_PC7 2 &pcfg_pull_up>;
f048b9a4
JX		 2501 };
2502 spi5_rx: spi5-rx {
2503 rockchip,pins =
d64420e8 2504 <2 RK_PC4 2 &pcfg_pull_up>;
f048b9a4
JX		 2505 };
2506 spi5_tx: spi5-tx {
2507 rockchip,pins =
d64420e8 2508 <2 RK_PC5 2 &pcfg_pull_up>;
f048b9a4
JX		 2509 };
2510 };
2511
ba2b043e
SZ		 2512 testclk {
2513 test_clkout0: test-clkout0 {
2514 rockchip,pins =
d64420e8 2515 <0 RK_PA0 1 &pcfg_pull_none>;
ba2b043e
SZ		 2516 };
2517
2518 test_clkout1: test-clkout1 {
2519 rockchip,pins =
d64420e8 2520 <2 RK_PD1 2 &pcfg_pull_none>;
ba2b043e
SZ		 2521 };
2522
2523 test_clkout2: test-clkout2 {
2524 rockchip,pins =
d64420e8 2525 <0 RK_PB0 3 &pcfg_pull_none>;
ba2b043e
SZ		 2526 };
2527 };
2528
95c27ba7 2529 tsadc {
2bc65fef 2530 otp_pin: otp-pin {
d64420e8 2531 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
95c27ba7
CW		 2532 };
2533
2534 otp_out: otp-out {
d64420e8 2535 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
95c27ba7
CW		 2536 };
2537 };
2538
f048b9a4
JX		 2539 uart0 {
2540 uart0_xfer: uart0-xfer {
2541 rockchip,pins =
d64420e8
HS		 2542 <2 RK_PC0 1 &pcfg_pull_up>,
2543 <2 RK_PC1 1 &pcfg_pull_none>;
f048b9a4
JX		 2544 };
2545
2546 uart0_cts: uart0-cts {
2547 rockchip,pins =
d64420e8 2548 <2 RK_PC2 1 &pcfg_pull_none>;
f048b9a4
JX		 2549 };
2550
2551 uart0_rts: uart0-rts {
2552 rockchip,pins =
d64420e8 2553 <2 RK_PC3 1 &pcfg_pull_none>;
f048b9a4
JX		 2554 };
2555 };
2556
2557 uart1 {
2558 uart1_xfer: uart1-xfer {
2559 rockchip,pins =
d64420e8
HS		 2560 <3 RK_PB4 2 &pcfg_pull_up>,
2561 <3 RK_PB5 2 &pcfg_pull_none>;
f048b9a4
JX		 2562 };
2563 };
2564
2565 uart2a {
2566 uart2a_xfer: uart2a-xfer {
2567 rockchip,pins =
d64420e8
HS		 2568 <4 RK_PB0 2 &pcfg_pull_up>,
2569 <4 RK_PB1 2 &pcfg_pull_none>;
f048b9a4
JX		 2570 };
2571 };
2572
2573 uart2b {
2574 uart2b_xfer: uart2b-xfer {
2575 rockchip,pins =
d64420e8
HS		 2576 <4 RK_PC0 2 &pcfg_pull_up>,
2577 <4 RK_PC1 2 &pcfg_pull_none>;
f048b9a4
JX		 2578 };
2579 };
2580
2581 uart2c {
2582 uart2c_xfer: uart2c-xfer {
2583 rockchip,pins =
d64420e8
HS		 2584 <4 RK_PC3 1 &pcfg_pull_up>,
2585 <4 RK_PC4 1 &pcfg_pull_none>;
f048b9a4
JX		 2586 };
2587 };
2588
2589 uart3 {
2590 uart3_xfer: uart3-xfer {
2591 rockchip,pins =
d64420e8
HS		 2592 <3 RK_PB6 2 &pcfg_pull_up>,
2593 <3 RK_PB7 2 &pcfg_pull_none>;
f048b9a4
JX		 2594 };
2595
2596 uart3_cts: uart3-cts {
2597 rockchip,pins =
40a0dd42 2598 <3 RK_PC0 2 &pcfg_pull_none>;
f048b9a4
JX		 2599 };
2600
2601 uart3_rts: uart3-rts {
2602 rockchip,pins =
40a0dd42 2603 <3 RK_PC1 2 &pcfg_pull_none>;
f048b9a4
JX		 2604 };
2605 };
2606
2607 uart4 {
2608 uart4_xfer: uart4-xfer {
2609 rockchip,pins =
d64420e8
HS		 2610 <1 RK_PA7 1 &pcfg_pull_up>,
2611 <1 RK_PB0 1 &pcfg_pull_none>;
f048b9a4
JX		 2612 };
2613 };
2614
2615 uarthdcp {
2616 uarthdcp_xfer: uarthdcp-xfer {
2617 rockchip,pins =
d64420e8
HS		 2618 <4 RK_PC5 2 &pcfg_pull_up>,
2619 <4 RK_PC6 2 &pcfg_pull_none>;
f048b9a4
JX		 2620 };
2621 };
2622
2623 pwm0 {
2624 pwm0_pin: pwm0-pin {
2625 rockchip,pins =
d64420e8 2626 <4 RK_PC2 1 &pcfg_pull_none>;
b4102328
RL		 2627 };
2628
2629 pwm0_pin_pull_down: pwm0-pin-pull-down {
2630 rockchip,pins =
d64420e8 2631 <4 RK_PC2 1 &pcfg_pull_down>;
f048b9a4
JX		 2632 };
2633
2634 vop0_pwm_pin: vop0-pwm-pin {
2635 rockchip,pins =
d64420e8 2636 <4 RK_PC2 2 &pcfg_pull_none>;
b4102328
RL		 2637 };
2638
2639 vop1_pwm_pin: vop1-pwm-pin {
2640 rockchip,pins =
d64420e8 2641 <4 RK_PC2 3 &pcfg_pull_none>;
f048b9a4
JX		 2642 };
2643 };
2644
2645 pwm1 {
2646 pwm1_pin: pwm1-pin {
2647 rockchip,pins =
d64420e8 2648 <4 RK_PC6 1 &pcfg_pull_none>;
f048b9a4
JX		 2649 };
2650
b4102328 2651 pwm1_pin_pull_down: pwm1-pin-pull-down {
f048b9a4 2652 rockchip,pins =
d64420e8 2653 <4 RK_PC6 1 &pcfg_pull_down>;
f048b9a4
JX		 2654 };
2655 };
2656
2657 pwm2 {
2658 pwm2_pin: pwm2-pin {
2659 rockchip,pins =
d64420e8 2660 <1 RK_PC3 1 &pcfg_pull_none>;
b4102328
RL		 2661 };
2662
2663 pwm2_pin_pull_down: pwm2-pin-pull-down {
2664 rockchip,pins =
d64420e8 2665 <1 RK_PC3 1 &pcfg_pull_down>;
f048b9a4
JX		 2666 };
2667 };
2668
2669 pwm3a {
2670 pwm3a_pin: pwm3a-pin {
2671 rockchip,pins =
d64420e8 2672 <0 RK_PA6 1 &pcfg_pull_none>;
f048b9a4
JX		 2673 };
2674 };
2675
2676 pwm3b {
2677 pwm3b_pin: pwm3b-pin {
2678 rockchip,pins =
d64420e8 2679 <1 RK_PB6 1 &pcfg_pull_none>;
f048b9a4
JX		 2680 };
2681 };
85aaa574 2682
b74a2e98
KY		 2683 hdmi {
2684 hdmi_i2c_xfer: hdmi-i2c-xfer {
2685 rockchip,pins =
d64420e8
HS		 2686 <4 RK_PC1 3 &pcfg_pull_none>,
2687 <4 RK_PC0 3 &pcfg_pull_none>;
b74a2e98
KY		 2688 };
2689
2690 hdmi_cec: hdmi-cec {
2691 rockchip,pins =
d64420e8 2692 <4 RK_PC7 1 &pcfg_pull_none>;
b74a2e98
KY		 2693 };
2694 };
2695
85aaa574 2696 pcie {
b74a2e98
KY		 2697 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2698 rockchip,pins =
2699 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2700 };
2701
2702 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2703 rockchip,pins =
2704 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2705 };
85aaa574
SL		 2706 };
2707
f048b9a4
JX		 2708 };
2709};
Linux 6.x block layer and io_uring tree(s)