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arm64: dts: rockchip: Fix power-controller node names for rk3328
[linux-block.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
CommitLineData
4ee99ceb 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
f048b9a4
JX		 2/*
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
f048b9a4
JX		 4 */
5
6#include <dt-bindings/clock/rk3399-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
807a2371 11#include <dt-bindings/power/rk3399-power.h>
95c27ba7 12#include <dt-bindings/thermal/thermal.h>
f048b9a4
JX		 13
14/ {
15 compatible = "rockchip,rk3399";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
2eca8411 22 ethernet0 = &gmac;
69e5a8fe
DW		 23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
f048b9a4
JX		 32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
38
39 cpus {
40 #address-cells = <2>;
41 #size-cells = <0>;
42
43 cpu-map {
44 cluster0 {
45 core0 {
46 cpu = <&cpu_l0>;
47 };
48 core1 {
49 cpu = <&cpu_l1>;
50 };
51 core2 {
52 cpu = <&cpu_l2>;
53 };
54 core3 {
55 cpu = <&cpu_l3>;
56 };
57 };
58
59 cluster1 {
60 core0 {
61 cpu = <&cpu_b0>;
62 };
63 core1 {
64 cpu = <&cpu_b1>;
65 };
66 };
67 };
68
69 cpu_l0: cpu@0 {
70 device_type = "cpu";
31af04cd 71 compatible = "arm,cortex-a53";
f048b9a4
JX		 72 reg = <0x0 0x0>;
73 enable-method = "psci";
97df3aa7 74 capacity-dmips-mhz = <485>;
f048b9a4 75 clocks = <&cru ARMCLKL>;
cc9b0918 76 #cooling-cells = <2>; /* min followed by max */
f4697bd7 77 dynamic-power-coefficient = <100>;
f888da16 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 79 };
80
81 cpu_l1: cpu@1 {
82 device_type = "cpu";
31af04cd 83 compatible = "arm,cortex-a53";
f048b9a4
JX		 84 reg = <0x0 0x1>;
85 enable-method = "psci";
97df3aa7 86 capacity-dmips-mhz = <485>;
f048b9a4 87 clocks = <&cru ARMCLKL>;
cc9b0918 88 #cooling-cells = <2>; /* min followed by max */
f4697bd7 89 dynamic-power-coefficient = <100>;
f888da16 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 91 };
92
93 cpu_l2: cpu@2 {
94 device_type = "cpu";
31af04cd 95 compatible = "arm,cortex-a53";
f048b9a4
JX		 96 reg = <0x0 0x2>;
97 enable-method = "psci";
97df3aa7 98 capacity-dmips-mhz = <485>;
f048b9a4 99 clocks = <&cru ARMCLKL>;
cc9b0918 100 #cooling-cells = <2>; /* min followed by max */
f4697bd7 101 dynamic-power-coefficient = <100>;
f888da16 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 103 };
104
105 cpu_l3: cpu@3 {
106 device_type = "cpu";
31af04cd 107 compatible = "arm,cortex-a53";
f048b9a4
JX		 108 reg = <0x0 0x3>;
109 enable-method = "psci";
97df3aa7 110 capacity-dmips-mhz = <485>;
f048b9a4 111 clocks = <&cru ARMCLKL>;
cc9b0918 112 #cooling-cells = <2>; /* min followed by max */
f4697bd7 113 dynamic-power-coefficient = <100>;
f888da16 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 115 };
116
117 cpu_b0: cpu@100 {
118 device_type = "cpu";
31af04cd 119 compatible = "arm,cortex-a72";
f048b9a4
JX		 120 reg = <0x0 0x100>;
121 enable-method = "psci";
97df3aa7 122 capacity-dmips-mhz = <1024>;
f048b9a4 123 clocks = <&cru ARMCLKB>;
cc9b0918 124 #cooling-cells = <2>; /* min followed by max */
45a995c0 125 dynamic-power-coefficient = <436>;
f888da16 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 127 };
128
129 cpu_b1: cpu@101 {
130 device_type = "cpu";
31af04cd 131 compatible = "arm,cortex-a72";
f048b9a4
JX		 132 reg = <0x0 0x101>;
133 enable-method = "psci";
97df3aa7 134 capacity-dmips-mhz = <1024>;
f048b9a4 135 clocks = <&cru ARMCLKB>;
cc9b0918 136 #cooling-cells = <2>; /* min followed by max */
45a995c0 137 dynamic-power-coefficient = <436>;
f888da16
TX		 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
139 };
140
141 idle-states {
142 entry-method = "psci";
143
144 CPU_SLEEP: cpu-sleep {
145 compatible = "arm,idle-state";
146 local-timer-stop;
147 arm,psci-suspend-param = <0x0010000>;
148 entry-latency-us = <120>;
149 exit-latency-us = <250>;
150 min-residency-us = <900>;
151 };
152
153 CLUSTER_SLEEP: cluster-sleep {
154 compatible = "arm,idle-state";
155 local-timer-stop;
156 arm,psci-suspend-param = <0x1010000>;
157 entry-latency-us = <400>;
158 exit-latency-us = <500>;
159 min-residency-us = <2000>;
160 };
f048b9a4
JX		 161 };
162 };
163
fbd4cc0e
MY		 164 display-subsystem {
165 compatible = "rockchip,display-subsystem";
166 ports = <&vopl_out>, <&vopb_out>;
167 };
168
6840eb0d
CW		 169 pmu_a53 {
170 compatible = "arm,cortex-a53-pmu";
171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
172 };
173
174 pmu_a72 {
175 compatible = "arm,cortex-a72-pmu";
176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
177 };
178
f048b9a4
JX		 179 psci {
180 compatible = "arm,psci-1.0";
181 method = "smc";
182 };
183
184 timer {
185 compatible = "arm,armv8-timer";
210bbd38
CW		 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
e6186820 190 arm,no-tick-in-suspend;
f048b9a4
JX		 191 };
192
193 xin24m: xin24m {
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
197 #clock-cells = <0>;
198 };
199
66aef3cb
BN		 200 pcie0: pcie@f8000000 {
201 compatible = "rockchip,rk3399-pcie";
202 reg = <0x0 0xf8000000 0x0 0x2000000>,
203 <0x0 0xfd000000 0x0 0x1000000>;
204 reg-names = "axi-base", "apb-base";
43f20b1c 205 device_type = "pci";
66aef3cb
BN		 206 #address-cells = <3>;
207 #size-cells = <2>;
208 #interrupt-cells = <1>;
209 aspm-no-l0s;
d633becc 210 bus-range = <0x0 0x1f>;
66aef3cb
BN		 211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
213 clock-names = "aclk", "aclk-perf",
214 "hclk", "pm";
215 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
218 interrupt-names = "sys", "legacy", "client";
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
221 <0 0 0 2 &pcie0_intc 1>,
222 <0 0 0 3 &pcie0_intc 2>,
223 <0 0 0 4 &pcie0_intc 3>;
224 max-link-speed = <1>;
225 msi-map = <0x0 &its 0x0 0x1000>;
e9a60cac
SL		 226 phys = <&pcie_phy 0>, <&pcie_phy 1>,
227 <&pcie_phy 2>, <&pcie_phy 3>;
228 phy-names = "pcie-phy-0", "pcie-phy-1",
229 "pcie-phy-2", "pcie-phy-3";
5b931210
JJ		 230 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
231 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
66aef3cb
BN		 232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
233 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
234 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
235 <&cru SRST_A_PCIE>;
236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
237 "pm", "pclk", "aclk";
238 status = "disabled";
239
240 pcie0_intc: interrupt-controller {
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <1>;
244 };
245 };
246
eb3a6a6a
RC		 247 gmac: ethernet@fe300000 {
248 compatible = "rockchip,rk3399-gmac";
249 reg = <0x0 0xfe300000 0x0 0x10000>;
250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
251 interrupt-names = "macirq";
252 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
253 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
254 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
255 <&cru PCLK_GMAC>;
256 clock-names = "stmmaceth", "mac_clk_rx",
257 "mac_clk_tx", "clk_mac_ref",
258 "clk_mac_refout", "aclk_mac",
259 "pclk_mac";
260 power-domains = <&power RK3399_PD_GMAC>;
261 resets = <&cru SRST_A_GMAC>;
262 reset-names = "stmmaceth";
263 rockchip,grf = <&grf>;
8a469ee3 264 snps,txpbl = <0x4>;
eb3a6a6a
RC		 265 status = "disabled";
266 };
267
3ef7c255 268 sdio0: mmc@fe310000 {
f048b9a4
JX		 269 compatible = "rockchip,rk3399-dw-mshc",
270 "rockchip,rk3288-dw-mshc";
271 reg = <0x0 0xfe310000 0x0 0x4000>;
210bbd38 272 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 273 max-frequency = <150000000>;
f048b9a4
JX		 274 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
275 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
277 fifo-depth = <0x100>;
b0f2110a 278 power-domains = <&power RK3399_PD_SDIOAUDIO>;
04dc7f62
HS		 279 resets = <&cru SRST_SDIO0>;
280 reset-names = "reset";
f048b9a4
JX		 281 status = "disabled";
282 };
283
3ef7c255 284 sdmmc: mmc@fe320000 {
f048b9a4
JX		 285 compatible = "rockchip,rk3399-dw-mshc",
286 "rockchip,rk3288-dw-mshc";
287 reg = <0x0 0xfe320000 0x0 0x4000>;
210bbd38 288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 289 max-frequency = <150000000>;
e702e13f
LH		 290 assigned-clocks = <&cru HCLK_SD>;
291 assigned-clock-rates = <200000000>;
f048b9a4
JX		 292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
295 fifo-depth = <0x100>;
1bc60bee 296 power-domains = <&power RK3399_PD_SD>;
04dc7f62
HS		 297 resets = <&cru SRST_SDMMC>;
298 reset-names = "reset";
f048b9a4
JX		 299 status = "disabled";
300 };
301
9a9f6427 302 sdhci: mmc@fe330000 {
b4e87c09
BN		 303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
304 reg = <0x0 0xfe330000 0x0 0x10000>;
210bbd38 305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
64e3481c 306 arasan,soc-ctl-syscon = <&grf>;
b4e87c09
BN		 307 assigned-clocks = <&cru SCLK_EMMC>;
308 assigned-clock-rates = <200000000>;
309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
310 clock-names = "clk_xin", "clk_ahb";
ed388cdd
DA		 311 clock-output-names = "emmc_cardclock";
312 #clock-cells = <0>;
b4e87c09
BN		 313 phys = <&emmc_phy>;
314 phy-names = "phy_arasan";
a1907df2 315 power-domains = <&power RK3399_PD_EMMC>;
a3eec13b 316 disable-cqe-dcmd;
b4e87c09
BN		 317 status = "disabled";
318 };
319
f048b9a4
JX		 320 usb_host0_ehci: usb@fe380000 {
321 compatible = "generic-ehci";
322 reg = <0x0 0xfe380000 0x0 0x20000>;
210bbd38 323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
325 <&u2phy0>;
103e9f85
FW		 326 phys = <&u2phy0_host>;
327 phy-names = "usb";
f048b9a4
JX		 328 status = "disabled";
329 };
330
331 usb_host0_ohci: usb@fe3a0000 {
332 compatible = "generic-ohci";
333 reg = <0x0 0xfe3a0000 0x0 0x20000>;
210bbd38 334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
336 <&u2phy0>;
b5d1c572
W		 337 phys = <&u2phy0_host>;
338 phy-names = "usb";
f048b9a4
JX		 339 status = "disabled";
340 };
341
342 usb_host1_ehci: usb@fe3c0000 {
343 compatible = "generic-ehci";
344 reg = <0x0 0xfe3c0000 0x0 0x20000>;
210bbd38 345 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 346 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
347 <&u2phy1>;
103e9f85
FW		 348 phys = <&u2phy1_host>;
349 phy-names = "usb";
f048b9a4
JX		 350 status = "disabled";
351 };
352
353 usb_host1_ohci: usb@fe3e0000 {
354 compatible = "generic-ohci";
355 reg = <0x0 0xfe3e0000 0x0 0x20000>;
210bbd38 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
358 <&u2phy1>;
b5d1c572
W		 359 phys = <&u2phy1_host>;
360 phy-names = "usb";
f048b9a4
JX		 361 status = "disabled";
362 };
363
7144224f
BN		 364 usbdrd3_0: usb@fe800000 {
365 compatible = "rockchip,rk3399-dwc3";
366 #address-cells = <2>;
367 #size-cells = <2>;
368 ranges;
369 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
9df8a2d9
EBS		 370 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
371 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 372 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 373 "bus_clk", "aclk_usb3_rksoc_axi_perf",
374 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 375 resets = <&cru SRST_A_USB3_OTG0>;
376 reset-names = "usb3-otg";
7144224f
BN		 377 status = "disabled";
378
190c7f6f 379 usbdrd_dwc3_0: usb@fe800000 {
7144224f
BN		 380 compatible = "snps,dwc3";
381 reg = <0x0 0xfe800000 0x0 0x100000>;
382 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
e6d237fd
EBS		 383 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
384 <&cru SCLK_USB3OTG0_SUSPEND>;
385 clock-names = "ref", "bus_early", "suspend";
7144224f 386 dr_mode = "otg";
bfdca173
EBS		 387 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
388 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 389 phy_type = "utmi_wide";
390 snps,dis_enblslpm_quirk;
391 snps,dis-u2-freeclk-exists-quirk;
392 snps,dis_u2_susphy_quirk;
393 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 394 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 395 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 396 status = "disabled";
397 };
398 };
399
400 usbdrd3_1: usb@fe900000 {
401 compatible = "rockchip,rk3399-dwc3";
402 #address-cells = <2>;
403 #size-cells = <2>;
404 ranges;
405 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
9df8a2d9
EBS		 406 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
407 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 408 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 409 "bus_clk", "aclk_usb3_rksoc_axi_perf",
410 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 411 resets = <&cru SRST_A_USB3_OTG1>;
412 reset-names = "usb3-otg";
7144224f
BN		 413 status = "disabled";
414
190c7f6f 415 usbdrd_dwc3_1: usb@fe900000 {
7144224f
BN		 416 compatible = "snps,dwc3";
417 reg = <0x0 0xfe900000 0x0 0x100000>;
418 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
e6d237fd
EBS		 419 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
420 <&cru SCLK_USB3OTG1_SUSPEND>;
421 clock-names = "ref", "bus_early", "suspend";
7144224f 422 dr_mode = "otg";
bfdca173
EBS		 423 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
424 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 425 phy_type = "utmi_wide";
426 snps,dis_enblslpm_quirk;
427 snps,dis-u2-freeclk-exists-quirk;
428 snps,dis_u2_susphy_quirk;
429 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 430 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 431 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 432 status = "disabled";
433 };
434 };
435
2d3c2d56
CZ		 436 cdn_dp: dp@fec00000 {
437 compatible = "rockchip,rk3399-cdn-dp";
438 reg = <0x0 0xfec00000 0x0 0x100000>;
439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
e702e13f
LH		 440 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
441 assigned-clock-rates = <100000000>, <200000000>;
2d3c2d56
CZ		 442 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
443 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
444 clock-names = "core-clk", "pclk", "spdif", "grf";
445 phys = <&tcphy0_dp>, <&tcphy1_dp>;
446 power-domains = <&power RK3399_PD_HDCP>;
447 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
448 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
449 reset-names = "spdif", "dptx", "apb", "core";
450 rockchip,grf = <&grf>;
451 #sound-dai-cells = <1>;
452 status = "disabled";
453
454 ports {
455 dp_in: port {
456 #address-cells = <1>;
457 #size-cells = <0>;
458
459 dp_in_vopb: endpoint@0 {
460 reg = <0>;
461 remote-endpoint = <&vopb_out_dp>;
462 };
463
464 dp_in_vopl: endpoint@1 {
465 reg = <1>;
466 remote-endpoint = <&vopl_out_dp>;
467 };
468 };
469 };
470 };
471
f048b9a4
JX		 472 gic: interrupt-controller@fee00000 {
473 compatible = "arm,gic-v3";
210bbd38 474 #interrupt-cells = <4>;
f048b9a4
JX		 475 #address-cells = <2>;
476 #size-cells = <2>;
477 ranges;
478 interrupt-controller;
479
480 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
481 <0x0 0xfef00000 0 0xc0000>, /* GICR */
482 <0x0 0xfff00000 0 0x10000>, /* GICC */
483 <0x0 0xfff10000 0 0x10000>, /* GICH */
484 <0x0 0xfff20000 0 0x10000>; /* GICV */
210bbd38 485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 486 its: interrupt-controller@fee20000 {
487 compatible = "arm,gic-v3-its";
488 msi-controller;
85dd7638 489 #msi-cells = <1>;
f048b9a4
JX		 490 reg = <0x0 0xfee20000 0x0 0x20000>;
491 };
6840eb0d
CW		 492
493 ppi-partitions {
494 ppi_cluster0: interrupt-partition-0 {
495 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
496 };
497
498 ppi_cluster1: interrupt-partition-1 {
499 affinity = <&cpu_b0 &cpu_b1>;
500 };
501 };
f048b9a4
JX		 502 };
503
fe996215
CW		 504 saradc: saradc@ff100000 {
505 compatible = "rockchip,rk3399-saradc";
506 reg = <0x0 0xff100000 0x0 0x100>;
210bbd38 507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
fe996215
CW		 508 #io-channel-cells = <1>;
509 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
510 clock-names = "saradc", "apb_pclk";
511 resets = <&cru SRST_P_SARADC>;
512 reset-names = "saradc-apb";
513 status = "disabled";
514 };
515
69e5a8fe
DW		 516 i2c1: i2c@ff110000 {
517 compatible = "rockchip,rk3399-i2c";
518 reg = <0x0 0xff110000 0x0 0x1000>;
519 assigned-clocks = <&cru SCLK_I2C1>;
520 assigned-clock-rates = <200000000>;
521 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
522 clock-names = "i2c", "pclk";
210bbd38 523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c1_xfer>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 status = "disabled";
529 };
530
531 i2c2: i2c@ff120000 {
532 compatible = "rockchip,rk3399-i2c";
533 reg = <0x0 0xff120000 0x0 0x1000>;
534 assigned-clocks = <&cru SCLK_I2C2>;
535 assigned-clock-rates = <200000000>;
536 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
537 clock-names = "i2c", "pclk";
210bbd38 538 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c2_xfer>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
545
546 i2c3: i2c@ff130000 {
547 compatible = "rockchip,rk3399-i2c";
548 reg = <0x0 0xff130000 0x0 0x1000>;
549 assigned-clocks = <&cru SCLK_I2C3>;
550 assigned-clock-rates = <200000000>;
551 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
552 clock-names = "i2c", "pclk";
210bbd38 553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c3_xfer>;
556 #address-cells = <1>;
557 #size-cells = <0>;
558 status = "disabled";
559 };
560
561 i2c5: i2c@ff140000 {
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff140000 0x0 0x1000>;
564 assigned-clocks = <&cru SCLK_I2C5>;
565 assigned-clock-rates = <200000000>;
566 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
567 clock-names = "i2c", "pclk";
210bbd38 568 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c5_xfer>;
571 #address-cells = <1>;
572 #size-cells = <0>;
573 status = "disabled";
574 };
575
576 i2c6: i2c@ff150000 {
577 compatible = "rockchip,rk3399-i2c";
578 reg = <0x0 0xff150000 0x0 0x1000>;
579 assigned-clocks = <&cru SCLK_I2C6>;
580 assigned-clock-rates = <200000000>;
581 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
582 clock-names = "i2c", "pclk";
210bbd38 583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c6_xfer>;
586 #address-cells = <1>;
587 #size-cells = <0>;
588 status = "disabled";
589 };
590
591 i2c7: i2c@ff160000 {
592 compatible = "rockchip,rk3399-i2c";
593 reg = <0x0 0xff160000 0x0 0x1000>;
594 assigned-clocks = <&cru SCLK_I2C7>;
595 assigned-clock-rates = <200000000>;
596 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
597 clock-names = "i2c", "pclk";
210bbd38 598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c7_xfer>;
601 #address-cells = <1>;
602 #size-cells = <0>;
603 status = "disabled";
604 };
605
f048b9a4
JX		 606 uart0: serial@ff180000 {
607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
608 reg = <0x0 0xff180000 0x0 0x100>;
609 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
610 clock-names = "baudclk", "apb_pclk";
210bbd38 611 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 612 reg-shift = <2>;
613 reg-io-width = <4>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&uart0_xfer>;
616 status = "disabled";
617 };
618
619 uart1: serial@ff190000 {
620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
621 reg = <0x0 0xff190000 0x0 0x100>;
622 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
623 clock-names = "baudclk", "apb_pclk";
210bbd38 624 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 625 reg-shift = <2>;
626 reg-io-width = <4>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&uart1_xfer>;
629 status = "disabled";
630 };
631
632 uart2: serial@ff1a0000 {
633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
634 reg = <0x0 0xff1a0000 0x0 0x100>;
635 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
636 clock-names = "baudclk", "apb_pclk";
210bbd38 637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 638 reg-shift = <2>;
639 reg-io-width = <4>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&uart2c_xfer>;
642 status = "disabled";
643 };
644
645 uart3: serial@ff1b0000 {
646 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
647 reg = <0x0 0xff1b0000 0x0 0x100>;
648 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
649 clock-names = "baudclk", "apb_pclk";
210bbd38 650 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 651 reg-shift = <2>;
652 reg-io-width = <4>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&uart3_xfer>;
655 status = "disabled";
656 };
657
658 spi0: spi@ff1c0000 {
659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
660 reg = <0x0 0xff1c0000 0x0 0x1000>;
661 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
662 clock-names = "spiclk", "apb_pclk";
210bbd38 663 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 664 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
665 dma-names = "tx", "rx";
f048b9a4
JX		 666 pinctrl-names = "default";
667 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
668 #address-cells = <1>;
669 #size-cells = <0>;
670 status = "disabled";
671 };
672
673 spi1: spi@ff1d0000 {
674 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
675 reg = <0x0 0xff1d0000 0x0 0x1000>;
676 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
677 clock-names = "spiclk", "apb_pclk";
210bbd38 678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 679 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
680 dma-names = "tx", "rx";
f048b9a4
JX		 681 pinctrl-names = "default";
682 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
683 #address-cells = <1>;
684 #size-cells = <0>;
685 status = "disabled";
686 };
687
688 spi2: spi@ff1e0000 {
689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
690 reg = <0x0 0xff1e0000 0x0 0x1000>;
691 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
692 clock-names = "spiclk", "apb_pclk";
210bbd38 693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 694 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
695 dma-names = "tx", "rx";
f048b9a4
JX		 696 pinctrl-names = "default";
697 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
698 #address-cells = <1>;
699 #size-cells = <0>;
700 status = "disabled";
701 };
702
703 spi4: spi@ff1f0000 {
704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
705 reg = <0x0 0xff1f0000 0x0 0x1000>;
706 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
707 clock-names = "spiclk", "apb_pclk";
210bbd38 708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 709 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
710 dma-names = "tx", "rx";
f048b9a4
JX		 711 pinctrl-names = "default";
712 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
713 #address-cells = <1>;
714 #size-cells = <0>;
715 status = "disabled";
716 };
717
718 spi5: spi@ff200000 {
719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
720 reg = <0x0 0xff200000 0x0 0x1000>;
721 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
722 clock-names = "spiclk", "apb_pclk";
210bbd38 723 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 724 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
725 dma-names = "tx", "rx";
f048b9a4
JX		 726 pinctrl-names = "default";
727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
b0f2110a 728 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 729 #address-cells = <1>;
730 #size-cells = <0>;
731 status = "disabled";
732 };
733
647cea2e 734 thermal_zones: thermal-zones {
e58061b5 735 cpu_thermal: cpu-thermal {
95c27ba7
CW		 736 polling-delay-passive = <100>;
737 polling-delay = <1000>;
738
739 thermal-sensors = <&tsadc 0>;
740
741 trips {
742 cpu_alert0: cpu_alert0 {
743 temperature = <70000>;
744 hysteresis = <2000>;
745 type = "passive";
746 };
747 cpu_alert1: cpu_alert1 {
748 temperature = <75000>;
749 hysteresis = <2000>;
750 type = "passive";
751 };
752 cpu_crit: cpu_crit {
753 temperature = <95000>;
754 hysteresis = <2000>;
755 type = "critical";
756 };
757 };
758
759 cooling-maps {
760 map0 {
761 trip = <&cpu_alert0>;
762 cooling-device =
cdd46460
VK		 763 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
764 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
95c27ba7
CW		 765 };
766 map1 {
767 trip = <&cpu_alert1>;
768 cooling-device =
769 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cdd46460
VK		 770 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
771 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
772 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
773 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
774 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
95c27ba7
CW		 775 };
776 };
777 };
778
e58061b5 779 gpu_thermal: gpu-thermal {
95c27ba7
CW		 780 polling-delay-passive = <100>;
781 polling-delay = <1000>;
782
783 thermal-sensors = <&tsadc 1>;
784
785 trips {
786 gpu_alert0: gpu_alert0 {
787 temperature = <75000>;
788 hysteresis = <2000>;
789 type = "passive";
790 };
791 gpu_crit: gpu_crit {
792 temperature = <95000>;
793 hysteresis = <2000>;
794 type = "critical";
795 };
796 };
36be9111
RM		 797
798 cooling-maps {
799 map0 {
800 trip = <&gpu_alert0>;
801 cooling-device =
802 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
803 };
804 };
95c27ba7
CW		 805 };
806 };
807
808 tsadc: tsadc@ff260000 {
809 compatible = "rockchip,rk3399-tsadc";
810 reg = <0x0 0xff260000 0x0 0x100>;
210bbd38 811 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
95c27ba7
CW		 812 assigned-clocks = <&cru SCLK_TSADC>;
813 assigned-clock-rates = <750000>;
814 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
815 clock-names = "tsadc", "apb_pclk";
816 resets = <&cru SRST_TSADC>;
817 reset-names = "tsadc-apb";
818 rockchip,grf = <&grf>;
819 rockchip,hw-tshut-temp = <95000>;
820 pinctrl-names = "init", "default", "sleep";
2bc65fef 821 pinctrl-0 = <&otp_pin>;
95c27ba7 822 pinctrl-1 = <&otp_out>;
2bc65fef 823 pinctrl-2 = <&otp_pin>;
95c27ba7
CW		 824 #thermal-sensor-cells = <1>;
825 status = "disabled";
826 };
827
a1907df2 828 qos_emmc: qos@ffa58000 {
bd3fd049 829 compatible = "rockchip,rk3399-qos", "syscon";
a1907df2
EZ		 830 reg = <0x0 0xffa58000 0x0 0x20>;
831 };
832
d43c97a5 833 qos_gmac: qos@ffa5c000 {
bd3fd049 834 compatible = "rockchip,rk3399-qos", "syscon";
d43c97a5
CW		 835 reg = <0x0 0xffa5c000 0x0 0x20>;
836 };
837
65f1e902 838 qos_pcie: qos@ffa60080 {
bd3fd049 839 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 840 reg = <0x0 0xffa60080 0x0 0x20>;
841 };
842
843 qos_usb_host0: qos@ffa60100 {
bd3fd049 844 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 845 reg = <0x0 0xffa60100 0x0 0x20>;
846 };
847
848 qos_usb_host1: qos@ffa60180 {
bd3fd049 849 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 850 reg = <0x0 0xffa60180 0x0 0x20>;
851 };
852
853 qos_usb_otg0: qos@ffa70000 {
bd3fd049 854 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 855 reg = <0x0 0xffa70000 0x0 0x20>;
856 };
857
858 qos_usb_otg1: qos@ffa70080 {
bd3fd049 859 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 860 reg = <0x0 0xffa70080 0x0 0x20>;
861 };
862
863 qos_sd: qos@ffa74000 {
bd3fd049 864 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 865 reg = <0x0 0xffa74000 0x0 0x20>;
866 };
867
868 qos_sdioaudio: qos@ffa76000 {
bd3fd049 869 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 870 reg = <0x0 0xffa76000 0x0 0x20>;
871 };
872
807a2371 873 qos_hdcp: qos@ffa90000 {
bd3fd049 874 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 875 reg = <0x0 0xffa90000 0x0 0x20>;
876 };
877
878 qos_iep: qos@ffa98000 {
bd3fd049 879 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 880 reg = <0x0 0xffa98000 0x0 0x20>;
881 };
882
883 qos_isp0_m0: qos@ffaa0000 {
bd3fd049 884 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 885 reg = <0x0 0xffaa0000 0x0 0x20>;
886 };
887
888 qos_isp0_m1: qos@ffaa0080 {
bd3fd049 889 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 890 reg = <0x0 0xffaa0080 0x0 0x20>;
891 };
892
893 qos_isp1_m0: qos@ffaa8000 {
bd3fd049 894 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 895 reg = <0x0 0xffaa8000 0x0 0x20>;
896 };
897
898 qos_isp1_m1: qos@ffaa8080 {
bd3fd049 899 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 900 reg = <0x0 0xffaa8080 0x0 0x20>;
901 };
902
903 qos_rga_r: qos@ffab0000 {
bd3fd049 904 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 905 reg = <0x0 0xffab0000 0x0 0x20>;
906 };
907
908 qos_rga_w: qos@ffab0080 {
bd3fd049 909 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 910 reg = <0x0 0xffab0080 0x0 0x20>;
911 };
912
913 qos_video_m0: qos@ffab8000 {
bd3fd049 914 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 915 reg = <0x0 0xffab8000 0x0 0x20>;
916 };
917
918 qos_video_m1_r: qos@ffac0000 {
bd3fd049 919 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 920 reg = <0x0 0xffac0000 0x0 0x20>;
921 };
922
923 qos_video_m1_w: qos@ffac0080 {
bd3fd049 924 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 925 reg = <0x0 0xffac0080 0x0 0x20>;
926 };
927
928 qos_vop_big_r: qos@ffac8000 {
bd3fd049 929 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 930 reg = <0x0 0xffac8000 0x0 0x20>;
931 };
932
933 qos_vop_big_w: qos@ffac8080 {
bd3fd049 934 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 935 reg = <0x0 0xffac8080 0x0 0x20>;
936 };
937
938 qos_vop_little: qos@ffad0000 {
bd3fd049 939 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 940 reg = <0x0 0xffad0000 0x0 0x20>;
941 };
942
65f1e902 943 qos_perihp: qos@ffad8080 {
bd3fd049 944 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 945 reg = <0x0 0xffad8080 0x0 0x20>;
946 };
947
807a2371 948 qos_gpu: qos@ffae0000 {
bd3fd049 949 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 950 reg = <0x0 0xffae0000 0x0 0x20>;
951 };
952
953 pmu: power-management@ff310000 {
954 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
955 reg = <0x0 0xff310000 0x0 0x1000>;
956
957 /*
958 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
959 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
960 * Some of the power domains are grouped together for every
961 * voltage domain.
962 * The detail contents as below.
963 */
964 power: power-controller {
965 compatible = "rockchip,rk3399-power-controller";
966 #power-domain-cells = <1>;
967 #address-cells = <1>;
968 #size-cells = <0>;
969
970 /* These power domains are grouped by VD_CENTER */
971 pd_iep@RK3399_PD_IEP {
972 reg = <RK3399_PD_IEP>;
973 clocks = <&cru ACLK_IEP>,
974 <&cru HCLK_IEP>;
975 pm_qos = <&qos_iep>;
976 };
977 pd_rga@RK3399_PD_RGA {
978 reg = <RK3399_PD_RGA>;
979 clocks = <&cru ACLK_RGA>,
980 <&cru HCLK_RGA>;
981 pm_qos = <&qos_rga_r>,
982 <&qos_rga_w>;
983 };
984 pd_vcodec@RK3399_PD_VCODEC {
985 reg = <RK3399_PD_VCODEC>;
986 clocks = <&cru ACLK_VCODEC>,
987 <&cru HCLK_VCODEC>;
988 pm_qos = <&qos_video_m0>;
989 };
990 pd_vdu@RK3399_PD_VDU {
991 reg = <RK3399_PD_VDU>;
992 clocks = <&cru ACLK_VDU>,
993 <&cru HCLK_VDU>;
994 pm_qos = <&qos_video_m1_r>,
995 <&qos_video_m1_w>;
996 };
997
998 /* These power domains are grouped by VD_GPU */
999 pd_gpu@RK3399_PD_GPU {
1000 reg = <RK3399_PD_GPU>;
1001 clocks = <&cru ACLK_GPU>;
1002 pm_qos = <&qos_gpu>;
1003 };
1004
1005 /* These power domains are grouped by VD_LOGIC */
3cf04a4e
EZ		 1006 pd_edp@RK3399_PD_EDP {
1007 reg = <RK3399_PD_EDP>;
1008 clocks = <&cru PCLK_EDP_CTRL>;
1009 };
a1907df2
EZ		 1010 pd_emmc@RK3399_PD_EMMC {
1011 reg = <RK3399_PD_EMMC>;
1012 clocks = <&cru ACLK_EMMC>;
1013 pm_qos = <&qos_emmc>;
1014 };
d43c97a5
CW		 1015 pd_gmac@RK3399_PD_GMAC {
1016 reg = <RK3399_PD_GMAC>;
2afc1db0
JC		 1017 clocks = <&cru ACLK_GMAC>,
1018 <&cru PCLK_GMAC>;
d43c97a5
CW		 1019 pm_qos = <&qos_gmac>;
1020 };
1bc60bee
EZ		 1021 pd_sd@RK3399_PD_SD {
1022 reg = <RK3399_PD_SD>;
1023 clocks = <&cru HCLK_SDMMC>,
1024 <&cru SCLK_SDMMC>;
1025 pm_qos = <&qos_sd>;
1026 };
b0f2110a
CW		 1027 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1028 reg = <RK3399_PD_SDIOAUDIO>;
1029 clocks = <&cru HCLK_SDIO>;
1030 pm_qos = <&qos_sdioaudio>;
1031 };
2b99e619
JJ		 1032 pd_tcpc0@RK3399_PD_TCPD0 {
1033 reg = <RK3399_PD_TCPD0>;
1034 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1035 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1036 };
1037 pd_tcpc1@RK3399_PD_TCPD1 {
1038 reg = <RK3399_PD_TCPD1>;
1039 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1040 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1041 };
a1bbaaa4
EBS		 1042 pd_usb3@RK3399_PD_USB3 {
1043 reg = <RK3399_PD_USB3>;
1044 clocks = <&cru ACLK_USB3>;
1045 pm_qos = <&qos_usb_otg0>,
1046 <&qos_usb_otg1>;
1047 };
807a2371
EZ		 1048 pd_vio@RK3399_PD_VIO {
1049 reg = <RK3399_PD_VIO>;
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052
1053 pd_hdcp@RK3399_PD_HDCP {
1054 reg = <RK3399_PD_HDCP>;
1055 clocks = <&cru ACLK_HDCP>,
1056 <&cru HCLK_HDCP>,
1057 <&cru PCLK_HDCP>;
1058 pm_qos = <&qos_hdcp>;
1059 };
1060 pd_isp0@RK3399_PD_ISP0 {
1061 reg = <RK3399_PD_ISP0>;
1062 clocks = <&cru ACLK_ISP0>,
1063 <&cru HCLK_ISP0>;
1064 pm_qos = <&qos_isp0_m0>,
1065 <&qos_isp0_m1>;
1066 };
1067 pd_isp1@RK3399_PD_ISP1 {
1068 reg = <RK3399_PD_ISP1>;
1069 clocks = <&cru ACLK_ISP1>,
1070 <&cru HCLK_ISP1>;
1071 pm_qos = <&qos_isp1_m0>,
1072 <&qos_isp1_m1>;
1073 };
1074 pd_vo@RK3399_PD_VO {
1075 reg = <RK3399_PD_VO>;
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1078
1079 pd_vopb@RK3399_PD_VOPB {
1080 reg = <RK3399_PD_VOPB>;
1081 clocks = <&cru ACLK_VOP0>,
1082 <&cru HCLK_VOP0>;
1083 pm_qos = <&qos_vop_big_r>,
1084 <&qos_vop_big_w>;
1085 };
1086 pd_vopl@RK3399_PD_VOPL {
1087 reg = <RK3399_PD_VOPL>;
1088 clocks = <&cru ACLK_VOP1>,
1089 <&cru HCLK_VOP1>;
1090 pm_qos = <&qos_vop_little>;
1091 };
1092 };
1093 };
1094 };
1095 };
1096
f048b9a4 1097 pmugrf: syscon@ff320000 {
16759262 1098 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
f048b9a4 1099 reg = <0x0 0xff320000 0x0 0x1000>;
6d0e3a45
HS		 1100
1101 pmu_io_domains: io-domains {
1102 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1103 status = "disabled";
1104 };
f048b9a4
JX		 1105 };
1106
1107 spi3: spi@ff350000 {
1108 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1109 reg = <0x0 0xff350000 0x0 0x1000>;
1110 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1111 clock-names = "spiclk", "apb_pclk";
210bbd38 1112 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1113 pinctrl-names = "default";
1114 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 status = "disabled";
1118 };
1119
1120 uart4: serial@ff370000 {
1121 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1122 reg = <0x0 0xff370000 0x0 0x100>;
1123 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1124 clock-names = "baudclk", "apb_pclk";
210bbd38 1125 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1126 reg-shift = <2>;
1127 reg-io-width = <4>;
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&uart4_xfer>;
1130 status = "disabled";
1131 };
1132
69e5a8fe
DW		 1133 i2c0: i2c@ff3c0000 {
1134 compatible = "rockchip,rk3399-i2c";
1135 reg = <0x0 0xff3c0000 0x0 0x1000>;
1136 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1137 assigned-clock-rates = <200000000>;
1138 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1139 clock-names = "i2c", "pclk";
210bbd38 1140 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1141 pinctrl-names = "default";
1142 pinctrl-0 = <&i2c0_xfer>;
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 status = "disabled";
1146 };
1147
1148 i2c4: i2c@ff3d0000 {
1149 compatible = "rockchip,rk3399-i2c";
1150 reg = <0x0 0xff3d0000 0x0 0x1000>;
1151 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1152 assigned-clock-rates = <200000000>;
1153 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1154 clock-names = "i2c", "pclk";
210bbd38 1155 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1156 pinctrl-names = "default";
1157 pinctrl-0 = <&i2c4_xfer>;
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160 status = "disabled";
1161 };
1162
1163 i2c8: i2c@ff3e0000 {
1164 compatible = "rockchip,rk3399-i2c";
1165 reg = <0x0 0xff3e0000 0x0 0x1000>;
1166 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1167 assigned-clock-rates = <200000000>;
1168 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1169 clock-names = "i2c", "pclk";
210bbd38 1170 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1171 pinctrl-names = "default";
1172 pinctrl-0 = <&i2c8_xfer>;
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1175 status = "disabled";
f048b9a4
JX		 1176 };
1177
1178 pwm0: pwm@ff420000 {
1179 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1180 reg = <0x0 0xff420000 0x0 0x10>;
1181 #pwm-cells = <3>;
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&pwm0_pin>;
1184 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1185 status = "disabled";
1186 };
1187
1188 pwm1: pwm@ff420010 {
1189 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1190 reg = <0x0 0xff420010 0x0 0x10>;
1191 #pwm-cells = <3>;
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&pwm1_pin>;
1194 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1195 status = "disabled";
1196 };
1197
1198 pwm2: pwm@ff420020 {
1199 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1200 reg = <0x0 0xff420020 0x0 0x10>;
1201 #pwm-cells = <3>;
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&pwm2_pin>;
1204 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1205 status = "disabled";
1206 };
1207
1208 pwm3: pwm@ff420030 {
1209 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1210 reg = <0x0 0xff420030 0x0 0x10>;
1211 #pwm-cells = <3>;
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&pwm3a_pin>;
1214 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1215 status = "disabled";
1216 };
1217
5cd4c31a
EG		 1218 vpu: video-codec@ff650000 {
1219 compatible = "rockchip,rk3399-vpu";
1220 reg = <0x0 0xff650000 0x0 0x800>;
1221 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1222 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1223 interrupt-names = "vepu", "vdpu";
1224 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1225 clock-names = "aclk", "hclk";
1226 iommus = <&vpu_mmu>;
1227 power-domains = <&power RK3399_PD_VCODEC>;
1228 };
1229
ae4fdcca
SX		 1230 vpu_mmu: iommu@ff650800 {
1231 compatible = "rockchip,iommu";
1232 reg = <0x0 0xff650800 0x0 0x40>;
1233 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1234 interrupt-names = "vpu_mmu";
df3bcde7
JC		 1235 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1236 clock-names = "aclk", "iface";
ae4fdcca 1237 #iommu-cells = <0>;
5cd4c31a 1238 power-domains = <&power RK3399_PD_VCODEC>;
ae4fdcca
SX		 1239 };
1240
cbd72144
BB		 1241 vdec: video-codec@ff660000 {
1242 compatible = "rockchip,rk3399-vdec";
1243 reg = <0x0 0xff660000 0x0 0x400>;
1244 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
cbd72144
BB		 1245 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1246 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1247 clock-names = "axi", "ahb", "cabac", "core";
1248 iommus = <&vdec_mmu>;
1249 power-domains = <&power RK3399_PD_VDU>;
1250 };
1251
ae4fdcca
SX		 1252 vdec_mmu: iommu@ff660480 {
1253 compatible = "rockchip,iommu";
1254 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1255 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1256 interrupt-names = "vdec_mmu";
df3bcde7
JC		 1257 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1258 clock-names = "aclk", "iface";
cbd72144 1259 power-domains = <&power RK3399_PD_VDU>;
ae4fdcca 1260 #iommu-cells = <0>;
ae4fdcca
SX		 1261 };
1262
1263 iep_mmu: iommu@ff670800 {
1264 compatible = "rockchip,iommu";
1265 reg = <0x0 0xff670800 0x0 0x40>;
1266 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1267 interrupt-names = "iep_mmu";
df3bcde7
JC		 1268 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1269 clock-names = "aclk", "iface";
ae4fdcca
SX		 1270 #iommu-cells = <0>;
1271 status = "disabled";
1272 };
1273
ec5ccfd7
JC		 1274 rga: rga@ff680000 {
1275 compatible = "rockchip,rk3399-rga";
1276 reg = <0x0 0xff680000 0x0 0x10000>;
1277 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1278 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1279 clock-names = "aclk", "hclk", "sclk";
1280 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1281 reset-names = "core", "axi", "ahb";
1282 power-domains = <&power RK3399_PD_RGA>;
1283 };
1284
b7ee3b27
FX		 1285 efuse0: efuse@ff690000 {
1286 compatible = "rockchip,rk3399-efuse";
1287 reg = <0x0 0xff690000 0x0 0x80>;
1288 #address-cells = <1>;
1289 #size-cells = <1>;
1290 clocks = <&cru PCLK_EFUSE1024NS>;
1291 clock-names = "pclk_efuse";
1292
1293 /* Data cells */
0d326927
ZX		 1294 cpu_id: cpu-id@7 {
1295 reg = <0x07 0x10>;
1296 };
b7ee3b27
FX		 1297 cpub_leakage: cpu-leakage@17 {
1298 reg = <0x17 0x1>;
1299 };
1300 gpu_leakage: gpu-leakage@18 {
1301 reg = <0x18 0x1>;
1302 };
1303 center_leakage: center-leakage@19 {
1304 reg = <0x19 0x1>;
1305 };
1306 cpul_leakage: cpu-leakage@1a {
1307 reg = <0x1a 0x1>;
1308 };
1309 logic_leakage: logic-leakage@1b {
1310 reg = <0x1b 0x1>;
1311 };
1312 wafer_info: wafer-info@1c {
1313 reg = <0x1c 0x1>;
1314 };
1315 };
1316
9e824449
RM		 1317 dmac_bus: dma-controller@ff6d0000 {
1318 compatible = "arm,pl330", "arm,primecell";
1319 reg = <0x0 0xff6d0000 0x0 0x4000>;
1320 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1321 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1322 #dma-cells = <1>;
1323 arm,pl330-periph-burst;
1324 clocks = <&cru ACLK_DMAC0_PERILP>;
1325 clock-names = "apb_pclk";
1326 };
1327
1328 dmac_peri: dma-controller@ff6e0000 {
1329 compatible = "arm,pl330", "arm,primecell";
1330 reg = <0x0 0xff6e0000 0x0 0x4000>;
1331 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1332 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1333 #dma-cells = <1>;
1334 arm,pl330-periph-burst;
1335 clocks = <&cru ACLK_DMAC1_PERILP>;
1336 clock-names = "apb_pclk";
1337 };
1338
f048b9a4
JX		 1339 pmucru: pmu-clock-controller@ff750000 {
1340 compatible = "rockchip,rk3399-pmucru";
1341 reg = <0x0 0xff750000 0x0 0x1000>;
8cbb59af 1342 rockchip,grf = <&pmugrf>;
f048b9a4
JX		 1343 #clock-cells = <1>;
1344 #reset-cells = <1>;
1345 assigned-clocks = <&pmucru PLL_PPLL>;
1346 assigned-clock-rates = <676000000>;
1347 };
1348
1349 cru: clock-controller@ff760000 {
1350 compatible = "rockchip,rk3399-cru";
1351 reg = <0x0 0xff760000 0x0 0x1000>;
8cbb59af 1352 rockchip,grf = <&grf>;
f048b9a4
JX		 1353 #clock-cells = <1>;
1354 #reset-cells = <1>;
a09906cd
XZ		 1355 assigned-clocks =
1356 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1357 <&cru PLL_NPLL>,
1358 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1359 <&cru PCLK_PERIHP>,
1360 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
bb4b6201 1361 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
3f7f3b0f 1362 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
e702e13f
LH		 1363 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1364 <&cru ACLK_GIC_PRE>,
1365 <&cru PCLK_DDR>;
a09906cd
XZ		 1366 assigned-clock-rates =
1367 <594000000>, <800000000>,
1368 <1000000000>,
1369 <150000000>, <75000000>,
1370 <37500000>,
1371 <100000000>, <100000000>,
bb4b6201 1372 <50000000>, <600000000>,
3f7f3b0f 1373 <100000000>, <50000000>,
e702e13f
LH		 1374 <400000000>, <400000000>,
1375 <200000000>,
1376 <200000000>;
f048b9a4
JX		 1377 };
1378
1379 grf: syscon@ff770000 {
16759262 1380 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
f048b9a4 1381 reg = <0x0 0xff770000 0x0 0x10000>;
16759262
BN		 1382 #address-cells = <1>;
1383 #size-cells = <1>;
b4e87c09 1384
6d0e3a45
HS		 1385 io_domains: io-domains {
1386 compatible = "rockchip,rk3399-io-voltage-domain";
1387 status = "disabled";
1388 };
1389
e4bfde13
SZ		 1390 mipi_dphy_rx0: mipi-dphy-rx0 {
1391 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1392 clocks = <&cru SCLK_MIPIDPHY_REF>,
1393 <&cru SCLK_DPHY_RX0_CFG>,
1394 <&cru PCLK_VIO_GRF>;
1395 clock-names = "dphy-ref", "dphy-cfg", "grf";
1396 power-domains = <&power RK3399_PD_VIO>;
1397 #phy-cells = <0>;
1398 status = "disabled";
1399 };
1400
103e9f85
FW		 1401 u2phy0: usb2-phy@e450 {
1402 compatible = "rockchip,rk3399-usb2phy";
1403 reg = <0xe450 0x10>;
1404 clocks = <&cru SCLK_USB2PHY0_REF>;
1405 clock-names = "phyclk";
1406 #clock-cells = <0>;
1407 clock-output-names = "clk_usbphy0_480m";
1408 status = "disabled";
1409
1410 u2phy0_host: host-port {
1411 #phy-cells = <0>;
210bbd38 1412 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1413 interrupt-names = "linestate";
1414 status = "disabled";
1415 };
fe7f2de1
WW		 1416
1417 u2phy0_otg: otg-port {
1418 #phy-cells = <0>;
1419 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1420 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1421 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1422 interrupt-names = "otg-bvalid", "otg-id",
1423 "linestate";
1424 status = "disabled";
1425 };
103e9f85
FW		 1426 };
1427
1428 u2phy1: usb2-phy@e460 {
1429 compatible = "rockchip,rk3399-usb2phy";
1430 reg = <0xe460 0x10>;
1431 clocks = <&cru SCLK_USB2PHY1_REF>;
1432 clock-names = "phyclk";
1433 #clock-cells = <0>;
1434 clock-output-names = "clk_usbphy1_480m";
1435 status = "disabled";
1436
1437 u2phy1_host: host-port {
1438 #phy-cells = <0>;
210bbd38 1439 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1440 interrupt-names = "linestate";
1441 status = "disabled";
1442 };
fe7f2de1
WW		 1443
1444 u2phy1_otg: otg-port {
1445 #phy-cells = <0>;
1446 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1447 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1448 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1449 interrupt-names = "otg-bvalid", "otg-id",
1450 "linestate";
1451 status = "disabled";
1452 };
103e9f85
FW		 1453 };
1454
b4e87c09
BN		 1455 emmc_phy: phy@f780 {
1456 compatible = "rockchip,rk3399-emmc-phy";
1457 reg = <0xf780 0x24>;
ed388cdd
DA		 1458 clocks = <&sdhci>;
1459 clock-names = "emmcclk";
b4e87c09
BN		 1460 #phy-cells = <0>;
1461 status = "disabled";
1462 };
29a0be1c
SL		 1463
1464 pcie_phy: pcie-phy {
1465 compatible = "rockchip,rk3399-pcie-phy";
1466 clocks = <&cru SCLK_PCIEPHY_REF>;
1467 clock-names = "refclk";
e9a60cac 1468 #phy-cells = <1>;
29a0be1c 1469 resets = <&cru SRST_PCIEPHY>;
fb8b7460 1470 drive-impedance-ohm = <50>;
29a0be1c
SL		 1471 reset-names = "phy";
1472 status = "disabled";
1473 };
f048b9a4
JX		 1474 };
1475
f606193a
CZ		 1476 tcphy0: phy@ff7c0000 {
1477 compatible = "rockchip,rk3399-typec-phy";
1478 reg = <0x0 0xff7c0000 0x0 0x40000>;
1479 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1480 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1481 clock-names = "tcpdcore", "tcpdphy-ref";
1482 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1483 assigned-clock-rates = <50000000>;
06ad4b2f 1484 power-domains = <&power RK3399_PD_TCPD0>;
f606193a
CZ		 1485 resets = <&cru SRST_UPHY0>,
1486 <&cru SRST_UPHY0_PIPE_L00>,
1487 <&cru SRST_P_UPHY0_TCPHY>;
1488 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1489 rockchip,grf = <&grf>;
f606193a
CZ		 1490 status = "disabled";
1491
1492 tcphy0_dp: dp-port {
1493 #phy-cells = <0>;
1494 };
1495
1496 tcphy0_usb3: usb3-port {
1497 #phy-cells = <0>;
1498 };
1499 };
1500
1501 tcphy1: phy@ff800000 {
1502 compatible = "rockchip,rk3399-typec-phy";
1503 reg = <0x0 0xff800000 0x0 0x40000>;
1504 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1505 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1506 clock-names = "tcpdcore", "tcpdphy-ref";
1507 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1508 assigned-clock-rates = <50000000>;
06ad4b2f 1509 power-domains = <&power RK3399_PD_TCPD1>;
f606193a
CZ		 1510 resets = <&cru SRST_UPHY1>,
1511 <&cru SRST_UPHY1_PIPE_L00>,
1512 <&cru SRST_P_UPHY1_TCPHY>;
1513 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1514 rockchip,grf = <&grf>;
f606193a
CZ		 1515 status = "disabled";
1516
1517 tcphy1_dp: dp-port {
1518 #phy-cells = <0>;
1519 };
1520
1521 tcphy1_usb3: usb3-port {
1522 #phy-cells = <0>;
1523 };
1524 };
1525
0895b3a8 1526 watchdog@ff848000 {
6b5c5086 1527 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
0895b3a8 1528 reg = <0x0 0xff848000 0x0 0x100>;
f048b9a4 1529 clocks = <&cru PCLK_WDT>;
210bbd38 1530 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1531 };
1532
1e8567d5
HT		 1533 rktimer: rktimer@ff850000 {
1534 compatible = "rockchip,rk3399-timer";
1535 reg = <0x0 0xff850000 0x0 0x1000>;
210bbd38 1536 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1e8567d5
HT		 1537 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1538 clock-names = "pclk", "timer";
1539 };
1540
f048b9a4
JX		 1541 spdif: spdif@ff870000 {
1542 compatible = "rockchip,rk3399-spdif";
1543 reg = <0x0 0xff870000 0x0 0x1000>;
210bbd38 1544 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1545 dmas = <&dmac_bus 7>;
1546 dma-names = "tx";
1547 clock-names = "mclk", "hclk";
1548 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1549 pinctrl-names = "default";
1550 pinctrl-0 = <&spdif_bus>;
b0f2110a 1551 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1552 #sound-dai-cells = <0>;
f048b9a4
JX		 1553 status = "disabled";
1554 };
1555
1556 i2s0: i2s@ff880000 {
1557 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1558 reg = <0x0 0xff880000 0x0 0x1000>;
1559 rockchip,grf = <&grf>;
210bbd38 1560 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1561 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1562 dma-names = "tx", "rx";
1563 clock-names = "i2s_clk", "i2s_hclk";
1564 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&i2s0_8ch_bus>;
b0f2110a 1567 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1568 #sound-dai-cells = <0>;
f048b9a4
JX		 1569 status = "disabled";
1570 };
1571
1572 i2s1: i2s@ff890000 {
1573 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1574 reg = <0x0 0xff890000 0x0 0x1000>;
210bbd38 1575 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1576 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1577 dma-names = "tx", "rx";
1578 clock-names = "i2s_clk", "i2s_hclk";
1579 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1580 pinctrl-names = "default";
1581 pinctrl-0 = <&i2s1_2ch_bus>;
b0f2110a 1582 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1583 #sound-dai-cells = <0>;
f048b9a4
JX		 1584 status = "disabled";
1585 };
1586
1587 i2s2: i2s@ff8a0000 {
1588 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1589 reg = <0x0 0xff8a0000 0x0 0x1000>;
210bbd38 1590 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1591 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1592 dma-names = "tx", "rx";
1593 clock-names = "i2s_clk", "i2s_hclk";
1594 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
b0f2110a 1595 power-domains = <&power RK3399_PD_SDIOAUDIO>;
0d60d48c 1596 #sound-dai-cells = <0>;
f048b9a4
JX		 1597 status = "disabled";
1598 };
1599
fbd4cc0e
MY		 1600 vopl: vop@ff8f0000 {
1601 compatible = "rockchip,rk3399-vop-lit";
1602 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1603 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1604 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1605 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1606 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1607 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1608 iommus = <&vopl_mmu>;
1609 power-domains = <&power RK3399_PD_VOPL>;
1610 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1611 reset-names = "axi", "ahb", "dclk";
1612 status = "disabled";
1613
1614 vopl_out: port {
1615 #address-cells = <1>;
1616 #size-cells = <0>;
f7a29e30 1617
d3f51f49
JC		 1618 vopl_out_mipi: endpoint@0 {
1619 reg = <0>;
1620 remote-endpoint = <&mipi_in_vopl>;
1621 };
1622
f7a29e30
YY		 1623 vopl_out_edp: endpoint@1 {
1624 reg = <1>;
1625 remote-endpoint = <&edp_in_vopl>;
1626 };
1627
81e923dd
JC		 1628 vopl_out_hdmi: endpoint@2 {
1629 reg = <2>;
1630 remote-endpoint = <&hdmi_in_vopl>;
1631 };
1df5d2ab
NY		 1632
1633 vopl_out_mipi1: endpoint@3 {
1634 reg = <3>;
1635 remote-endpoint = <&mipi1_in_vopl>;
1636 };
2d3c2d56
CZ		 1637
1638 vopl_out_dp: endpoint@4 {
1639 reg = <4>;
1640 remote-endpoint = <&dp_in_vopl>;
1641 };
fbd4cc0e
MY		 1642 };
1643 };
1644
1645 vopl_mmu: iommu@ff8f3f00 {
1646 compatible = "rockchip,iommu";
1647 reg = <0x0 0xff8f3f00 0x0 0x100>;
1648 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1649 interrupt-names = "vopl_mmu";
1650 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
df3bcde7 1651 clock-names = "aclk", "iface";
fbd4cc0e
MY		 1652 power-domains = <&power RK3399_PD_VOPL>;
1653 #iommu-cells = <0>;
1654 status = "disabled";
1655 };
1656
1657 vopb: vop@ff900000 {
1658 compatible = "rockchip,rk3399-vop-big";
1659 reg = <0x0 0xff900000 0x0 0x3efc>;
1660 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1661 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1662 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1663 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1664 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1665 iommus = <&vopb_mmu>;
1666 power-domains = <&power RK3399_PD_VOPB>;
1667 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1668 reset-names = "axi", "ahb", "dclk";
1669 status = "disabled";
1670
1671 vopb_out: port {
1672 #address-cells = <1>;
1673 #size-cells = <0>;
f7a29e30
YY		 1674
1675 vopb_out_edp: endpoint@0 {
1676 reg = <0>;
1677 remote-endpoint = <&edp_in_vopb>;
1678 };
1679
d3f51f49
JC		 1680 vopb_out_mipi: endpoint@1 {
1681 reg = <1>;
1682 remote-endpoint = <&mipi_in_vopb>;
1683 };
1684
81e923dd
JC		 1685 vopb_out_hdmi: endpoint@2 {
1686 reg = <2>;
1687 remote-endpoint = <&hdmi_in_vopb>;
1688 };
1df5d2ab
NY		 1689
1690 vopb_out_mipi1: endpoint@3 {
1691 reg = <3>;
1692 remote-endpoint = <&mipi1_in_vopb>;
1693 };
2d3c2d56
CZ		 1694
1695 vopb_out_dp: endpoint@4 {
1696 reg = <4>;
1697 remote-endpoint = <&dp_in_vopb>;
1698 };
fbd4cc0e
MY		 1699 };
1700 };
1701
1702 vopb_mmu: iommu@ff903f00 {
1703 compatible = "rockchip,iommu";
1704 reg = <0x0 0xff903f00 0x0 0x100>;
1705 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1706 interrupt-names = "vopb_mmu";
1707 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
df3bcde7 1708 clock-names = "aclk", "iface";
fbd4cc0e
MY		 1709 power-domains = <&power RK3399_PD_VOPB>;
1710 #iommu-cells = <0>;
1711 status = "disabled";
1712 };
1713
97a0115c
SZ		 1714 isp0: isp0@ff910000 {
1715 compatible = "rockchip,rk3399-cif-isp";
1716 reg = <0x0 0xff910000 0x0 0x4000>;
1717 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1718 clocks = <&cru SCLK_ISP0>,
1719 <&cru ACLK_ISP0_WRAPPER>,
1720 <&cru HCLK_ISP0_WRAPPER>;
1721 clock-names = "isp", "aclk", "hclk";
1722 iommus = <&isp0_mmu>;
1723 phys = <&mipi_dphy_rx0>;
1724 phy-names = "dphy";
1725 power-domains = <&power RK3399_PD_ISP0>;
1726 status = "disabled";
1727
1728 ports {
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1731
1732 port@0 {
1733 reg = <0>;
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1736 };
1737 };
1738 };
1739
ae4fdcca
SX		 1740 isp0_mmu: iommu@ff914000 {
1741 compatible = "rockchip,iommu";
1742 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1743 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1744 interrupt-names = "isp0_mmu";
c432a29d 1745 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
df3bcde7 1746 clock-names = "aclk", "iface";
ae4fdcca 1747 #iommu-cells = <0>;
c432a29d 1748 power-domains = <&power RK3399_PD_ISP0>;
ae4fdcca 1749 rockchip,disable-mmu-reset;
ae4fdcca
SX		 1750 };
1751
1752 isp1_mmu: iommu@ff924000 {
1753 compatible = "rockchip,iommu";
1754 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1755 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1756 interrupt-names = "isp1_mmu";
c432a29d 1757 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
df3bcde7 1758 clock-names = "aclk", "iface";
ae4fdcca 1759 #iommu-cells = <0>;
c432a29d 1760 power-domains = <&power RK3399_PD_ISP1>;
ae4fdcca 1761 rockchip,disable-mmu-reset;
ae4fdcca
SX		 1762 };
1763
0d60d48c
VB		 1764 hdmi_sound: hdmi-sound {
1765 compatible = "simple-audio-card";
1766 simple-audio-card,format = "i2s";
1767 simple-audio-card,mclk-fs = <256>;
1768 simple-audio-card,name = "hdmi-sound";
1769 status = "disabled";
1770
1771 simple-audio-card,cpu {
1772 sound-dai = <&i2s2>;
1773 };
1774 simple-audio-card,codec {
1775 sound-dai = <&hdmi>;
1776 };
1777 };
1778
81e923dd
JC		 1779 hdmi: hdmi@ff940000 {
1780 compatible = "rockchip,rk3399-dw-hdmi";
1781 reg = <0x0 0xff940000 0x0 0x20000>;
1782 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
db2fd26d
PHH		 1783 clocks = <&cru PCLK_HDMI_CTRL>,
1784 <&cru SCLK_HDMI_SFR>,
1785 <&cru PLL_VPLL>,
1786 <&cru PCLK_VIO_GRF>,
1787 <&cru SCLK_HDMI_CEC>;
1788 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
81e923dd
JC		 1789 power-domains = <&power RK3399_PD_HDCP>;
1790 reg-io-width = <4>;
1791 rockchip,grf = <&grf>;
0d60d48c 1792 #sound-dai-cells = <0>;
81e923dd
JC		 1793 status = "disabled";
1794
1795 ports {
1796 hdmi_in: port {
1797 #address-cells = <1>;
1798 #size-cells = <0>;
1799
1800 hdmi_in_vopb: endpoint@0 {
1801 reg = <0>;
1802 remote-endpoint = <&vopb_out_hdmi>;
1803 };
1804 hdmi_in_vopl: endpoint@1 {
1805 reg = <1>;
1806 remote-endpoint = <&vopl_out_hdmi>;
1807 };
1808 };
1809 };
1810 };
1811
d3f51f49
JC		 1812 mipi_dsi: mipi@ff960000 {
1813 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1814 reg = <0x0 0xff960000 0x0 0x8000>;
1815 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
bb4e6ff0 1816 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
0bc15d85
NY		 1817 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1818 clock-names = "ref", "pclk", "phy_cfg", "grf";
d3f51f49 1819 power-domains = <&power RK3399_PD_VIO>;
3813a10a
BN		 1820 resets = <&cru SRST_P_MIPI_DSI0>;
1821 reset-names = "apb";
d3f51f49 1822 rockchip,grf = <&grf>;
91e75bde
HS		 1823 #address-cells = <1>;
1824 #size-cells = <0>;
d3f51f49
JC		 1825 status = "disabled";
1826
1827 ports {
c856cb5d
NY		 1828 #address-cells = <1>;
1829 #size-cells = <0>;
1830
1831 mipi_in: port@0 {
1832 reg = <0>;
d3f51f49
JC		 1833 #address-cells = <1>;
1834 #size-cells = <0>;
1835
1836 mipi_in_vopb: endpoint@0 {
1837 reg = <0>;
1838 remote-endpoint = <&vopb_out_mipi>;
1839 };
1840 mipi_in_vopl: endpoint@1 {
1841 reg = <1>;
1842 remote-endpoint = <&vopl_out_mipi>;
1843 };
1844 };
1845 };
1846 };
1847
1df5d2ab
NY		 1848 mipi_dsi1: mipi@ff968000 {
1849 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1850 reg = <0x0 0xff968000 0x0 0x8000>;
1851 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1852 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1853 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1854 clock-names = "ref", "pclk", "phy_cfg", "grf";
1855 power-domains = <&power RK3399_PD_VIO>;
1856 resets = <&cru SRST_P_MIPI_DSI1>;
1857 reset-names = "apb";
1858 rockchip,grf = <&grf>;
91e75bde
HS		 1859 #address-cells = <1>;
1860 #size-cells = <0>;
1df5d2ab
NY		 1861 status = "disabled";
1862
1863 ports {
1864 #address-cells = <1>;
1865 #size-cells = <0>;
1866
1867 mipi1_in: port@0 {
1868 reg = <0>;
1869 #address-cells = <1>;
1870 #size-cells = <0>;
1871
1872 mipi1_in_vopb: endpoint@0 {
1873 reg = <0>;
1874 remote-endpoint = <&vopb_out_mipi1>;
1875 };
1876
1877 mipi1_in_vopl: endpoint@1 {
1878 reg = <1>;
1879 remote-endpoint = <&vopl_out_mipi1>;
1880 };
1881 };
1882 };
1883 };
1884
f7a29e30
YY		 1885 edp: edp@ff970000 {
1886 compatible = "rockchip,rk3399-edp";
1887 reg = <0x0 0xff970000 0x0 0x8000>;
1888 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
7b0390ea
YY		 1889 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1890 clock-names = "dp", "pclk", "grf";
f7a29e30
YY		 1891 pinctrl-names = "default";
1892 pinctrl-0 = <&edp_hpd>;
1893 power-domains = <&power RK3399_PD_EDP>;
1894 resets = <&cru SRST_P_EDP_CTRL>;
1895 reset-names = "dp";
1896 rockchip,grf = <&grf>;
1897 status = "disabled";
1898
1899 ports {
1900 #address-cells = <1>;
1901 #size-cells = <0>;
1902 edp_in: port@0 {
1903 reg = <0>;
1904 #address-cells = <1>;
1905 #size-cells = <0>;
1906
1907 edp_in_vopb: endpoint@0 {
1908 reg = <0>;
1909 remote-endpoint = <&vopb_out_edp>;
1910 };
1911
1912 edp_in_vopl: endpoint@1 {
1913 reg = <1>;
1914 remote-endpoint = <&vopl_out_edp>;
1915 };
1916 };
1917 };
1918 };
1919
68d19331
CW		 1920 gpu: gpu@ff9a0000 {
1921 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1922 reg = <0x0 0xff9a0000 0x0 0x10000>;
c604fd81
JJ		 1923 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1924 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1925 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1926 interrupt-names = "job", "mmu", "gpu";
68d19331 1927 clocks = <&cru ACLK_GPU>;
36be9111 1928 #cooling-cells = <2>;
68d19331 1929 power-domains = <&power RK3399_PD_GPU>;
f048b9a4
JX		 1930 status = "disabled";
1931 };
1932
1933 pinctrl: pinctrl {
1934 compatible = "rockchip,rk3399-pinctrl";
1935 rockchip,grf = <&grf>;
1936 rockchip,pmu = <&pmugrf>;
1937 #address-cells = <2>;
1938 #size-cells = <2>;
1939 ranges;
1940
1941 gpio0: gpio0@ff720000 {
1942 compatible = "rockchip,gpio-bank";
1943 reg = <0x0 0xff720000 0x0 0x100>;
1944 clocks = <&pmucru PCLK_GPIO0_PMU>;
210bbd38 1945 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1946
1947 gpio-controller;
1948 #gpio-cells = <0x2>;
1949
1950 interrupt-controller;
1951 #interrupt-cells = <0x2>;
1952 };
1953
1954 gpio1: gpio1@ff730000 {
1955 compatible = "rockchip,gpio-bank";
1956 reg = <0x0 0xff730000 0x0 0x100>;
1957 clocks = <&pmucru PCLK_GPIO1_PMU>;
210bbd38 1958 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1959
1960 gpio-controller;
1961 #gpio-cells = <0x2>;
1962
1963 interrupt-controller;
1964 #interrupt-cells = <0x2>;
1965 };
1966
1967 gpio2: gpio2@ff780000 {
1968 compatible = "rockchip,gpio-bank";
1969 reg = <0x0 0xff780000 0x0 0x100>;
1970 clocks = <&cru PCLK_GPIO2>;
210bbd38 1971 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1972
1973 gpio-controller;
1974 #gpio-cells = <0x2>;
1975
1976 interrupt-controller;
1977 #interrupt-cells = <0x2>;
1978 };
1979
1980 gpio3: gpio3@ff788000 {
1981 compatible = "rockchip,gpio-bank";
1982 reg = <0x0 0xff788000 0x0 0x100>;
1983 clocks = <&cru PCLK_GPIO3>;
210bbd38 1984 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1985
1986 gpio-controller;
1987 #gpio-cells = <0x2>;
1988
1989 interrupt-controller;
1990 #interrupt-cells = <0x2>;
1991 };
1992
1993 gpio4: gpio4@ff790000 {
1994 compatible = "rockchip,gpio-bank";
1995 reg = <0x0 0xff790000 0x0 0x100>;
1996 clocks = <&cru PCLK_GPIO4>;
210bbd38 1997 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1998
1999 gpio-controller;
2000 #gpio-cells = <0x2>;
2001
2002 interrupt-controller;
2003 #interrupt-cells = <0x2>;
2004 };
2005
2006 pcfg_pull_up: pcfg-pull-up {
2007 bias-pull-up;
2008 };
2009
2010 pcfg_pull_down: pcfg-pull-down {
2011 bias-pull-down;
2012 };
2013
2014 pcfg_pull_none: pcfg-pull-none {
2015 bias-disable;
2016 };
2017
2018 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2019 bias-disable;
2020 drive-strength = <12>;
2021 };
2022
b4102328
RL		 2023 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2024 bias-disable;
2025 drive-strength = <13>;
2026 };
2027
2028 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2029 bias-disable;
2030 drive-strength = <18>;
2031 };
2032
2033 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2034 bias-disable;
2035 drive-strength = <20>;
2036 };
2037
2038 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2039 bias-pull-up;
2040 drive-strength = <2>;
2041 };
2042
f048b9a4
JX		 2043 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2044 bias-pull-up;
2045 drive-strength = <8>;
2046 };
2047
b4102328
RL		 2048 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2049 bias-pull-up;
2050 drive-strength = <18>;
2051 };
2052
2053 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2054 bias-pull-up;
2055 drive-strength = <20>;
2056 };
2057
f048b9a4
JX		 2058 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2059 bias-pull-down;
2060 drive-strength = <4>;
2061 };
2062
b4102328
RL		 2063 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2064 bias-pull-down;
2065 drive-strength = <8>;
f048b9a4
JX		 2066 };
2067
2068 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2069 bias-pull-down;
2070 drive-strength = <12>;
2071 };
2072
b4102328
RL		 2073 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2074 bias-pull-down;
2075 drive-strength = <18>;
2076 };
2077
2078 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2079 bias-pull-down;
2080 drive-strength = <20>;
2081 };
2082
2083 pcfg_output_high: pcfg-output-high {
2084 output-high;
2085 };
2086
2087 pcfg_output_low: pcfg-output-low {
2088 output-low;
f048b9a4
JX		 2089 };
2090
a8bcaea7
DA		 2091 clock {
2092 clk_32k: clk-32k {
d64420e8 2093 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
a8bcaea7
DA		 2094 };
2095 };
2096
8742466a
BN		 2097 edp {
2098 edp_hpd: edp-hpd {
2099 rockchip,pins =
d64420e8 2100 <4 RK_PC7 2 &pcfg_pull_none>;
8742466a
BN		 2101 };
2102 };
2103
eb3a6a6a
RC		 2104 gmac {
2105 rgmii_pins: rgmii-pins {
2106 rockchip,pins =
2107 /* mac_txclk */
d64420e8 2108 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2109 /* mac_rxclk */
d64420e8 2110 <3 RK_PB6 1 &pcfg_pull_none>,
eb3a6a6a 2111 /* mac_mdio */
d64420e8 2112 <3 RK_PB5 1 &pcfg_pull_none>,
eb3a6a6a 2113 /* mac_txen */
d64420e8 2114 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2115 /* mac_clk */
d64420e8 2116 <3 RK_PB3 1 &pcfg_pull_none>,
eb3a6a6a 2117 /* mac_rxdv */
d64420e8 2118 <3 RK_PB1 1 &pcfg_pull_none>,
eb3a6a6a 2119 /* mac_mdc */
d64420e8 2120 <3 RK_PB0 1 &pcfg_pull_none>,
eb3a6a6a 2121 /* mac_rxd1 */
d64420e8 2122 <3 RK_PA7 1 &pcfg_pull_none>,
eb3a6a6a 2123 /* mac_rxd0 */
d64420e8 2124 <3 RK_PA6 1 &pcfg_pull_none>,
eb3a6a6a 2125 /* mac_txd1 */
d64420e8 2126 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2127 /* mac_txd0 */
d64420e8 2128 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2129 /* mac_rxd3 */
d64420e8 2130 <3 RK_PA3 1 &pcfg_pull_none>,
eb3a6a6a 2131 /* mac_rxd2 */
d64420e8 2132 <3 RK_PA2 1 &pcfg_pull_none>,
eb3a6a6a 2133 /* mac_txd3 */
d64420e8 2134 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2135 /* mac_txd2 */
d64420e8 2136 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
eb3a6a6a
RC		 2137 };
2138
2139 rmii_pins: rmii-pins {
2140 rockchip,pins =
2141 /* mac_mdio */
d64420e8 2142 <3 RK_PB5 1 &pcfg_pull_none>,
eb3a6a6a 2143 /* mac_txen */
d64420e8 2144 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2145 /* mac_clk */
d64420e8 2146 <3 RK_PB3 1 &pcfg_pull_none>,
eb3a6a6a 2147 /* mac_rxer */
d64420e8 2148 <3 RK_PB2 1 &pcfg_pull_none>,
eb3a6a6a 2149 /* mac_rxdv */
d64420e8 2150 <3 RK_PB1 1 &pcfg_pull_none>,
eb3a6a6a 2151 /* mac_mdc */
d64420e8 2152 <3 RK_PB0 1 &pcfg_pull_none>,
eb3a6a6a 2153 /* mac_rxd1 */
d64420e8 2154 <3 RK_PA7 1 &pcfg_pull_none>,
eb3a6a6a 2155 /* mac_rxd0 */
d64420e8 2156 <3 RK_PA6 1 &pcfg_pull_none>,
eb3a6a6a 2157 /* mac_txd1 */
d64420e8 2158 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2159 /* mac_txd0 */
d64420e8 2160 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
eb3a6a6a
RC		 2161 };
2162 };
2163
f048b9a4
JX		 2164 i2c0 {
2165 i2c0_xfer: i2c0-xfer {
2166 rockchip,pins =
d64420e8
HS		 2167 <1 RK_PB7 2 &pcfg_pull_none>,
2168 <1 RK_PC0 2 &pcfg_pull_none>;
f048b9a4
JX		 2169 };
2170 };
2171
2172 i2c1 {
2173 i2c1_xfer: i2c1-xfer {
2174 rockchip,pins =
d64420e8
HS		 2175 <4 RK_PA2 1 &pcfg_pull_none>,
2176 <4 RK_PA1 1 &pcfg_pull_none>;
f048b9a4
JX		 2177 };
2178 };
2179
2180 i2c2 {
2181 i2c2_xfer: i2c2-xfer {
2182 rockchip,pins =
d64420e8
HS		 2183 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2184 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
f048b9a4
JX		 2185 };
2186 };
2187
2188 i2c3 {
2189 i2c3_xfer: i2c3-xfer {
2190 rockchip,pins =
d64420e8
HS		 2191 <4 RK_PC1 1 &pcfg_pull_none>,
2192 <4 RK_PC0 1 &pcfg_pull_none>;
f048b9a4
JX		 2193 };
2194 };
2195
2196 i2c4 {
2197 i2c4_xfer: i2c4-xfer {
2198 rockchip,pins =
d64420e8
HS		 2199 <1 RK_PB4 1 &pcfg_pull_none>,
2200 <1 RK_PB3 1 &pcfg_pull_none>;
f048b9a4
JX		 2201 };
2202 };
2203
2204 i2c5 {
2205 i2c5_xfer: i2c5-xfer {
2206 rockchip,pins =
d64420e8
HS		 2207 <3 RK_PB3 2 &pcfg_pull_none>,
2208 <3 RK_PB2 2 &pcfg_pull_none>;
f048b9a4
JX		 2209 };
2210 };
2211
2212 i2c6 {
2213 i2c6_xfer: i2c6-xfer {
2214 rockchip,pins =
d64420e8
HS		 2215 <2 RK_PB2 2 &pcfg_pull_none>,
2216 <2 RK_PB1 2 &pcfg_pull_none>;
f048b9a4
JX		 2217 };
2218 };
2219
2220 i2c7 {
2221 i2c7_xfer: i2c7-xfer {
2222 rockchip,pins =
d64420e8
HS		 2223 <2 RK_PB0 2 &pcfg_pull_none>,
2224 <2 RK_PA7 2 &pcfg_pull_none>;
f048b9a4
JX		 2225 };
2226 };
2227
2228 i2c8 {
2229 i2c8_xfer: i2c8-xfer {
2230 rockchip,pins =
d64420e8
HS		 2231 <1 RK_PC5 1 &pcfg_pull_none>,
2232 <1 RK_PC4 1 &pcfg_pull_none>;
f048b9a4
JX		 2233 };
2234 };
2235
2236 i2s0 {
0efaf807
KG		 2237 i2s0_2ch_bus: i2s0-2ch-bus {
2238 rockchip,pins =
d64420e8
HS		 2239 <3 RK_PD0 1 &pcfg_pull_none>,
2240 <3 RK_PD1 1 &pcfg_pull_none>,
2241 <3 RK_PD2 1 &pcfg_pull_none>,
2242 <3 RK_PD3 1 &pcfg_pull_none>,
2243 <3 RK_PD7 1 &pcfg_pull_none>,
2244 <4 RK_PA0 1 &pcfg_pull_none>;
0efaf807
KG		 2245 };
2246
f048b9a4
JX		 2247 i2s0_8ch_bus: i2s0-8ch-bus {
2248 rockchip,pins =
d64420e8
HS		 2249 <3 RK_PD0 1 &pcfg_pull_none>,
2250 <3 RK_PD1 1 &pcfg_pull_none>,
2251 <3 RK_PD2 1 &pcfg_pull_none>,
2252 <3 RK_PD3 1 &pcfg_pull_none>,
2253 <3 RK_PD4 1 &pcfg_pull_none>,
2254 <3 RK_PD5 1 &pcfg_pull_none>,
2255 <3 RK_PD6 1 &pcfg_pull_none>,
2256 <3 RK_PD7 1 &pcfg_pull_none>,
2257 <4 RK_PA0 1 &pcfg_pull_none>;
f048b9a4
JX		 2258 };
2259 };
2260
2261 i2s1 {
2262 i2s1_2ch_bus: i2s1-2ch-bus {
2263 rockchip,pins =
d64420e8
HS		 2264 <4 RK_PA3 1 &pcfg_pull_none>,
2265 <4 RK_PA4 1 &pcfg_pull_none>,
2266 <4 RK_PA5 1 &pcfg_pull_none>,
2267 <4 RK_PA6 1 &pcfg_pull_none>,
2268 <4 RK_PA7 1 &pcfg_pull_none>;
f048b9a4
JX		 2269 };
2270 };
2271
b74a2e98
KY		 2272 sdio0 {
2273 sdio0_bus1: sdio0-bus1 {
2274 rockchip,pins =
d64420e8 2275 <2 RK_PC4 1 &pcfg_pull_up>;
b74a2e98
KY		 2276 };
2277
2278 sdio0_bus4: sdio0-bus4 {
2279 rockchip,pins =
d64420e8
HS		 2280 <2 RK_PC4 1 &pcfg_pull_up>,
2281 <2 RK_PC5 1 &pcfg_pull_up>,
2282 <2 RK_PC6 1 &pcfg_pull_up>,
2283 <2 RK_PC7 1 &pcfg_pull_up>;
b74a2e98
KY		 2284 };
2285
2286 sdio0_cmd: sdio0-cmd {
2287 rockchip,pins =
d64420e8 2288 <2 RK_PD0 1 &pcfg_pull_up>;
b74a2e98
KY		 2289 };
2290
2291 sdio0_clk: sdio0-clk {
2292 rockchip,pins =
d64420e8 2293 <2 RK_PD1 1 &pcfg_pull_none>;
b74a2e98
KY		 2294 };
2295
2296 sdio0_cd: sdio0-cd {
2297 rockchip,pins =
d64420e8 2298 <2 RK_PD2 1 &pcfg_pull_up>;
b74a2e98
KY		 2299 };
2300
2301 sdio0_pwr: sdio0-pwr {
2302 rockchip,pins =
d64420e8 2303 <2 RK_PD3 1 &pcfg_pull_up>;
b74a2e98
KY		 2304 };
2305
2306 sdio0_bkpwr: sdio0-bkpwr {
2307 rockchip,pins =
d64420e8 2308 <2 RK_PD4 1 &pcfg_pull_up>;
b74a2e98
KY		 2309 };
2310
2311 sdio0_wp: sdio0-wp {
2312 rockchip,pins =
d64420e8 2313 <0 RK_PA3 1 &pcfg_pull_up>;
b74a2e98
KY		 2314 };
2315
2316 sdio0_int: sdio0-int {
2317 rockchip,pins =
d64420e8 2318 <0 RK_PA4 1 &pcfg_pull_up>;
b74a2e98
KY		 2319 };
2320 };
2321
2322 sdmmc {
2323 sdmmc_bus1: sdmmc-bus1 {
2324 rockchip,pins =
d64420e8 2325 <4 RK_PB0 1 &pcfg_pull_up>;
b74a2e98
KY		 2326 };
2327
2328 sdmmc_bus4: sdmmc-bus4 {
2329 rockchip,pins =
d64420e8
HS		 2330 <4 RK_PB0 1 &pcfg_pull_up>,
2331 <4 RK_PB1 1 &pcfg_pull_up>,
2332 <4 RK_PB2 1 &pcfg_pull_up>,
2333 <4 RK_PB3 1 &pcfg_pull_up>;
b74a2e98
KY		 2334 };
2335
2336 sdmmc_clk: sdmmc-clk {
2337 rockchip,pins =
d64420e8 2338 <4 RK_PB4 1 &pcfg_pull_none>;
b74a2e98
KY		 2339 };
2340
2341 sdmmc_cmd: sdmmc-cmd {
2342 rockchip,pins =
d64420e8 2343 <4 RK_PB5 1 &pcfg_pull_up>;
b74a2e98
KY		 2344 };
2345
6122308e 2346 sdmmc_cd: sdmmc-cd {
b74a2e98 2347 rockchip,pins =
d64420e8 2348 <0 RK_PA7 1 &pcfg_pull_up>;
b74a2e98
KY		 2349 };
2350
2351 sdmmc_wp: sdmmc-wp {
2352 rockchip,pins =
d64420e8 2353 <0 RK_PB0 1 &pcfg_pull_up>;
b74a2e98
KY		 2354 };
2355 };
2356
a7ecfad4 2357 suspend {
5d26ad9c 2358 ap_pwroff: ap-pwroff {
d64420e8 2359 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
5d26ad9c
DA		 2360 };
2361
2362 ddrio_pwroff: ddrio-pwroff {
d64420e8 2363 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
5d26ad9c
DA		 2364 };
2365 };
2366
f048b9a4
JX		 2367 spdif {
2368 spdif_bus: spdif-bus {
2369 rockchip,pins =
d64420e8 2370 <4 RK_PC5 1 &pcfg_pull_none>;
f048b9a4 2371 };
b74a2e98
KY		 2372
2373 spdif_bus_1: spdif-bus-1 {
2374 rockchip,pins =
d64420e8 2375 <3 RK_PC0 3 &pcfg_pull_none>;
b74a2e98 2376 };
f048b9a4
JX		 2377 };
2378
2379 spi0 {
2380 spi0_clk: spi0-clk {
2381 rockchip,pins =
d64420e8 2382 <3 RK_PA6 2 &pcfg_pull_up>;
f048b9a4
JX		 2383 };
2384 spi0_cs0: spi0-cs0 {
2385 rockchip,pins =
d64420e8 2386 <3 RK_PA7 2 &pcfg_pull_up>;
f048b9a4
JX		 2387 };
2388 spi0_cs1: spi0-cs1 {
2389 rockchip,pins =
d64420e8 2390 <3 RK_PB0 2 &pcfg_pull_up>;
f048b9a4
JX		 2391 };
2392 spi0_tx: spi0-tx {
2393 rockchip,pins =
d64420e8 2394 <3 RK_PA5 2 &pcfg_pull_up>;
f048b9a4
JX		 2395 };
2396 spi0_rx: spi0-rx {
2397 rockchip,pins =
d64420e8 2398 <3 RK_PA4 2 &pcfg_pull_up>;
f048b9a4
JX		 2399 };
2400 };
2401
2402 spi1 {
2403 spi1_clk: spi1-clk {
2404 rockchip,pins =
d64420e8 2405 <1 RK_PB1 2 &pcfg_pull_up>;
f048b9a4
JX		 2406 };
2407 spi1_cs0: spi1-cs0 {
2408 rockchip,pins =
d64420e8 2409 <1 RK_PB2 2 &pcfg_pull_up>;
f048b9a4
JX		 2410 };
2411 spi1_rx: spi1-rx {
2412 rockchip,pins =
d64420e8 2413 <1 RK_PA7 2 &pcfg_pull_up>;
f048b9a4
JX		 2414 };
2415 spi1_tx: spi1-tx {
2416 rockchip,pins =
d64420e8 2417 <1 RK_PB0 2 &pcfg_pull_up>;
f048b9a4
JX		 2418 };
2419 };
2420
2421 spi2 {
2422 spi2_clk: spi2-clk {
2423 rockchip,pins =
d64420e8 2424 <2 RK_PB3 1 &pcfg_pull_up>;
f048b9a4
JX		 2425 };
2426 spi2_cs0: spi2-cs0 {
2427 rockchip,pins =
d64420e8 2428 <2 RK_PB4 1 &pcfg_pull_up>;
f048b9a4
JX		 2429 };
2430 spi2_rx: spi2-rx {
2431 rockchip,pins =
d64420e8 2432 <2 RK_PB1 1 &pcfg_pull_up>;
f048b9a4
JX		 2433 };
2434 spi2_tx: spi2-tx {
2435 rockchip,pins =
d64420e8 2436 <2 RK_PB2 1 &pcfg_pull_up>;
f048b9a4
JX		 2437 };
2438 };
2439
2440 spi3 {
2441 spi3_clk: spi3-clk {
2442 rockchip,pins =
d64420e8 2443 <1 RK_PC1 1 &pcfg_pull_up>;
f048b9a4
JX		 2444 };
2445 spi3_cs0: spi3-cs0 {
2446 rockchip,pins =
d64420e8 2447 <1 RK_PC2 1 &pcfg_pull_up>;
f048b9a4
JX		 2448 };
2449 spi3_rx: spi3-rx {
2450 rockchip,pins =
d64420e8 2451 <1 RK_PB7 1 &pcfg_pull_up>;
f048b9a4
JX		 2452 };
2453 spi3_tx: spi3-tx {
2454 rockchip,pins =
d64420e8 2455 <1 RK_PC0 1 &pcfg_pull_up>;
f048b9a4
JX		 2456 };
2457 };
2458
2459 spi4 {
2460 spi4_clk: spi4-clk {
2461 rockchip,pins =
d64420e8 2462 <3 RK_PA2 2 &pcfg_pull_up>;
f048b9a4
JX		 2463 };
2464 spi4_cs0: spi4-cs0 {
2465 rockchip,pins =
d64420e8 2466 <3 RK_PA3 2 &pcfg_pull_up>;
f048b9a4
JX		 2467 };
2468 spi4_rx: spi4-rx {
2469 rockchip,pins =
d64420e8 2470 <3 RK_PA0 2 &pcfg_pull_up>;
f048b9a4
JX		 2471 };
2472 spi4_tx: spi4-tx {
2473 rockchip,pins =
d64420e8 2474 <3 RK_PA1 2 &pcfg_pull_up>;
f048b9a4
JX		 2475 };
2476 };
2477
2478 spi5 {
2479 spi5_clk: spi5-clk {
2480 rockchip,pins =
d64420e8 2481 <2 RK_PC6 2 &pcfg_pull_up>;
f048b9a4
JX		 2482 };
2483 spi5_cs0: spi5-cs0 {
2484 rockchip,pins =
d64420e8 2485 <2 RK_PC7 2 &pcfg_pull_up>;
f048b9a4
JX		 2486 };
2487 spi5_rx: spi5-rx {
2488 rockchip,pins =
d64420e8 2489 <2 RK_PC4 2 &pcfg_pull_up>;
f048b9a4
JX		 2490 };
2491 spi5_tx: spi5-tx {
2492 rockchip,pins =
d64420e8 2493 <2 RK_PC5 2 &pcfg_pull_up>;
f048b9a4
JX		 2494 };
2495 };
2496
ba2b043e
SZ		 2497 testclk {
2498 test_clkout0: test-clkout0 {
2499 rockchip,pins =
d64420e8 2500 <0 RK_PA0 1 &pcfg_pull_none>;
ba2b043e
SZ		 2501 };
2502
2503 test_clkout1: test-clkout1 {
2504 rockchip,pins =
d64420e8 2505 <2 RK_PD1 2 &pcfg_pull_none>;
ba2b043e
SZ		 2506 };
2507
2508 test_clkout2: test-clkout2 {
2509 rockchip,pins =
d64420e8 2510 <0 RK_PB0 3 &pcfg_pull_none>;
ba2b043e
SZ		 2511 };
2512 };
2513
95c27ba7 2514 tsadc {
2bc65fef 2515 otp_pin: otp-pin {
d64420e8 2516 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
95c27ba7
CW		 2517 };
2518
2519 otp_out: otp-out {
d64420e8 2520 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
95c27ba7
CW		 2521 };
2522 };
2523
f048b9a4
JX		 2524 uart0 {
2525 uart0_xfer: uart0-xfer {
2526 rockchip,pins =
d64420e8
HS		 2527 <2 RK_PC0 1 &pcfg_pull_up>,
2528 <2 RK_PC1 1 &pcfg_pull_none>;
f048b9a4
JX		 2529 };
2530
2531 uart0_cts: uart0-cts {
2532 rockchip,pins =
d64420e8 2533 <2 RK_PC2 1 &pcfg_pull_none>;
f048b9a4
JX		 2534 };
2535
2536 uart0_rts: uart0-rts {
2537 rockchip,pins =
d64420e8 2538 <2 RK_PC3 1 &pcfg_pull_none>;
f048b9a4
JX		 2539 };
2540 };
2541
2542 uart1 {
2543 uart1_xfer: uart1-xfer {
2544 rockchip,pins =
d64420e8
HS		 2545 <3 RK_PB4 2 &pcfg_pull_up>,
2546 <3 RK_PB5 2 &pcfg_pull_none>;
f048b9a4
JX		 2547 };
2548 };
2549
2550 uart2a {
2551 uart2a_xfer: uart2a-xfer {
2552 rockchip,pins =
d64420e8
HS		 2553 <4 RK_PB0 2 &pcfg_pull_up>,
2554 <4 RK_PB1 2 &pcfg_pull_none>;
f048b9a4
JX		 2555 };
2556 };
2557
2558 uart2b {
2559 uart2b_xfer: uart2b-xfer {
2560 rockchip,pins =
d64420e8
HS		 2561 <4 RK_PC0 2 &pcfg_pull_up>,
2562 <4 RK_PC1 2 &pcfg_pull_none>;
f048b9a4
JX		 2563 };
2564 };
2565
2566 uart2c {
2567 uart2c_xfer: uart2c-xfer {
2568 rockchip,pins =
d64420e8
HS		 2569 <4 RK_PC3 1 &pcfg_pull_up>,
2570 <4 RK_PC4 1 &pcfg_pull_none>;
f048b9a4
JX		 2571 };
2572 };
2573
2574 uart3 {
2575 uart3_xfer: uart3-xfer {
2576 rockchip,pins =
d64420e8
HS		 2577 <3 RK_PB6 2 &pcfg_pull_up>,
2578 <3 RK_PB7 2 &pcfg_pull_none>;
f048b9a4
JX		 2579 };
2580
2581 uart3_cts: uart3-cts {
2582 rockchip,pins =
40a0dd42 2583 <3 RK_PC0 2 &pcfg_pull_none>;
f048b9a4
JX		 2584 };
2585
2586 uart3_rts: uart3-rts {
2587 rockchip,pins =
40a0dd42 2588 <3 RK_PC1 2 &pcfg_pull_none>;
f048b9a4
JX		 2589 };
2590 };
2591
2592 uart4 {
2593 uart4_xfer: uart4-xfer {
2594 rockchip,pins =
d64420e8
HS		 2595 <1 RK_PA7 1 &pcfg_pull_up>,
2596 <1 RK_PB0 1 &pcfg_pull_none>;
f048b9a4
JX		 2597 };
2598 };
2599
2600 uarthdcp {
2601 uarthdcp_xfer: uarthdcp-xfer {
2602 rockchip,pins =
d64420e8
HS		 2603 <4 RK_PC5 2 &pcfg_pull_up>,
2604 <4 RK_PC6 2 &pcfg_pull_none>;
f048b9a4
JX		 2605 };
2606 };
2607
2608 pwm0 {
2609 pwm0_pin: pwm0-pin {
2610 rockchip,pins =
d64420e8 2611 <4 RK_PC2 1 &pcfg_pull_none>;
b4102328
RL		 2612 };
2613
2614 pwm0_pin_pull_down: pwm0-pin-pull-down {
2615 rockchip,pins =
d64420e8 2616 <4 RK_PC2 1 &pcfg_pull_down>;
f048b9a4
JX		 2617 };
2618
2619 vop0_pwm_pin: vop0-pwm-pin {
2620 rockchip,pins =
d64420e8 2621 <4 RK_PC2 2 &pcfg_pull_none>;
b4102328
RL		 2622 };
2623
2624 vop1_pwm_pin: vop1-pwm-pin {
2625 rockchip,pins =
d64420e8 2626 <4 RK_PC2 3 &pcfg_pull_none>;
f048b9a4
JX		 2627 };
2628 };
2629
2630 pwm1 {
2631 pwm1_pin: pwm1-pin {
2632 rockchip,pins =
d64420e8 2633 <4 RK_PC6 1 &pcfg_pull_none>;
f048b9a4
JX		 2634 };
2635
b4102328 2636 pwm1_pin_pull_down: pwm1-pin-pull-down {
f048b9a4 2637 rockchip,pins =
d64420e8 2638 <4 RK_PC6 1 &pcfg_pull_down>;
f048b9a4
JX		 2639 };
2640 };
2641
2642 pwm2 {
2643 pwm2_pin: pwm2-pin {
2644 rockchip,pins =
d64420e8 2645 <1 RK_PC3 1 &pcfg_pull_none>;
b4102328
RL		 2646 };
2647
2648 pwm2_pin_pull_down: pwm2-pin-pull-down {
2649 rockchip,pins =
d64420e8 2650 <1 RK_PC3 1 &pcfg_pull_down>;
f048b9a4
JX		 2651 };
2652 };
2653
2654 pwm3a {
2655 pwm3a_pin: pwm3a-pin {
2656 rockchip,pins =
d64420e8 2657 <0 RK_PA6 1 &pcfg_pull_none>;
f048b9a4
JX		 2658 };
2659 };
2660
2661 pwm3b {
2662 pwm3b_pin: pwm3b-pin {
2663 rockchip,pins =
d64420e8 2664 <1 RK_PB6 1 &pcfg_pull_none>;
f048b9a4
JX		 2665 };
2666 };
85aaa574 2667
b74a2e98
KY		 2668 hdmi {
2669 hdmi_i2c_xfer: hdmi-i2c-xfer {
2670 rockchip,pins =
d64420e8
HS		 2671 <4 RK_PC1 3 &pcfg_pull_none>,
2672 <4 RK_PC0 3 &pcfg_pull_none>;
b74a2e98
KY		 2673 };
2674
2675 hdmi_cec: hdmi-cec {
2676 rockchip,pins =
d64420e8 2677 <4 RK_PC7 1 &pcfg_pull_none>;
b74a2e98
KY		 2678 };
2679 };
2680
85aaa574 2681 pcie {
b74a2e98
KY		 2682 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2683 rockchip,pins =
2684 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2685 };
2686
2687 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2688 rockchip,pins =
2689 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2690 };
85aaa574
SL		 2691 };
2692
f048b9a4
JX		 2693 };
2694};
Linux 6.x block layer and io_uring tree(s)