projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| f048b9a4 JX |
1 | /* |
| 2 | * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd | |
| 3 | * | |
| 4 | * This file is dual-licensed: you can use it either under the terms | |
| 5 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 6 | * licensing only applies to this file, and not this project as a | |
| 7 | * whole. | |
| 8 | * | |
| 9 | * a) This library is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of the | |
| 12 | * License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This library is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * Or, alternatively, | |
| 20 | * | |
| 21 | * b) Permission is hereby granted, free of charge, to any person | |
| 22 | * obtaining a copy of this software and associated documentation | |
| 23 | * files (the "Software"), to deal in the Software without | |
| 24 | * restriction, including without limitation the rights to use, | |
| 25 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 26 | * sell copies of the Software, and to permit persons to whom the | |
| 27 | * Software is furnished to do so, subject to the following | |
| 28 | * conditions: | |
| 29 | * | |
| 30 | * The above copyright notice and this permission notice shall be | |
| 31 | * included in all copies or substantial portions of the Software. | |
| 32 | * | |
| 33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 40 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 41 | */ | |
| 42 | ||
| 43 | #include <dt-bindings/clock/rk3399-cru.h> | |
| 44 | #include <dt-bindings/gpio/gpio.h> | |
| 45 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 46 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 47 | #include <dt-bindings/pinctrl/rockchip.h> | |
| 807a2371 | 48 | #include <dt-bindings/power/rk3399-power.h> |
| 95c27ba7 | 49 | #include <dt-bindings/thermal/thermal.h> |
| f048b9a4 JX |
50 | |
| 51 | / { | |
| 52 | compatible = "rockchip,rk3399"; | |
| 53 | ||
| 54 | interrupt-parent = <&gic>; | |
| 55 | #address-cells = <2>; | |
| 56 | #size-cells = <2>; | |
| 57 | ||
| 58 | aliases { | |
| 69e5a8fe DW |
59 | i2c0 = &i2c0; |
| 60 | i2c1 = &i2c1; | |
| 61 | i2c2 = &i2c2; | |
| 62 | i2c3 = &i2c3; | |
| 63 | i2c4 = &i2c4; | |
| 64 | i2c5 = &i2c5; | |
| 65 | i2c6 = &i2c6; | |
| 66 | i2c7 = &i2c7; | |
| 67 | i2c8 = &i2c8; | |
| f048b9a4 JX |
68 | serial0 = &uart0; |
| 69 | serial1 = &uart1; | |
| 70 | serial2 = &uart2; | |
| 71 | serial3 = &uart3; | |
| 72 | serial4 = &uart4; | |
| 73 | }; | |
| 74 | ||
| 75 | cpus { | |
| 76 | #address-cells = <2>; | |
| 77 | #size-cells = <0>; | |
| 78 | ||
| 79 | cpu-map { | |
| 80 | cluster0 { | |
| 81 | core0 { | |
| 82 | cpu = <&cpu_l0>; | |
| 83 | }; | |
| 84 | core1 { | |
| 85 | cpu = <&cpu_l1>; | |
| 86 | }; | |
| 87 | core2 { | |
| 88 | cpu = <&cpu_l2>; | |
| 89 | }; | |
| 90 | core3 { | |
| 91 | cpu = <&cpu_l3>; | |
| 92 | }; | |
| 93 | }; | |
| 94 | ||
| 95 | cluster1 { | |
| 96 | core0 { | |
| 97 | cpu = <&cpu_b0>; | |
| 98 | }; | |
| 99 | core1 { | |
| 100 | cpu = <&cpu_b1>; | |
| 101 | }; | |
| 102 | }; | |
| 103 | }; | |
| 104 | ||
| 105 | cpu_l0: cpu@0 { | |
| 106 | device_type = "cpu"; | |
| 107 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 108 | reg = <0x0 0x0>; | |
| 109 | enable-method = "psci"; | |
| 110 | #cooling-cells = <2>; /* min followed by max */ | |
| 111 | clocks = <&cru ARMCLKL>; | |
| 112 | }; | |
| 113 | ||
| 114 | cpu_l1: cpu@1 { | |
| 115 | device_type = "cpu"; | |
| 116 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 117 | reg = <0x0 0x1>; | |
| 118 | enable-method = "psci"; | |
| 119 | clocks = <&cru ARMCLKL>; | |
| 120 | }; | |
| 121 | ||
| 122 | cpu_l2: cpu@2 { | |
| 123 | device_type = "cpu"; | |
| 124 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 125 | reg = <0x0 0x2>; | |
| 126 | enable-method = "psci"; | |
| 127 | clocks = <&cru ARMCLKL>; | |
| 128 | }; | |
| 129 | ||
| 130 | cpu_l3: cpu@3 { | |
| 131 | device_type = "cpu"; | |
| 132 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 133 | reg = <0x0 0x3>; | |
| 134 | enable-method = "psci"; | |
| 135 | clocks = <&cru ARMCLKL>; | |
| 136 | }; | |
| 137 | ||
| 138 | cpu_b0: cpu@100 { | |
| 139 | device_type = "cpu"; | |
| 140 | compatible = "arm,cortex-a72", "arm,armv8"; | |
| 141 | reg = <0x0 0x100>; | |
| 142 | enable-method = "psci"; | |
| 143 | #cooling-cells = <2>; /* min followed by max */ | |
| 144 | clocks = <&cru ARMCLKB>; | |
| 145 | }; | |
| 146 | ||
| 147 | cpu_b1: cpu@101 { | |
| 148 | device_type = "cpu"; | |
| 149 | compatible = "arm,cortex-a72", "arm,armv8"; | |
| 150 | reg = <0x0 0x101>; | |
| 151 | enable-method = "psci"; | |
| 152 | clocks = <&cru ARMCLKB>; | |
| 153 | }; | |
| 154 | }; | |
| 155 | ||
| 156 | psci { | |
| 157 | compatible = "arm,psci-1.0"; | |
| 158 | method = "smc"; | |
| 159 | }; | |
| 160 | ||
| 161 | timer { | |
| 162 | compatible = "arm,armv8-timer"; | |
| 163 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, | |
| 164 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, | |
| 165 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, | |
| 166 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; | |
| 167 | }; | |
| 168 | ||
| 169 | xin24m: xin24m { | |
| 170 | compatible = "fixed-clock"; | |
| 171 | clock-frequency = <24000000>; | |
| 172 | clock-output-names = "xin24m"; | |
| 173 | #clock-cells = <0>; | |
| 174 | }; | |
| 175 | ||
| 176 | amba { | |
| 15b7cc78 | 177 | compatible = "simple-bus"; |
| f048b9a4 JX |
178 | #address-cells = <2>; |
| 179 | #size-cells = <2>; | |
| 180 | ranges; | |
| 181 | ||
| 182 | dmac_bus: dma-controller@ff6d0000 { | |
| 183 | compatible = "arm,pl330", "arm,primecell"; | |
| 184 | reg = <0x0 0xff6d0000 0x0 0x4000>; | |
| 185 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, | |
| 186 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 187 | #dma-cells = <1>; | |
| 188 | clocks = <&cru ACLK_DMAC0_PERILP>; | |
| 189 | clock-names = "apb_pclk"; | |
| 190 | }; | |
| 191 | ||
| 192 | dmac_peri: dma-controller@ff6e0000 { | |
| 193 | compatible = "arm,pl330", "arm,primecell"; | |
| 194 | reg = <0x0 0xff6e0000 0x0 0x4000>; | |
| 195 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
| 196 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 197 | #dma-cells = <1>; | |
| 198 | clocks = <&cru ACLK_DMAC1_PERILP>; | |
| 199 | clock-names = "apb_pclk"; | |
| 200 | }; | |
| 201 | }; | |
| 202 | ||
| 203 | sdio0: dwmmc@fe310000 { | |
| 204 | compatible = "rockchip,rk3399-dw-mshc", | |
| 205 | "rockchip,rk3288-dw-mshc"; | |
| 206 | reg = <0x0 0xfe310000 0x0 0x4000>; | |
| 207 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
| 208 | clock-freq-min-max = <400000 150000000>; | |
| 209 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, | |
| 210 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; | |
| 211 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
| 212 | fifo-depth = <0x100>; | |
| 213 | status = "disabled"; | |
| 214 | }; | |
| 215 | ||
| 216 | sdmmc: dwmmc@fe320000 { | |
| 217 | compatible = "rockchip,rk3399-dw-mshc", | |
| 218 | "rockchip,rk3288-dw-mshc"; | |
| 219 | reg = <0x0 0xfe320000 0x0 0x4000>; | |
| 220 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
| 221 | clock-freq-min-max = <400000 150000000>; | |
| 222 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, | |
| 223 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | |
| 224 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
| 225 | fifo-depth = <0x100>; | |
| 226 | status = "disabled"; | |
| 227 | }; | |
| 228 | ||
| b4e87c09 BN |
229 | sdhci: sdhci@fe330000 { |
| 230 | compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; | |
| 231 | reg = <0x0 0xfe330000 0x0 0x10000>; | |
| 232 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 64e3481c | 233 | arasan,soc-ctl-syscon = <&grf>; |
| b4e87c09 BN |
234 | assigned-clocks = <&cru SCLK_EMMC>; |
| 235 | assigned-clock-rates = <200000000>; | |
| 236 | clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; | |
| 237 | clock-names = "clk_xin", "clk_ahb"; | |
| ed388cdd DA |
238 | clock-output-names = "emmc_cardclock"; |
| 239 | #clock-cells = <0>; | |
| b4e87c09 BN |
240 | phys = <&emmc_phy>; |
| 241 | phy-names = "phy_arasan"; | |
| 242 | status = "disabled"; | |
| 243 | }; | |
| 244 | ||
| f048b9a4 JX |
245 | usb_host0_ehci: usb@fe380000 { |
| 246 | compatible = "generic-ehci"; | |
| 247 | reg = <0x0 0xfe380000 0x0 0x20000>; | |
| 248 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| 249 | clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; | |
| 250 | clock-names = "hclk_host0", "hclk_host0_arb"; | |
| 251 | status = "disabled"; | |
| 252 | }; | |
| 253 | ||
| 254 | usb_host0_ohci: usb@fe3a0000 { | |
| 255 | compatible = "generic-ohci"; | |
| 256 | reg = <0x0 0xfe3a0000 0x0 0x20000>; | |
| 257 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
| 258 | clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; | |
| 259 | clock-names = "hclk_host0", "hclk_host0_arb"; | |
| 260 | status = "disabled"; | |
| 261 | }; | |
| 262 | ||
| 263 | usb_host1_ehci: usb@fe3c0000 { | |
| 264 | compatible = "generic-ehci"; | |
| 265 | reg = <0x0 0xfe3c0000 0x0 0x20000>; | |
| 266 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 267 | clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; | |
| 268 | clock-names = "hclk_host1", "hclk_host1_arb"; | |
| 269 | status = "disabled"; | |
| 270 | }; | |
| 271 | ||
| 272 | usb_host1_ohci: usb@fe3e0000 { | |
| 273 | compatible = "generic-ohci"; | |
| 274 | reg = <0x0 0xfe3e0000 0x0 0x20000>; | |
| 275 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
| 276 | clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; | |
| 277 | clock-names = "hclk_host1", "hclk_host1_arb"; | |
| 278 | status = "disabled"; | |
| 279 | }; | |
| 280 | ||
| 281 | gic: interrupt-controller@fee00000 { | |
| 282 | compatible = "arm,gic-v3"; | |
| 283 | #interrupt-cells = <3>; | |
| 284 | #address-cells = <2>; | |
| 285 | #size-cells = <2>; | |
| 286 | ranges; | |
| 287 | interrupt-controller; | |
| 288 | ||
| 289 | reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ | |
| 290 | <0x0 0xfef00000 0 0xc0000>, /* GICR */ | |
| 291 | <0x0 0xfff00000 0 0x10000>, /* GICC */ | |
| 292 | <0x0 0xfff10000 0 0x10000>, /* GICH */ | |
| 293 | <0x0 0xfff20000 0 0x10000>; /* GICV */ | |
| 294 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 295 | its: interrupt-controller@fee20000 { | |
| 296 | compatible = "arm,gic-v3-its"; | |
| 297 | msi-controller; | |
| 298 | reg = <0x0 0xfee20000 0x0 0x20000>; | |
| 299 | }; | |
| 300 | }; | |
| 301 | ||
| 69e5a8fe DW |
302 | i2c1: i2c@ff110000 { |
| 303 | compatible = "rockchip,rk3399-i2c"; | |
| 304 | reg = <0x0 0xff110000 0x0 0x1000>; | |
| 305 | assigned-clocks = <&cru SCLK_I2C1>; | |
| 306 | assigned-clock-rates = <200000000>; | |
| 307 | clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; | |
| 308 | clock-names = "i2c", "pclk"; | |
| 309 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
| 310 | pinctrl-names = "default"; | |
| 311 | pinctrl-0 = <&i2c1_xfer>; | |
| 312 | #address-cells = <1>; | |
| 313 | #size-cells = <0>; | |
| 314 | status = "disabled"; | |
| 315 | }; | |
| 316 | ||
| 317 | i2c2: i2c@ff120000 { | |
| 318 | compatible = "rockchip,rk3399-i2c"; | |
| 319 | reg = <0x0 0xff120000 0x0 0x1000>; | |
| 320 | assigned-clocks = <&cru SCLK_I2C2>; | |
| 321 | assigned-clock-rates = <200000000>; | |
| 322 | clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; | |
| 323 | clock-names = "i2c", "pclk"; | |
| 324 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| 325 | pinctrl-names = "default"; | |
| 326 | pinctrl-0 = <&i2c2_xfer>; | |
| 327 | #address-cells = <1>; | |
| 328 | #size-cells = <0>; | |
| 329 | status = "disabled"; | |
| 330 | }; | |
| 331 | ||
| 332 | i2c3: i2c@ff130000 { | |
| 333 | compatible = "rockchip,rk3399-i2c"; | |
| 334 | reg = <0x0 0xff130000 0x0 0x1000>; | |
| 335 | assigned-clocks = <&cru SCLK_I2C3>; | |
| 336 | assigned-clock-rates = <200000000>; | |
| 337 | clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; | |
| 338 | clock-names = "i2c", "pclk"; | |
| 339 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| 340 | pinctrl-names = "default"; | |
| 341 | pinctrl-0 = <&i2c3_xfer>; | |
| 342 | #address-cells = <1>; | |
| 343 | #size-cells = <0>; | |
| 344 | status = "disabled"; | |
| 345 | }; | |
| 346 | ||
| 347 | i2c5: i2c@ff140000 { | |
| 348 | compatible = "rockchip,rk3399-i2c"; | |
| 349 | reg = <0x0 0xff140000 0x0 0x1000>; | |
| 350 | assigned-clocks = <&cru SCLK_I2C5>; | |
| 351 | assigned-clock-rates = <200000000>; | |
| 352 | clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; | |
| 353 | clock-names = "i2c", "pclk"; | |
| 354 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 355 | pinctrl-names = "default"; | |
| 356 | pinctrl-0 = <&i2c5_xfer>; | |
| 357 | #address-cells = <1>; | |
| 358 | #size-cells = <0>; | |
| 359 | status = "disabled"; | |
| 360 | }; | |
| 361 | ||
| 362 | i2c6: i2c@ff150000 { | |
| 363 | compatible = "rockchip,rk3399-i2c"; | |
| 364 | reg = <0x0 0xff150000 0x0 0x1000>; | |
| 365 | assigned-clocks = <&cru SCLK_I2C6>; | |
| 366 | assigned-clock-rates = <200000000>; | |
| 367 | clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; | |
| 368 | clock-names = "i2c", "pclk"; | |
| 369 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 370 | pinctrl-names = "default"; | |
| 371 | pinctrl-0 = <&i2c6_xfer>; | |
| 372 | #address-cells = <1>; | |
| 373 | #size-cells = <0>; | |
| 374 | status = "disabled"; | |
| 375 | }; | |
| 376 | ||
| 377 | i2c7: i2c@ff160000 { | |
| 378 | compatible = "rockchip,rk3399-i2c"; | |
| 379 | reg = <0x0 0xff160000 0x0 0x1000>; | |
| 380 | assigned-clocks = <&cru SCLK_I2C7>; | |
| 381 | assigned-clock-rates = <200000000>; | |
| 382 | clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; | |
| 383 | clock-names = "i2c", "pclk"; | |
| 384 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 385 | pinctrl-names = "default"; | |
| 386 | pinctrl-0 = <&i2c7_xfer>; | |
| 387 | #address-cells = <1>; | |
| 388 | #size-cells = <0>; | |
| 389 | status = "disabled"; | |
| 390 | }; | |
| 391 | ||
| f048b9a4 JX |
392 | uart0: serial@ff180000 { |
| 393 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 394 | reg = <0x0 0xff180000 0x0 0x100>; | |
| 395 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
| 396 | clock-names = "baudclk", "apb_pclk"; | |
| 397 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
| 398 | reg-shift = <2>; | |
| 399 | reg-io-width = <4>; | |
| 400 | pinctrl-names = "default"; | |
| 401 | pinctrl-0 = <&uart0_xfer>; | |
| 402 | status = "disabled"; | |
| 403 | }; | |
| 404 | ||
| 405 | uart1: serial@ff190000 { | |
| 406 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 407 | reg = <0x0 0xff190000 0x0 0x100>; | |
| 408 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
| 409 | clock-names = "baudclk", "apb_pclk"; | |
| 410 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| 411 | reg-shift = <2>; | |
| 412 | reg-io-width = <4>; | |
| 413 | pinctrl-names = "default"; | |
| 414 | pinctrl-0 = <&uart1_xfer>; | |
| 415 | status = "disabled"; | |
| 416 | }; | |
| 417 | ||
| 418 | uart2: serial@ff1a0000 { | |
| 419 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 420 | reg = <0x0 0xff1a0000 0x0 0x100>; | |
| 421 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
| 422 | clock-names = "baudclk", "apb_pclk"; | |
| 423 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
| 424 | reg-shift = <2>; | |
| 425 | reg-io-width = <4>; | |
| 426 | pinctrl-names = "default"; | |
| 427 | pinctrl-0 = <&uart2c_xfer>; | |
| 428 | status = "disabled"; | |
| 429 | }; | |
| 430 | ||
| 431 | uart3: serial@ff1b0000 { | |
| 432 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 433 | reg = <0x0 0xff1b0000 0x0 0x100>; | |
| 434 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
| 435 | clock-names = "baudclk", "apb_pclk"; | |
| 436 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 437 | reg-shift = <2>; | |
| 438 | reg-io-width = <4>; | |
| 439 | pinctrl-names = "default"; | |
| 440 | pinctrl-0 = <&uart3_xfer>; | |
| 441 | status = "disabled"; | |
| 442 | }; | |
| 443 | ||
| 444 | spi0: spi@ff1c0000 { | |
| 445 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 446 | reg = <0x0 0xff1c0000 0x0 0x1000>; | |
| 447 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
| 448 | clock-names = "spiclk", "apb_pclk"; | |
| 449 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
| 450 | pinctrl-names = "default"; | |
| 451 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; | |
| 452 | #address-cells = <1>; | |
| 453 | #size-cells = <0>; | |
| 454 | status = "disabled"; | |
| 455 | }; | |
| 456 | ||
| 457 | spi1: spi@ff1d0000 { | |
| 458 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 459 | reg = <0x0 0xff1d0000 0x0 0x1000>; | |
| 460 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
| 461 | clock-names = "spiclk", "apb_pclk"; | |
| 462 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
| 463 | pinctrl-names = "default"; | |
| 464 | pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; | |
| 465 | #address-cells = <1>; | |
| 466 | #size-cells = <0>; | |
| 467 | status = "disabled"; | |
| 468 | }; | |
| 469 | ||
| 470 | spi2: spi@ff1e0000 { | |
| 471 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 472 | reg = <0x0 0xff1e0000 0x0 0x1000>; | |
| 473 | clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; | |
| 474 | clock-names = "spiclk", "apb_pclk"; | |
| 475 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
| 476 | pinctrl-names = "default"; | |
| 477 | pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; | |
| 478 | #address-cells = <1>; | |
| 479 | #size-cells = <0>; | |
| 480 | status = "disabled"; | |
| 481 | }; | |
| 482 | ||
| 483 | spi4: spi@ff1f0000 { | |
| 484 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 485 | reg = <0x0 0xff1f0000 0x0 0x1000>; | |
| 486 | clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; | |
| 487 | clock-names = "spiclk", "apb_pclk"; | |
| 488 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
| 489 | pinctrl-names = "default"; | |
| 490 | pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; | |
| 491 | #address-cells = <1>; | |
| 492 | #size-cells = <0>; | |
| 493 | status = "disabled"; | |
| 494 | }; | |
| 495 | ||
| 496 | spi5: spi@ff200000 { | |
| 497 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 498 | reg = <0x0 0xff200000 0x0 0x1000>; | |
| 499 | clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; | |
| 500 | clock-names = "spiclk", "apb_pclk"; | |
| 501 | interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
| 502 | pinctrl-names = "default"; | |
| 503 | pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; | |
| 504 | #address-cells = <1>; | |
| 505 | #size-cells = <0>; | |
| 506 | status = "disabled"; | |
| 507 | }; | |
| 508 | ||
| 95c27ba7 CW |
509 | thermal-zones { |
| 510 | cpu_thermal: cpu { | |
| 511 | polling-delay-passive = <100>; | |
| 512 | polling-delay = <1000>; | |
| 513 | ||
| 514 | thermal-sensors = <&tsadc 0>; | |
| 515 | ||
| 516 | trips { | |
| 517 | cpu_alert0: cpu_alert0 { | |
| 518 | temperature = <70000>; | |
| 519 | hysteresis = <2000>; | |
| 520 | type = "passive"; | |
| 521 | }; | |
| 522 | cpu_alert1: cpu_alert1 { | |
| 523 | temperature = <75000>; | |
| 524 | hysteresis = <2000>; | |
| 525 | type = "passive"; | |
| 526 | }; | |
| 527 | cpu_crit: cpu_crit { | |
| 528 | temperature = <95000>; | |
| 529 | hysteresis = <2000>; | |
| 530 | type = "critical"; | |
| 531 | }; | |
| 532 | }; | |
| 533 | ||
| 534 | cooling-maps { | |
| 535 | map0 { | |
| 536 | trip = <&cpu_alert0>; | |
| 537 | cooling-device = | |
| 538 | <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 539 | }; | |
| 540 | map1 { | |
| 541 | trip = <&cpu_alert1>; | |
| 542 | cooling-device = | |
| 543 | <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 544 | <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 545 | }; | |
| 546 | }; | |
| 547 | }; | |
| 548 | ||
| 549 | gpu_thermal: gpu { | |
| 550 | polling-delay-passive = <100>; | |
| 551 | polling-delay = <1000>; | |
| 552 | ||
| 553 | thermal-sensors = <&tsadc 1>; | |
| 554 | ||
| 555 | trips { | |
| 556 | gpu_alert0: gpu_alert0 { | |
| 557 | temperature = <75000>; | |
| 558 | hysteresis = <2000>; | |
| 559 | type = "passive"; | |
| 560 | }; | |
| 561 | gpu_crit: gpu_crit { | |
| 562 | temperature = <95000>; | |
| 563 | hysteresis = <2000>; | |
| 564 | type = "critical"; | |
| 565 | }; | |
| 566 | }; | |
| 567 | ||
| 568 | cooling-maps { | |
| 569 | map0 { | |
| 570 | trip = <&gpu_alert0>; | |
| 571 | cooling-device = | |
| 572 | <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 573 | }; | |
| 574 | }; | |
| 575 | }; | |
| 576 | }; | |
| 577 | ||
| 578 | tsadc: tsadc@ff260000 { | |
| 579 | compatible = "rockchip,rk3399-tsadc"; | |
| 580 | reg = <0x0 0xff260000 0x0 0x100>; | |
| 581 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
| 582 | assigned-clocks = <&cru SCLK_TSADC>; | |
| 583 | assigned-clock-rates = <750000>; | |
| 584 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | |
| 585 | clock-names = "tsadc", "apb_pclk"; | |
| 586 | resets = <&cru SRST_TSADC>; | |
| 587 | reset-names = "tsadc-apb"; | |
| 588 | rockchip,grf = <&grf>; | |
| 589 | rockchip,hw-tshut-temp = <95000>; | |
| 590 | pinctrl-names = "init", "default", "sleep"; | |
| 591 | pinctrl-0 = <&otp_gpio>; | |
| 592 | pinctrl-1 = <&otp_out>; | |
| 593 | pinctrl-2 = <&otp_gpio>; | |
| 594 | #thermal-sensor-cells = <1>; | |
| 595 | status = "disabled"; | |
| 596 | }; | |
| 597 | ||
| 807a2371 EZ |
598 | qos_hdcp: qos@ffa90000 { |
| 599 | compatible = "syscon"; | |
| 600 | reg = <0x0 0xffa90000 0x0 0x20>; | |
| 601 | }; | |
| 602 | ||
| 603 | qos_iep: qos@ffa98000 { | |
| 604 | compatible = "syscon"; | |
| 605 | reg = <0x0 0xffa98000 0x0 0x20>; | |
| 606 | }; | |
| 607 | ||
| 608 | qos_isp0_m0: qos@ffaa0000 { | |
| 609 | compatible = "syscon"; | |
| 610 | reg = <0x0 0xffaa0000 0x0 0x20>; | |
| 611 | }; | |
| 612 | ||
| 613 | qos_isp0_m1: qos@ffaa0080 { | |
| 614 | compatible = "syscon"; | |
| 615 | reg = <0x0 0xffaa0080 0x0 0x20>; | |
| 616 | }; | |
| 617 | ||
| 618 | qos_isp1_m0: qos@ffaa8000 { | |
| 619 | compatible = "syscon"; | |
| 620 | reg = <0x0 0xffaa8000 0x0 0x20>; | |
| 621 | }; | |
| 622 | ||
| 623 | qos_isp1_m1: qos@ffaa8080 { | |
| 624 | compatible = "syscon"; | |
| 625 | reg = <0x0 0xffaa8080 0x0 0x20>; | |
| 626 | }; | |
| 627 | ||
| 628 | qos_rga_r: qos@ffab0000 { | |
| 629 | compatible = "syscon"; | |
| 630 | reg = <0x0 0xffab0000 0x0 0x20>; | |
| 631 | }; | |
| 632 | ||
| 633 | qos_rga_w: qos@ffab0080 { | |
| 634 | compatible = "syscon"; | |
| 635 | reg = <0x0 0xffab0080 0x0 0x20>; | |
| 636 | }; | |
| 637 | ||
| 638 | qos_video_m0: qos@ffab8000 { | |
| 639 | compatible = "syscon"; | |
| 640 | reg = <0x0 0xffab8000 0x0 0x20>; | |
| 641 | }; | |
| 642 | ||
| 643 | qos_video_m1_r: qos@ffac0000 { | |
| 644 | compatible = "syscon"; | |
| 645 | reg = <0x0 0xffac0000 0x0 0x20>; | |
| 646 | }; | |
| 647 | ||
| 648 | qos_video_m1_w: qos@ffac0080 { | |
| 649 | compatible = "syscon"; | |
| 650 | reg = <0x0 0xffac0080 0x0 0x20>; | |
| 651 | }; | |
| 652 | ||
| 653 | qos_vop_big_r: qos@ffac8000 { | |
| 654 | compatible = "syscon"; | |
| 655 | reg = <0x0 0xffac8000 0x0 0x20>; | |
| 656 | }; | |
| 657 | ||
| 658 | qos_vop_big_w: qos@ffac8080 { | |
| 659 | compatible = "syscon"; | |
| 660 | reg = <0x0 0xffac8080 0x0 0x20>; | |
| 661 | }; | |
| 662 | ||
| 663 | qos_vop_little: qos@ffad0000 { | |
| 664 | compatible = "syscon"; | |
| 665 | reg = <0x0 0xffad0000 0x0 0x20>; | |
| 666 | }; | |
| 667 | ||
| 668 | qos_gpu: qos@ffae0000 { | |
| 669 | compatible = "syscon"; | |
| 670 | reg = <0x0 0xffae0000 0x0 0x20>; | |
| 671 | }; | |
| 672 | ||
| 673 | pmu: power-management@ff310000 { | |
| 674 | compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; | |
| 675 | reg = <0x0 0xff310000 0x0 0x1000>; | |
| 676 | ||
| 677 | /* | |
| 678 | * Note: RK3399 supports 6 voltage domains including VD_CORE_L, | |
| 679 | * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. | |
| 680 | * Some of the power domains are grouped together for every | |
| 681 | * voltage domain. | |
| 682 | * The detail contents as below. | |
| 683 | */ | |
| 684 | power: power-controller { | |
| 685 | compatible = "rockchip,rk3399-power-controller"; | |
| 686 | #power-domain-cells = <1>; | |
| 687 | #address-cells = <1>; | |
| 688 | #size-cells = <0>; | |
| 689 | ||
| 690 | /* These power domains are grouped by VD_CENTER */ | |
| 691 | pd_iep@RK3399_PD_IEP { | |
| 692 | reg = <RK3399_PD_IEP>; | |
| 693 | clocks = <&cru ACLK_IEP>, | |
| 694 | <&cru HCLK_IEP>; | |
| 695 | pm_qos = <&qos_iep>; | |
| 696 | }; | |
| 697 | pd_rga@RK3399_PD_RGA { | |
| 698 | reg = <RK3399_PD_RGA>; | |
| 699 | clocks = <&cru ACLK_RGA>, | |
| 700 | <&cru HCLK_RGA>; | |
| 701 | pm_qos = <&qos_rga_r>, | |
| 702 | <&qos_rga_w>; | |
| 703 | }; | |
| 704 | pd_vcodec@RK3399_PD_VCODEC { | |
| 705 | reg = <RK3399_PD_VCODEC>; | |
| 706 | clocks = <&cru ACLK_VCODEC>, | |
| 707 | <&cru HCLK_VCODEC>; | |
| 708 | pm_qos = <&qos_video_m0>; | |
| 709 | }; | |
| 710 | pd_vdu@RK3399_PD_VDU { | |
| 711 | reg = <RK3399_PD_VDU>; | |
| 712 | clocks = <&cru ACLK_VDU>, | |
| 713 | <&cru HCLK_VDU>; | |
| 714 | pm_qos = <&qos_video_m1_r>, | |
| 715 | <&qos_video_m1_w>; | |
| 716 | }; | |
| 717 | ||
| 718 | /* These power domains are grouped by VD_GPU */ | |
| 719 | pd_gpu@RK3399_PD_GPU { | |
| 720 | reg = <RK3399_PD_GPU>; | |
| 721 | clocks = <&cru ACLK_GPU>; | |
| 722 | pm_qos = <&qos_gpu>; | |
| 723 | }; | |
| 724 | ||
| 725 | /* These power domains are grouped by VD_LOGIC */ | |
| 726 | pd_vio@RK3399_PD_VIO { | |
| 727 | reg = <RK3399_PD_VIO>; | |
| 728 | #address-cells = <1>; | |
| 729 | #size-cells = <0>; | |
| 730 | ||
| 731 | pd_hdcp@RK3399_PD_HDCP { | |
| 732 | reg = <RK3399_PD_HDCP>; | |
| 733 | clocks = <&cru ACLK_HDCP>, | |
| 734 | <&cru HCLK_HDCP>, | |
| 735 | <&cru PCLK_HDCP>; | |
| 736 | pm_qos = <&qos_hdcp>; | |
| 737 | }; | |
| 738 | pd_isp0@RK3399_PD_ISP0 { | |
| 739 | reg = <RK3399_PD_ISP0>; | |
| 740 | clocks = <&cru ACLK_ISP0>, | |
| 741 | <&cru HCLK_ISP0>; | |
| 742 | pm_qos = <&qos_isp0_m0>, | |
| 743 | <&qos_isp0_m1>; | |
| 744 | }; | |
| 745 | pd_isp1@RK3399_PD_ISP1 { | |
| 746 | reg = <RK3399_PD_ISP1>; | |
| 747 | clocks = <&cru ACLK_ISP1>, | |
| 748 | <&cru HCLK_ISP1>; | |
| 749 | pm_qos = <&qos_isp1_m0>, | |
| 750 | <&qos_isp1_m1>; | |
| 751 | }; | |
| 752 | pd_vo@RK3399_PD_VO { | |
| 753 | reg = <RK3399_PD_VO>; | |
| 754 | #address-cells = <1>; | |
| 755 | #size-cells = <0>; | |
| 756 | ||
| 757 | pd_vopb@RK3399_PD_VOPB { | |
| 758 | reg = <RK3399_PD_VOPB>; | |
| 759 | clocks = <&cru ACLK_VOP0>, | |
| 760 | <&cru HCLK_VOP0>; | |
| 761 | pm_qos = <&qos_vop_big_r>, | |
| 762 | <&qos_vop_big_w>; | |
| 763 | }; | |
| 764 | pd_vopl@RK3399_PD_VOPL { | |
| 765 | reg = <RK3399_PD_VOPL>; | |
| 766 | clocks = <&cru ACLK_VOP1>, | |
| 767 | <&cru HCLK_VOP1>; | |
| 768 | pm_qos = <&qos_vop_little>; | |
| 769 | }; | |
| 770 | }; | |
| 771 | }; | |
| 772 | }; | |
| 773 | }; | |
| 774 | ||
| f048b9a4 | 775 | pmugrf: syscon@ff320000 { |
| 16759262 | 776 | compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; |
| f048b9a4 | 777 | reg = <0x0 0xff320000 0x0 0x1000>; |
| 16759262 BN |
778 | #address-cells = <1>; |
| 779 | #size-cells = <1>; | |
| 6d0e3a45 HS |
780 | |
| 781 | pmu_io_domains: io-domains { | |
| 782 | compatible = "rockchip,rk3399-pmu-io-voltage-domain"; | |
| 783 | status = "disabled"; | |
| 784 | }; | |
| f048b9a4 JX |
785 | }; |
| 786 | ||
| 787 | spi3: spi@ff350000 { | |
| 788 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 789 | reg = <0x0 0xff350000 0x0 0x1000>; | |
| 790 | clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; | |
| 791 | clock-names = "spiclk", "apb_pclk"; | |
| 792 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
| 793 | pinctrl-names = "default"; | |
| 794 | pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; | |
| 795 | #address-cells = <1>; | |
| 796 | #size-cells = <0>; | |
| 797 | status = "disabled"; | |
| 798 | }; | |
| 799 | ||
| 800 | uart4: serial@ff370000 { | |
| 801 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 802 | reg = <0x0 0xff370000 0x0 0x100>; | |
| 803 | clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; | |
| 804 | clock-names = "baudclk", "apb_pclk"; | |
| 805 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
| 806 | reg-shift = <2>; | |
| 807 | reg-io-width = <4>; | |
| 808 | pinctrl-names = "default"; | |
| 809 | pinctrl-0 = <&uart4_xfer>; | |
| 810 | status = "disabled"; | |
| 811 | }; | |
| 812 | ||
| 69e5a8fe DW |
813 | i2c0: i2c@ff3c0000 { |
| 814 | compatible = "rockchip,rk3399-i2c"; | |
| 815 | reg = <0x0 0xff3c0000 0x0 0x1000>; | |
| 816 | assigned-clocks = <&pmucru SCLK_I2C0_PMU>; | |
| 817 | assigned-clock-rates = <200000000>; | |
| 818 | clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; | |
| 819 | clock-names = "i2c", "pclk"; | |
| 820 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
| 821 | pinctrl-names = "default"; | |
| 822 | pinctrl-0 = <&i2c0_xfer>; | |
| 823 | #address-cells = <1>; | |
| 824 | #size-cells = <0>; | |
| 825 | status = "disabled"; | |
| 826 | }; | |
| 827 | ||
| 828 | i2c4: i2c@ff3d0000 { | |
| 829 | compatible = "rockchip,rk3399-i2c"; | |
| 830 | reg = <0x0 0xff3d0000 0x0 0x1000>; | |
| 831 | assigned-clocks = <&pmucru SCLK_I2C4_PMU>; | |
| 832 | assigned-clock-rates = <200000000>; | |
| 833 | clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; | |
| 834 | clock-names = "i2c", "pclk"; | |
| 835 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
| 836 | pinctrl-names = "default"; | |
| 837 | pinctrl-0 = <&i2c4_xfer>; | |
| 838 | #address-cells = <1>; | |
| 839 | #size-cells = <0>; | |
| 840 | status = "disabled"; | |
| 841 | }; | |
| 842 | ||
| 843 | i2c8: i2c@ff3e0000 { | |
| 844 | compatible = "rockchip,rk3399-i2c"; | |
| 845 | reg = <0x0 0xff3e0000 0x0 0x1000>; | |
| 846 | assigned-clocks = <&pmucru SCLK_I2C8_PMU>; | |
| 847 | assigned-clock-rates = <200000000>; | |
| 848 | clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; | |
| 849 | clock-names = "i2c", "pclk"; | |
| 850 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
| 851 | pinctrl-names = "default"; | |
| 852 | pinctrl-0 = <&i2c8_xfer>; | |
| 853 | #address-cells = <1>; | |
| 854 | #size-cells = <0>; | |
| 855 | status = "disabled"; | |
| f048b9a4 JX |
856 | }; |
| 857 | ||
| 858 | pwm0: pwm@ff420000 { | |
| 859 | compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| 860 | reg = <0x0 0xff420000 0x0 0x10>; | |
| 861 | #pwm-cells = <3>; | |
| 862 | pinctrl-names = "default"; | |
| 863 | pinctrl-0 = <&pwm0_pin>; | |
| 864 | clocks = <&pmucru PCLK_RKPWM_PMU>; | |
| 865 | clock-names = "pwm"; | |
| 866 | status = "disabled"; | |
| 867 | }; | |
| 868 | ||
| 869 | pwm1: pwm@ff420010 { | |
| 870 | compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| 871 | reg = <0x0 0xff420010 0x0 0x10>; | |
| 872 | #pwm-cells = <3>; | |
| 873 | pinctrl-names = "default"; | |
| 874 | pinctrl-0 = <&pwm1_pin>; | |
| 875 | clocks = <&pmucru PCLK_RKPWM_PMU>; | |
| 876 | clock-names = "pwm"; | |
| 877 | status = "disabled"; | |
| 878 | }; | |
| 879 | ||
| 880 | pwm2: pwm@ff420020 { | |
| 881 | compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| 882 | reg = <0x0 0xff420020 0x0 0x10>; | |
| 883 | #pwm-cells = <3>; | |
| 884 | pinctrl-names = "default"; | |
| 885 | pinctrl-0 = <&pwm2_pin>; | |
| 886 | clocks = <&pmucru PCLK_RKPWM_PMU>; | |
| 887 | clock-names = "pwm"; | |
| 888 | status = "disabled"; | |
| 889 | }; | |
| 890 | ||
| 891 | pwm3: pwm@ff420030 { | |
| 892 | compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| 893 | reg = <0x0 0xff420030 0x0 0x10>; | |
| 894 | #pwm-cells = <3>; | |
| 895 | pinctrl-names = "default"; | |
| 896 | pinctrl-0 = <&pwm3a_pin>; | |
| 897 | clocks = <&pmucru PCLK_RKPWM_PMU>; | |
| 898 | clock-names = "pwm"; | |
| 899 | status = "disabled"; | |
| 900 | }; | |
| 901 | ||
| 902 | pmucru: pmu-clock-controller@ff750000 { | |
| 903 | compatible = "rockchip,rk3399-pmucru"; | |
| 904 | reg = <0x0 0xff750000 0x0 0x1000>; | |
| 905 | #clock-cells = <1>; | |
| 906 | #reset-cells = <1>; | |
| 907 | assigned-clocks = <&pmucru PLL_PPLL>; | |
| 908 | assigned-clock-rates = <676000000>; | |
| 909 | }; | |
| 910 | ||
| 911 | cru: clock-controller@ff760000 { | |
| 912 | compatible = "rockchip,rk3399-cru"; | |
| 913 | reg = <0x0 0xff760000 0x0 0x1000>; | |
| 914 | #clock-cells = <1>; | |
| 915 | #reset-cells = <1>; | |
| a09906cd XZ |
916 | assigned-clocks = |
| 917 | <&cru PLL_GPLL>, <&cru PLL_CPLL>, | |
| 918 | <&cru PLL_NPLL>, | |
| 919 | <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, | |
| 920 | <&cru PCLK_PERIHP>, | |
| 921 | <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, | |
| 922 | <&cru PCLK_PERILP0>, | |
| 923 | <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; | |
| 924 | assigned-clock-rates = | |
| 925 | <594000000>, <800000000>, | |
| 926 | <1000000000>, | |
| 927 | <150000000>, <75000000>, | |
| 928 | <37500000>, | |
| 929 | <100000000>, <100000000>, | |
| 930 | <50000000>, | |
| 931 | <100000000>, <50000000>; | |
| f048b9a4 JX |
932 | }; |
| 933 | ||
| 934 | grf: syscon@ff770000 { | |
| 16759262 | 935 | compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; |
| f048b9a4 | 936 | reg = <0x0 0xff770000 0x0 0x10000>; |
| 16759262 BN |
937 | #address-cells = <1>; |
| 938 | #size-cells = <1>; | |
| b4e87c09 | 939 | |
| 6d0e3a45 HS |
940 | io_domains: io-domains { |
| 941 | compatible = "rockchip,rk3399-io-voltage-domain"; | |
| 942 | status = "disabled"; | |
| 943 | }; | |
| 944 | ||
| b4e87c09 BN |
945 | emmc_phy: phy@f780 { |
| 946 | compatible = "rockchip,rk3399-emmc-phy"; | |
| 947 | reg = <0xf780 0x24>; | |
| ed388cdd DA |
948 | clocks = <&sdhci>; |
| 949 | clock-names = "emmcclk"; | |
| b4e87c09 BN |
950 | #phy-cells = <0>; |
| 951 | status = "disabled"; | |
| 952 | }; | |
| f048b9a4 JX |
953 | }; |
| 954 | ||
| 955 | watchdog@ff840000 { | |
| 956 | compatible = "snps,dw-wdt"; | |
| 957 | reg = <0x0 0xff840000 0x0 0x100>; | |
| 958 | clocks = <&cru PCLK_WDT>; | |
| 959 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
| 960 | }; | |
| 961 | ||
| 1e8567d5 HT |
962 | rktimer: rktimer@ff850000 { |
| 963 | compatible = "rockchip,rk3399-timer"; | |
| 964 | reg = <0x0 0xff850000 0x0 0x1000>; | |
| 965 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| 966 | clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; | |
| 967 | clock-names = "pclk", "timer"; | |
| 968 | }; | |
| 969 | ||
| f048b9a4 JX |
970 | spdif: spdif@ff870000 { |
| 971 | compatible = "rockchip,rk3399-spdif"; | |
| 972 | reg = <0x0 0xff870000 0x0 0x1000>; | |
| 973 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
| 974 | dmas = <&dmac_bus 7>; | |
| 975 | dma-names = "tx"; | |
| 976 | clock-names = "mclk", "hclk"; | |
| 977 | clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; | |
| 978 | pinctrl-names = "default"; | |
| 979 | pinctrl-0 = <&spdif_bus>; | |
| 980 | status = "disabled"; | |
| 981 | }; | |
| 982 | ||
| 983 | i2s0: i2s@ff880000 { | |
| 984 | compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| 985 | reg = <0x0 0xff880000 0x0 0x1000>; | |
| 986 | rockchip,grf = <&grf>; | |
| 987 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
| 988 | dmas = <&dmac_bus 0>, <&dmac_bus 1>; | |
| 989 | dma-names = "tx", "rx"; | |
| 990 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 991 | clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; | |
| 992 | pinctrl-names = "default"; | |
| 993 | pinctrl-0 = <&i2s0_8ch_bus>; | |
| 994 | status = "disabled"; | |
| 995 | }; | |
| 996 | ||
| 997 | i2s1: i2s@ff890000 { | |
| 998 | compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| 999 | reg = <0x0 0xff890000 0x0 0x1000>; | |
| 1000 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| 1001 | dmas = <&dmac_bus 2>, <&dmac_bus 3>; | |
| 1002 | dma-names = "tx", "rx"; | |
| 1003 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 1004 | clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; | |
| 1005 | pinctrl-names = "default"; | |
| 1006 | pinctrl-0 = <&i2s1_2ch_bus>; | |
| 1007 | status = "disabled"; | |
| 1008 | }; | |
| 1009 | ||
| 1010 | i2s2: i2s@ff8a0000 { | |
| 1011 | compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| 1012 | reg = <0x0 0xff8a0000 0x0 0x1000>; | |
| 1013 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
| 1014 | dmas = <&dmac_bus 4>, <&dmac_bus 5>; | |
| 1015 | dma-names = "tx", "rx"; | |
| 1016 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 1017 | clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; | |
| 1018 | status = "disabled"; | |
| 1019 | }; | |
| 1020 | ||
| 1021 | pinctrl: pinctrl { | |
| 1022 | compatible = "rockchip,rk3399-pinctrl"; | |
| 1023 | rockchip,grf = <&grf>; | |
| 1024 | rockchip,pmu = <&pmugrf>; | |
| 1025 | #address-cells = <2>; | |
| 1026 | #size-cells = <2>; | |
| 1027 | ranges; | |
| 1028 | ||
| 1029 | gpio0: gpio0@ff720000 { | |
| 1030 | compatible = "rockchip,gpio-bank"; | |
| 1031 | reg = <0x0 0xff720000 0x0 0x100>; | |
| 1032 | clocks = <&pmucru PCLK_GPIO0_PMU>; | |
| 1033 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 1034 | ||
| 1035 | gpio-controller; | |
| 1036 | #gpio-cells = <0x2>; | |
| 1037 | ||
| 1038 | interrupt-controller; | |
| 1039 | #interrupt-cells = <0x2>; | |
| 1040 | }; | |
| 1041 | ||
| 1042 | gpio1: gpio1@ff730000 { | |
| 1043 | compatible = "rockchip,gpio-bank"; | |
| 1044 | reg = <0x0 0xff730000 0x0 0x100>; | |
| 1045 | clocks = <&pmucru PCLK_GPIO1_PMU>; | |
| 1046 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
| 1047 | ||
| 1048 | gpio-controller; | |
| 1049 | #gpio-cells = <0x2>; | |
| 1050 | ||
| 1051 | interrupt-controller; | |
| 1052 | #interrupt-cells = <0x2>; | |
| 1053 | }; | |
| 1054 | ||
| 1055 | gpio2: gpio2@ff780000 { | |
| 1056 | compatible = "rockchip,gpio-bank"; | |
| 1057 | reg = <0x0 0xff780000 0x0 0x100>; | |
| 1058 | clocks = <&cru PCLK_GPIO2>; | |
| 1059 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 1060 | ||
| 1061 | gpio-controller; | |
| 1062 | #gpio-cells = <0x2>; | |
| 1063 | ||
| 1064 | interrupt-controller; | |
| 1065 | #interrupt-cells = <0x2>; | |
| 1066 | }; | |
| 1067 | ||
| 1068 | gpio3: gpio3@ff788000 { | |
| 1069 | compatible = "rockchip,gpio-bank"; | |
| 1070 | reg = <0x0 0xff788000 0x0 0x100>; | |
| 1071 | clocks = <&cru PCLK_GPIO3>; | |
| 1072 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 1073 | ||
| 1074 | gpio-controller; | |
| 1075 | #gpio-cells = <0x2>; | |
| 1076 | ||
| 1077 | interrupt-controller; | |
| 1078 | #interrupt-cells = <0x2>; | |
| 1079 | }; | |
| 1080 | ||
| 1081 | gpio4: gpio4@ff790000 { | |
| 1082 | compatible = "rockchip,gpio-bank"; | |
| 1083 | reg = <0x0 0xff790000 0x0 0x100>; | |
| 1084 | clocks = <&cru PCLK_GPIO4>; | |
| 1085 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
| 1086 | ||
| 1087 | gpio-controller; | |
| 1088 | #gpio-cells = <0x2>; | |
| 1089 | ||
| 1090 | interrupt-controller; | |
| 1091 | #interrupt-cells = <0x2>; | |
| 1092 | }; | |
| 1093 | ||
| 1094 | pcfg_pull_up: pcfg-pull-up { | |
| 1095 | bias-pull-up; | |
| 1096 | }; | |
| 1097 | ||
| 1098 | pcfg_pull_down: pcfg-pull-down { | |
| 1099 | bias-pull-down; | |
| 1100 | }; | |
| 1101 | ||
| 1102 | pcfg_pull_none: pcfg-pull-none { | |
| 1103 | bias-disable; | |
| 1104 | }; | |
| 1105 | ||
| 1106 | pcfg_pull_none_12ma: pcfg-pull-none-12ma { | |
| 1107 | bias-disable; | |
| 1108 | drive-strength = <12>; | |
| 1109 | }; | |
| 1110 | ||
| 1111 | pcfg_pull_up_8ma: pcfg-pull-up-8ma { | |
| 1112 | bias-pull-up; | |
| 1113 | drive-strength = <8>; | |
| 1114 | }; | |
| 1115 | ||
| 1116 | pcfg_pull_down_4ma: pcfg-pull-down-4ma { | |
| 1117 | bias-pull-down; | |
| 1118 | drive-strength = <4>; | |
| 1119 | }; | |
| 1120 | ||
| 1121 | pcfg_pull_up_2ma: pcfg-pull-up-2ma { | |
| 1122 | bias-pull-up; | |
| 1123 | drive-strength = <2>; | |
| 1124 | }; | |
| 1125 | ||
| 1126 | pcfg_pull_down_12ma: pcfg-pull-down-12ma { | |
| 1127 | bias-pull-down; | |
| 1128 | drive-strength = <12>; | |
| 1129 | }; | |
| 1130 | ||
| 1131 | pcfg_pull_none_13ma: pcfg-pull-none-13ma { | |
| 1132 | bias-disable; | |
| 1133 | drive-strength = <13>; | |
| 1134 | }; | |
| 1135 | ||
| 1136 | i2c0 { | |
| 1137 | i2c0_xfer: i2c0-xfer { | |
| 1138 | rockchip,pins = | |
| 1139 | <1 15 RK_FUNC_2 &pcfg_pull_none>, | |
| 1140 | <1 16 RK_FUNC_2 &pcfg_pull_none>; | |
| 1141 | }; | |
| 1142 | }; | |
| 1143 | ||
| 1144 | i2c1 { | |
| 1145 | i2c1_xfer: i2c1-xfer { | |
| 1146 | rockchip,pins = | |
| 1147 | <4 2 RK_FUNC_1 &pcfg_pull_none>, | |
| 1148 | <4 1 RK_FUNC_1 &pcfg_pull_none>; | |
| 1149 | }; | |
| 1150 | }; | |
| 1151 | ||
| 1152 | i2c2 { | |
| 1153 | i2c2_xfer: i2c2-xfer { | |
| 1154 | rockchip,pins = | |
| 1155 | <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, | |
| 1156 | <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; | |
| 1157 | }; | |
| 1158 | }; | |
| 1159 | ||
| 1160 | i2c3 { | |
| 1161 | i2c3_xfer: i2c3-xfer { | |
| 1162 | rockchip,pins = | |
| 1163 | <4 17 RK_FUNC_1 &pcfg_pull_none>, | |
| 1164 | <4 16 RK_FUNC_1 &pcfg_pull_none>; | |
| 1165 | }; | |
| 1166 | }; | |
| 1167 | ||
| 1168 | i2c4 { | |
| 1169 | i2c4_xfer: i2c4-xfer { | |
| 1170 | rockchip,pins = | |
| 1171 | <1 12 RK_FUNC_1 &pcfg_pull_none>, | |
| 1172 | <1 11 RK_FUNC_1 &pcfg_pull_none>; | |
| 1173 | }; | |
| 1174 | }; | |
| 1175 | ||
| 1176 | i2c5 { | |
| 1177 | i2c5_xfer: i2c5-xfer { | |
| 1178 | rockchip,pins = | |
| 1179 | <3 11 RK_FUNC_2 &pcfg_pull_none>, | |
| 1180 | <3 10 RK_FUNC_2 &pcfg_pull_none>; | |
| 1181 | }; | |
| 1182 | }; | |
| 1183 | ||
| 1184 | i2c6 { | |
| 1185 | i2c6_xfer: i2c6-xfer { | |
| 1186 | rockchip,pins = | |
| 1187 | <2 10 RK_FUNC_2 &pcfg_pull_none>, | |
| 1188 | <2 9 RK_FUNC_2 &pcfg_pull_none>; | |
| 1189 | }; | |
| 1190 | }; | |
| 1191 | ||
| 1192 | i2c7 { | |
| 1193 | i2c7_xfer: i2c7-xfer { | |
| 1194 | rockchip,pins = | |
| 1195 | <2 8 RK_FUNC_2 &pcfg_pull_none>, | |
| 1196 | <2 7 RK_FUNC_2 &pcfg_pull_none>; | |
| 1197 | }; | |
| 1198 | }; | |
| 1199 | ||
| 1200 | i2c8 { | |
| 1201 | i2c8_xfer: i2c8-xfer { | |
| 1202 | rockchip,pins = | |
| 1203 | <1 21 RK_FUNC_1 &pcfg_pull_none>, | |
| 1204 | <1 20 RK_FUNC_1 &pcfg_pull_none>; | |
| 1205 | }; | |
| 1206 | }; | |
| 1207 | ||
| 1208 | i2s0 { | |
| 1209 | i2s0_8ch_bus: i2s0-8ch-bus { | |
| 1210 | rockchip,pins = | |
| 1211 | <3 24 RK_FUNC_1 &pcfg_pull_none>, | |
| 1212 | <3 25 RK_FUNC_1 &pcfg_pull_none>, | |
| 1213 | <3 26 RK_FUNC_1 &pcfg_pull_none>, | |
| 1214 | <3 27 RK_FUNC_1 &pcfg_pull_none>, | |
| 1215 | <3 28 RK_FUNC_1 &pcfg_pull_none>, | |
| 1216 | <3 29 RK_FUNC_1 &pcfg_pull_none>, | |
| 1217 | <3 30 RK_FUNC_1 &pcfg_pull_none>, | |
| 1218 | <3 31 RK_FUNC_1 &pcfg_pull_none>, | |
| 1219 | <4 0 RK_FUNC_1 &pcfg_pull_none>; | |
| 1220 | }; | |
| 1221 | }; | |
| 1222 | ||
| 1223 | i2s1 { | |
| 1224 | i2s1_2ch_bus: i2s1-2ch-bus { | |
| 1225 | rockchip,pins = | |
| 1226 | <4 3 RK_FUNC_1 &pcfg_pull_none>, | |
| 1227 | <4 4 RK_FUNC_1 &pcfg_pull_none>, | |
| 1228 | <4 5 RK_FUNC_1 &pcfg_pull_none>, | |
| 1229 | <4 6 RK_FUNC_1 &pcfg_pull_none>, | |
| 1230 | <4 7 RK_FUNC_1 &pcfg_pull_none>; | |
| 1231 | }; | |
| 1232 | }; | |
| 1233 | ||
| 5d26ad9c DA |
1234 | sleep { |
| 1235 | ap_pwroff: ap-pwroff { | |
| 1236 | rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; | |
| 1237 | }; | |
| 1238 | ||
| 1239 | ddrio_pwroff: ddrio-pwroff { | |
| 1240 | rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
| 1241 | }; | |
| 1242 | }; | |
| 1243 | ||
| f048b9a4 JX |
1244 | spdif { |
| 1245 | spdif_bus: spdif-bus { | |
| 1246 | rockchip,pins = | |
| 1247 | <4 21 RK_FUNC_1 &pcfg_pull_none>; | |
| 1248 | }; | |
| 1249 | }; | |
| 1250 | ||
| 1251 | spi0 { | |
| 1252 | spi0_clk: spi0-clk { | |
| 1253 | rockchip,pins = | |
| 1254 | <3 6 RK_FUNC_2 &pcfg_pull_up>; | |
| 1255 | }; | |
| 1256 | spi0_cs0: spi0-cs0 { | |
| 1257 | rockchip,pins = | |
| 1258 | <3 7 RK_FUNC_2 &pcfg_pull_up>; | |
| 1259 | }; | |
| 1260 | spi0_cs1: spi0-cs1 { | |
| 1261 | rockchip,pins = | |
| 1262 | <3 8 RK_FUNC_2 &pcfg_pull_up>; | |
| 1263 | }; | |
| 1264 | spi0_tx: spi0-tx { | |
| 1265 | rockchip,pins = | |
| 1266 | <3 5 RK_FUNC_2 &pcfg_pull_up>; | |
| 1267 | }; | |
| 1268 | spi0_rx: spi0-rx { | |
| 1269 | rockchip,pins = | |
| 1270 | <3 4 RK_FUNC_2 &pcfg_pull_up>; | |
| 1271 | }; | |
| 1272 | }; | |
| 1273 | ||
| 1274 | spi1 { | |
| 1275 | spi1_clk: spi1-clk { | |
| 1276 | rockchip,pins = | |
| 1277 | <1 9 RK_FUNC_2 &pcfg_pull_up>; | |
| 1278 | }; | |
| 1279 | spi1_cs0: spi1-cs0 { | |
| 1280 | rockchip,pins = | |
| 1281 | <1 10 RK_FUNC_2 &pcfg_pull_up>; | |
| 1282 | }; | |
| 1283 | spi1_rx: spi1-rx { | |
| 1284 | rockchip,pins = | |
| 1285 | <1 7 RK_FUNC_2 &pcfg_pull_up>; | |
| 1286 | }; | |
| 1287 | spi1_tx: spi1-tx { | |
| 1288 | rockchip,pins = | |
| 1289 | <1 8 RK_FUNC_2 &pcfg_pull_up>; | |
| 1290 | }; | |
| 1291 | }; | |
| 1292 | ||
| 1293 | spi2 { | |
| 1294 | spi2_clk: spi2-clk { | |
| 1295 | rockchip,pins = | |
| 1296 | <2 11 RK_FUNC_1 &pcfg_pull_up>; | |
| 1297 | }; | |
| 1298 | spi2_cs0: spi2-cs0 { | |
| 1299 | rockchip,pins = | |
| 1300 | <2 12 RK_FUNC_1 &pcfg_pull_up>; | |
| 1301 | }; | |
| 1302 | spi2_rx: spi2-rx { | |
| 1303 | rockchip,pins = | |
| 1304 | <2 9 RK_FUNC_1 &pcfg_pull_up>; | |
| 1305 | }; | |
| 1306 | spi2_tx: spi2-tx { | |
| 1307 | rockchip,pins = | |
| 1308 | <2 10 RK_FUNC_1 &pcfg_pull_up>; | |
| 1309 | }; | |
| 1310 | }; | |
| 1311 | ||
| 1312 | spi3 { | |
| 1313 | spi3_clk: spi3-clk { | |
| 1314 | rockchip,pins = | |
| 1315 | <1 17 RK_FUNC_1 &pcfg_pull_up>; | |
| 1316 | }; | |
| 1317 | spi3_cs0: spi3-cs0 { | |
| 1318 | rockchip,pins = | |
| 1319 | <1 18 RK_FUNC_1 &pcfg_pull_up>; | |
| 1320 | }; | |
| 1321 | spi3_rx: spi3-rx { | |
| 1322 | rockchip,pins = | |
| 1323 | <1 15 RK_FUNC_1 &pcfg_pull_up>; | |
| 1324 | }; | |
| 1325 | spi3_tx: spi3-tx { | |
| 1326 | rockchip,pins = | |
| 1327 | <1 16 RK_FUNC_1 &pcfg_pull_up>; | |
| 1328 | }; | |
| 1329 | }; | |
| 1330 | ||
| 1331 | spi4 { | |
| 1332 | spi4_clk: spi4-clk { | |
| 1333 | rockchip,pins = | |
| 1334 | <3 2 RK_FUNC_2 &pcfg_pull_up>; | |
| 1335 | }; | |
| 1336 | spi4_cs0: spi4-cs0 { | |
| 1337 | rockchip,pins = | |
| 1338 | <3 3 RK_FUNC_2 &pcfg_pull_up>; | |
| 1339 | }; | |
| 1340 | spi4_rx: spi4-rx { | |
| 1341 | rockchip,pins = | |
| 1342 | <3 0 RK_FUNC_2 &pcfg_pull_up>; | |
| 1343 | }; | |
| 1344 | spi4_tx: spi4-tx { | |
| 1345 | rockchip,pins = | |
| 1346 | <3 1 RK_FUNC_2 &pcfg_pull_up>; | |
| 1347 | }; | |
| 1348 | }; | |
| 1349 | ||
| 1350 | spi5 { | |
| 1351 | spi5_clk: spi5-clk { | |
| 1352 | rockchip,pins = | |
| 1353 | <2 22 RK_FUNC_2 &pcfg_pull_up>; | |
| 1354 | }; | |
| 1355 | spi5_cs0: spi5-cs0 { | |
| 1356 | rockchip,pins = | |
| 1357 | <2 23 RK_FUNC_2 &pcfg_pull_up>; | |
| 1358 | }; | |
| 1359 | spi5_rx: spi5-rx { | |
| 1360 | rockchip,pins = | |
| 1361 | <2 20 RK_FUNC_2 &pcfg_pull_up>; | |
| 1362 | }; | |
| 1363 | spi5_tx: spi5-tx { | |
| 1364 | rockchip,pins = | |
| 1365 | <2 21 RK_FUNC_2 &pcfg_pull_up>; | |
| 1366 | }; | |
| 1367 | }; | |
| 1368 | ||
| 95c27ba7 CW |
1369 | tsadc { |
| 1370 | otp_gpio: otp-gpio { | |
| 1371 | rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; | |
| 1372 | }; | |
| 1373 | ||
| 1374 | otp_out: otp-out { | |
| 1375 | rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; | |
| 1376 | }; | |
| 1377 | }; | |
| 1378 | ||
| f048b9a4 JX |
1379 | uart0 { |
| 1380 | uart0_xfer: uart0-xfer { | |
| 1381 | rockchip,pins = | |
| 1382 | <2 16 RK_FUNC_1 &pcfg_pull_up>, | |
| 1383 | <2 17 RK_FUNC_1 &pcfg_pull_none>; | |
| 1384 | }; | |
| 1385 | ||
| 1386 | uart0_cts: uart0-cts { | |
| 1387 | rockchip,pins = | |
| 1388 | <2 18 RK_FUNC_1 &pcfg_pull_none>; | |
| 1389 | }; | |
| 1390 | ||
| 1391 | uart0_rts: uart0-rts { | |
| 1392 | rockchip,pins = | |
| 1393 | <2 19 RK_FUNC_1 &pcfg_pull_none>; | |
| 1394 | }; | |
| 1395 | }; | |
| 1396 | ||
| 1397 | uart1 { | |
| 1398 | uart1_xfer: uart1-xfer { | |
| 1399 | rockchip,pins = | |
| 1400 | <3 12 RK_FUNC_2 &pcfg_pull_up>, | |
| 1401 | <3 13 RK_FUNC_2 &pcfg_pull_none>; | |
| 1402 | }; | |
| 1403 | }; | |
| 1404 | ||
| 1405 | uart2a { | |
| 1406 | uart2a_xfer: uart2a-xfer { | |
| 1407 | rockchip,pins = | |
| 1408 | <4 8 RK_FUNC_2 &pcfg_pull_up>, | |
| 1409 | <4 9 RK_FUNC_2 &pcfg_pull_none>; | |
| 1410 | }; | |
| 1411 | }; | |
| 1412 | ||
| 1413 | uart2b { | |
| 1414 | uart2b_xfer: uart2b-xfer { | |
| 1415 | rockchip,pins = | |
| 1416 | <4 16 RK_FUNC_2 &pcfg_pull_up>, | |
| 1417 | <4 17 RK_FUNC_2 &pcfg_pull_none>; | |
| 1418 | }; | |
| 1419 | }; | |
| 1420 | ||
| 1421 | uart2c { | |
| 1422 | uart2c_xfer: uart2c-xfer { | |
| 1423 | rockchip,pins = | |
| 1424 | <4 19 RK_FUNC_1 &pcfg_pull_up>, | |
| 1425 | <4 20 RK_FUNC_1 &pcfg_pull_none>; | |
| 1426 | }; | |
| 1427 | }; | |
| 1428 | ||
| 1429 | uart3 { | |
| 1430 | uart3_xfer: uart3-xfer { | |
| 1431 | rockchip,pins = | |
| 1432 | <3 14 RK_FUNC_2 &pcfg_pull_up>, | |
| 1433 | <3 15 RK_FUNC_2 &pcfg_pull_none>; | |
| 1434 | }; | |
| 1435 | ||
| 1436 | uart3_cts: uart3-cts { | |
| 1437 | rockchip,pins = | |
| 1438 | <3 18 RK_FUNC_2 &pcfg_pull_none>; | |
| 1439 | }; | |
| 1440 | ||
| 1441 | uart3_rts: uart3-rts { | |
| 1442 | rockchip,pins = | |
| 1443 | <3 19 RK_FUNC_2 &pcfg_pull_none>; | |
| 1444 | }; | |
| 1445 | }; | |
| 1446 | ||
| 1447 | uart4 { | |
| 1448 | uart4_xfer: uart4-xfer { | |
| 1449 | rockchip,pins = | |
| 1450 | <1 7 RK_FUNC_1 &pcfg_pull_up>, | |
| 1451 | <1 8 RK_FUNC_1 &pcfg_pull_none>; | |
| 1452 | }; | |
| 1453 | }; | |
| 1454 | ||
| 1455 | uarthdcp { | |
| 1456 | uarthdcp_xfer: uarthdcp-xfer { | |
| 1457 | rockchip,pins = | |
| 1458 | <4 21 RK_FUNC_2 &pcfg_pull_up>, | |
| 1459 | <4 22 RK_FUNC_2 &pcfg_pull_none>; | |
| 1460 | }; | |
| 1461 | }; | |
| 1462 | ||
| 1463 | pwm0 { | |
| 1464 | pwm0_pin: pwm0-pin { | |
| 1465 | rockchip,pins = | |
| 1466 | <4 18 RK_FUNC_1 &pcfg_pull_none>; | |
| 1467 | }; | |
| 1468 | ||
| 1469 | vop0_pwm_pin: vop0-pwm-pin { | |
| 1470 | rockchip,pins = | |
| 1471 | <4 18 RK_FUNC_2 &pcfg_pull_none>; | |
| 1472 | }; | |
| 1473 | }; | |
| 1474 | ||
| 1475 | pwm1 { | |
| 1476 | pwm1_pin: pwm1-pin { | |
| 1477 | rockchip,pins = | |
| 1478 | <4 22 RK_FUNC_1 &pcfg_pull_none>; | |
| 1479 | }; | |
| 1480 | ||
| 1481 | vop1_pwm_pin: vop1-pwm-pin { | |
| 1482 | rockchip,pins = | |
| 1483 | <4 18 RK_FUNC_3 &pcfg_pull_none>; | |
| 1484 | }; | |
| 1485 | }; | |
| 1486 | ||
| 1487 | pwm2 { | |
| 1488 | pwm2_pin: pwm2-pin { | |
| 1489 | rockchip,pins = | |
| 1490 | <1 19 RK_FUNC_1 &pcfg_pull_none>; | |
| 1491 | }; | |
| 1492 | }; | |
| 1493 | ||
| 1494 | pwm3a { | |
| 1495 | pwm3a_pin: pwm3a-pin { | |
| 1496 | rockchip,pins = | |
| 1497 | <0 6 RK_FUNC_1 &pcfg_pull_none>; | |
| 1498 | }; | |
| 1499 | }; | |
| 1500 | ||
| 1501 | pwm3b { | |
| 1502 | pwm3b_pin: pwm3b-pin { | |
| 1503 | rockchip,pins = | |
| 1504 | <1 14 RK_FUNC_1 &pcfg_pull_none>; | |
| 1505 | }; | |
| 1506 | }; | |
| 1507 | }; | |
| 1508 | }; |