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arm64: dts: rockchip: add 'chassis-type' property
[linux-block.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
CommitLineData
4ee99ceb 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
f048b9a4
JX		 2/*
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
f048b9a4
JX		 4 */
5
6#include <dt-bindings/clock/rk3399-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
807a2371 11#include <dt-bindings/power/rk3399-power.h>
95c27ba7 12#include <dt-bindings/thermal/thermal.h>
f048b9a4
JX		 13
14/ {
15 compatible = "rockchip,rk3399";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
2eca8411 22 ethernet0 = &gmac;
69e5a8fe
DW		 23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
f048b9a4
JX		 32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
38
39 cpus {
40 #address-cells = <2>;
41 #size-cells = <0>;
42
43 cpu-map {
44 cluster0 {
45 core0 {
46 cpu = <&cpu_l0>;
47 };
48 core1 {
49 cpu = <&cpu_l1>;
50 };
51 core2 {
52 cpu = <&cpu_l2>;
53 };
54 core3 {
55 cpu = <&cpu_l3>;
56 };
57 };
58
59 cluster1 {
60 core0 {
61 cpu = <&cpu_b0>;
62 };
63 core1 {
64 cpu = <&cpu_b1>;
65 };
66 };
67 };
68
69 cpu_l0: cpu@0 {
70 device_type = "cpu";
31af04cd 71 compatible = "arm,cortex-a53";
f048b9a4
JX		 72 reg = <0x0 0x0>;
73 enable-method = "psci";
97df3aa7 74 capacity-dmips-mhz = <485>;
f048b9a4 75 clocks = <&cru ARMCLKL>;
cc9b0918 76 #cooling-cells = <2>; /* min followed by max */
f4697bd7 77 dynamic-power-coefficient = <100>;
f888da16 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 79 };
80
81 cpu_l1: cpu@1 {
82 device_type = "cpu";
31af04cd 83 compatible = "arm,cortex-a53";
f048b9a4
JX		 84 reg = <0x0 0x1>;
85 enable-method = "psci";
97df3aa7 86 capacity-dmips-mhz = <485>;
f048b9a4 87 clocks = <&cru ARMCLKL>;
cc9b0918 88 #cooling-cells = <2>; /* min followed by max */
f4697bd7 89 dynamic-power-coefficient = <100>;
f888da16 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 91 };
92
93 cpu_l2: cpu@2 {
94 device_type = "cpu";
31af04cd 95 compatible = "arm,cortex-a53";
f048b9a4
JX		 96 reg = <0x0 0x2>;
97 enable-method = "psci";
97df3aa7 98 capacity-dmips-mhz = <485>;
f048b9a4 99 clocks = <&cru ARMCLKL>;
cc9b0918 100 #cooling-cells = <2>; /* min followed by max */
f4697bd7 101 dynamic-power-coefficient = <100>;
f888da16 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 103 };
104
105 cpu_l3: cpu@3 {
106 device_type = "cpu";
31af04cd 107 compatible = "arm,cortex-a53";
f048b9a4
JX		 108 reg = <0x0 0x3>;
109 enable-method = "psci";
97df3aa7 110 capacity-dmips-mhz = <485>;
f048b9a4 111 clocks = <&cru ARMCLKL>;
cc9b0918 112 #cooling-cells = <2>; /* min followed by max */
f4697bd7 113 dynamic-power-coefficient = <100>;
f888da16 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 115 };
116
117 cpu_b0: cpu@100 {
118 device_type = "cpu";
31af04cd 119 compatible = "arm,cortex-a72";
f048b9a4
JX		 120 reg = <0x0 0x100>;
121 enable-method = "psci";
97df3aa7 122 capacity-dmips-mhz = <1024>;
f048b9a4 123 clocks = <&cru ARMCLKB>;
cc9b0918 124 #cooling-cells = <2>; /* min followed by max */
45a995c0 125 dynamic-power-coefficient = <436>;
f888da16 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
f048b9a4
JX		 127 };
128
129 cpu_b1: cpu@101 {
130 device_type = "cpu";
31af04cd 131 compatible = "arm,cortex-a72";
f048b9a4
JX		 132 reg = <0x0 0x101>;
133 enable-method = "psci";
97df3aa7 134 capacity-dmips-mhz = <1024>;
f048b9a4 135 clocks = <&cru ARMCLKB>;
cc9b0918 136 #cooling-cells = <2>; /* min followed by max */
45a995c0 137 dynamic-power-coefficient = <436>;
f888da16
TX		 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
139 };
140
141 idle-states {
142 entry-method = "psci";
143
144 CPU_SLEEP: cpu-sleep {
145 compatible = "arm,idle-state";
146 local-timer-stop;
147 arm,psci-suspend-param = <0x0010000>;
148 entry-latency-us = <120>;
149 exit-latency-us = <250>;
150 min-residency-us = <900>;
151 };
152
153 CLUSTER_SLEEP: cluster-sleep {
154 compatible = "arm,idle-state";
155 local-timer-stop;
156 arm,psci-suspend-param = <0x1010000>;
157 entry-latency-us = <400>;
158 exit-latency-us = <500>;
159 min-residency-us = <2000>;
160 };
f048b9a4
JX		 161 };
162 };
163
fbd4cc0e
MY		 164 display-subsystem {
165 compatible = "rockchip,display-subsystem";
166 ports = <&vopl_out>, <&vopb_out>;
167 };
168
6840eb0d
CW		 169 pmu_a53 {
170 compatible = "arm,cortex-a53-pmu";
171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
172 };
173
174 pmu_a72 {
175 compatible = "arm,cortex-a72-pmu";
176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
177 };
178
f048b9a4
JX		 179 psci {
180 compatible = "arm,psci-1.0";
181 method = "smc";
182 };
183
184 timer {
185 compatible = "arm,armv8-timer";
210bbd38
CW		 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
e6186820 190 arm,no-tick-in-suspend;
f048b9a4
JX		 191 };
192
193 xin24m: xin24m {
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
197 #clock-cells = <0>;
198 };
199
66aef3cb
BN		 200 pcie0: pcie@f8000000 {
201 compatible = "rockchip,rk3399-pcie";
202 reg = <0x0 0xf8000000 0x0 0x2000000>,
203 <0x0 0xfd000000 0x0 0x1000000>;
204 reg-names = "axi-base", "apb-base";
43f20b1c 205 device_type = "pci";
66aef3cb
BN		 206 #address-cells = <3>;
207 #size-cells = <2>;
208 #interrupt-cells = <1>;
209 aspm-no-l0s;
d633becc 210 bus-range = <0x0 0x1f>;
66aef3cb
BN		 211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
213 clock-names = "aclk", "aclk-perf",
214 "hclk", "pm";
215 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
218 interrupt-names = "sys", "legacy", "client";
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
221 <0 0 0 2 &pcie0_intc 1>,
222 <0 0 0 3 &pcie0_intc 2>,
223 <0 0 0 4 &pcie0_intc 3>;
224 max-link-speed = <1>;
225 msi-map = <0x0 &its 0x0 0x1000>;
e9a60cac
SL		 226 phys = <&pcie_phy 0>, <&pcie_phy 1>,
227 <&pcie_phy 2>, <&pcie_phy 3>;
228 phy-names = "pcie-phy-0", "pcie-phy-1",
229 "pcie-phy-2", "pcie-phy-3";
8efe01b4 230 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
5b931210 231 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
66aef3cb
BN		 232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
233 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
234 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
235 <&cru SRST_A_PCIE>;
236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
237 "pm", "pclk", "aclk";
238 status = "disabled";
239
240 pcie0_intc: interrupt-controller {
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <1>;
244 };
245 };
246
eb3a6a6a
RC		 247 gmac: ethernet@fe300000 {
248 compatible = "rockchip,rk3399-gmac";
249 reg = <0x0 0xfe300000 0x0 0x10000>;
250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
251 interrupt-names = "macirq";
252 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
253 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
254 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
255 <&cru PCLK_GMAC>;
256 clock-names = "stmmaceth", "mac_clk_rx",
257 "mac_clk_tx", "clk_mac_ref",
258 "clk_mac_refout", "aclk_mac",
259 "pclk_mac";
260 power-domains = <&power RK3399_PD_GMAC>;
261 resets = <&cru SRST_A_GMAC>;
262 reset-names = "stmmaceth";
263 rockchip,grf = <&grf>;
8a469ee3 264 snps,txpbl = <0x4>;
eb3a6a6a
RC		 265 status = "disabled";
266 };
267
3ef7c255 268 sdio0: mmc@fe310000 {
f048b9a4
JX		 269 compatible = "rockchip,rk3399-dw-mshc",
270 "rockchip,rk3288-dw-mshc";
271 reg = <0x0 0xfe310000 0x0 0x4000>;
210bbd38 272 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 273 max-frequency = <150000000>;
f048b9a4
JX		 274 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
275 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
277 fifo-depth = <0x100>;
b0f2110a 278 power-domains = <&power RK3399_PD_SDIOAUDIO>;
04dc7f62
HS		 279 resets = <&cru SRST_SDIO0>;
280 reset-names = "reset";
f048b9a4
JX		 281 status = "disabled";
282 };
283
3ef7c255 284 sdmmc: mmc@fe320000 {
f048b9a4
JX		 285 compatible = "rockchip,rk3399-dw-mshc",
286 "rockchip,rk3288-dw-mshc";
287 reg = <0x0 0xfe320000 0x0 0x4000>;
210bbd38 288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 289 max-frequency = <150000000>;
e702e13f
LH		 290 assigned-clocks = <&cru HCLK_SD>;
291 assigned-clock-rates = <200000000>;
f048b9a4
JX		 292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
295 fifo-depth = <0x100>;
1bc60bee 296 power-domains = <&power RK3399_PD_SD>;
04dc7f62
HS		 297 resets = <&cru SRST_SDMMC>;
298 reset-names = "reset";
f048b9a4
JX		 299 status = "disabled";
300 };
301
9a9f6427 302 sdhci: mmc@fe330000 {
b4e87c09
BN		 303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
304 reg = <0x0 0xfe330000 0x0 0x10000>;
210bbd38 305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
64e3481c 306 arasan,soc-ctl-syscon = <&grf>;
b4e87c09
BN		 307 assigned-clocks = <&cru SCLK_EMMC>;
308 assigned-clock-rates = <200000000>;
309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
310 clock-names = "clk_xin", "clk_ahb";
ed388cdd
DA		 311 clock-output-names = "emmc_cardclock";
312 #clock-cells = <0>;
b4e87c09
BN		 313 phys = <&emmc_phy>;
314 phy-names = "phy_arasan";
a1907df2 315 power-domains = <&power RK3399_PD_EMMC>;
a3eec13b 316 disable-cqe-dcmd;
b4e87c09
BN		 317 status = "disabled";
318 };
319
f048b9a4
JX		 320 usb_host0_ehci: usb@fe380000 {
321 compatible = "generic-ehci";
322 reg = <0x0 0xfe380000 0x0 0x20000>;
210bbd38 323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
325 <&u2phy0>;
103e9f85
FW		 326 phys = <&u2phy0_host>;
327 phy-names = "usb";
f048b9a4
JX		 328 status = "disabled";
329 };
330
331 usb_host0_ohci: usb@fe3a0000 {
332 compatible = "generic-ohci";
333 reg = <0x0 0xfe3a0000 0x0 0x20000>;
210bbd38 334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
336 <&u2phy0>;
b5d1c572
W		 337 phys = <&u2phy0_host>;
338 phy-names = "usb";
f048b9a4
JX		 339 status = "disabled";
340 };
341
342 usb_host1_ehci: usb@fe3c0000 {
343 compatible = "generic-ehci";
344 reg = <0x0 0xfe3c0000 0x0 0x20000>;
210bbd38 345 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 346 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
347 <&u2phy1>;
103e9f85
FW		 348 phys = <&u2phy1_host>;
349 phy-names = "usb";
f048b9a4
JX		 350 status = "disabled";
351 };
352
353 usb_host1_ohci: usb@fe3e0000 {
354 compatible = "generic-ohci";
355 reg = <0x0 0xfe3e0000 0x0 0x20000>;
210bbd38 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
358 <&u2phy1>;
b5d1c572
W		 359 phys = <&u2phy1_host>;
360 phy-names = "usb";
f048b9a4
JX		 361 status = "disabled";
362 };
363
75dccea5
BN		 364 debug@fe430000 {
365 compatible = "arm,coresight-cpu-debug", "arm,primecell";
366 reg = <0 0xfe430000 0 0x1000>;
367 clocks = <&cru PCLK_COREDBG_L>;
368 clock-names = "apb_pclk";
369 cpu = <&cpu_l0>;
370 };
371
372 debug@fe432000 {
373 compatible = "arm,coresight-cpu-debug", "arm,primecell";
374 reg = <0 0xfe432000 0 0x1000>;
375 clocks = <&cru PCLK_COREDBG_L>;
376 clock-names = "apb_pclk";
377 cpu = <&cpu_l1>;
378 };
379
380 debug@fe434000 {
381 compatible = "arm,coresight-cpu-debug", "arm,primecell";
382 reg = <0 0xfe434000 0 0x1000>;
383 clocks = <&cru PCLK_COREDBG_L>;
384 clock-names = "apb_pclk";
385 cpu = <&cpu_l2>;
386 };
387
388 debug@fe436000 {
389 compatible = "arm,coresight-cpu-debug", "arm,primecell";
390 reg = <0 0xfe436000 0 0x1000>;
391 clocks = <&cru PCLK_COREDBG_L>;
392 clock-names = "apb_pclk";
393 cpu = <&cpu_l3>;
394 };
395
396 debug@fe610000 {
397 compatible = "arm,coresight-cpu-debug", "arm,primecell";
398 reg = <0 0xfe610000 0 0x1000>;
399 clocks = <&cru PCLK_COREDBG_B>;
400 clock-names = "apb_pclk";
401 cpu = <&cpu_b0>;
402 };
403
404 debug@fe710000 {
405 compatible = "arm,coresight-cpu-debug", "arm,primecell";
406 reg = <0 0xfe710000 0 0x1000>;
407 clocks = <&cru PCLK_COREDBG_B>;
408 clock-names = "apb_pclk";
409 cpu = <&cpu_b1>;
410 };
411
7144224f
BN		 412 usbdrd3_0: usb@fe800000 {
413 compatible = "rockchip,rk3399-dwc3";
414 #address-cells = <2>;
415 #size-cells = <2>;
416 ranges;
417 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
9df8a2d9
EBS		 418 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
419 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 420 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 421 "bus_clk", "aclk_usb3_rksoc_axi_perf",
422 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 423 resets = <&cru SRST_A_USB3_OTG0>;
424 reset-names = "usb3-otg";
7144224f
BN		 425 status = "disabled";
426
190c7f6f 427 usbdrd_dwc3_0: usb@fe800000 {
7144224f
BN		 428 compatible = "snps,dwc3";
429 reg = <0x0 0xfe800000 0x0 0x100000>;
430 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
e6d237fd
EBS		 431 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
432 <&cru SCLK_USB3OTG0_SUSPEND>;
433 clock-names = "ref", "bus_early", "suspend";
7144224f 434 dr_mode = "otg";
bfdca173
EBS		 435 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
436 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 437 phy_type = "utmi_wide";
438 snps,dis_enblslpm_quirk;
439 snps,dis-u2-freeclk-exists-quirk;
440 snps,dis_u2_susphy_quirk;
441 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 442 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 443 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 444 status = "disabled";
445 };
446 };
447
448 usbdrd3_1: usb@fe900000 {
449 compatible = "rockchip,rk3399-dwc3";
450 #address-cells = <2>;
451 #size-cells = <2>;
452 ranges;
453 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
9df8a2d9
EBS		 454 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
455 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 456 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 457 "bus_clk", "aclk_usb3_rksoc_axi_perf",
458 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 459 resets = <&cru SRST_A_USB3_OTG1>;
460 reset-names = "usb3-otg";
7144224f
BN		 461 status = "disabled";
462
190c7f6f 463 usbdrd_dwc3_1: usb@fe900000 {
7144224f
BN		 464 compatible = "snps,dwc3";
465 reg = <0x0 0xfe900000 0x0 0x100000>;
466 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
e6d237fd
EBS		 467 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
468 <&cru SCLK_USB3OTG1_SUSPEND>;
469 clock-names = "ref", "bus_early", "suspend";
7144224f 470 dr_mode = "otg";
bfdca173
EBS		 471 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
472 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 473 phy_type = "utmi_wide";
474 snps,dis_enblslpm_quirk;
475 snps,dis-u2-freeclk-exists-quirk;
476 snps,dis_u2_susphy_quirk;
477 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 478 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 479 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 480 status = "disabled";
481 };
482 };
483
2d3c2d56
CZ		 484 cdn_dp: dp@fec00000 {
485 compatible = "rockchip,rk3399-cdn-dp";
486 reg = <0x0 0xfec00000 0x0 0x100000>;
487 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
e702e13f
LH		 488 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
489 assigned-clock-rates = <100000000>, <200000000>;
2d3c2d56
CZ		 490 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
491 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
492 clock-names = "core-clk", "pclk", "spdif", "grf";
493 phys = <&tcphy0_dp>, <&tcphy1_dp>;
494 power-domains = <&power RK3399_PD_HDCP>;
495 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
496 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
497 reset-names = "spdif", "dptx", "apb", "core";
498 rockchip,grf = <&grf>;
499 #sound-dai-cells = <1>;
500 status = "disabled";
501
502 ports {
503 dp_in: port {
504 #address-cells = <1>;
505 #size-cells = <0>;
506
507 dp_in_vopb: endpoint@0 {
508 reg = <0>;
509 remote-endpoint = <&vopb_out_dp>;
510 };
511
512 dp_in_vopl: endpoint@1 {
513 reg = <1>;
514 remote-endpoint = <&vopl_out_dp>;
515 };
516 };
517 };
518 };
519
f048b9a4
JX		 520 gic: interrupt-controller@fee00000 {
521 compatible = "arm,gic-v3";
210bbd38 522 #interrupt-cells = <4>;
f048b9a4
JX		 523 #address-cells = <2>;
524 #size-cells = <2>;
525 ranges;
526 interrupt-controller;
527
528 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
529 <0x0 0xfef00000 0 0xc0000>, /* GICR */
530 <0x0 0xfff00000 0 0x10000>, /* GICC */
531 <0x0 0xfff10000 0 0x10000>, /* GICH */
532 <0x0 0xfff20000 0 0x10000>; /* GICV */
210bbd38 533 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 534 its: interrupt-controller@fee20000 {
535 compatible = "arm,gic-v3-its";
536 msi-controller;
85dd7638 537 #msi-cells = <1>;
f048b9a4
JX		 538 reg = <0x0 0xfee20000 0x0 0x20000>;
539 };
6840eb0d
CW		 540
541 ppi-partitions {
542 ppi_cluster0: interrupt-partition-0 {
543 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
544 };
545
546 ppi_cluster1: interrupt-partition-1 {
547 affinity = <&cpu_b0 &cpu_b1>;
548 };
549 };
f048b9a4
JX		 550 };
551
fe996215
CW		 552 saradc: saradc@ff100000 {
553 compatible = "rockchip,rk3399-saradc";
554 reg = <0x0 0xff100000 0x0 0x100>;
210bbd38 555 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
fe996215
CW		 556 #io-channel-cells = <1>;
557 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
558 clock-names = "saradc", "apb_pclk";
559 resets = <&cru SRST_P_SARADC>;
560 reset-names = "saradc-apb";
561 status = "disabled";
562 };
563
69e5a8fe
DW		 564 i2c1: i2c@ff110000 {
565 compatible = "rockchip,rk3399-i2c";
566 reg = <0x0 0xff110000 0x0 0x1000>;
567 assigned-clocks = <&cru SCLK_I2C1>;
568 assigned-clock-rates = <200000000>;
569 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
570 clock-names = "i2c", "pclk";
210bbd38 571 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c1_xfer>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 status = "disabled";
577 };
578
579 i2c2: i2c@ff120000 {
580 compatible = "rockchip,rk3399-i2c";
581 reg = <0x0 0xff120000 0x0 0x1000>;
582 assigned-clocks = <&cru SCLK_I2C2>;
583 assigned-clock-rates = <200000000>;
584 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
585 clock-names = "i2c", "pclk";
210bbd38 586 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 587 pinctrl-names = "default";
588 pinctrl-0 = <&i2c2_xfer>;
589 #address-cells = <1>;
590 #size-cells = <0>;
591 status = "disabled";
592 };
593
594 i2c3: i2c@ff130000 {
595 compatible = "rockchip,rk3399-i2c";
596 reg = <0x0 0xff130000 0x0 0x1000>;
597 assigned-clocks = <&cru SCLK_I2C3>;
598 assigned-clock-rates = <200000000>;
599 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
600 clock-names = "i2c", "pclk";
210bbd38 601 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 602 pinctrl-names = "default";
603 pinctrl-0 = <&i2c3_xfer>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 status = "disabled";
607 };
608
609 i2c5: i2c@ff140000 {
610 compatible = "rockchip,rk3399-i2c";
611 reg = <0x0 0xff140000 0x0 0x1000>;
612 assigned-clocks = <&cru SCLK_I2C5>;
613 assigned-clock-rates = <200000000>;
614 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
615 clock-names = "i2c", "pclk";
210bbd38 616 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 617 pinctrl-names = "default";
618 pinctrl-0 = <&i2c5_xfer>;
619 #address-cells = <1>;
620 #size-cells = <0>;
621 status = "disabled";
622 };
623
624 i2c6: i2c@ff150000 {
625 compatible = "rockchip,rk3399-i2c";
626 reg = <0x0 0xff150000 0x0 0x1000>;
627 assigned-clocks = <&cru SCLK_I2C6>;
628 assigned-clock-rates = <200000000>;
629 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
630 clock-names = "i2c", "pclk";
210bbd38 631 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c6_xfer>;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 status = "disabled";
637 };
638
639 i2c7: i2c@ff160000 {
640 compatible = "rockchip,rk3399-i2c";
641 reg = <0x0 0xff160000 0x0 0x1000>;
642 assigned-clocks = <&cru SCLK_I2C7>;
643 assigned-clock-rates = <200000000>;
644 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
645 clock-names = "i2c", "pclk";
210bbd38 646 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 647 pinctrl-names = "default";
648 pinctrl-0 = <&i2c7_xfer>;
649 #address-cells = <1>;
650 #size-cells = <0>;
651 status = "disabled";
652 };
653
f048b9a4
JX		 654 uart0: serial@ff180000 {
655 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
656 reg = <0x0 0xff180000 0x0 0x100>;
657 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
658 clock-names = "baudclk", "apb_pclk";
210bbd38 659 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 660 reg-shift = <2>;
661 reg-io-width = <4>;
662 pinctrl-names = "default";
663 pinctrl-0 = <&uart0_xfer>;
664 status = "disabled";
665 };
666
667 uart1: serial@ff190000 {
668 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
669 reg = <0x0 0xff190000 0x0 0x100>;
670 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
671 clock-names = "baudclk", "apb_pclk";
210bbd38 672 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 673 reg-shift = <2>;
674 reg-io-width = <4>;
675 pinctrl-names = "default";
676 pinctrl-0 = <&uart1_xfer>;
677 status = "disabled";
678 };
679
680 uart2: serial@ff1a0000 {
681 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
682 reg = <0x0 0xff1a0000 0x0 0x100>;
683 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
684 clock-names = "baudclk", "apb_pclk";
210bbd38 685 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 686 reg-shift = <2>;
687 reg-io-width = <4>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&uart2c_xfer>;
690 status = "disabled";
691 };
692
693 uart3: serial@ff1b0000 {
694 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
695 reg = <0x0 0xff1b0000 0x0 0x100>;
696 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
697 clock-names = "baudclk", "apb_pclk";
210bbd38 698 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 699 reg-shift = <2>;
700 reg-io-width = <4>;
701 pinctrl-names = "default";
702 pinctrl-0 = <&uart3_xfer>;
703 status = "disabled";
704 };
705
706 spi0: spi@ff1c0000 {
707 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
708 reg = <0x0 0xff1c0000 0x0 0x1000>;
709 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
710 clock-names = "spiclk", "apb_pclk";
210bbd38 711 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 712 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
713 dma-names = "tx", "rx";
f048b9a4
JX		 714 pinctrl-names = "default";
715 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
716 #address-cells = <1>;
717 #size-cells = <0>;
718 status = "disabled";
719 };
720
721 spi1: spi@ff1d0000 {
722 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
723 reg = <0x0 0xff1d0000 0x0 0x1000>;
724 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
725 clock-names = "spiclk", "apb_pclk";
210bbd38 726 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 727 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
728 dma-names = "tx", "rx";
f048b9a4
JX		 729 pinctrl-names = "default";
730 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 status = "disabled";
734 };
735
736 spi2: spi@ff1e0000 {
737 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
738 reg = <0x0 0xff1e0000 0x0 0x1000>;
739 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
740 clock-names = "spiclk", "apb_pclk";
210bbd38 741 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 742 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
743 dma-names = "tx", "rx";
f048b9a4
JX		 744 pinctrl-names = "default";
745 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
746 #address-cells = <1>;
747 #size-cells = <0>;
748 status = "disabled";
749 };
750
751 spi4: spi@ff1f0000 {
752 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
753 reg = <0x0 0xff1f0000 0x0 0x1000>;
754 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
755 clock-names = "spiclk", "apb_pclk";
210bbd38 756 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 757 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
758 dma-names = "tx", "rx";
f048b9a4
JX		 759 pinctrl-names = "default";
760 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
761 #address-cells = <1>;
762 #size-cells = <0>;
763 status = "disabled";
764 };
765
766 spi5: spi@ff200000 {
767 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
768 reg = <0x0 0xff200000 0x0 0x1000>;
769 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
770 clock-names = "spiclk", "apb_pclk";
210bbd38 771 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
b0fe0f47
ERB		 772 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
773 dma-names = "tx", "rx";
f048b9a4
JX		 774 pinctrl-names = "default";
775 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
b0f2110a 776 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 777 #address-cells = <1>;
778 #size-cells = <0>;
779 status = "disabled";
780 };
781
647cea2e 782 thermal_zones: thermal-zones {
e58061b5 783 cpu_thermal: cpu-thermal {
95c27ba7
CW		 784 polling-delay-passive = <100>;
785 polling-delay = <1000>;
786
787 thermal-sensors = <&tsadc 0>;
788
789 trips {
790 cpu_alert0: cpu_alert0 {
791 temperature = <70000>;
792 hysteresis = <2000>;
793 type = "passive";
794 };
795 cpu_alert1: cpu_alert1 {
796 temperature = <75000>;
797 hysteresis = <2000>;
798 type = "passive";
799 };
800 cpu_crit: cpu_crit {
801 temperature = <95000>;
802 hysteresis = <2000>;
803 type = "critical";
804 };
805 };
806
807 cooling-maps {
808 map0 {
809 trip = <&cpu_alert0>;
810 cooling-device =
cdd46460
VK		 811 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
812 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
95c27ba7
CW		 813 };
814 map1 {
815 trip = <&cpu_alert1>;
816 cooling-device =
817 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cdd46460
VK		 818 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
819 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
820 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
821 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
822 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
95c27ba7
CW		 823 };
824 };
825 };
826
e58061b5 827 gpu_thermal: gpu-thermal {
95c27ba7
CW		 828 polling-delay-passive = <100>;
829 polling-delay = <1000>;
830
831 thermal-sensors = <&tsadc 1>;
832
833 trips {
834 gpu_alert0: gpu_alert0 {
835 temperature = <75000>;
836 hysteresis = <2000>;
837 type = "passive";
838 };
839 gpu_crit: gpu_crit {
840 temperature = <95000>;
841 hysteresis = <2000>;
842 type = "critical";
843 };
844 };
36be9111
RM		 845
846 cooling-maps {
847 map0 {
848 trip = <&gpu_alert0>;
849 cooling-device =
850 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
851 };
852 };
95c27ba7
CW		 853 };
854 };
855
856 tsadc: tsadc@ff260000 {
857 compatible = "rockchip,rk3399-tsadc";
858 reg = <0x0 0xff260000 0x0 0x100>;
210bbd38 859 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
95c27ba7
CW		 860 assigned-clocks = <&cru SCLK_TSADC>;
861 assigned-clock-rates = <750000>;
862 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
863 clock-names = "tsadc", "apb_pclk";
864 resets = <&cru SRST_TSADC>;
865 reset-names = "tsadc-apb";
866 rockchip,grf = <&grf>;
867 rockchip,hw-tshut-temp = <95000>;
868 pinctrl-names = "init", "default", "sleep";
2bc65fef 869 pinctrl-0 = <&otp_pin>;
95c27ba7 870 pinctrl-1 = <&otp_out>;
2bc65fef 871 pinctrl-2 = <&otp_pin>;
95c27ba7
CW		 872 #thermal-sensor-cells = <1>;
873 status = "disabled";
874 };
875
a1907df2 876 qos_emmc: qos@ffa58000 {
bd3fd049 877 compatible = "rockchip,rk3399-qos", "syscon";
a1907df2
EZ		 878 reg = <0x0 0xffa58000 0x0 0x20>;
879 };
880
d43c97a5 881 qos_gmac: qos@ffa5c000 {
bd3fd049 882 compatible = "rockchip,rk3399-qos", "syscon";
d43c97a5
CW		 883 reg = <0x0 0xffa5c000 0x0 0x20>;
884 };
885
65f1e902 886 qos_pcie: qos@ffa60080 {
bd3fd049 887 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 888 reg = <0x0 0xffa60080 0x0 0x20>;
889 };
890
891 qos_usb_host0: qos@ffa60100 {
bd3fd049 892 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 893 reg = <0x0 0xffa60100 0x0 0x20>;
894 };
895
896 qos_usb_host1: qos@ffa60180 {
bd3fd049 897 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 898 reg = <0x0 0xffa60180 0x0 0x20>;
899 };
900
901 qos_usb_otg0: qos@ffa70000 {
bd3fd049 902 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 903 reg = <0x0 0xffa70000 0x0 0x20>;
904 };
905
906 qos_usb_otg1: qos@ffa70080 {
bd3fd049 907 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 908 reg = <0x0 0xffa70080 0x0 0x20>;
909 };
910
911 qos_sd: qos@ffa74000 {
bd3fd049 912 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 913 reg = <0x0 0xffa74000 0x0 0x20>;
914 };
915
916 qos_sdioaudio: qos@ffa76000 {
bd3fd049 917 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 918 reg = <0x0 0xffa76000 0x0 0x20>;
919 };
920
807a2371 921 qos_hdcp: qos@ffa90000 {
bd3fd049 922 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 923 reg = <0x0 0xffa90000 0x0 0x20>;
924 };
925
926 qos_iep: qos@ffa98000 {
bd3fd049 927 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 928 reg = <0x0 0xffa98000 0x0 0x20>;
929 };
930
931 qos_isp0_m0: qos@ffaa0000 {
bd3fd049 932 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 933 reg = <0x0 0xffaa0000 0x0 0x20>;
934 };
935
936 qos_isp0_m1: qos@ffaa0080 {
bd3fd049 937 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 938 reg = <0x0 0xffaa0080 0x0 0x20>;
939 };
940
941 qos_isp1_m0: qos@ffaa8000 {
bd3fd049 942 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 943 reg = <0x0 0xffaa8000 0x0 0x20>;
944 };
945
946 qos_isp1_m1: qos@ffaa8080 {
bd3fd049 947 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 948 reg = <0x0 0xffaa8080 0x0 0x20>;
949 };
950
951 qos_rga_r: qos@ffab0000 {
bd3fd049 952 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 953 reg = <0x0 0xffab0000 0x0 0x20>;
954 };
955
956 qos_rga_w: qos@ffab0080 {
bd3fd049 957 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 958 reg = <0x0 0xffab0080 0x0 0x20>;
959 };
960
961 qos_video_m0: qos@ffab8000 {
bd3fd049 962 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 963 reg = <0x0 0xffab8000 0x0 0x20>;
964 };
965
966 qos_video_m1_r: qos@ffac0000 {
bd3fd049 967 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 968 reg = <0x0 0xffac0000 0x0 0x20>;
969 };
970
971 qos_video_m1_w: qos@ffac0080 {
bd3fd049 972 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 973 reg = <0x0 0xffac0080 0x0 0x20>;
974 };
975
976 qos_vop_big_r: qos@ffac8000 {
bd3fd049 977 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 978 reg = <0x0 0xffac8000 0x0 0x20>;
979 };
980
981 qos_vop_big_w: qos@ffac8080 {
bd3fd049 982 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 983 reg = <0x0 0xffac8080 0x0 0x20>;
984 };
985
986 qos_vop_little: qos@ffad0000 {
bd3fd049 987 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 988 reg = <0x0 0xffad0000 0x0 0x20>;
989 };
990
65f1e902 991 qos_perihp: qos@ffad8080 {
bd3fd049 992 compatible = "rockchip,rk3399-qos", "syscon";
65f1e902
KY		 993 reg = <0x0 0xffad8080 0x0 0x20>;
994 };
995
807a2371 996 qos_gpu: qos@ffae0000 {
bd3fd049 997 compatible = "rockchip,rk3399-qos", "syscon";
807a2371
EZ		 998 reg = <0x0 0xffae0000 0x0 0x20>;
999 };
1000
1001 pmu: power-management@ff310000 {
1002 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1003 reg = <0x0 0xff310000 0x0 0x1000>;
1004
1005 /*
1006 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
1007 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
1008 * Some of the power domains are grouped together for every
1009 * voltage domain.
1010 * The detail contents as below.
1011 */
1012 power: power-controller {
1013 compatible = "rockchip,rk3399-power-controller";
1014 #power-domain-cells = <1>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017
1018 /* These power domains are grouped by VD_CENTER */
148bbe29 1019 power-domain@RK3399_PD_IEP {
807a2371
EZ		 1020 reg = <RK3399_PD_IEP>;
1021 clocks = <&cru ACLK_IEP>,
1022 <&cru HCLK_IEP>;
1023 pm_qos = <&qos_iep>;
837188d4 1024 #power-domain-cells = <0>;
807a2371 1025 };
148bbe29 1026 power-domain@RK3399_PD_RGA {
807a2371
EZ		 1027 reg = <RK3399_PD_RGA>;
1028 clocks = <&cru ACLK_RGA>,
1029 <&cru HCLK_RGA>;
1030 pm_qos = <&qos_rga_r>,
1031 <&qos_rga_w>;
837188d4 1032 #power-domain-cells = <0>;
807a2371 1033 };
148bbe29 1034 power-domain@RK3399_PD_VCODEC {
807a2371
EZ		 1035 reg = <RK3399_PD_VCODEC>;
1036 clocks = <&cru ACLK_VCODEC>,
1037 <&cru HCLK_VCODEC>;
1038 pm_qos = <&qos_video_m0>;
837188d4 1039 #power-domain-cells = <0>;
807a2371 1040 };
148bbe29 1041 power-domain@RK3399_PD_VDU {
807a2371
EZ		 1042 reg = <RK3399_PD_VDU>;
1043 clocks = <&cru ACLK_VDU>,
1044 <&cru HCLK_VDU>;
1045 pm_qos = <&qos_video_m1_r>,
1046 <&qos_video_m1_w>;
837188d4 1047 #power-domain-cells = <0>;
807a2371
EZ		 1048 };
1049
1050 /* These power domains are grouped by VD_GPU */
148bbe29 1051 power-domain@RK3399_PD_GPU {
807a2371
EZ		 1052 reg = <RK3399_PD_GPU>;
1053 clocks = <&cru ACLK_GPU>;
1054 pm_qos = <&qos_gpu>;
837188d4 1055 #power-domain-cells = <0>;
807a2371
EZ		 1056 };
1057
1058 /* These power domains are grouped by VD_LOGIC */
148bbe29 1059 power-domain@RK3399_PD_EDP {
3cf04a4e
EZ		 1060 reg = <RK3399_PD_EDP>;
1061 clocks = <&cru PCLK_EDP_CTRL>;
837188d4 1062 #power-domain-cells = <0>;
3cf04a4e 1063 };
148bbe29 1064 power-domain@RK3399_PD_EMMC {
a1907df2
EZ		 1065 reg = <RK3399_PD_EMMC>;
1066 clocks = <&cru ACLK_EMMC>;
1067 pm_qos = <&qos_emmc>;
837188d4 1068 #power-domain-cells = <0>;
a1907df2 1069 };
148bbe29 1070 power-domain@RK3399_PD_GMAC {
d43c97a5 1071 reg = <RK3399_PD_GMAC>;
2afc1db0
JC		 1072 clocks = <&cru ACLK_GMAC>,
1073 <&cru PCLK_GMAC>;
d43c97a5 1074 pm_qos = <&qos_gmac>;
837188d4 1075 #power-domain-cells = <0>;
d43c97a5 1076 };
148bbe29 1077 power-domain@RK3399_PD_SD {
1bc60bee
EZ		 1078 reg = <RK3399_PD_SD>;
1079 clocks = <&cru HCLK_SDMMC>,
1080 <&cru SCLK_SDMMC>;
1081 pm_qos = <&qos_sd>;
837188d4 1082 #power-domain-cells = <0>;
1bc60bee 1083 };
148bbe29 1084 power-domain@RK3399_PD_SDIOAUDIO {
b0f2110a
CW		 1085 reg = <RK3399_PD_SDIOAUDIO>;
1086 clocks = <&cru HCLK_SDIO>;
1087 pm_qos = <&qos_sdioaudio>;
837188d4 1088 #power-domain-cells = <0>;
b0f2110a 1089 };
148bbe29 1090 power-domain@RK3399_PD_TCPD0 {
2b99e619
JJ		 1091 reg = <RK3399_PD_TCPD0>;
1092 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1093 <&cru SCLK_UPHY0_TCPDPHY_REF>;
837188d4 1094 #power-domain-cells = <0>;
2b99e619 1095 };
148bbe29 1096 power-domain@RK3399_PD_TCPD1 {
2b99e619
JJ		 1097 reg = <RK3399_PD_TCPD1>;
1098 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1099 <&cru SCLK_UPHY1_TCPDPHY_REF>;
837188d4 1100 #power-domain-cells = <0>;
2b99e619 1101 };
148bbe29 1102 power-domain@RK3399_PD_USB3 {
a1bbaaa4
EBS		 1103 reg = <RK3399_PD_USB3>;
1104 clocks = <&cru ACLK_USB3>;
1105 pm_qos = <&qos_usb_otg0>,
1106 <&qos_usb_otg1>;
837188d4 1107 #power-domain-cells = <0>;
a1bbaaa4 1108 };
148bbe29 1109 power-domain@RK3399_PD_VIO {
807a2371 1110 reg = <RK3399_PD_VIO>;
837188d4 1111 #power-domain-cells = <1>;
807a2371
EZ		 1112 #address-cells = <1>;
1113 #size-cells = <0>;
1114
148bbe29 1115 power-domain@RK3399_PD_HDCP {
807a2371
EZ		 1116 reg = <RK3399_PD_HDCP>;
1117 clocks = <&cru ACLK_HDCP>,
1118 <&cru HCLK_HDCP>,
1119 <&cru PCLK_HDCP>;
1120 pm_qos = <&qos_hdcp>;
837188d4 1121 #power-domain-cells = <0>;
807a2371 1122 };
148bbe29 1123 power-domain@RK3399_PD_ISP0 {
807a2371
EZ		 1124 reg = <RK3399_PD_ISP0>;
1125 clocks = <&cru ACLK_ISP0>,
1126 <&cru HCLK_ISP0>;
1127 pm_qos = <&qos_isp0_m0>,
1128 <&qos_isp0_m1>;
837188d4 1129 #power-domain-cells = <0>;
807a2371 1130 };
148bbe29 1131 power-domain@RK3399_PD_ISP1 {
807a2371
EZ		 1132 reg = <RK3399_PD_ISP1>;
1133 clocks = <&cru ACLK_ISP1>,
1134 <&cru HCLK_ISP1>;
1135 pm_qos = <&qos_isp1_m0>,
1136 <&qos_isp1_m1>;
837188d4 1137 #power-domain-cells = <0>;
807a2371 1138 };
148bbe29 1139 power-domain@RK3399_PD_VO {
807a2371 1140 reg = <RK3399_PD_VO>;
837188d4 1141 #power-domain-cells = <1>;
807a2371
EZ		 1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144
148bbe29 1145 power-domain@RK3399_PD_VOPB {
807a2371
EZ		 1146 reg = <RK3399_PD_VOPB>;
1147 clocks = <&cru ACLK_VOP0>,
1148 <&cru HCLK_VOP0>;
1149 pm_qos = <&qos_vop_big_r>,
1150 <&qos_vop_big_w>;
837188d4 1151 #power-domain-cells = <0>;
807a2371 1152 };
148bbe29 1153 power-domain@RK3399_PD_VOPL {
807a2371
EZ		 1154 reg = <RK3399_PD_VOPL>;
1155 clocks = <&cru ACLK_VOP1>,
1156 <&cru HCLK_VOP1>;
1157 pm_qos = <&qos_vop_little>;
837188d4 1158 #power-domain-cells = <0>;
807a2371
EZ		 1159 };
1160 };
1161 };
1162 };
1163 };
1164
f048b9a4 1165 pmugrf: syscon@ff320000 {
16759262 1166 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
f048b9a4 1167 reg = <0x0 0xff320000 0x0 0x1000>;
6d0e3a45
HS		 1168
1169 pmu_io_domains: io-domains {
1170 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1171 status = "disabled";
1172 };
f048b9a4
JX		 1173 };
1174
1175 spi3: spi@ff350000 {
1176 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1177 reg = <0x0 0xff350000 0x0 0x1000>;
1178 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1179 clock-names = "spiclk", "apb_pclk";
210bbd38 1180 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1181 pinctrl-names = "default";
1182 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 status = "disabled";
1186 };
1187
1188 uart4: serial@ff370000 {
1189 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1190 reg = <0x0 0xff370000 0x0 0x100>;
1191 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1192 clock-names = "baudclk", "apb_pclk";
210bbd38 1193 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1194 reg-shift = <2>;
1195 reg-io-width = <4>;
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&uart4_xfer>;
1198 status = "disabled";
1199 };
1200
69e5a8fe
DW		 1201 i2c0: i2c@ff3c0000 {
1202 compatible = "rockchip,rk3399-i2c";
1203 reg = <0x0 0xff3c0000 0x0 0x1000>;
1204 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1205 assigned-clock-rates = <200000000>;
1206 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1207 clock-names = "i2c", "pclk";
210bbd38 1208 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1209 pinctrl-names = "default";
1210 pinctrl-0 = <&i2c0_xfer>;
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213 status = "disabled";
1214 };
1215
1216 i2c4: i2c@ff3d0000 {
1217 compatible = "rockchip,rk3399-i2c";
1218 reg = <0x0 0xff3d0000 0x0 0x1000>;
1219 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1220 assigned-clock-rates = <200000000>;
1221 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1222 clock-names = "i2c", "pclk";
210bbd38 1223 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1224 pinctrl-names = "default";
1225 pinctrl-0 = <&i2c4_xfer>;
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1228 status = "disabled";
1229 };
1230
1231 i2c8: i2c@ff3e0000 {
1232 compatible = "rockchip,rk3399-i2c";
1233 reg = <0x0 0xff3e0000 0x0 0x1000>;
1234 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1235 assigned-clock-rates = <200000000>;
1236 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1237 clock-names = "i2c", "pclk";
210bbd38 1238 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1239 pinctrl-names = "default";
1240 pinctrl-0 = <&i2c8_xfer>;
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1243 status = "disabled";
f048b9a4
JX		 1244 };
1245
1246 pwm0: pwm@ff420000 {
1247 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1248 reg = <0x0 0xff420000 0x0 0x10>;
1249 #pwm-cells = <3>;
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&pwm0_pin>;
1252 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1253 status = "disabled";
1254 };
1255
1256 pwm1: pwm@ff420010 {
1257 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1258 reg = <0x0 0xff420010 0x0 0x10>;
1259 #pwm-cells = <3>;
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&pwm1_pin>;
1262 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1263 status = "disabled";
1264 };
1265
1266 pwm2: pwm@ff420020 {
1267 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1268 reg = <0x0 0xff420020 0x0 0x10>;
1269 #pwm-cells = <3>;
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&pwm2_pin>;
1272 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1273 status = "disabled";
1274 };
1275
1276 pwm3: pwm@ff420030 {
1277 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1278 reg = <0x0 0xff420030 0x0 0x10>;
1279 #pwm-cells = <3>;
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&pwm3a_pin>;
1282 clocks = <&pmucru PCLK_RKPWM_PMU>;
f048b9a4
JX		 1283 status = "disabled";
1284 };
1285
5cd4c31a
EG		 1286 vpu: video-codec@ff650000 {
1287 compatible = "rockchip,rk3399-vpu";
1288 reg = <0x0 0xff650000 0x0 0x800>;
1289 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1290 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
87543bb6 1291 interrupt-names = "vepu", "vdpu";
5cd4c31a
EG		 1292 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1293 clock-names = "aclk", "hclk";
1294 iommus = <&vpu_mmu>;
1295 power-domains = <&power RK3399_PD_VCODEC>;
1296 };
1297
ae4fdcca
SX		 1298 vpu_mmu: iommu@ff650800 {
1299 compatible = "rockchip,iommu";
1300 reg = <0x0 0xff650800 0x0 0x40>;
1301 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
df3bcde7
JC		 1302 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1303 clock-names = "aclk", "iface";
ae4fdcca 1304 #iommu-cells = <0>;
5cd4c31a 1305 power-domains = <&power RK3399_PD_VCODEC>;
ae4fdcca
SX		 1306 };
1307
cbd72144
BB		 1308 vdec: video-codec@ff660000 {
1309 compatible = "rockchip,rk3399-vdec";
1310 reg = <0x0 0xff660000 0x0 0x400>;
1311 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
cbd72144
BB		 1312 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1313 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1314 clock-names = "axi", "ahb", "cabac", "core";
1315 iommus = <&vdec_mmu>;
1316 power-domains = <&power RK3399_PD_VDU>;
1317 };
1318
ae4fdcca
SX		 1319 vdec_mmu: iommu@ff660480 {
1320 compatible = "rockchip,iommu";
1321 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1322 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
df3bcde7
JC		 1323 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1324 clock-names = "aclk", "iface";
cbd72144 1325 power-domains = <&power RK3399_PD_VDU>;
ae4fdcca 1326 #iommu-cells = <0>;
ae4fdcca
SX		 1327 };
1328
1329 iep_mmu: iommu@ff670800 {
1330 compatible = "rockchip,iommu";
1331 reg = <0x0 0xff670800 0x0 0x40>;
1332 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
df3bcde7
JC		 1333 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1334 clock-names = "aclk", "iface";
ae4fdcca
SX		 1335 #iommu-cells = <0>;
1336 status = "disabled";
1337 };
1338
ec5ccfd7
JC		 1339 rga: rga@ff680000 {
1340 compatible = "rockchip,rk3399-rga";
1341 reg = <0x0 0xff680000 0x0 0x10000>;
1342 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1343 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1344 clock-names = "aclk", "hclk", "sclk";
1345 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1346 reset-names = "core", "axi", "ahb";
1347 power-domains = <&power RK3399_PD_RGA>;
1348 };
1349
b7ee3b27
FX		 1350 efuse0: efuse@ff690000 {
1351 compatible = "rockchip,rk3399-efuse";
1352 reg = <0x0 0xff690000 0x0 0x80>;
1353 #address-cells = <1>;
1354 #size-cells = <1>;
1355 clocks = <&cru PCLK_EFUSE1024NS>;
1356 clock-names = "pclk_efuse";
1357
1358 /* Data cells */
0d326927
ZX		 1359 cpu_id: cpu-id@7 {
1360 reg = <0x07 0x10>;
1361 };
b7ee3b27
FX		 1362 cpub_leakage: cpu-leakage@17 {
1363 reg = <0x17 0x1>;
1364 };
1365 gpu_leakage: gpu-leakage@18 {
1366 reg = <0x18 0x1>;
1367 };
1368 center_leakage: center-leakage@19 {
1369 reg = <0x19 0x1>;
1370 };
1371 cpul_leakage: cpu-leakage@1a {
1372 reg = <0x1a 0x1>;
1373 };
1374 logic_leakage: logic-leakage@1b {
1375 reg = <0x1b 0x1>;
1376 };
1377 wafer_info: wafer-info@1c {
1378 reg = <0x1c 0x1>;
1379 };
1380 };
1381
9e824449
RM		 1382 dmac_bus: dma-controller@ff6d0000 {
1383 compatible = "arm,pl330", "arm,primecell";
1384 reg = <0x0 0xff6d0000 0x0 0x4000>;
1385 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1386 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1387 #dma-cells = <1>;
1388 arm,pl330-periph-burst;
1389 clocks = <&cru ACLK_DMAC0_PERILP>;
1390 clock-names = "apb_pclk";
1391 };
1392
1393 dmac_peri: dma-controller@ff6e0000 {
1394 compatible = "arm,pl330", "arm,primecell";
1395 reg = <0x0 0xff6e0000 0x0 0x4000>;
1396 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1397 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1398 #dma-cells = <1>;
1399 arm,pl330-periph-burst;
1400 clocks = <&cru ACLK_DMAC1_PERILP>;
1401 clock-names = "apb_pclk";
1402 };
1403
f048b9a4
JX		 1404 pmucru: pmu-clock-controller@ff750000 {
1405 compatible = "rockchip,rk3399-pmucru";
1406 reg = <0x0 0xff750000 0x0 0x1000>;
8cbb59af 1407 rockchip,grf = <&pmugrf>;
f048b9a4
JX		 1408 #clock-cells = <1>;
1409 #reset-cells = <1>;
1410 assigned-clocks = <&pmucru PLL_PPLL>;
1411 assigned-clock-rates = <676000000>;
1412 };
1413
1414 cru: clock-controller@ff760000 {
1415 compatible = "rockchip,rk3399-cru";
1416 reg = <0x0 0xff760000 0x0 0x1000>;
8cbb59af 1417 rockchip,grf = <&grf>;
f048b9a4
JX		 1418 #clock-cells = <1>;
1419 #reset-cells = <1>;
a09906cd
XZ		 1420 assigned-clocks =
1421 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1422 <&cru PLL_NPLL>,
1423 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1424 <&cru PCLK_PERIHP>,
1425 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
bb4b6201 1426 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
3f7f3b0f 1427 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
e702e13f
LH		 1428 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1429 <&cru ACLK_GIC_PRE>,
1430 <&cru PCLK_DDR>;
a09906cd
XZ		 1431 assigned-clock-rates =
1432 <594000000>, <800000000>,
1433 <1000000000>,
1434 <150000000>, <75000000>,
1435 <37500000>,
1436 <100000000>, <100000000>,
bb4b6201 1437 <50000000>, <600000000>,
3f7f3b0f 1438 <100000000>, <50000000>,
e702e13f
LH		 1439 <400000000>, <400000000>,
1440 <200000000>,
1441 <200000000>;
f048b9a4
JX		 1442 };
1443
1444 grf: syscon@ff770000 {
16759262 1445 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
f048b9a4 1446 reg = <0x0 0xff770000 0x0 0x10000>;
16759262
BN		 1447 #address-cells = <1>;
1448 #size-cells = <1>;
b4e87c09 1449
6d0e3a45
HS		 1450 io_domains: io-domains {
1451 compatible = "rockchip,rk3399-io-voltage-domain";
1452 status = "disabled";
1453 };
1454
e4bfde13
SZ		 1455 mipi_dphy_rx0: mipi-dphy-rx0 {
1456 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1457 clocks = <&cru SCLK_MIPIDPHY_REF>,
1458 <&cru SCLK_DPHY_RX0_CFG>,
1459 <&cru PCLK_VIO_GRF>;
1460 clock-names = "dphy-ref", "dphy-cfg", "grf";
1461 power-domains = <&power RK3399_PD_VIO>;
1462 #phy-cells = <0>;
1463 status = "disabled";
1464 };
1465
8c3d6425 1466 u2phy0: usb2phy@e450 {
103e9f85
FW		 1467 compatible = "rockchip,rk3399-usb2phy";
1468 reg = <0xe450 0x10>;
1469 clocks = <&cru SCLK_USB2PHY0_REF>;
1470 clock-names = "phyclk";
1471 #clock-cells = <0>;
1472 clock-output-names = "clk_usbphy0_480m";
1473 status = "disabled";
1474
1475 u2phy0_host: host-port {
1476 #phy-cells = <0>;
210bbd38 1477 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1478 interrupt-names = "linestate";
1479 status = "disabled";
1480 };
fe7f2de1
WW		 1481
1482 u2phy0_otg: otg-port {
1483 #phy-cells = <0>;
1484 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1485 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1486 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1487 interrupt-names = "otg-bvalid", "otg-id",
1488 "linestate";
1489 status = "disabled";
1490 };
103e9f85
FW		 1491 };
1492
8c3d6425 1493 u2phy1: usb2phy@e460 {
103e9f85
FW		 1494 compatible = "rockchip,rk3399-usb2phy";
1495 reg = <0xe460 0x10>;
1496 clocks = <&cru SCLK_USB2PHY1_REF>;
1497 clock-names = "phyclk";
1498 #clock-cells = <0>;
1499 clock-output-names = "clk_usbphy1_480m";
1500 status = "disabled";
1501
1502 u2phy1_host: host-port {
1503 #phy-cells = <0>;
210bbd38 1504 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1505 interrupt-names = "linestate";
1506 status = "disabled";
1507 };
fe7f2de1
WW		 1508
1509 u2phy1_otg: otg-port {
1510 #phy-cells = <0>;
1511 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1512 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1513 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1514 interrupt-names = "otg-bvalid", "otg-id",
1515 "linestate";
1516 status = "disabled";
1517 };
103e9f85
FW		 1518 };
1519
b4e87c09
BN		 1520 emmc_phy: phy@f780 {
1521 compatible = "rockchip,rk3399-emmc-phy";
1522 reg = <0xf780 0x24>;
ed388cdd
DA		 1523 clocks = <&sdhci>;
1524 clock-names = "emmcclk";
b4e87c09
BN		 1525 #phy-cells = <0>;
1526 status = "disabled";
1527 };
29a0be1c
SL		 1528
1529 pcie_phy: pcie-phy {
1530 compatible = "rockchip,rk3399-pcie-phy";
1531 clocks = <&cru SCLK_PCIEPHY_REF>;
1532 clock-names = "refclk";
e9a60cac 1533 #phy-cells = <1>;
29a0be1c 1534 resets = <&cru SRST_PCIEPHY>;
fb8b7460 1535 drive-impedance-ohm = <50>;
29a0be1c
SL		 1536 reset-names = "phy";
1537 status = "disabled";
1538 };
f048b9a4
JX		 1539 };
1540
f606193a
CZ		 1541 tcphy0: phy@ff7c0000 {
1542 compatible = "rockchip,rk3399-typec-phy";
1543 reg = <0x0 0xff7c0000 0x0 0x40000>;
1544 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1545 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1546 clock-names = "tcpdcore", "tcpdphy-ref";
1547 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1548 assigned-clock-rates = <50000000>;
06ad4b2f 1549 power-domains = <&power RK3399_PD_TCPD0>;
f606193a
CZ		 1550 resets = <&cru SRST_UPHY0>,
1551 <&cru SRST_UPHY0_PIPE_L00>,
1552 <&cru SRST_P_UPHY0_TCPHY>;
1553 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1554 rockchip,grf = <&grf>;
f606193a
CZ		 1555 status = "disabled";
1556
1557 tcphy0_dp: dp-port {
1558 #phy-cells = <0>;
1559 };
1560
1561 tcphy0_usb3: usb3-port {
1562 #phy-cells = <0>;
1563 };
1564 };
1565
1566 tcphy1: phy@ff800000 {
1567 compatible = "rockchip,rk3399-typec-phy";
1568 reg = <0x0 0xff800000 0x0 0x40000>;
1569 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1570 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1571 clock-names = "tcpdcore", "tcpdphy-ref";
1572 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1573 assigned-clock-rates = <50000000>;
06ad4b2f 1574 power-domains = <&power RK3399_PD_TCPD1>;
f606193a
CZ		 1575 resets = <&cru SRST_UPHY1>,
1576 <&cru SRST_UPHY1_PIPE_L00>,
1577 <&cru SRST_P_UPHY1_TCPHY>;
1578 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1579 rockchip,grf = <&grf>;
f606193a
CZ		 1580 status = "disabled";
1581
1582 tcphy1_dp: dp-port {
1583 #phy-cells = <0>;
1584 };
1585
1586 tcphy1_usb3: usb3-port {
1587 #phy-cells = <0>;
1588 };
1589 };
1590
0895b3a8 1591 watchdog@ff848000 {
6b5c5086 1592 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
0895b3a8 1593 reg = <0x0 0xff848000 0x0 0x100>;
f048b9a4 1594 clocks = <&cru PCLK_WDT>;
210bbd38 1595 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1596 };
1597
1e8567d5
HT		 1598 rktimer: rktimer@ff850000 {
1599 compatible = "rockchip,rk3399-timer";
1600 reg = <0x0 0xff850000 0x0 0x1000>;
210bbd38 1601 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1e8567d5
HT		 1602 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1603 clock-names = "pclk", "timer";
1604 };
1605
f048b9a4
JX		 1606 spdif: spdif@ff870000 {
1607 compatible = "rockchip,rk3399-spdif";
1608 reg = <0x0 0xff870000 0x0 0x1000>;
210bbd38 1609 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1610 dmas = <&dmac_bus 7>;
1611 dma-names = "tx";
1612 clock-names = "mclk", "hclk";
1613 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1614 pinctrl-names = "default";
1615 pinctrl-0 = <&spdif_bus>;
b0f2110a 1616 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1617 #sound-dai-cells = <0>;
f048b9a4
JX		 1618 status = "disabled";
1619 };
1620
1621 i2s0: i2s@ff880000 {
1622 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1623 reg = <0x0 0xff880000 0x0 0x1000>;
1624 rockchip,grf = <&grf>;
210bbd38 1625 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1626 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1627 dma-names = "tx", "rx";
1628 clock-names = "i2s_clk", "i2s_hclk";
1629 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1630 pinctrl-names = "default";
1631 pinctrl-0 = <&i2s0_8ch_bus>;
b0f2110a 1632 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1633 #sound-dai-cells = <0>;
f048b9a4
JX		 1634 status = "disabled";
1635 };
1636
1637 i2s1: i2s@ff890000 {
1638 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1639 reg = <0x0 0xff890000 0x0 0x1000>;
210bbd38 1640 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1641 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1642 dma-names = "tx", "rx";
1643 clock-names = "i2s_clk", "i2s_hclk";
1644 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1645 pinctrl-names = "default";
1646 pinctrl-0 = <&i2s1_2ch_bus>;
b0f2110a 1647 power-domains = <&power RK3399_PD_SDIOAUDIO>;
4486baca 1648 #sound-dai-cells = <0>;
f048b9a4
JX		 1649 status = "disabled";
1650 };
1651
1652 i2s2: i2s@ff8a0000 {
1653 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1654 reg = <0x0 0xff8a0000 0x0 0x1000>;
210bbd38 1655 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1656 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1657 dma-names = "tx", "rx";
1658 clock-names = "i2s_clk", "i2s_hclk";
1659 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
b0f2110a 1660 power-domains = <&power RK3399_PD_SDIOAUDIO>;
0d60d48c 1661 #sound-dai-cells = <0>;
f048b9a4
JX		 1662 status = "disabled";
1663 };
1664
fbd4cc0e
MY		 1665 vopl: vop@ff8f0000 {
1666 compatible = "rockchip,rk3399-vop-lit";
1667 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1668 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1669 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1670 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1671 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1672 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1673 iommus = <&vopl_mmu>;
1674 power-domains = <&power RK3399_PD_VOPL>;
1675 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1676 reset-names = "axi", "ahb", "dclk";
1677 status = "disabled";
1678
1679 vopl_out: port {
1680 #address-cells = <1>;
1681 #size-cells = <0>;
f7a29e30 1682
d3f51f49
JC		 1683 vopl_out_mipi: endpoint@0 {
1684 reg = <0>;
1685 remote-endpoint = <&mipi_in_vopl>;
1686 };
1687
f7a29e30
YY		 1688 vopl_out_edp: endpoint@1 {
1689 reg = <1>;
1690 remote-endpoint = <&edp_in_vopl>;
1691 };
1692
81e923dd
JC		 1693 vopl_out_hdmi: endpoint@2 {
1694 reg = <2>;
1695 remote-endpoint = <&hdmi_in_vopl>;
1696 };
1df5d2ab
NY		 1697
1698 vopl_out_mipi1: endpoint@3 {
1699 reg = <3>;
1700 remote-endpoint = <&mipi1_in_vopl>;
1701 };
2d3c2d56
CZ		 1702
1703 vopl_out_dp: endpoint@4 {
1704 reg = <4>;
1705 remote-endpoint = <&dp_in_vopl>;
1706 };
fbd4cc0e
MY		 1707 };
1708 };
1709
1710 vopl_mmu: iommu@ff8f3f00 {
1711 compatible = "rockchip,iommu";
1712 reg = <0x0 0xff8f3f00 0x0 0x100>;
1713 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
fbd4cc0e 1714 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
df3bcde7 1715 clock-names = "aclk", "iface";
fbd4cc0e
MY		 1716 power-domains = <&power RK3399_PD_VOPL>;
1717 #iommu-cells = <0>;
1718 status = "disabled";
1719 };
1720
1721 vopb: vop@ff900000 {
1722 compatible = "rockchip,rk3399-vop-big";
1723 reg = <0x0 0xff900000 0x0 0x3efc>;
1724 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1725 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1726 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1727 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1728 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1729 iommus = <&vopb_mmu>;
1730 power-domains = <&power RK3399_PD_VOPB>;
1731 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1732 reset-names = "axi", "ahb", "dclk";
1733 status = "disabled";
1734
1735 vopb_out: port {
1736 #address-cells = <1>;
1737 #size-cells = <0>;
f7a29e30
YY		 1738
1739 vopb_out_edp: endpoint@0 {
1740 reg = <0>;
1741 remote-endpoint = <&edp_in_vopb>;
1742 };
1743
d3f51f49
JC		 1744 vopb_out_mipi: endpoint@1 {
1745 reg = <1>;
1746 remote-endpoint = <&mipi_in_vopb>;
1747 };
1748
81e923dd
JC		 1749 vopb_out_hdmi: endpoint@2 {
1750 reg = <2>;
1751 remote-endpoint = <&hdmi_in_vopb>;
1752 };
1df5d2ab
NY		 1753
1754 vopb_out_mipi1: endpoint@3 {
1755 reg = <3>;
1756 remote-endpoint = <&mipi1_in_vopb>;
1757 };
2d3c2d56
CZ		 1758
1759 vopb_out_dp: endpoint@4 {
1760 reg = <4>;
1761 remote-endpoint = <&dp_in_vopb>;
1762 };
fbd4cc0e
MY		 1763 };
1764 };
1765
1766 vopb_mmu: iommu@ff903f00 {
1767 compatible = "rockchip,iommu";
1768 reg = <0x0 0xff903f00 0x0 0x100>;
1769 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
fbd4cc0e 1770 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
df3bcde7 1771 clock-names = "aclk", "iface";
fbd4cc0e
MY		 1772 power-domains = <&power RK3399_PD_VOPB>;
1773 #iommu-cells = <0>;
1774 status = "disabled";
1775 };
1776
97a0115c
SZ		 1777 isp0: isp0@ff910000 {
1778 compatible = "rockchip,rk3399-cif-isp";
1779 reg = <0x0 0xff910000 0x0 0x4000>;
1780 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1781 clocks = <&cru SCLK_ISP0>,
1782 <&cru ACLK_ISP0_WRAPPER>,
1783 <&cru HCLK_ISP0_WRAPPER>;
1784 clock-names = "isp", "aclk", "hclk";
1785 iommus = <&isp0_mmu>;
1786 phys = <&mipi_dphy_rx0>;
1787 phy-names = "dphy";
1788 power-domains = <&power RK3399_PD_ISP0>;
1789 status = "disabled";
1790
1791 ports {
1792 #address-cells = <1>;
1793 #size-cells = <0>;
1794
1795 port@0 {
1796 reg = <0>;
1797 #address-cells = <1>;
1798 #size-cells = <0>;
1799 };
1800 };
1801 };
1802
ae4fdcca
SX		 1803 isp0_mmu: iommu@ff914000 {
1804 compatible = "rockchip,iommu";
1805 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1806 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
c432a29d 1807 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
df3bcde7 1808 clock-names = "aclk", "iface";
ae4fdcca 1809 #iommu-cells = <0>;
c432a29d 1810 power-domains = <&power RK3399_PD_ISP0>;
ae4fdcca 1811 rockchip,disable-mmu-reset;
ae4fdcca
SX		 1812 };
1813
c349ae38
HS		 1814 isp1: isp1@ff920000 {
1815 compatible = "rockchip,rk3399-cif-isp";
1816 reg = <0x0 0xff920000 0x0 0x4000>;
1817 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1818 clocks = <&cru SCLK_ISP1>,
1819 <&cru ACLK_ISP1_WRAPPER>,
1820 <&cru HCLK_ISP1_WRAPPER>;
1821 clock-names = "isp", "aclk", "hclk";
1822 iommus = <&isp1_mmu>;
1823 phys = <&mipi_dsi1>;
1824 phy-names = "dphy";
1825 power-domains = <&power RK3399_PD_ISP1>;
1826 status = "disabled";
1827
1828 ports {
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1831
1832 port@0 {
1833 reg = <0>;
1834 #address-cells = <1>;
1835 #size-cells = <0>;
1836 };
1837 };
1838 };
1839
ae4fdcca
SX		 1840 isp1_mmu: iommu@ff924000 {
1841 compatible = "rockchip,iommu";
1842 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1843 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
c432a29d 1844 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
df3bcde7 1845 clock-names = "aclk", "iface";
ae4fdcca 1846 #iommu-cells = <0>;
c432a29d 1847 power-domains = <&power RK3399_PD_ISP1>;
ae4fdcca 1848 rockchip,disable-mmu-reset;
ae4fdcca
SX		 1849 };
1850
0d60d48c
VB		 1851 hdmi_sound: hdmi-sound {
1852 compatible = "simple-audio-card";
1853 simple-audio-card,format = "i2s";
1854 simple-audio-card,mclk-fs = <256>;
1855 simple-audio-card,name = "hdmi-sound";
1856 status = "disabled";
1857
1858 simple-audio-card,cpu {
1859 sound-dai = <&i2s2>;
1860 };
1861 simple-audio-card,codec {
1862 sound-dai = <&hdmi>;
1863 };
1864 };
1865
81e923dd
JC		 1866 hdmi: hdmi@ff940000 {
1867 compatible = "rockchip,rk3399-dw-hdmi";
1868 reg = <0x0 0xff940000 0x0 0x20000>;
1869 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
db2fd26d
PHH		 1870 clocks = <&cru PCLK_HDMI_CTRL>,
1871 <&cru SCLK_HDMI_SFR>,
1872 <&cru PLL_VPLL>,
1873 <&cru PCLK_VIO_GRF>,
1874 <&cru SCLK_HDMI_CEC>;
1875 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
81e923dd
JC		 1876 power-domains = <&power RK3399_PD_HDCP>;
1877 reg-io-width = <4>;
1878 rockchip,grf = <&grf>;
0d60d48c 1879 #sound-dai-cells = <0>;
81e923dd
JC		 1880 status = "disabled";
1881
1882 ports {
1883 hdmi_in: port {
1884 #address-cells = <1>;
1885 #size-cells = <0>;
1886
1887 hdmi_in_vopb: endpoint@0 {
1888 reg = <0>;
1889 remote-endpoint = <&vopb_out_hdmi>;
1890 };
1891 hdmi_in_vopl: endpoint@1 {
1892 reg = <1>;
1893 remote-endpoint = <&vopl_out_hdmi>;
1894 };
1895 };
1896 };
1897 };
1898
d3f51f49
JC		 1899 mipi_dsi: mipi@ff960000 {
1900 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1901 reg = <0x0 0xff960000 0x0 0x8000>;
1902 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
bb4e6ff0 1903 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
0bc15d85
NY		 1904 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1905 clock-names = "ref", "pclk", "phy_cfg", "grf";
d3f51f49 1906 power-domains = <&power RK3399_PD_VIO>;
3813a10a
BN		 1907 resets = <&cru SRST_P_MIPI_DSI0>;
1908 reset-names = "apb";
d3f51f49 1909 rockchip,grf = <&grf>;
91e75bde
HS		 1910 #address-cells = <1>;
1911 #size-cells = <0>;
d3f51f49
JC		 1912 status = "disabled";
1913
1914 ports {
c856cb5d
NY		 1915 #address-cells = <1>;
1916 #size-cells = <0>;
1917
1918 mipi_in: port@0 {
1919 reg = <0>;
d3f51f49
JC		 1920 #address-cells = <1>;
1921 #size-cells = <0>;
1922
1923 mipi_in_vopb: endpoint@0 {
1924 reg = <0>;
1925 remote-endpoint = <&vopb_out_mipi>;
1926 };
1927 mipi_in_vopl: endpoint@1 {
1928 reg = <1>;
1929 remote-endpoint = <&vopl_out_mipi>;
1930 };
1931 };
1932 };
1933 };
1934
1df5d2ab
NY		 1935 mipi_dsi1: mipi@ff968000 {
1936 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1937 reg = <0x0 0xff968000 0x0 0x8000>;
1938 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1939 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1940 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1941 clock-names = "ref", "pclk", "phy_cfg", "grf";
1942 power-domains = <&power RK3399_PD_VIO>;
1943 resets = <&cru SRST_P_MIPI_DSI1>;
1944 reset-names = "apb";
1945 rockchip,grf = <&grf>;
91e75bde
HS		 1946 #address-cells = <1>;
1947 #size-cells = <0>;
8d47d12e 1948 #phy-cells = <0>;
1df5d2ab
NY		 1949 status = "disabled";
1950
1951 ports {
1952 #address-cells = <1>;
1953 #size-cells = <0>;
1954
1955 mipi1_in: port@0 {
1956 reg = <0>;
1957 #address-cells = <1>;
1958 #size-cells = <0>;
1959
1960 mipi1_in_vopb: endpoint@0 {
1961 reg = <0>;
1962 remote-endpoint = <&vopb_out_mipi1>;
1963 };
1964
1965 mipi1_in_vopl: endpoint@1 {
1966 reg = <1>;
1967 remote-endpoint = <&vopl_out_mipi1>;
1968 };
1969 };
1970 };
1971 };
1972
f7a29e30
YY		 1973 edp: edp@ff970000 {
1974 compatible = "rockchip,rk3399-edp";
1975 reg = <0x0 0xff970000 0x0 0x8000>;
1976 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
7b0390ea
YY		 1977 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1978 clock-names = "dp", "pclk", "grf";
f7a29e30
YY		 1979 pinctrl-names = "default";
1980 pinctrl-0 = <&edp_hpd>;
1981 power-domains = <&power RK3399_PD_EDP>;
1982 resets = <&cru SRST_P_EDP_CTRL>;
1983 reset-names = "dp";
1984 rockchip,grf = <&grf>;
1985 status = "disabled";
1986
1987 ports {
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1990 edp_in: port@0 {
1991 reg = <0>;
1992 #address-cells = <1>;
1993 #size-cells = <0>;
1994
1995 edp_in_vopb: endpoint@0 {
1996 reg = <0>;
1997 remote-endpoint = <&vopb_out_edp>;
1998 };
1999
2000 edp_in_vopl: endpoint@1 {
2001 reg = <1>;
2002 remote-endpoint = <&vopl_out_edp>;
2003 };
2004 };
2005 };
2006 };
2007
68d19331
CW		 2008 gpu: gpu@ff9a0000 {
2009 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2010 reg = <0x0 0xff9a0000 0x0 0x10000>;
c604fd81
JJ		 2011 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
2012 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
2013 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
2014 interrupt-names = "job", "mmu", "gpu";
68d19331 2015 clocks = <&cru ACLK_GPU>;
36be9111 2016 #cooling-cells = <2>;
68d19331 2017 power-domains = <&power RK3399_PD_GPU>;
f048b9a4
JX		 2018 status = "disabled";
2019 };
2020
2021 pinctrl: pinctrl {
2022 compatible = "rockchip,rk3399-pinctrl";
2023 rockchip,grf = <&grf>;
2024 rockchip,pmu = <&pmugrf>;
2025 #address-cells = <2>;
2026 #size-cells = <2>;
2027 ranges;
2028
2029 gpio0: gpio0@ff720000 {
2030 compatible = "rockchip,gpio-bank";
2031 reg = <0x0 0xff720000 0x0 0x100>;
2032 clocks = <&pmucru PCLK_GPIO0_PMU>;
210bbd38 2033 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2034
2035 gpio-controller;
2036 #gpio-cells = <0x2>;
2037
2038 interrupt-controller;
2039 #interrupt-cells = <0x2>;
2040 };
2041
2042 gpio1: gpio1@ff730000 {
2043 compatible = "rockchip,gpio-bank";
2044 reg = <0x0 0xff730000 0x0 0x100>;
2045 clocks = <&pmucru PCLK_GPIO1_PMU>;
210bbd38 2046 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2047
2048 gpio-controller;
2049 #gpio-cells = <0x2>;
2050
2051 interrupt-controller;
2052 #interrupt-cells = <0x2>;
2053 };
2054
2055 gpio2: gpio2@ff780000 {
2056 compatible = "rockchip,gpio-bank";
2057 reg = <0x0 0xff780000 0x0 0x100>;
2058 clocks = <&cru PCLK_GPIO2>;
210bbd38 2059 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2060
2061 gpio-controller;
2062 #gpio-cells = <0x2>;
2063
2064 interrupt-controller;
2065 #interrupt-cells = <0x2>;
2066 };
2067
2068 gpio3: gpio3@ff788000 {
2069 compatible = "rockchip,gpio-bank";
2070 reg = <0x0 0xff788000 0x0 0x100>;
2071 clocks = <&cru PCLK_GPIO3>;
210bbd38 2072 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2073
2074 gpio-controller;
2075 #gpio-cells = <0x2>;
2076
2077 interrupt-controller;
2078 #interrupt-cells = <0x2>;
2079 };
2080
2081 gpio4: gpio4@ff790000 {
2082 compatible = "rockchip,gpio-bank";
2083 reg = <0x0 0xff790000 0x0 0x100>;
2084 clocks = <&cru PCLK_GPIO4>;
210bbd38 2085 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 2086
2087 gpio-controller;
2088 #gpio-cells = <0x2>;
2089
2090 interrupt-controller;
2091 #interrupt-cells = <0x2>;
2092 };
2093
2094 pcfg_pull_up: pcfg-pull-up {
2095 bias-pull-up;
2096 };
2097
2098 pcfg_pull_down: pcfg-pull-down {
2099 bias-pull-down;
2100 };
2101
2102 pcfg_pull_none: pcfg-pull-none {
2103 bias-disable;
2104 };
2105
2106 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2107 bias-disable;
2108 drive-strength = <12>;
2109 };
2110
b4102328
RL		 2111 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2112 bias-disable;
2113 drive-strength = <13>;
2114 };
2115
2116 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2117 bias-disable;
2118 drive-strength = <18>;
2119 };
2120
2121 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2122 bias-disable;
2123 drive-strength = <20>;
2124 };
2125
2126 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2127 bias-pull-up;
2128 drive-strength = <2>;
2129 };
2130
f048b9a4
JX		 2131 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2132 bias-pull-up;
2133 drive-strength = <8>;
2134 };
2135
b4102328
RL		 2136 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2137 bias-pull-up;
2138 drive-strength = <18>;
2139 };
2140
2141 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2142 bias-pull-up;
2143 drive-strength = <20>;
2144 };
2145
f048b9a4
JX		 2146 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2147 bias-pull-down;
2148 drive-strength = <4>;
2149 };
2150
b4102328
RL		 2151 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2152 bias-pull-down;
2153 drive-strength = <8>;
f048b9a4
JX		 2154 };
2155
2156 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2157 bias-pull-down;
2158 drive-strength = <12>;
2159 };
2160
b4102328
RL		 2161 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2162 bias-pull-down;
2163 drive-strength = <18>;
2164 };
2165
2166 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2167 bias-pull-down;
2168 drive-strength = <20>;
2169 };
2170
2171 pcfg_output_high: pcfg-output-high {
2172 output-high;
2173 };
2174
2175 pcfg_output_low: pcfg-output-low {
2176 output-low;
f048b9a4
JX		 2177 };
2178
a8bcaea7
DA		 2179 clock {
2180 clk_32k: clk-32k {
d64420e8 2181 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
a8bcaea7
DA		 2182 };
2183 };
2184
f1400702
HS		 2185 cif {
2186 cif_clkin: cif-clkin {
2187 rockchip,pins =
2188 <2 RK_PB2 3 &pcfg_pull_none>;
2189 };
2190
2191 cif_clkouta: cif-clkouta {
2192 rockchip,pins =
2193 <2 RK_PB3 3 &pcfg_pull_none>;
2194 };
2195 };
2196
8742466a
BN		 2197 edp {
2198 edp_hpd: edp-hpd {
2199 rockchip,pins =
d64420e8 2200 <4 RK_PC7 2 &pcfg_pull_none>;
8742466a
BN		 2201 };
2202 };
2203
eb3a6a6a
RC		 2204 gmac {
2205 rgmii_pins: rgmii-pins {
2206 rockchip,pins =
2207 /* mac_txclk */
d64420e8 2208 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2209 /* mac_rxclk */
d64420e8 2210 <3 RK_PB6 1 &pcfg_pull_none>,
eb3a6a6a 2211 /* mac_mdio */
d64420e8 2212 <3 RK_PB5 1 &pcfg_pull_none>,
eb3a6a6a 2213 /* mac_txen */
d64420e8 2214 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2215 /* mac_clk */
d64420e8 2216 <3 RK_PB3 1 &pcfg_pull_none>,
eb3a6a6a 2217 /* mac_rxdv */
d64420e8 2218 <3 RK_PB1 1 &pcfg_pull_none>,
eb3a6a6a 2219 /* mac_mdc */
d64420e8 2220 <3 RK_PB0 1 &pcfg_pull_none>,
eb3a6a6a 2221 /* mac_rxd1 */
d64420e8 2222 <3 RK_PA7 1 &pcfg_pull_none>,
eb3a6a6a 2223 /* mac_rxd0 */
d64420e8 2224 <3 RK_PA6 1 &pcfg_pull_none>,
eb3a6a6a 2225 /* mac_txd1 */
d64420e8 2226 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2227 /* mac_txd0 */
d64420e8 2228 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2229 /* mac_rxd3 */
d64420e8 2230 <3 RK_PA3 1 &pcfg_pull_none>,
eb3a6a6a 2231 /* mac_rxd2 */
d64420e8 2232 <3 RK_PA2 1 &pcfg_pull_none>,
eb3a6a6a 2233 /* mac_txd3 */
d64420e8 2234 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2235 /* mac_txd2 */
d64420e8 2236 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
eb3a6a6a
RC		 2237 };
2238
2239 rmii_pins: rmii-pins {
2240 rockchip,pins =
2241 /* mac_mdio */
d64420e8 2242 <3 RK_PB5 1 &pcfg_pull_none>,
eb3a6a6a 2243 /* mac_txen */
d64420e8 2244 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2245 /* mac_clk */
d64420e8 2246 <3 RK_PB3 1 &pcfg_pull_none>,
eb3a6a6a 2247 /* mac_rxer */
d64420e8 2248 <3 RK_PB2 1 &pcfg_pull_none>,
eb3a6a6a 2249 /* mac_rxdv */
d64420e8 2250 <3 RK_PB1 1 &pcfg_pull_none>,
eb3a6a6a 2251 /* mac_mdc */
d64420e8 2252 <3 RK_PB0 1 &pcfg_pull_none>,
eb3a6a6a 2253 /* mac_rxd1 */
d64420e8 2254 <3 RK_PA7 1 &pcfg_pull_none>,
eb3a6a6a 2255 /* mac_rxd0 */
d64420e8 2256 <3 RK_PA6 1 &pcfg_pull_none>,
eb3a6a6a 2257 /* mac_txd1 */
d64420e8 2258 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
eb3a6a6a 2259 /* mac_txd0 */
d64420e8 2260 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
eb3a6a6a
RC		 2261 };
2262 };
2263
f048b9a4
JX		 2264 i2c0 {
2265 i2c0_xfer: i2c0-xfer {
2266 rockchip,pins =
d64420e8
HS		 2267 <1 RK_PB7 2 &pcfg_pull_none>,
2268 <1 RK_PC0 2 &pcfg_pull_none>;
f048b9a4
JX		 2269 };
2270 };
2271
2272 i2c1 {
2273 i2c1_xfer: i2c1-xfer {
2274 rockchip,pins =
d64420e8
HS		 2275 <4 RK_PA2 1 &pcfg_pull_none>,
2276 <4 RK_PA1 1 &pcfg_pull_none>;
f048b9a4
JX		 2277 };
2278 };
2279
2280 i2c2 {
2281 i2c2_xfer: i2c2-xfer {
2282 rockchip,pins =
d64420e8
HS		 2283 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2284 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
f048b9a4
JX		 2285 };
2286 };
2287
2288 i2c3 {
2289 i2c3_xfer: i2c3-xfer {
2290 rockchip,pins =
d64420e8
HS		 2291 <4 RK_PC1 1 &pcfg_pull_none>,
2292 <4 RK_PC0 1 &pcfg_pull_none>;
f048b9a4
JX		 2293 };
2294 };
2295
2296 i2c4 {
2297 i2c4_xfer: i2c4-xfer {
2298 rockchip,pins =
d64420e8
HS		 2299 <1 RK_PB4 1 &pcfg_pull_none>,
2300 <1 RK_PB3 1 &pcfg_pull_none>;
f048b9a4
JX		 2301 };
2302 };
2303
2304 i2c5 {
2305 i2c5_xfer: i2c5-xfer {
2306 rockchip,pins =
d64420e8
HS		 2307 <3 RK_PB3 2 &pcfg_pull_none>,
2308 <3 RK_PB2 2 &pcfg_pull_none>;
f048b9a4
JX		 2309 };
2310 };
2311
2312 i2c6 {
2313 i2c6_xfer: i2c6-xfer {
2314 rockchip,pins =
d64420e8
HS		 2315 <2 RK_PB2 2 &pcfg_pull_none>,
2316 <2 RK_PB1 2 &pcfg_pull_none>;
f048b9a4
JX		 2317 };
2318 };
2319
2320 i2c7 {
2321 i2c7_xfer: i2c7-xfer {
2322 rockchip,pins =
d64420e8
HS		 2323 <2 RK_PB0 2 &pcfg_pull_none>,
2324 <2 RK_PA7 2 &pcfg_pull_none>;
f048b9a4
JX		 2325 };
2326 };
2327
2328 i2c8 {
2329 i2c8_xfer: i2c8-xfer {
2330 rockchip,pins =
d64420e8
HS		 2331 <1 RK_PC5 1 &pcfg_pull_none>,
2332 <1 RK_PC4 1 &pcfg_pull_none>;
f048b9a4
JX		 2333 };
2334 };
2335
2336 i2s0 {
0efaf807
KG		 2337 i2s0_2ch_bus: i2s0-2ch-bus {
2338 rockchip,pins =
d64420e8
HS		 2339 <3 RK_PD0 1 &pcfg_pull_none>,
2340 <3 RK_PD1 1 &pcfg_pull_none>,
2341 <3 RK_PD2 1 &pcfg_pull_none>,
2342 <3 RK_PD3 1 &pcfg_pull_none>,
2343 <3 RK_PD7 1 &pcfg_pull_none>,
2344 <4 RK_PA0 1 &pcfg_pull_none>;
0efaf807
KG		 2345 };
2346
f048b9a4
JX		 2347 i2s0_8ch_bus: i2s0-8ch-bus {
2348 rockchip,pins =
d64420e8
HS		 2349 <3 RK_PD0 1 &pcfg_pull_none>,
2350 <3 RK_PD1 1 &pcfg_pull_none>,
2351 <3 RK_PD2 1 &pcfg_pull_none>,
2352 <3 RK_PD3 1 &pcfg_pull_none>,
2353 <3 RK_PD4 1 &pcfg_pull_none>,
2354 <3 RK_PD5 1 &pcfg_pull_none>,
2355 <3 RK_PD6 1 &pcfg_pull_none>,
2356 <3 RK_PD7 1 &pcfg_pull_none>,
2357 <4 RK_PA0 1 &pcfg_pull_none>;
f048b9a4
JX		 2358 };
2359 };
2360
2361 i2s1 {
2362 i2s1_2ch_bus: i2s1-2ch-bus {
2363 rockchip,pins =
d64420e8
HS		 2364 <4 RK_PA3 1 &pcfg_pull_none>,
2365 <4 RK_PA4 1 &pcfg_pull_none>,
2366 <4 RK_PA5 1 &pcfg_pull_none>,
2367 <4 RK_PA6 1 &pcfg_pull_none>,
2368 <4 RK_PA7 1 &pcfg_pull_none>;
f048b9a4
JX		 2369 };
2370 };
2371
b74a2e98
KY		 2372 sdio0 {
2373 sdio0_bus1: sdio0-bus1 {
2374 rockchip,pins =
d64420e8 2375 <2 RK_PC4 1 &pcfg_pull_up>;
b74a2e98
KY		 2376 };
2377
2378 sdio0_bus4: sdio0-bus4 {
2379 rockchip,pins =
d64420e8
HS		 2380 <2 RK_PC4 1 &pcfg_pull_up>,
2381 <2 RK_PC5 1 &pcfg_pull_up>,
2382 <2 RK_PC6 1 &pcfg_pull_up>,
2383 <2 RK_PC7 1 &pcfg_pull_up>;
b74a2e98
KY		 2384 };
2385
2386 sdio0_cmd: sdio0-cmd {
2387 rockchip,pins =
d64420e8 2388 <2 RK_PD0 1 &pcfg_pull_up>;
b74a2e98
KY		 2389 };
2390
2391 sdio0_clk: sdio0-clk {
2392 rockchip,pins =
d64420e8 2393 <2 RK_PD1 1 &pcfg_pull_none>;
b74a2e98
KY		 2394 };
2395
2396 sdio0_cd: sdio0-cd {
2397 rockchip,pins =
d64420e8 2398 <2 RK_PD2 1 &pcfg_pull_up>;
b74a2e98
KY		 2399 };
2400
2401 sdio0_pwr: sdio0-pwr {
2402 rockchip,pins =
d64420e8 2403 <2 RK_PD3 1 &pcfg_pull_up>;
b74a2e98
KY		 2404 };
2405
2406 sdio0_bkpwr: sdio0-bkpwr {
2407 rockchip,pins =
d64420e8 2408 <2 RK_PD4 1 &pcfg_pull_up>;
b74a2e98
KY		 2409 };
2410
2411 sdio0_wp: sdio0-wp {
2412 rockchip,pins =
d64420e8 2413 <0 RK_PA3 1 &pcfg_pull_up>;
b74a2e98
KY		 2414 };
2415
2416 sdio0_int: sdio0-int {
2417 rockchip,pins =
d64420e8 2418 <0 RK_PA4 1 &pcfg_pull_up>;
b74a2e98
KY		 2419 };
2420 };
2421
2422 sdmmc {
2423 sdmmc_bus1: sdmmc-bus1 {
2424 rockchip,pins =
d64420e8 2425 <4 RK_PB0 1 &pcfg_pull_up>;
b74a2e98
KY		 2426 };
2427
2428 sdmmc_bus4: sdmmc-bus4 {
2429 rockchip,pins =
d64420e8
HS		 2430 <4 RK_PB0 1 &pcfg_pull_up>,
2431 <4 RK_PB1 1 &pcfg_pull_up>,
2432 <4 RK_PB2 1 &pcfg_pull_up>,
2433 <4 RK_PB3 1 &pcfg_pull_up>;
b74a2e98
KY		 2434 };
2435
2436 sdmmc_clk: sdmmc-clk {
2437 rockchip,pins =
d64420e8 2438 <4 RK_PB4 1 &pcfg_pull_none>;
b74a2e98
KY		 2439 };
2440
2441 sdmmc_cmd: sdmmc-cmd {
2442 rockchip,pins =
d64420e8 2443 <4 RK_PB5 1 &pcfg_pull_up>;
b74a2e98
KY		 2444 };
2445
6122308e 2446 sdmmc_cd: sdmmc-cd {
b74a2e98 2447 rockchip,pins =
d64420e8 2448 <0 RK_PA7 1 &pcfg_pull_up>;
b74a2e98
KY		 2449 };
2450
2451 sdmmc_wp: sdmmc-wp {
2452 rockchip,pins =
d64420e8 2453 <0 RK_PB0 1 &pcfg_pull_up>;
b74a2e98
KY		 2454 };
2455 };
2456
a7ecfad4 2457 suspend {
5d26ad9c 2458 ap_pwroff: ap-pwroff {
d64420e8 2459 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
5d26ad9c
DA		 2460 };
2461
2462 ddrio_pwroff: ddrio-pwroff {
d64420e8 2463 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
5d26ad9c
DA		 2464 };
2465 };
2466
f048b9a4
JX		 2467 spdif {
2468 spdif_bus: spdif-bus {
2469 rockchip,pins =
d64420e8 2470 <4 RK_PC5 1 &pcfg_pull_none>;
f048b9a4 2471 };
b74a2e98
KY		 2472
2473 spdif_bus_1: spdif-bus-1 {
2474 rockchip,pins =
d64420e8 2475 <3 RK_PC0 3 &pcfg_pull_none>;
b74a2e98 2476 };
f048b9a4
JX		 2477 };
2478
2479 spi0 {
2480 spi0_clk: spi0-clk {
2481 rockchip,pins =
d64420e8 2482 <3 RK_PA6 2 &pcfg_pull_up>;
f048b9a4
JX		 2483 };
2484 spi0_cs0: spi0-cs0 {
2485 rockchip,pins =
d64420e8 2486 <3 RK_PA7 2 &pcfg_pull_up>;
f048b9a4
JX		 2487 };
2488 spi0_cs1: spi0-cs1 {
2489 rockchip,pins =
d64420e8 2490 <3 RK_PB0 2 &pcfg_pull_up>;
f048b9a4
JX		 2491 };
2492 spi0_tx: spi0-tx {
2493 rockchip,pins =
d64420e8 2494 <3 RK_PA5 2 &pcfg_pull_up>;
f048b9a4
JX		 2495 };
2496 spi0_rx: spi0-rx {
2497 rockchip,pins =
d64420e8 2498 <3 RK_PA4 2 &pcfg_pull_up>;
f048b9a4
JX		 2499 };
2500 };
2501
2502 spi1 {
2503 spi1_clk: spi1-clk {
2504 rockchip,pins =
d64420e8 2505 <1 RK_PB1 2 &pcfg_pull_up>;
f048b9a4
JX		 2506 };
2507 spi1_cs0: spi1-cs0 {
2508 rockchip,pins =
d64420e8 2509 <1 RK_PB2 2 &pcfg_pull_up>;
f048b9a4
JX		 2510 };
2511 spi1_rx: spi1-rx {
2512 rockchip,pins =
d64420e8 2513 <1 RK_PA7 2 &pcfg_pull_up>;
f048b9a4
JX		 2514 };
2515 spi1_tx: spi1-tx {
2516 rockchip,pins =
d64420e8 2517 <1 RK_PB0 2 &pcfg_pull_up>;
f048b9a4
JX		 2518 };
2519 };
2520
2521 spi2 {
2522 spi2_clk: spi2-clk {
2523 rockchip,pins =
d64420e8 2524 <2 RK_PB3 1 &pcfg_pull_up>;
f048b9a4
JX		 2525 };
2526 spi2_cs0: spi2-cs0 {
2527 rockchip,pins =
d64420e8 2528 <2 RK_PB4 1 &pcfg_pull_up>;
f048b9a4
JX		 2529 };
2530 spi2_rx: spi2-rx {
2531 rockchip,pins =
d64420e8 2532 <2 RK_PB1 1 &pcfg_pull_up>;
f048b9a4
JX		 2533 };
2534 spi2_tx: spi2-tx {
2535 rockchip,pins =
d64420e8 2536 <2 RK_PB2 1 &pcfg_pull_up>;
f048b9a4
JX		 2537 };
2538 };
2539
2540 spi3 {
2541 spi3_clk: spi3-clk {
2542 rockchip,pins =
d64420e8 2543 <1 RK_PC1 1 &pcfg_pull_up>;
f048b9a4
JX		 2544 };
2545 spi3_cs0: spi3-cs0 {
2546 rockchip,pins =
d64420e8 2547 <1 RK_PC2 1 &pcfg_pull_up>;
f048b9a4
JX		 2548 };
2549 spi3_rx: spi3-rx {
2550 rockchip,pins =
d64420e8 2551 <1 RK_PB7 1 &pcfg_pull_up>;
f048b9a4
JX		 2552 };
2553 spi3_tx: spi3-tx {
2554 rockchip,pins =
d64420e8 2555 <1 RK_PC0 1 &pcfg_pull_up>;
f048b9a4
JX		 2556 };
2557 };
2558
2559 spi4 {
2560 spi4_clk: spi4-clk {
2561 rockchip,pins =
d64420e8 2562 <3 RK_PA2 2 &pcfg_pull_up>;
f048b9a4
JX		 2563 };
2564 spi4_cs0: spi4-cs0 {
2565 rockchip,pins =
d64420e8 2566 <3 RK_PA3 2 &pcfg_pull_up>;
f048b9a4
JX		 2567 };
2568 spi4_rx: spi4-rx {
2569 rockchip,pins =
d64420e8 2570 <3 RK_PA0 2 &pcfg_pull_up>;
f048b9a4
JX		 2571 };
2572 spi4_tx: spi4-tx {
2573 rockchip,pins =
d64420e8 2574 <3 RK_PA1 2 &pcfg_pull_up>;
f048b9a4
JX		 2575 };
2576 };
2577
2578 spi5 {
2579 spi5_clk: spi5-clk {
2580 rockchip,pins =
d64420e8 2581 <2 RK_PC6 2 &pcfg_pull_up>;
f048b9a4
JX		 2582 };
2583 spi5_cs0: spi5-cs0 {
2584 rockchip,pins =
d64420e8 2585 <2 RK_PC7 2 &pcfg_pull_up>;
f048b9a4
JX		 2586 };
2587 spi5_rx: spi5-rx {
2588 rockchip,pins =
d64420e8 2589 <2 RK_PC4 2 &pcfg_pull_up>;
f048b9a4
JX		 2590 };
2591 spi5_tx: spi5-tx {
2592 rockchip,pins =
d64420e8 2593 <2 RK_PC5 2 &pcfg_pull_up>;
f048b9a4
JX		 2594 };
2595 };
2596
ba2b043e
SZ		 2597 testclk {
2598 test_clkout0: test-clkout0 {
2599 rockchip,pins =
d64420e8 2600 <0 RK_PA0 1 &pcfg_pull_none>;
ba2b043e
SZ		 2601 };
2602
2603 test_clkout1: test-clkout1 {
2604 rockchip,pins =
d64420e8 2605 <2 RK_PD1 2 &pcfg_pull_none>;
ba2b043e
SZ		 2606 };
2607
2608 test_clkout2: test-clkout2 {
2609 rockchip,pins =
d64420e8 2610 <0 RK_PB0 3 &pcfg_pull_none>;
ba2b043e
SZ		 2611 };
2612 };
2613
95c27ba7 2614 tsadc {
2bc65fef 2615 otp_pin: otp-pin {
d64420e8 2616 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
95c27ba7
CW		 2617 };
2618
2619 otp_out: otp-out {
d64420e8 2620 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
95c27ba7
CW		 2621 };
2622 };
2623
f048b9a4
JX		 2624 uart0 {
2625 uart0_xfer: uart0-xfer {
2626 rockchip,pins =
d64420e8
HS		 2627 <2 RK_PC0 1 &pcfg_pull_up>,
2628 <2 RK_PC1 1 &pcfg_pull_none>;
f048b9a4
JX		 2629 };
2630
2631 uart0_cts: uart0-cts {
2632 rockchip,pins =
d64420e8 2633 <2 RK_PC2 1 &pcfg_pull_none>;
f048b9a4
JX		 2634 };
2635
2636 uart0_rts: uart0-rts {
2637 rockchip,pins =
d64420e8 2638 <2 RK_PC3 1 &pcfg_pull_none>;
f048b9a4
JX		 2639 };
2640 };
2641
2642 uart1 {
2643 uart1_xfer: uart1-xfer {
2644 rockchip,pins =
d64420e8
HS		 2645 <3 RK_PB4 2 &pcfg_pull_up>,
2646 <3 RK_PB5 2 &pcfg_pull_none>;
f048b9a4
JX		 2647 };
2648 };
2649
2650 uart2a {
2651 uart2a_xfer: uart2a-xfer {
2652 rockchip,pins =
d64420e8
HS		 2653 <4 RK_PB0 2 &pcfg_pull_up>,
2654 <4 RK_PB1 2 &pcfg_pull_none>;
f048b9a4
JX		 2655 };
2656 };
2657
2658 uart2b {
2659 uart2b_xfer: uart2b-xfer {
2660 rockchip,pins =
d64420e8
HS		 2661 <4 RK_PC0 2 &pcfg_pull_up>,
2662 <4 RK_PC1 2 &pcfg_pull_none>;
f048b9a4
JX		 2663 };
2664 };
2665
2666 uart2c {
2667 uart2c_xfer: uart2c-xfer {
2668 rockchip,pins =
d64420e8
HS		 2669 <4 RK_PC3 1 &pcfg_pull_up>,
2670 <4 RK_PC4 1 &pcfg_pull_none>;
f048b9a4
JX		 2671 };
2672 };
2673
2674 uart3 {
2675 uart3_xfer: uart3-xfer {
2676 rockchip,pins =
d64420e8
HS		 2677 <3 RK_PB6 2 &pcfg_pull_up>,
2678 <3 RK_PB7 2 &pcfg_pull_none>;
f048b9a4
JX		 2679 };
2680
2681 uart3_cts: uart3-cts {
2682 rockchip,pins =
40a0dd42 2683 <3 RK_PC0 2 &pcfg_pull_none>;
f048b9a4
JX		 2684 };
2685
2686 uart3_rts: uart3-rts {
2687 rockchip,pins =
40a0dd42 2688 <3 RK_PC1 2 &pcfg_pull_none>;
f048b9a4
JX		 2689 };
2690 };
2691
2692 uart4 {
2693 uart4_xfer: uart4-xfer {
2694 rockchip,pins =
d64420e8
HS		 2695 <1 RK_PA7 1 &pcfg_pull_up>,
2696 <1 RK_PB0 1 &pcfg_pull_none>;
f048b9a4
JX		 2697 };
2698 };
2699
2700 uarthdcp {
2701 uarthdcp_xfer: uarthdcp-xfer {
2702 rockchip,pins =
d64420e8
HS		 2703 <4 RK_PC5 2 &pcfg_pull_up>,
2704 <4 RK_PC6 2 &pcfg_pull_none>;
f048b9a4
JX		 2705 };
2706 };
2707
2708 pwm0 {
2709 pwm0_pin: pwm0-pin {
2710 rockchip,pins =
d64420e8 2711 <4 RK_PC2 1 &pcfg_pull_none>;
b4102328
RL		 2712 };
2713
2714 pwm0_pin_pull_down: pwm0-pin-pull-down {
2715 rockchip,pins =
d64420e8 2716 <4 RK_PC2 1 &pcfg_pull_down>;
f048b9a4
JX		 2717 };
2718
2719 vop0_pwm_pin: vop0-pwm-pin {
2720 rockchip,pins =
d64420e8 2721 <4 RK_PC2 2 &pcfg_pull_none>;
b4102328
RL		 2722 };
2723
2724 vop1_pwm_pin: vop1-pwm-pin {
2725 rockchip,pins =
d64420e8 2726 <4 RK_PC2 3 &pcfg_pull_none>;
f048b9a4
JX		 2727 };
2728 };
2729
2730 pwm1 {
2731 pwm1_pin: pwm1-pin {
2732 rockchip,pins =
d64420e8 2733 <4 RK_PC6 1 &pcfg_pull_none>;
f048b9a4
JX		 2734 };
2735
b4102328 2736 pwm1_pin_pull_down: pwm1-pin-pull-down {
f048b9a4 2737 rockchip,pins =
d64420e8 2738 <4 RK_PC6 1 &pcfg_pull_down>;
f048b9a4
JX		 2739 };
2740 };
2741
2742 pwm2 {
2743 pwm2_pin: pwm2-pin {
2744 rockchip,pins =
d64420e8 2745 <1 RK_PC3 1 &pcfg_pull_none>;
b4102328
RL		 2746 };
2747
2748 pwm2_pin_pull_down: pwm2-pin-pull-down {
2749 rockchip,pins =
d64420e8 2750 <1 RK_PC3 1 &pcfg_pull_down>;
f048b9a4
JX		 2751 };
2752 };
2753
2754 pwm3a {
2755 pwm3a_pin: pwm3a-pin {
2756 rockchip,pins =
d64420e8 2757 <0 RK_PA6 1 &pcfg_pull_none>;
f048b9a4
JX		 2758 };
2759 };
2760
2761 pwm3b {
2762 pwm3b_pin: pwm3b-pin {
2763 rockchip,pins =
d64420e8 2764 <1 RK_PB6 1 &pcfg_pull_none>;
f048b9a4
JX		 2765 };
2766 };
85aaa574 2767
b74a2e98
KY		 2768 hdmi {
2769 hdmi_i2c_xfer: hdmi-i2c-xfer {
2770 rockchip,pins =
d64420e8
HS		 2771 <4 RK_PC1 3 &pcfg_pull_none>,
2772 <4 RK_PC0 3 &pcfg_pull_none>;
b74a2e98
KY		 2773 };
2774
2775 hdmi_cec: hdmi-cec {
2776 rockchip,pins =
d64420e8 2777 <4 RK_PC7 1 &pcfg_pull_none>;
b74a2e98
KY		 2778 };
2779 };
2780
85aaa574 2781 pcie {
b74a2e98
KY		 2782 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2783 rockchip,pins =
2784 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2785 };
2786
2787 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2788 rockchip,pins =
2789 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2790 };
85aaa574
SL		 2791 };
2792
f048b9a4
JX		 2793 };
2794};
Linux 6.x block layer and io_uring tree(s)