Commit | Line | Data |
---|---|---|
cba59c25 | 1 | // SPDX-License-Identifier: GPL-2.0 |
253ed045 GU |
2 | /* |
3 | * Device Tree Source for the R-Car Gen3 ULCB board | |
4 | * | |
5 | * Copyright (C) 2016 Renesas Electronics Corp. | |
6 | * Copyright (C) 2016 Cogent Embedded, Inc. | |
253ed045 GU |
7 | */ |
8 | ||
9 | #include <dt-bindings/gpio/gpio.h> | |
10 | #include <dt-bindings/input/input.h> | |
11 | ||
12 | / { | |
13 | model = "Renesas R-Car Gen3 ULCB board"; | |
14 | ||
15 | aliases { | |
59c14853 WS |
16 | i2c0 = &i2c0; |
17 | i2c1 = &i2c1; | |
18 | i2c2 = &i2c2; | |
19 | i2c3 = &i2c3; | |
20 | i2c4 = &i2c4; | |
21 | i2c5 = &i2c5; | |
22 | i2c6 = &i2c6; | |
23 | i2c7 = &i2c_dvfs; | |
253ed045 GU |
24 | serial0 = &scif2; |
25 | ethernet0 = &avb; | |
d765a4f3 YS |
26 | mmc0 = &sdhi2; |
27 | mmc1 = &sdhi0; | |
253ed045 GU |
28 | }; |
29 | ||
30 | chosen { | |
b31b43c9 | 31 | bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; |
253ed045 GU |
32 | stdout-path = "serial0:115200n8"; |
33 | }; | |
34 | ||
35 | audio_clkout: audio-clkout { | |
36 | /* | |
37 | * This is same as <&rcar_sound 0> | |
38 | * but needed to avoid cs2000/rcar_sound probe dead-lock | |
39 | */ | |
40 | compatible = "fixed-clock"; | |
41 | #clock-cells = <0>; | |
822cecb1 | 42 | clock-frequency = <12288000>; |
253ed045 GU |
43 | }; |
44 | ||
9f9b22e8 VB |
45 | hdmi0-out { |
46 | compatible = "hdmi-connector"; | |
47 | type = "a"; | |
48 | ||
49 | port { | |
50 | hdmi0_con: endpoint { | |
9fd8bbef | 51 | remote-endpoint = <&rcar_dw_hdmi0_out>; |
9f9b22e8 VB |
52 | }; |
53 | }; | |
54 | }; | |
55 | ||
253ed045 GU |
56 | keyboard { |
57 | compatible = "gpio-keys"; | |
58 | ||
59 | key-1 { | |
60 | linux,code = <KEY_1>; | |
61 | label = "SW3"; | |
62 | wakeup-source; | |
63 | debounce-interval = <20>; | |
64 | gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; | |
65 | }; | |
66 | }; | |
67 | ||
68 | leds { | |
69 | compatible = "gpio-leds"; | |
70 | ||
71 | led5 { | |
72 | gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; | |
73 | }; | |
74 | led6 { | |
75 | gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; | |
76 | }; | |
77 | }; | |
78 | ||
5cf12ac9 | 79 | reg_1p8v: regulator-1p8v { |
253ed045 GU |
80 | compatible = "regulator-fixed"; |
81 | regulator-name = "fixed-1.8V"; | |
82 | regulator-min-microvolt = <1800000>; | |
83 | regulator-max-microvolt = <1800000>; | |
84 | regulator-boot-on; | |
85 | regulator-always-on; | |
86 | }; | |
87 | ||
5cf12ac9 | 88 | reg_3p3v: regulator-3p3v { |
253ed045 GU |
89 | compatible = "regulator-fixed"; |
90 | regulator-name = "fixed-3.3V"; | |
91 | regulator-min-microvolt = <3300000>; | |
92 | regulator-max-microvolt = <3300000>; | |
93 | regulator-boot-on; | |
94 | regulator-always-on; | |
95 | }; | |
96 | ||
253ed045 GU |
97 | vcc_sdhi0: regulator-vcc-sdhi0 { |
98 | compatible = "regulator-fixed"; | |
99 | ||
100 | regulator-name = "SDHI0 Vcc"; | |
101 | regulator-min-microvolt = <3300000>; | |
102 | regulator-max-microvolt = <3300000>; | |
103 | ||
104 | gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; | |
105 | enable-active-high; | |
106 | }; | |
107 | ||
108 | vccq_sdhi0: regulator-vccq-sdhi0 { | |
109 | compatible = "regulator-gpio"; | |
110 | ||
111 | regulator-name = "SDHI0 VccQ"; | |
112 | regulator-min-microvolt = <1800000>; | |
113 | regulator-max-microvolt = <3300000>; | |
114 | ||
115 | gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; | |
116 | gpios-states = <1>; | |
36f06212 | 117 | states = <3300000 1>, <1800000 0>; |
253ed045 GU |
118 | }; |
119 | ||
120 | x12_clk: x12 { | |
121 | compatible = "fixed-clock"; | |
122 | #clock-cells = <0>; | |
123 | clock-frequency = <24576000>; | |
124 | }; | |
8cb6898c VB |
125 | |
126 | x23_clk: x23-clock { | |
127 | compatible = "fixed-clock"; | |
128 | #clock-cells = <0>; | |
129 | clock-frequency = <25000000>; | |
130 | }; | |
253ed045 GU |
131 | }; |
132 | ||
2b35ca2f YG |
133 | &a57_0 { |
134 | cpu-supply = <&dvfs>; | |
135 | }; | |
136 | ||
253ed045 GU |
137 | &audio_clk_a { |
138 | clock-frequency = <22579200>; | |
139 | }; | |
140 | ||
141 | &avb { | |
142 | pinctrl-0 = <&avb_pins>; | |
143 | pinctrl-names = "default"; | |
253ed045 | 144 | phy-handle = <&phy0>; |
9b810181 | 145 | tx-internal-delay-ps = <2000>; |
253ed045 GU |
146 | status = "okay"; |
147 | ||
148 | phy0: ethernet-phy@0 { | |
722d55f3 GU |
149 | compatible = "ethernet-phy-id0022.1622", |
150 | "ethernet-phy-ieee802.3-c22"; | |
253ed045 GU |
151 | rxc-skew-ps = <1500>; |
152 | reg = <0>; | |
153 | interrupt-parent = <&gpio2>; | |
154 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; | |
ef4a3bc8 | 155 | reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; |
253ed045 GU |
156 | }; |
157 | }; | |
158 | ||
7da2ed12 LP |
159 | &du { |
160 | status = "okay"; | |
161 | }; | |
162 | ||
253ed045 GU |
163 | &ehci1 { |
164 | status = "okay"; | |
165 | }; | |
166 | ||
167 | &extal_clk { | |
168 | clock-frequency = <16666666>; | |
169 | }; | |
170 | ||
171 | &extalr_clk { | |
172 | clock-frequency = <32768>; | |
173 | }; | |
174 | ||
2a50b40f VB |
175 | &hdmi0 { |
176 | status = "okay"; | |
177 | ||
178 | ports { | |
179 | port@1 { | |
180 | reg = <1>; | |
181 | rcar_dw_hdmi0_out: endpoint { | |
182 | remote-endpoint = <&hdmi0_con>; | |
183 | }; | |
184 | }; | |
c693b210 KM |
185 | port@2 { |
186 | reg = <2>; | |
c693b210 | 187 | }; |
2a50b40f VB |
188 | }; |
189 | }; | |
190 | ||
253ed045 GU |
191 | &i2c2 { |
192 | pinctrl-0 = <&i2c2_pins>; | |
193 | pinctrl-names = "default"; | |
194 | ||
195 | status = "okay"; | |
196 | ||
197 | clock-frequency = <100000>; | |
198 | ||
199 | ak4613: codec@10 { | |
200 | compatible = "asahi-kasei,ak4613"; | |
253ed045 GU |
201 | reg = <0x10>; |
202 | clocks = <&rcar_sound 3>; | |
203 | ||
204 | asahi-kasei,in1-single-end; | |
205 | asahi-kasei,in2-single-end; | |
206 | asahi-kasei,out1-single-end; | |
207 | asahi-kasei,out2-single-end; | |
208 | asahi-kasei,out3-single-end; | |
209 | asahi-kasei,out4-single-end; | |
210 | asahi-kasei,out5-single-end; | |
211 | asahi-kasei,out6-single-end; | |
212 | }; | |
213 | ||
214 | cs2000: clk-multiplier@4f { | |
215 | #clock-cells = <0>; | |
216 | compatible = "cirrus,cs2000-cp"; | |
217 | reg = <0x4f>; | |
218 | clocks = <&audio_clkout>, <&x12_clk>; | |
219 | clock-names = "clk_in", "ref_clk"; | |
220 | ||
221 | assigned-clocks = <&cs2000>; | |
222 | assigned-clock-rates = <24576000>; /* 1/1 divide */ | |
223 | }; | |
224 | }; | |
225 | ||
476b2e4f VB |
226 | &i2c4 { |
227 | status = "okay"; | |
228 | ||
229 | clock-frequency = <400000>; | |
8cb6898c VB |
230 | |
231 | versaclock5: clock-generator@6a { | |
232 | compatible = "idt,5p49v5925"; | |
233 | reg = <0x6a>; | |
234 | #clock-cells = <1>; | |
235 | clocks = <&x23_clk>; | |
236 | clock-names = "xin"; | |
237 | }; | |
476b2e4f VB |
238 | }; |
239 | ||
a4fedb3a VB |
240 | &i2c_dvfs { |
241 | status = "okay"; | |
786f3cc0 | 242 | |
11a33f81 WS |
243 | clock-frequency = <400000>; |
244 | ||
786f3cc0 GU |
245 | pmic: pmic@30 { |
246 | pinctrl-0 = <&irq0_pins>; | |
247 | pinctrl-names = "default"; | |
248 | ||
249 | compatible = "rohm,bd9571mwv"; | |
250 | reg = <0x30>; | |
251 | interrupt-parent = <&intc_ex>; | |
252 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | |
253 | interrupt-controller; | |
254 | #interrupt-cells = <2>; | |
255 | gpio-controller; | |
256 | #gpio-cells = <2>; | |
1c81a633 GU |
257 | rohm,ddr-backup-power = <0xf>; |
258 | rohm,rstbmode-pulse; | |
786f3cc0 GU |
259 | |
260 | regulators { | |
261 | dvfs: dvfs { | |
262 | regulator-name = "dvfs"; | |
263 | regulator-min-microvolt = <750000>; | |
264 | regulator-max-microvolt = <1030000>; | |
265 | regulator-boot-on; | |
266 | regulator-always-on; | |
267 | }; | |
268 | }; | |
269 | }; | |
a4fedb3a VB |
270 | }; |
271 | ||
253ed045 GU |
272 | &ohci1 { |
273 | status = "okay"; | |
274 | }; | |
275 | ||
276 | &pfc { | |
277 | pinctrl-0 = <&scif_clk_pins>; | |
278 | pinctrl-names = "default"; | |
279 | ||
280 | avb_pins: avb { | |
133ace3f | 281 | mux { |
1518ad14 | 282 | groups = "avb_link", "avb_mdio", "avb_mii"; |
133ace3f SH |
283 | function = "avb"; |
284 | }; | |
285 | ||
1518ad14 GU |
286 | pins_mdio { |
287 | groups = "avb_mdio"; | |
133ace3f SH |
288 | drive-strength = <24>; |
289 | }; | |
290 | ||
291 | pins_mii_tx { | |
292 | pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", | |
293 | "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; | |
294 | drive-strength = <12>; | |
295 | }; | |
253ed045 GU |
296 | }; |
297 | ||
298 | i2c2_pins: i2c2 { | |
299 | groups = "i2c2_a"; | |
300 | function = "i2c2"; | |
301 | }; | |
302 | ||
786f3cc0 GU |
303 | irq0_pins: irq0 { |
304 | groups = "intc_ex_irq0"; | |
305 | function = "intc_ex"; | |
306 | }; | |
307 | ||
253ed045 GU |
308 | scif2_pins: scif2 { |
309 | groups = "scif2_data_a"; | |
310 | function = "scif2"; | |
311 | }; | |
312 | ||
313 | scif_clk_pins: scif_clk { | |
314 | groups = "scif_clk_a"; | |
315 | function = "scif_clk"; | |
316 | }; | |
317 | ||
318 | sdhi0_pins: sd0 { | |
319 | groups = "sdhi0_data4", "sdhi0_ctrl"; | |
320 | function = "sdhi0"; | |
321 | power-source = <3300>; | |
322 | }; | |
323 | ||
324 | sdhi0_pins_uhs: sd0_uhs { | |
325 | groups = "sdhi0_data4", "sdhi0_ctrl"; | |
326 | function = "sdhi0"; | |
327 | power-source = <1800>; | |
328 | }; | |
329 | ||
330 | sdhi2_pins: sd2 { | |
c5dd01aa | 331 | groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; |
253ed045 GU |
332 | function = "sdhi2"; |
333 | power-source = <1800>; | |
334 | }; | |
335 | ||
336 | sound_pins: sound { | |
337 | groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; | |
338 | function = "ssi"; | |
339 | }; | |
340 | ||
341 | sound_clk_pins: sound-clk { | |
342 | groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", | |
343 | "audio_clkout_a", "audio_clkout3_a"; | |
344 | function = "audio_clk"; | |
345 | }; | |
346 | ||
347 | usb1_pins: usb1 { | |
348 | groups = "usb1"; | |
349 | function = "usb1"; | |
350 | }; | |
351 | }; | |
352 | ||
353 | &rcar_sound { | |
3ebf49c0 | 354 | pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; |
253ed045 GU |
355 | pinctrl-names = "default"; |
356 | ||
253ed045 GU |
357 | /* audio_clkout0/1/2/3 */ |
358 | #clock-cells = <1>; | |
2752660a | 359 | clock-frequency = <12288000 11289600>; |
253ed045 GU |
360 | |
361 | status = "okay"; | |
362 | ||
363 | /* update <audio_clk_b> to <cs2000> */ | |
364 | clocks = <&cpg CPG_MOD 1005>, | |
365 | <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, | |
366 | <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, | |
367 | <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, | |
368 | <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, | |
369 | <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, | |
370 | <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, | |
371 | <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, | |
372 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | |
373 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | |
374 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | |
375 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
376 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
377 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, | |
378 | <&audio_clk_a>, <&cs2000>, | |
379 | <&audio_clk_c>, | |
380 | <&cpg CPG_CORE CPG_AUDIO_CLK_I>; | |
253ed045 GU |
381 | }; |
382 | ||
79e903fb GU |
383 | &rpc { |
384 | /* Left disabled. To be enabled by firmware when unlocked. */ | |
385 | ||
386 | flash@0 { | |
387 | compatible = "cypress,hyperflash", "cfi-flash"; | |
388 | reg = <0>; | |
389 | ||
390 | partitions { | |
391 | compatible = "fixed-partitions"; | |
392 | #address-cells = <1>; | |
393 | #size-cells = <1>; | |
394 | ||
395 | bootparam@0 { | |
396 | reg = <0x00000000 0x040000>; | |
397 | read-only; | |
398 | }; | |
399 | bl2@40000 { | |
400 | reg = <0x00040000 0x140000>; | |
401 | read-only; | |
402 | }; | |
403 | cert_header_sa6@180000 { | |
404 | reg = <0x00180000 0x040000>; | |
405 | read-only; | |
406 | }; | |
407 | bl31@1c0000 { | |
408 | reg = <0x001c0000 0x040000>; | |
409 | read-only; | |
410 | }; | |
411 | tee@200000 { | |
412 | reg = <0x00200000 0x440000>; | |
413 | read-only; | |
414 | }; | |
415 | uboot@640000 { | |
416 | reg = <0x00640000 0x100000>; | |
417 | read-only; | |
418 | }; | |
419 | dtb@740000 { | |
420 | reg = <0x00740000 0x080000>; | |
421 | }; | |
422 | kernel@7c0000 { | |
423 | reg = <0x007c0000 0x1400000>; | |
424 | }; | |
425 | user@1bc0000 { | |
426 | reg = <0x01bc0000 0x2440000>; | |
427 | }; | |
428 | }; | |
429 | }; | |
430 | }; | |
431 | ||
0a05b3d7 YK |
432 | &rwdt { |
433 | timeout-sec = <60>; | |
434 | status = "okay"; | |
435 | }; | |
436 | ||
253ed045 GU |
437 | &scif2 { |
438 | pinctrl-0 = <&scif2_pins>; | |
439 | pinctrl-names = "default"; | |
440 | ||
441 | status = "okay"; | |
442 | }; | |
443 | ||
444 | &scif_clk { | |
445 | clock-frequency = <14745600>; | |
446 | }; | |
447 | ||
448 | &sdhi0 { | |
449 | pinctrl-0 = <&sdhi0_pins>; | |
450 | pinctrl-1 = <&sdhi0_pins_uhs>; | |
451 | pinctrl-names = "default", "state_uhs"; | |
452 | ||
453 | vmmc-supply = <&vcc_sdhi0>; | |
454 | vqmmc-supply = <&vccq_sdhi0>; | |
455 | cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; | |
456 | bus-width = <4>; | |
457 | sd-uhs-sdr50; | |
9bc03b57 | 458 | sd-uhs-sdr104; |
253ed045 GU |
459 | status = "okay"; |
460 | }; | |
461 | ||
462 | &sdhi2 { | |
463 | /* used for on-board 8bit eMMC */ | |
464 | pinctrl-0 = <&sdhi2_pins>; | |
5f65328d | 465 | pinctrl-1 = <&sdhi2_pins>; |
253ed045 GU |
466 | pinctrl-names = "default", "state_uhs"; |
467 | ||
468 | vmmc-supply = <®_3p3v>; | |
469 | vqmmc-supply = <®_1p8v>; | |
470 | bus-width = <8>; | |
471 | mmc-hs200-1_8v; | |
e536d27e | 472 | mmc-hs400-1_8v; |
d68c9edf WS |
473 | no-sd; |
474 | no-sdio; | |
253ed045 | 475 | non-removable; |
992d7a8b | 476 | full-pwr-cycle-in-suspend; |
253ed045 GU |
477 | status = "okay"; |
478 | }; | |
479 | ||
480 | &ssi1 { | |
481 | shared-pin; | |
482 | }; | |
483 | ||
484 | &usb2_phy1 { | |
485 | pinctrl-0 = <&usb1_pins>; | |
486 | pinctrl-names = "default"; | |
487 | ||
488 | status = "okay"; | |
489 | }; | |
3e2db2c2 KM |
490 | |
491 | /* | |
492 | * For sound-test. | |
493 | * | |
494 | * We can switch Audio Card for testing | |
495 | * | |
496 | * #include "ulcb-audio-graph-card.dtsi" | |
497 | */ | |
498 | #include "ulcb-audio-graph-card2.dtsi" |