[linux-block.git] / arch / arm64 / boot / dts / renesas / ulcb.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Car Gen3 ULCB board
 *
 * Copyright (C) 2016 Renesas Electronics Corp.
 * Copyright (C) 2016 Cogent Embedded, Inc.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Renesas R-Car Gen3 ULCB board";

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c_dvfs;
		serial0 = &scif2;
		ethernet0 = &avb;
		mmc0 = &sdhi2;
		mmc1 = &sdhi0;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
		stdout-path = "serial0:115200n8";
	};

	audio_clkout: audio-clkout {
		/*
		 * This is same as <&rcar_sound 0>
		 * but needed to avoid cs2000/rcar_sound probe dead-lock
		 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12288000>;
	};

	hdmi0-out {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi0_con: endpoint {
				remote-endpoint = <&rcar_dw_hdmi0_out>;
			};
		};
	};

	keyboard {
		compatible = "gpio-keys";

		key-1 {
			linux,code = <KEY_1>;
			label = "SW3";
			wakeup-source;
			debounce-interval = <20>;
			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led5 {
			gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
		};
		led6 {
			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
		};
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI0 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI0 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};

	x12_clk: x12 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	x23_clk: x23-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};
};

&a57_0 {
	cpu-supply = <&dvfs>;
};

&audio_clk_a {
	clock-frequency = <22579200>;
};

&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy0>;
	tx-internal-delay-ps = <2000>;
	status = "okay";

	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id0022.1622",
			     "ethernet-phy-ieee802.3-c22";
		rxc-skew-ps = <1500>;
		reg = <0>;
		interrupt-parent = <&gpio2>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
	};
};

&du {
	status = "okay";
};

&ehci1 {
	status = "okay";
};

&extal_clk {
	clock-frequency = <16666666>;
};

&extalr_clk {
	clock-frequency = <32768>;
};

&hdmi0 {
	status = "okay";

	ports {
		port@1 {
			reg = <1>;
			rcar_dw_hdmi0_out: endpoint {
				remote-endpoint = <&hdmi0_con>;
			};
		};
		port@2 {
			reg = <2>;
		};
	};
};

&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "default";

	status = "okay";

	clock-frequency = <100000>;

	ak4613: codec@10 {
		compatible = "asahi-kasei,ak4613";
		reg = <0x10>;
		clocks = <&rcar_sound 3>;

		asahi-kasei,in1-single-end;
		asahi-kasei,in2-single-end;
		asahi-kasei,out1-single-end;
		asahi-kasei,out2-single-end;
		asahi-kasei,out3-single-end;
		asahi-kasei,out4-single-end;
		asahi-kasei,out5-single-end;
		asahi-kasei,out6-single-end;
	};

	cs2000: clk-multiplier@4f {
		#clock-cells = <0>;
		compatible = "cirrus,cs2000-cp";
		reg = <0x4f>;
		clocks = <&audio_clkout>, <&x12_clk>;
		clock-names = "clk_in", "ref_clk";

		assigned-clocks = <&cs2000>;
		assigned-clock-rates = <24576000>; /* 1/1 divide */
	};
};

&i2c4 {
	status = "okay";

	clock-frequency = <400000>;

	versaclock5: clock-generator@6a {
		compatible = "idt,5p49v5925";
		reg = <0x6a>;
		#clock-cells = <1>;
		clocks = <&x23_clk>;
		clock-names = "xin";
	};
};

&i2c_dvfs {
	status = "okay";

	clock-frequency = <400000>;

	pmic: pmic@30 {
		pinctrl-0 = <&irq0_pins>;
		pinctrl-names = "default";

		compatible = "rohm,bd9571mwv";
		reg = <0x30>;
		interrupt-parent = <&intc_ex>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
		rohm,ddr-backup-power = <0xf>;
		rohm,rstbmode-pulse;

		regulators {
			dvfs: dvfs {
				regulator-name = "dvfs";
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <1030000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	eeprom@50 {
		compatible = "rohm,br24t01", "atmel,24c01";
		reg = <0x50>;
		pagesize = <8>;
	};
};

&ohci1 {
	status = "okay";
};

&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	avb_pins: avb {
		mux {
			groups = "avb_link", "avb_mdio", "avb_mii";
			function = "avb";
		};

		pins_mdio {
			groups = "avb_mdio";
			drive-strength = <24>;
		};

		pins_mii_tx {
			pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
			       "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
			drive-strength = <12>;
		};
	};

	i2c2_pins: i2c2 {
		groups = "i2c2_a";
		function = "i2c2";
	};

	irq0_pins: irq0 {
		groups = "intc_ex_irq0";
		function = "intc_ex";
	};

	scif2_pins: scif2 {
		groups = "scif2_data_a";
		function = "scif2";
	};

	scif_clk_pins: scif_clk {
		groups = "scif_clk_a";
		function = "scif_clk";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <1800>;
	};

	sdhi2_pins: sd2 {
		groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
		function = "sdhi2";
		power-source = <1800>;
	};

	sound_pins: sound {
		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
		function = "ssi";
	};

	sound_clk_pins: sound-clk {
		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
			 "audio_clkout_a", "audio_clkout3_a";
		function = "audio_clk";
	};

	usb1_pins: usb1 {
		groups = "usb1";
		function = "usb1";
	};
};

&rcar_sound {
	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
	pinctrl-names = "default";

	/* audio_clkout0/1/2/3 */
	#clock-cells = <1>;
	clock-frequency = <12288000 11289600>;

	status = "okay";

	/* update <audio_clk_b> to <cs2000> */
	clocks = <&cpg CPG_MOD 1005>,
		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
		 <&audio_clk_a>, <&cs2000>,
		 <&audio_clk_c>,
		 <&cpg CPG_MOD 922>;
};

&rpc {
	/* Left disabled.  To be enabled by firmware when unlocked. */

	flash@0 {
		compatible = "cypress,hyperflash", "cfi-flash";
		reg = <0>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			bootparam@0 {
				reg = <0x00000000 0x040000>;
				read-only;
			};
			bl2@40000 {
				reg = <0x00040000 0x140000>;
				read-only;
			};
			cert_header_sa6@180000 {
				reg = <0x00180000 0x040000>;
				read-only;
			};
			bl31@1c0000 {
				reg = <0x001c0000 0x040000>;
				read-only;
			};
			tee@200000 {
				reg = <0x00200000 0x440000>;
				read-only;
			};
			uboot@640000 {
				reg = <0x00640000 0x100000>;
				read-only;
			};
			dtb@740000 {
				reg = <0x00740000 0x080000>;
			};
			kernel@7c0000 {
				reg = <0x007c0000 0x1400000>;
			};
			user@1bc0000 {
				reg = <0x01bc0000 0x2440000>;
			};
		};
	};
};

&rwdt {
	timeout-sec = <60>;
	status = "okay";
};

&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scif_clk {
	clock-frequency = <14745600>;
};

&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

&sdhi2 {
	/* used for on-board 8bit eMMC */
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	bus-width = <8>;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	no-sd;
	no-sdio;
	non-removable;
	full-pwr-cycle-in-suspend;
	status = "okay";
};

&ssi1 {
	shared-pin;
};

&usb2_phy1 {
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";

	status = "okay";
};


/*
 * For sound-test.
 *
 * We can switch Audio Card for testing
 *
 * #include "ulcb-simple-audio-card.dtsi"
 * #include "ulcb-simple-audio-card-mix+split.dtsi"
 * #include "ulcb-audio-graph-card.dtsi"
 * #include "ulcb-audio-graph-card-mix+split.dtsi"
 * #include "ulcb-audio-graph-card2-mix+split.dtsi"
 */
#include "ulcb-audio-graph-card2.dtsi"
Commit	Line	Data
cba59c25	1	// SPDX-License-Identifier: GPL-2.0
253ed045 GU	2	/*
	3	* Device Tree Source for the R-Car Gen3 ULCB board
	4	*
	5	* Copyright (C) 2016 Renesas Electronics Corp.
	6	* Copyright (C) 2016 Cogent Embedded, Inc.
253ed045 GU	7	*/
	8
	9	#include <dt-bindings/gpio/gpio.h>
	10	#include <dt-bindings/input/input.h>
	11
	12	/ {
	13	model = "Renesas R-Car Gen3 ULCB board";
	14
	15	aliases {
59c14853 WS	16	i2c0 = &i2c0;
	17	i2c1 = &i2c1;
	18	i2c2 = &i2c2;
	19	i2c3 = &i2c3;
	20	i2c4 = &i2c4;
	21	i2c5 = &i2c5;
	22	i2c6 = &i2c6;
	23	i2c7 = &i2c_dvfs;
253ed045 GU	24	serial0 = &scif2;
253ed045 GU	25	ethernet0 = &avb;
d765a4f3 YS	26	mmc0 = &sdhi2;
d765a4f3 YS	27	mmc1 = &sdhi0;
253ed045 GU	28	};
	29
	30	chosen {
b31b43c9	31	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
253ed045 GU	32	stdout-path = "serial0:115200n8";
	33	};
	34
	35	audio_clkout: audio-clkout {
	36	/*
	37	* This is same as <&rcar_sound 0>
	38	* but needed to avoid cs2000/rcar_sound probe dead-lock
	39	*/
	40	compatible = "fixed-clock";
	41	#clock-cells = <0>;
822cecb1	42	clock-frequency = <12288000>;
253ed045 GU	43	};
253ed045 GU	44
9f9b22e8 VB	45	hdmi0-out {
	46	compatible = "hdmi-connector";
	47	type = "a";
	48
	49	port {
	50	hdmi0_con: endpoint {
9fd8bbef	51	remote-endpoint = <&rcar_dw_hdmi0_out>;
9f9b22e8 VB	52	};
	53	};
	54	};
	55
253ed045 GU	56	keyboard {
	57	compatible = "gpio-keys";
	58
	59	key-1 {
	60	linux,code = <KEY_1>;
	61	label = "SW3";
	62	wakeup-source;
	63	debounce-interval = <20>;
	64	gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
	65	};
	66	};
	67
	68	leds {
	69	compatible = "gpio-leds";
	70
	71	led5 {
	72	gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
	73	};
	74	led6 {
	75	gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
	76	};
	77	};
	78
5cf12ac9	79	reg_1p8v: regulator-1p8v {
253ed045 GU	80	compatible = "regulator-fixed";
	81	regulator-name = "fixed-1.8V";
	82	regulator-min-microvolt = <1800000>;
	83	regulator-max-microvolt = <1800000>;
	84	regulator-boot-on;
	85	regulator-always-on;
	86	};
	87
5cf12ac9	88	reg_3p3v: regulator-3p3v {
253ed045 GU	89	compatible = "regulator-fixed";
	90	regulator-name = "fixed-3.3V";
	91	regulator-min-microvolt = <3300000>;
	92	regulator-max-microvolt = <3300000>;
	93	regulator-boot-on;
	94	regulator-always-on;
	95	};
	96
253ed045 GU	97	vcc_sdhi0: regulator-vcc-sdhi0 {
	98	compatible = "regulator-fixed";
	99
	100	regulator-name = "SDHI0 Vcc";
	101	regulator-min-microvolt = <3300000>;
	102	regulator-max-microvolt = <3300000>;
	103
	104	gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
	105	enable-active-high;
	106	};
	107
	108	vccq_sdhi0: regulator-vccq-sdhi0 {
	109	compatible = "regulator-gpio";
	110
	111	regulator-name = "SDHI0 VccQ";
	112	regulator-min-microvolt = <1800000>;
	113	regulator-max-microvolt = <3300000>;
	114
	115	gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
	116	gpios-states = <1>;
36f06212	117	states = <3300000 1>, <1800000 0>;
253ed045 GU	118	};
	119
	120	x12_clk: x12 {
	121	compatible = "fixed-clock";
	122	#clock-cells = <0>;
	123	clock-frequency = <24576000>;
	124	};
8cb6898c VB	125
	126	x23_clk: x23-clock {
	127	compatible = "fixed-clock";
	128	#clock-cells = <0>;
	129	clock-frequency = <25000000>;
	130	};
253ed045 GU	131	};
253ed045 GU	132
2b35ca2f YG	133	&a57_0 {
	134	cpu-supply = <&dvfs>;
	135	};
	136
253ed045 GU	137	&audio_clk_a {
	138	clock-frequency = <22579200>;
	139	};
	140
	141	&avb {
	142	pinctrl-0 = <&avb_pins>;
	143	pinctrl-names = "default";
253ed045	144	phy-handle = <&phy0>;
9b810181	145	tx-internal-delay-ps = <2000>;
253ed045 GU	146	status = "okay";
	147
	148	phy0: ethernet-phy@0 {
722d55f3 GU	149	compatible = "ethernet-phy-id0022.1622",
722d55f3 GU	150	"ethernet-phy-ieee802.3-c22";
253ed045 GU	151	rxc-skew-ps = <1500>;
	152	reg = <0>;
	153	interrupt-parent = <&gpio2>;
	154	interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
ef4a3bc8	155	reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
253ed045 GU	156	};
	157	};
	158
7da2ed12 LP	159	&du {
	160	status = "okay";
	161	};
	162
253ed045 GU	163	&ehci1 {
	164	status = "okay";
	165	};
	166
	167	&extal_clk {
	168	clock-frequency = <16666666>;
	169	};
	170
	171	&extalr_clk {
	172	clock-frequency = <32768>;
	173	};
	174
2a50b40f VB	175	&hdmi0 {
	176	status = "okay";
	177
	178	ports {
	179	port@1 {
	180	reg = <1>;
	181	rcar_dw_hdmi0_out: endpoint {
	182	remote-endpoint = <&hdmi0_con>;
	183	};
	184	};
c693b210 KM	185	port@2 {
c693b210 KM	186	reg = <2>;
c693b210	187	};
2a50b40f VB	188	};
	189	};
	190
253ed045 GU	191	&i2c2 {
	192	pinctrl-0 = <&i2c2_pins>;
	193	pinctrl-names = "default";
	194
	195	status = "okay";
	196
	197	clock-frequency = <100000>;
	198
	199	ak4613: codec@10 {
	200	compatible = "asahi-kasei,ak4613";
253ed045 GU	201	reg = <0x10>;
	202	clocks = <&rcar_sound 3>;
	203
	204	asahi-kasei,in1-single-end;
	205	asahi-kasei,in2-single-end;
	206	asahi-kasei,out1-single-end;
	207	asahi-kasei,out2-single-end;
	208	asahi-kasei,out3-single-end;
	209	asahi-kasei,out4-single-end;
	210	asahi-kasei,out5-single-end;
	211	asahi-kasei,out6-single-end;
	212	};
	213
	214	cs2000: clk-multiplier@4f {
	215	#clock-cells = <0>;
	216	compatible = "cirrus,cs2000-cp";
	217	reg = <0x4f>;
	218	clocks = <&audio_clkout>, <&x12_clk>;
	219	clock-names = "clk_in", "ref_clk";
	220
	221	assigned-clocks = <&cs2000>;
	222	assigned-clock-rates = <24576000>; /* 1/1 divide */
	223	};
	224	};
	225
476b2e4f VB	226	&i2c4 {
	227	status = "okay";
	228
	229	clock-frequency = <400000>;
8cb6898c VB	230
	231	versaclock5: clock-generator@6a {
	232	compatible = "idt,5p49v5925";
	233	reg = <0x6a>;
	234	#clock-cells = <1>;
	235	clocks = <&x23_clk>;
	236	clock-names = "xin";
	237	};
476b2e4f VB	238	};
476b2e4f VB	239
a4fedb3a VB	240	&i2c_dvfs {
a4fedb3a VB	241	status = "okay";
786f3cc0	242
11a33f81 WS	243	clock-frequency = <400000>;
11a33f81 WS	244
786f3cc0 GU	245	pmic: pmic@30 {
	246	pinctrl-0 = <&irq0_pins>;
	247	pinctrl-names = "default";
	248
	249	compatible = "rohm,bd9571mwv";
	250	reg = <0x30>;
	251	interrupt-parent = <&intc_ex>;
	252	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	253	interrupt-controller;
	254	#interrupt-cells = <2>;
	255	gpio-controller;
	256	#gpio-cells = <2>;
1c81a633 GU	257	rohm,ddr-backup-power = <0xf>;
1c81a633 GU	258	rohm,rstbmode-pulse;
786f3cc0 GU	259
	260	regulators {
	261	dvfs: dvfs {
	262	regulator-name = "dvfs";
	263	regulator-min-microvolt = <750000>;
	264	regulator-max-microvolt = <1030000>;
	265	regulator-boot-on;
	266	regulator-always-on;
	267	};
	268	};
	269	};
d5136914 GU	270
	271	eeprom@50 {
	272	compatible = "rohm,br24t01", "atmel,24c01";
	273	reg = <0x50>;
	274	pagesize = <8>;
	275	};
a4fedb3a VB	276	};
a4fedb3a VB	277
253ed045 GU	278	&ohci1 {
	279	status = "okay";
	280	};
	281
	282	&pfc {
	283	pinctrl-0 = <&scif_clk_pins>;
	284	pinctrl-names = "default";
	285
	286	avb_pins: avb {
133ace3f	287	mux {
1518ad14	288	groups = "avb_link", "avb_mdio", "avb_mii";
133ace3f SH	289	function = "avb";
	290	};
	291
1518ad14 GU	292	pins_mdio {
1518ad14 GU	293	groups = "avb_mdio";
133ace3f SH	294	drive-strength = <24>;
	295	};
	296
	297	pins_mii_tx {
	298	pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
	299	"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
	300	drive-strength = <12>;
	301	};
253ed045 GU	302	};
	303
	304	i2c2_pins: i2c2 {
	305	groups = "i2c2_a";
	306	function = "i2c2";
	307	};
	308
786f3cc0 GU	309	irq0_pins: irq0 {
	310	groups = "intc_ex_irq0";
	311	function = "intc_ex";
	312	};
	313
253ed045 GU	314	scif2_pins: scif2 {
	315	groups = "scif2_data_a";
	316	function = "scif2";
	317	};
	318
	319	scif_clk_pins: scif_clk {
	320	groups = "scif_clk_a";
	321	function = "scif_clk";
	322	};
	323
	324	sdhi0_pins: sd0 {
	325	groups = "sdhi0_data4", "sdhi0_ctrl";
	326	function = "sdhi0";
	327	power-source = <3300>;
	328	};
	329
	330	sdhi0_pins_uhs: sd0_uhs {
	331	groups = "sdhi0_data4", "sdhi0_ctrl";
	332	function = "sdhi0";
	333	power-source = <1800>;
	334	};
	335
	336	sdhi2_pins: sd2 {
c5dd01aa	337	groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
253ed045 GU	338	function = "sdhi2";
	339	power-source = <1800>;
	340	};
	341
	342	sound_pins: sound {
	343	groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
	344	function = "ssi";
	345	};
	346
	347	sound_clk_pins: sound-clk {
	348	groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
	349	"audio_clkout_a", "audio_clkout3_a";
	350	function = "audio_clk";
	351	};
	352
	353	usb1_pins: usb1 {
	354	groups = "usb1";
	355	function = "usb1";
	356	};
	357	};
	358
	359	&rcar_sound {
3ebf49c0	360	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
253ed045 GU	361	pinctrl-names = "default";
253ed045 GU	362
253ed045 GU	363	/* audio_clkout0/1/2/3 */
253ed045 GU	364	#clock-cells = <1>;
2752660a	365	clock-frequency = <12288000 11289600>;
253ed045 GU	366
	367	status = "okay";
	368
	369	/* update <audio_clk_b> to <cs2000> */
	370	clocks = <&cpg CPG_MOD 1005>,
	371	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	372	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	373	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	374	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	375	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	376	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	377	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	378	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	379	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	380	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	381	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	382	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	383	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	384	<&audio_clk_a>, <&cs2000>,
	385	<&audio_clk_c>,
f2802c62	386	<&cpg CPG_MOD 922>;
253ed045 GU	387	};
253ed045 GU	388
79e903fb GU	389	&rpc {
	390	/* Left disabled. To be enabled by firmware when unlocked. */
	391
	392	flash@0 {
	393	compatible = "cypress,hyperflash", "cfi-flash";
	394	reg = <0>;
	395
	396	partitions {
	397	compatible = "fixed-partitions";
	398	#address-cells = <1>;
	399	#size-cells = <1>;
	400
	401	bootparam@0 {
	402	reg = <0x00000000 0x040000>;
	403	read-only;
	404	};
	405	bl2@40000 {
	406	reg = <0x00040000 0x140000>;
	407	read-only;
	408	};
	409	cert_header_sa6@180000 {
	410	reg = <0x00180000 0x040000>;
	411	read-only;
	412	};
	413	bl31@1c0000 {
	414	reg = <0x001c0000 0x040000>;
	415	read-only;
	416	};
	417	tee@200000 {
	418	reg = <0x00200000 0x440000>;
	419	read-only;
	420	};
	421	uboot@640000 {
	422	reg = <0x00640000 0x100000>;
	423	read-only;
	424	};
	425	dtb@740000 {
	426	reg = <0x00740000 0x080000>;
	427	};
	428	kernel@7c0000 {
	429	reg = <0x007c0000 0x1400000>;
	430	};
	431	user@1bc0000 {
	432	reg = <0x01bc0000 0x2440000>;
	433	};
	434	};
	435	};
	436	};
	437
0a05b3d7 YK	438	&rwdt {
	439	timeout-sec = <60>;
	440	status = "okay";
	441	};
	442
253ed045 GU	443	&scif2 {
	444	pinctrl-0 = <&scif2_pins>;
	445	pinctrl-names = "default";
	446
	447	status = "okay";
	448	};
	449
	450	&scif_clk {
	451	clock-frequency = <14745600>;
	452	};
	453
	454	&sdhi0 {
	455	pinctrl-0 = <&sdhi0_pins>;
	456	pinctrl-1 = <&sdhi0_pins_uhs>;
	457	pinctrl-names = "default", "state_uhs";
	458
	459	vmmc-supply = <&vcc_sdhi0>;
	460	vqmmc-supply = <&vccq_sdhi0>;
	461	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
	462	bus-width = <4>;
	463	sd-uhs-sdr50;
9bc03b57	464	sd-uhs-sdr104;
253ed045 GU	465	status = "okay";
	466	};
	467
	468	&sdhi2 {
	469	/* used for on-board 8bit eMMC */
	470	pinctrl-0 = <&sdhi2_pins>;
5f65328d	471	pinctrl-1 = <&sdhi2_pins>;
253ed045 GU	472	pinctrl-names = "default", "state_uhs";
	473
	474	vmmc-supply = <&reg_3p3v>;
	475	vqmmc-supply = <&reg_1p8v>;
	476	bus-width = <8>;
	477	mmc-hs200-1_8v;
e536d27e	478	mmc-hs400-1_8v;
d68c9edf WS	479	no-sd;
d68c9edf WS	480	no-sdio;
253ed045	481	non-removable;
992d7a8b	482	full-pwr-cycle-in-suspend;
253ed045 GU	483	status = "okay";
	484	};
	485
	486	&ssi1 {
	487	shared-pin;
	488	};
	489
	490	&usb2_phy1 {
	491	pinctrl-0 = <&usb1_pins>;
	492	pinctrl-names = "default";
	493
	494	status = "okay";
	495	};
3e2db2c2	496
c9d95cf0	497
3e2db2c2 KM	498	/*
	499	* For sound-test.
	500	*
	501	* We can switch Audio Card for testing
	502	*
62661f3b	503	* #include "ulcb-simple-audio-card.dtsi"
c9d95cf0	504	* #include "ulcb-simple-audio-card-mix+split.dtsi"
3e2db2c2	505	* #include "ulcb-audio-graph-card.dtsi"
ccb26ac5	506	* #include "ulcb-audio-graph-card-mix+split.dtsi"
15ec87e0	507	* #include "ulcb-audio-graph-card2-mix+split.dtsi"
3e2db2c2 KM	508	*/
3e2db2c2 KM	509	#include "ulcb-audio-graph-card2.dtsi"