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ce0c63b6 BD |
1 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
2 | /* | |
3 | * Device Tree Source for the RZ/G2LC SMARC pincontrol parts | |
4 | * | |
5 | * Copyright (C) 2021 Renesas Electronics Corp. | |
6 | */ | |
7 | ||
8 | #include <dt-bindings/gpio/gpio.h> | |
9 | #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> | |
10 | ||
11 | &pinctrl { | |
12 | pinctrl-0 = <&sound_clk_pins>; | |
13 | pinctrl-names = "default"; | |
14 | ||
46da6327 BD |
15 | #if SW_SCIF_CAN |
16 | /* SW8 should be at position 2->1 */ | |
17 | can1_pins: can1 { | |
18 | pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */ | |
19 | <RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */ | |
20 | }; | |
21 | #endif | |
22 | ||
46da6327 BD |
23 | #if SW_RSPI_CAN |
24 | /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ | |
48d8ee5b | 25 | can1-stb-hog { |
46da6327 BD |
26 | gpio-hog; |
27 | gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>; | |
28 | output-low; | |
29 | line-name = "can1_stb"; | |
30 | }; | |
31 | ||
32 | can1_pins: can1 { | |
33 | pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */ | |
34 | <RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */ | |
35 | }; | |
36 | #endif | |
37 | ||
4fa1edc8 BD |
38 | i2c0_pins: i2c0 { |
39 | pins = "RIIC0_SDA", "RIIC0_SCL"; | |
40 | input-enable; | |
41 | }; | |
42 | ||
43 | i2c1_pins: i2c1 { | |
44 | pins = "RIIC1_SDA", "RIIC1_SCL"; | |
45 | input-enable; | |
46 | }; | |
47 | ||
48 | i2c2_pins: i2c2 { | |
49 | pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */ | |
50 | <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */ | |
51 | }; | |
52 | ||
5d7de61f BD |
53 | mtu3_pins: mtu3 { |
54 | mtu3-pwm { | |
55 | pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */ | |
56 | <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */ | |
57 | <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */ | |
58 | <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */ | |
59 | }; | |
60 | }; | |
61 | ||
a2b642d8 BD |
62 | scif0_pins: scif0 { |
63 | pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ | |
64 | <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ | |
65 | }; | |
66 | ||
67 | scif1_pins: scif1 { | |
68 | pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ | |
69 | <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ | |
70 | <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ | |
71 | <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ | |
72 | }; | |
73 | ||
81a27b1f BD |
74 | sd1-pwr-en-hog { |
75 | gpio-hog; | |
76 | gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; | |
77 | output-high; | |
78 | line-name = "sd1_pwr_en"; | |
79 | }; | |
80 | ||
81 | sdhi1_pins: sd1 { | |
82 | sd1_data { | |
83 | pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; | |
84 | power-source = <3300>; | |
85 | }; | |
86 | ||
87 | sd1_ctrl { | |
88 | pins = "SD1_CLK", "SD1_CMD"; | |
89 | power-source = <3300>; | |
90 | }; | |
91 | ||
92 | sd1_mux { | |
93 | pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ | |
94 | }; | |
95 | }; | |
96 | ||
97 | sdhi1_pins_uhs: sd1_uhs { | |
98 | sd1_data_uhs { | |
99 | pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; | |
100 | power-source = <1800>; | |
101 | }; | |
102 | ||
103 | sd1_ctrl_uhs { | |
104 | pins = "SD1_CLK", "SD1_CMD"; | |
105 | power-source = <1800>; | |
106 | }; | |
107 | ||
108 | sd1_mux_uhs { | |
109 | pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ | |
110 | }; | |
111 | }; | |
112 | ||
ce0c63b6 BD |
113 | sound_clk_pins: sound_clk { |
114 | pins = "AUDIO_CLK1", "AUDIO_CLK2"; | |
115 | input-enable; | |
116 | }; | |
1889f479 | 117 | |
061ba41c BD |
118 | spi1_pins: spi1 { |
119 | pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */ | |
120 | <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */ | |
121 | <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */ | |
122 | <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */ | |
123 | }; | |
124 | ||
4eb6a6bb BD |
125 | ssi0_pins: ssi0 { |
126 | pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */ | |
127 | <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */ | |
128 | <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */ | |
129 | <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */ | |
130 | }; | |
131 | ||
1889f479 BD |
132 | usb0_pins: usb0 { |
133 | pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */ | |
134 | <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */ | |
135 | <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */ | |
136 | }; | |
137 | ||
138 | usb1_pins: usb1 { | |
139 | pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */ | |
140 | <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */ | |
141 | }; | |
ce0c63b6 BD |
142 | }; |
143 |