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93be50c7 KM |
1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
2 | /* | |
3 | * Device Tree Source for the R-Car S4 Starter Kit board | |
4 | * | |
5 | * Copyright (C) 2023 Renesas Electronics Corp. | |
6 | */ | |
7 | ||
8 | /dts-v1/; | |
9 | #include <dt-bindings/gpio/gpio.h> | |
10 | #include "r8a779f4.dtsi" | |
11 | ||
12 | / { | |
13 | model = "R-Car S4 Starter Kit board"; | |
14 | compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0"; | |
15 | ||
16 | aliases { | |
17 | serial0 = &hscif0; | |
18 | serial1 = &hscif1; | |
19 | eth0 = &rswitch; | |
20 | }; | |
21 | ||
22 | chosen { | |
23 | bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; | |
24 | stdout-path = "serial0:921600n8"; | |
25 | }; | |
26 | ||
27 | memory@48000000 { | |
28 | device_type = "memory"; | |
29 | /* first 128MB is reserved for secure area. */ | |
30 | /* The last 512MB is reserved for CR. */ | |
31 | reg = <0x0 0x48000000 0x0 0x58000000>; | |
32 | }; | |
33 | ||
34 | memory@480000000 { | |
35 | device_type = "memory"; | |
36 | reg = <0x4 0x80000000 0x0 0x80000000>; | |
37 | }; | |
38 | ||
39 | vcc_sdhi: regulator-vcc-sdhi { | |
40 | compatible = "regulator-fixed"; | |
41 | regulator-name = "SDHI Vcc"; | |
42 | regulator-min-microvolt = <3300000>; | |
43 | regulator-max-microvolt = <3300000>; | |
44 | gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; | |
45 | enable-active-high; | |
46 | }; | |
47 | }; | |
48 | ||
49 | ð_serdes { | |
50 | status = "okay"; | |
51 | }; | |
52 | ||
53 | &extal_clk { | |
54 | clock-frequency = <20000000>; | |
55 | }; | |
56 | ||
57 | &extalr_clk { | |
58 | clock-frequency = <32768>; | |
59 | }; | |
60 | ||
61 | &hscif0 { | |
62 | pinctrl-0 = <&hscif0_pins>; | |
63 | pinctrl-names = "default"; | |
64 | ||
65 | uart-has-rtscts; | |
66 | status = "okay"; | |
67 | }; | |
68 | ||
69 | &hscif1 { | |
70 | pinctrl-0 = <&hscif1_pins>; | |
71 | pinctrl-names = "default"; | |
72 | ||
73 | uart-has-rtscts; | |
74 | status = "okay"; | |
75 | }; | |
76 | ||
77 | &i2c2 { | |
78 | pinctrl-0 = <&i2c2_pins>; | |
79 | pinctrl-names = "default"; | |
80 | ||
81 | status = "okay"; | |
82 | clock-frequency = <400000>; | |
83 | }; | |
84 | ||
85 | &i2c4 { | |
86 | pinctrl-0 = <&i2c4_pins>; | |
87 | pinctrl-names = "default"; | |
88 | ||
89 | status = "okay"; | |
90 | clock-frequency = <400000>; | |
91 | }; | |
92 | ||
93 | &i2c5 { | |
94 | pinctrl-0 = <&i2c5_pins>; | |
95 | pinctrl-names = "default"; | |
96 | ||
97 | status = "okay"; | |
98 | clock-frequency = <400000>; | |
99 | ||
100 | eeprom@50 { | |
101 | compatible = "st,24c16", "atmel,24c16"; | |
102 | reg = <0x50>; | |
103 | pagesize = <16>; | |
104 | }; | |
105 | }; | |
106 | ||
107 | &mmc0 { | |
108 | pinctrl-0 = <&sd_pins>; | |
109 | pinctrl-names = "default"; | |
110 | ||
111 | vmmc-supply = <&vcc_sdhi>; | |
112 | cd-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; | |
113 | bus-width = <4>; | |
114 | status = "okay"; | |
115 | }; | |
116 | ||
117 | &pfc { | |
118 | pinctrl-0 = <&scif_clk_pins>; | |
119 | pinctrl-names = "default"; | |
120 | ||
121 | hscif0_pins: hscif0 { | |
122 | groups = "hscif0_data", "hscif0_ctrl"; | |
123 | function = "hscif0"; | |
124 | }; | |
125 | ||
126 | hscif1_pins: hscif1 { | |
127 | groups = "hscif1_data", "hscif1_ctrl"; | |
128 | function = "hscif1"; | |
129 | }; | |
130 | ||
131 | i2c2_pins: i2c2 { | |
132 | groups = "i2c2"; | |
133 | function = "i2c2"; | |
134 | }; | |
135 | ||
136 | i2c4_pins: i2c4 { | |
137 | groups = "i2c4"; | |
138 | function = "i2c4"; | |
139 | }; | |
140 | ||
141 | i2c5_pins: i2c5 { | |
142 | groups = "i2c5"; | |
143 | function = "i2c5"; | |
144 | }; | |
145 | ||
146 | scif_clk_pins: scif_clk { | |
147 | groups = "scif_clk"; | |
148 | function = "scif_clk"; | |
149 | }; | |
150 | ||
151 | sd_pins: sd { | |
152 | groups = "mmc_data4", "mmc_ctrl"; | |
153 | function = "mmc"; | |
154 | power-source = <3300>; | |
155 | }; | |
156 | ||
157 | tsn0_pins: tsn0 { | |
158 | groups = "tsn0_mdio_b", "tsn0_link_b"; | |
159 | function = "tsn0"; | |
160 | drive-strength = <18>; | |
161 | power-source = <3300>; | |
162 | }; | |
163 | ||
164 | tsn1_pins: tsn1 { | |
165 | groups = "tsn1_mdio_b", "tsn1_link_b"; | |
166 | function = "tsn1"; | |
167 | drive-strength = <18>; | |
168 | power-source = <3300>; | |
169 | }; | |
170 | }; | |
171 | ||
172 | &rswitch { | |
173 | pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>; | |
174 | pinctrl-names = "default"; | |
175 | status = "okay"; | |
176 | ||
177 | ethernet-ports { | |
178 | #address-cells = <1>; | |
179 | #size-cells = <0>; | |
180 | ||
181 | port@0 { | |
182 | reg = <0>; | |
183 | phy-handle = <&ic99>; | |
184 | phy-mode = "sgmii"; | |
185 | phys = <ð_serdes 0>; | |
186 | ||
187 | mdio { | |
188 | #address-cells = <1>; | |
189 | #size-cells = <0>; | |
190 | ||
191 | ic99: ethernet-phy@1 { | |
192 | reg = <1>; | |
193 | compatible = "ethernet-phy-ieee802.3-c45"; | |
194 | interrupt-parent = <&gpio3>; | |
195 | interrupts = <10 IRQ_TYPE_LEVEL_LOW>; | |
196 | }; | |
197 | }; | |
198 | }; | |
199 | ||
200 | port@1 { | |
201 | reg = <1>; | |
202 | phy-handle = <&ic102>; | |
203 | phy-mode = "sgmii"; | |
204 | phys = <ð_serdes 1>; | |
205 | ||
206 | mdio { | |
207 | #address-cells = <1>; | |
208 | #size-cells = <0>; | |
209 | ||
210 | ic102: ethernet-phy@2 { | |
211 | reg = <2>; | |
212 | compatible = "ethernet-phy-ieee802.3-c45"; | |
213 | interrupt-parent = <&gpio3>; | |
214 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; | |
215 | }; | |
216 | }; | |
217 | }; | |
218 | ||
219 | port@2 { | |
220 | status = "disabled"; | |
221 | }; | |
222 | }; | |
223 | }; | |
224 | ||
225 | &rwdt { | |
226 | timeout-sec = <60>; | |
227 | status = "okay"; | |
228 | }; | |
229 | ||
230 | &scif_clk { | |
231 | clock-frequency = <24000000>; | |
232 | }; | |
233 | ||
234 | &ufs { | |
235 | status = "okay"; | |
236 | }; | |
237 | ||
238 | &ufs30_clk { | |
239 | clock-frequency = <38400000>; | |
240 | }; |