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arm64: dts: renesas: r8a77995: Enable IPMMU devices
[linux-2.6-block.git] / arch / arm64 / boot / dts / renesas / r8a77995.dtsi
CommitLineData
d917e0b2
GU		 1/*
2 * Device Tree Source for the r8a77995 SoC
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2017 Glider bvba
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
5889ded1 12#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
d917e0b2 13#include <dt-bindings/interrupt-controller/arm-gic.h>
9066b042 14#include <dt-bindings/power/r8a77995-sysc.h>
d917e0b2
GU		 15
16/ {
17 compatible = "renesas,r8a77995";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21559e2b
YK		 21 /* External CAN clock - to be overridden by boards that provide it */
22 can_clk: can {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
d917e0b2
GU		 26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 a53_0: cpu@0 {
33 compatible = "arm,cortex-a53", "arm,armv8";
34 reg = <0x0>;
35 device_type = "cpu";
9066b042 36 power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
d917e0b2
GU		 37 next-level-cache = <&L2_CA53>;
38 enable-method = "psci";
39 };
40
41 L2_CA53: cache-controller-1 {
42 compatible = "cache";
9066b042 43 power-domains = <&sysc R8A77995_PD_CA53_SCU>;
d917e0b2
GU		 44 cache-unified;
45 cache-level = <2>;
46 };
47 };
48
49 extal_clk: extal {
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 /* This value must be overridden by the board */
53 clock-frequency = <0>;
54 };
55
f320eead
SH		 56 pmu_a53 {
57 compatible = "arm,cortex-a53-pmu";
58 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
59 };
60
21559e2b
YK		 61 psci {
62 compatible = "arm,psci-1.0", "arm,psci-0.2";
63 method = "smc";
64 };
65
d917e0b2
GU		 66 scif_clk: scif {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <0>;
70 };
71
72 soc {
73 compatible = "simple-bus";
74 interrupt-parent = <&gic>;
75 #address-cells = <2>;
76 #size-cells = <2>;
77 ranges;
78
d917e0b2
GU		 79 rwdt: watchdog@e6020000 {
80 compatible = "renesas,r8a77995-wdt",
81 "renesas,rcar-gen3-wdt";
82 reg = <0 0xe6020000 0 0x0c>;
83 clocks = <&cpg CPG_MOD 402>;
9066b042 84 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
d917e0b2
GU		 85 resets = <&cpg 402>;
86 status = "disabled";
87 };
88
7c55747f
YK		 89 gpio0: gpio@e6050000 {
90 compatible = "renesas,gpio-r8a77995",
91 "renesas,rcar-gen3-gpio",
92 "renesas,gpio-rcar";
93 reg = <0 0xe6050000 0 0x50>;
94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
95 #gpio-cells = <2>;
96 gpio-controller;
97 gpio-ranges = <&pfc 0 0 9>;
98 #interrupt-cells = <2>;
99 interrupt-controller;
100 clocks = <&cpg CPG_MOD 912>;
101 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
102 resets = <&cpg 912>;
a3901e73
SH		 103 };
104
7c55747f
YK		 105 gpio1: gpio@e6051000 {
106 compatible = "renesas,gpio-r8a77995",
107 "renesas,rcar-gen3-gpio",
108 "renesas,gpio-rcar";
109 reg = <0 0xe6051000 0 0x50>;
110 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
111 #gpio-cells = <2>;
112 gpio-controller;
113 gpio-ranges = <&pfc 0 32 32>;
114 #interrupt-cells = <2>;
115 interrupt-controller;
116 clocks = <&cpg CPG_MOD 911>;
117 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
118 resets = <&cpg 911>;
a3901e73
SH		 119 };
120
7c55747f
YK		 121 gpio2: gpio@e6052000 {
122 compatible = "renesas,gpio-r8a77995",
123 "renesas,rcar-gen3-gpio",
124 "renesas,gpio-rcar";
125 reg = <0 0xe6052000 0 0x50>;
126 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
127 #gpio-cells = <2>;
128 gpio-controller;
129 gpio-ranges = <&pfc 0 64 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 clocks = <&cpg CPG_MOD 910>;
133 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
134 resets = <&cpg 910>;
a3901e73
SH		 135 };
136
7c55747f
YK		 137 gpio3: gpio@e6053000 {
138 compatible = "renesas,gpio-r8a77995",
139 "renesas,rcar-gen3-gpio",
140 "renesas,gpio-rcar";
141 reg = <0 0xe6053000 0 0x50>;
142 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
143 #gpio-cells = <2>;
144 gpio-controller;
145 gpio-ranges = <&pfc 0 96 10>;
146 #interrupt-cells = <2>;
147 interrupt-controller;
148 clocks = <&cpg CPG_MOD 909>;
149 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
150 resets = <&cpg 909>;
a3901e73
SH		 151 };
152
7c55747f
YK		 153 gpio4: gpio@e6054000 {
154 compatible = "renesas,gpio-r8a77995",
155 "renesas,rcar-gen3-gpio",
156 "renesas,gpio-rcar";
157 reg = <0 0xe6054000 0 0x50>;
158 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
159 #gpio-cells = <2>;
160 gpio-controller;
161 gpio-ranges = <&pfc 0 128 32>;
162 #interrupt-cells = <2>;
163 interrupt-controller;
164 clocks = <&cpg CPG_MOD 908>;
165 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
166 resets = <&cpg 908>;
a3901e73
SH		 167 };
168
7c55747f
YK		 169 gpio5: gpio@e6055000 {
170 compatible = "renesas,gpio-r8a77995",
171 "renesas,rcar-gen3-gpio",
172 "renesas,gpio-rcar";
173 reg = <0 0xe6055000 0 0x50>;
174 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
175 #gpio-cells = <2>;
176 gpio-controller;
177 gpio-ranges = <&pfc 0 160 21>;
178 #interrupt-cells = <2>;
179 interrupt-controller;
180 clocks = <&cpg CPG_MOD 907>;
181 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
182 resets = <&cpg 907>;
a3901e73
SH		 183 };
184
7c55747f
YK		 185 gpio6: gpio@e6055400 {
186 compatible = "renesas,gpio-r8a77995",
187 "renesas,rcar-gen3-gpio",
188 "renesas,gpio-rcar";
189 reg = <0 0xe6055400 0 0x50>;
190 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
191 #gpio-cells = <2>;
192 gpio-controller;
193 gpio-ranges = <&pfc 0 192 14>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 clocks = <&cpg CPG_MOD 906>;
197 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
198 resets = <&cpg 906>;
a3901e73
SH		 199 };
200
7c55747f
YK		 201 pfc: pin-controller@e6060000 {
202 compatible = "renesas,pfc-r8a77995";
203 reg = <0 0xe6060000 0 0x508>;
a3901e73
SH		 204 };
205
d917e0b2
GU		 206 cpg: clock-controller@e6150000 {
207 compatible = "renesas,r8a77995-cpg-mssr";
208 reg = <0 0xe6150000 0 0x1000>;
209 clocks = <&extal_clk>;
210 clock-names = "extal";
211 #clock-cells = <2>;
212 #power-domain-cells = <0>;
213 #reset-cells = <1>;
214 };
215
216 rst: reset-controller@e6160000 {
217 compatible = "renesas,r8a77995-rst";
218 reg = <0 0xe6160000 0 0x0200>;
219 };
220
d917e0b2
GU		 221 sysc: system-controller@e6180000 {
222 compatible = "renesas,r8a77995-sysc";
223 reg = <0 0xe6180000 0 0x0400>;
224 #power-domain-cells = <1>;
225 };
226
eb5a5078
GU		 227 intc_ex: interrupt-controller@e61c0000 {
228 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 reg = <0 0xe61c0000 0 0x200>;
232 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
233 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
234 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
235 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
236 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
237 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cpg CPG_MOD 407>;
239 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
240 resets = <&cpg 407>;
241 };
242
7c55747f
YK		 243 i2c0: i2c@e6500000 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 compatible = "renesas,i2c-r8a77995",
247 "renesas,rcar-gen3-i2c";
248 reg = <0 0xe6500000 0 0x40>;
249 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cpg CPG_MOD 931>;
251 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
252 resets = <&cpg 931>;
253 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
254 <&dmac2 0x91>, <&dmac2 0x90>;
255 dma-names = "tx", "rx", "tx", "rx";
256 i2c-scl-internal-delay-ns = <6>;
257 status = "disabled";
258 };
259
260 i2c1: i2c@e6508000 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "renesas,i2c-r8a77995",
264 "renesas,rcar-gen3-i2c";
265 reg = <0 0xe6508000 0 0x40>;
266 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&cpg CPG_MOD 930>;
268 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
269 resets = <&cpg 930>;
270 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
271 <&dmac2 0x93>, <&dmac2 0x92>;
272 dma-names = "tx", "rx", "tx", "rx";
273 i2c-scl-internal-delay-ns = <6>;
274 status = "disabled";
275 };
276
277 i2c2: i2c@e6510000 {
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "renesas,i2c-r8a77995",
281 "renesas,rcar-gen3-i2c";
282 reg = <0 0xe6510000 0 0x40>;
283 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cpg CPG_MOD 929>;
285 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
286 resets = <&cpg 929>;
287 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
288 <&dmac2 0x95>, <&dmac2 0x94>;
289 dma-names = "tx", "rx", "tx", "rx";
290 i2c-scl-internal-delay-ns = <6>;
291 status = "disabled";
292 };
293
294 i2c3: i2c@e66d0000 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "renesas,i2c-r8a77995",
298 "renesas,rcar-gen3-i2c";
299 reg = <0 0xe66d0000 0 0x40>;
300 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&cpg CPG_MOD 928>;
302 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
303 resets = <&cpg 928>;
304 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
305 dma-names = "tx", "rx";
306 i2c-scl-internal-delay-ns = <6>;
307 status = "disabled";
308 };
309
310 canfd: can@e66c0000 {
311 compatible = "renesas,r8a77995-canfd",
312 "renesas,rcar-gen3-canfd";
313 reg = <0 0xe66c0000 0 0x8000>;
314 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&cpg CPG_MOD 914>,
317 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
318 <&can_clk>;
319 clock-names = "fck", "canfd", "can_clk";
320 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
321 assigned-clock-rates = <40000000>;
322 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
323 resets = <&cpg 914>;
324 status = "disabled";
325
326 channel0 {
327 status = "disabled";
328 };
329
330 channel1 {
331 status = "disabled";
332 };
333 };
334
942164ca
UH		 335 dmac0: dma-controller@e6700000 {
336 compatible = "renesas,dmac-r8a77995",
337 "renesas,rcar-dmac";
338 reg = <0 0xe6700000 0 0x10000>;
339 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-names = "error",
349 "ch0", "ch1", "ch2", "ch3",
350 "ch4", "ch5", "ch6", "ch7";
351 clocks = <&cpg CPG_MOD 219>;
352 clock-names = "fck";
353 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
354 resets = <&cpg 219>;
355 #dma-cells = <1>;
356 dma-channels = <8>;
357 };
358
359 dmac1: dma-controller@e7300000 {
360 compatible = "renesas,dmac-r8a77995",
361 "renesas,rcar-dmac";
362 reg = <0 0xe7300000 0 0x10000>;
363 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
372 interrupt-names = "error",
373 "ch0", "ch1", "ch2", "ch3",
374 "ch4", "ch5", "ch6", "ch7";
375 clocks = <&cpg CPG_MOD 218>;
376 clock-names = "fck";
377 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
378 resets = <&cpg 218>;
379 #dma-cells = <1>;
380 dma-channels = <8>;
381 };
382
383 dmac2: dma-controller@e7310000 {
384 compatible = "renesas,dmac-r8a77995",
385 "renesas,rcar-dmac";
386 reg = <0 0xe7310000 0 0x10000>;
387 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-names = "error",
397 "ch0", "ch1", "ch2", "ch3",
398 "ch4", "ch5", "ch6", "ch7";
399 clocks = <&cpg CPG_MOD 217>;
400 clock-names = "fck";
401 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
402 resets = <&cpg 217>;
403 #dma-cells = <1>;
404 dma-channels = <8>;
405 };
406
7c55747f
YK		 407 ipmmu_ds0: mmu@e6740000 {
408 compatible = "renesas,ipmmu-r8a77995";
409 reg = <0 0xe6740000 0 0x1000>;
410 renesas,ipmmu-main = <&ipmmu_mm 0>;
411 #iommu-cells = <1>;
11581f5d
YS		 412 };
413
7c55747f
YK		 414 ipmmu_ds1: mmu@e7740000 {
415 compatible = "renesas,ipmmu-r8a77995";
416 reg = <0 0xe7740000 0 0x1000>;
417 renesas,ipmmu-main = <&ipmmu_mm 1>;
418 #iommu-cells = <1>;
11581f5d
YS		 419 };
420
7c55747f
YK		 421 ipmmu_hc: mmu@e6570000 {
422 compatible = "renesas,ipmmu-r8a77995";
423 reg = <0 0xe6570000 0 0x1000>;
424 renesas,ipmmu-main = <&ipmmu_mm 2>;
425 #iommu-cells = <1>;
11581f5d
YS		 426 };
427
7c55747f
YK		 428 ipmmu_mm: mmu@e67b0000 {
429 compatible = "renesas,ipmmu-r8a77995";
430 reg = <0 0xe67b0000 0 0x1000>;
431 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
433 #iommu-cells = <1>;
11581f5d
YS		 434 };
435
7c55747f
YK		 436 ipmmu_mp: mmu@ec670000 {
437 compatible = "renesas,ipmmu-r8a77995";
438 reg = <0 0xec670000 0 0x1000>;
439 renesas,ipmmu-main = <&ipmmu_mm 4>;
440 #iommu-cells = <1>;
11581f5d
YS		 441 };
442
7c55747f
YK		 443 ipmmu_pv0: mmu@fd800000 {
444 compatible = "renesas,ipmmu-r8a77995";
445 reg = <0 0xfd800000 0 0x1000>;
446 renesas,ipmmu-main = <&ipmmu_mm 6>;
447 #iommu-cells = <1>;
11581f5d
YS		 448 };
449
7c55747f
YK		 450 ipmmu_rt: mmu@ffc80000 {
451 compatible = "renesas,ipmmu-r8a77995";
452 reg = <0 0xffc80000 0 0x1000>;
453 renesas,ipmmu-main = <&ipmmu_mm 10>;
454 #iommu-cells = <1>;
acaa51a3
UH		 455 };
456
7c55747f
YK		 457 ipmmu_vc0: mmu@fe6b0000 {
458 compatible = "renesas,ipmmu-r8a77995";
459 reg = <0 0xfe6b0000 0 0x1000>;
460 renesas,ipmmu-main = <&ipmmu_mm 12>;
461 #iommu-cells = <1>;
acaa51a3
UH		 462 };
463
7c55747f
YK		 464 ipmmu_vi0: mmu@febd0000 {
465 compatible = "renesas,ipmmu-r8a77995";
466 reg = <0 0xfebd0000 0 0x1000>;
467 renesas,ipmmu-main = <&ipmmu_mm 14>;
468 #iommu-cells = <1>;
7c55747f 469 };
e2767b0f 470
7c55747f
YK		 471 ipmmu_vp0: mmu@fe990000 {
472 compatible = "renesas,ipmmu-r8a77995";
473 reg = <0 0xfe990000 0 0x1000>;
474 renesas,ipmmu-main = <&ipmmu_mm 16>;
475 #iommu-cells = <1>;
e2767b0f
UH		 476 };
477
f9ba0c4c
YS		 478 avb: ethernet@e6800000 {
479 compatible = "renesas,etheravb-r8a77995",
480 "renesas,etheravb-rcar-gen3";
fa3d4c67 481 reg = <0 0xe6800000 0 0x800>;
f9ba0c4c
YS		 482 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
507 interrupt-names = "ch0", "ch1", "ch2", "ch3",
508 "ch4", "ch5", "ch6", "ch7",
509 "ch8", "ch9", "ch10", "ch11",
510 "ch12", "ch13", "ch14", "ch15",
511 "ch16", "ch17", "ch18", "ch19",
512 "ch20", "ch21", "ch22", "ch23",
513 "ch24";
514 clocks = <&cpg CPG_MOD 812>;
515 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
516 resets = <&cpg 812>;
e9131e54 517 phy-mode = "rgmii";
2ebdfea2 518 iommus = <&ipmmu_ds0 16>;
f9ba0c4c
YS		 519 #address-cells = <1>;
520 #size-cells = <0>;
521 status = "disabled";
522 };
523
7c55747f
YK		 524 can0: can@e6c30000 {
525 compatible = "renesas,can-r8a77995",
526 "renesas,rcar-gen3-can";
527 reg = <0 0xe6c30000 0 0x1000>;
528 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&cpg CPG_MOD 916>,
530 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
531 <&can_clk>;
532 clock-names = "clkp1", "clkp2", "can_clk";
533 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
534 assigned-clock-rates = <40000000>;
ffcd060f 535 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
7c55747f 536 resets = <&cpg 916>;
ffcd060f
UH		 537 status = "disabled";
538 };
539
7c55747f
YK		 540 can1: can@e6c38000 {
541 compatible = "renesas,can-r8a77995",
542 "renesas,rcar-gen3-can";
543 reg = <0 0xe6c38000 0 0x1000>;
544 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&cpg CPG_MOD 915>,
546 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
547 <&can_clk>;
548 clock-names = "clkp1", "clkp2", "can_clk";
549 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
550 assigned-clock-rates = <40000000>;
ffcd060f 551 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
7c55747f 552 resets = <&cpg 915>;
ffcd060f
UH		 553 status = "disabled";
554 };
555
d40a4347
YS		 556 pwm0: pwm@e6e30000 {
557 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
558 reg = <0 0xe6e30000 0 0x8>;
559 #pwm-cells = <2>;
560 clocks = <&cpg CPG_MOD 523>;
561 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
562 resets = <&cpg 523>;
563 status = "disabled";
564 };
565
566 pwm1: pwm@e6e31000 {
567 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
568 reg = <0 0xe6e31000 0 0x8>;
569 #pwm-cells = <2>;
570 clocks = <&cpg CPG_MOD 523>;
571 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
572 resets = <&cpg 523>;
573 status = "disabled";
574 };
575
576 pwm2: pwm@e6e32000 {
577 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
578 reg = <0 0xe6e32000 0 0x8>;
579 #pwm-cells = <2>;
580 clocks = <&cpg CPG_MOD 523>;
581 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
582 resets = <&cpg 523>;
583 status = "disabled";
584 };
585
586 pwm3: pwm@e6e33000 {
587 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
588 reg = <0 0xe6e33000 0 0x8>;
589 #pwm-cells = <2>;
590 clocks = <&cpg CPG_MOD 523>;
591 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
592 resets = <&cpg 523>;
593 status = "disabled";
594 };
595
7c55747f
YK		 596 scif2: serial@e6e88000 {
597 compatible = "renesas,scif-r8a77995",
598 "renesas,rcar-gen3-scif", "renesas,scif";
599 reg = <0 0xe6e88000 0 64>;
600 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cpg CPG_MOD 310>,
602 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
603 <&scif_clk>;
604 clock-names = "fck", "brg_int", "scif_clk";
605 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
606 <&dmac2 0x13>, <&dmac2 0x12>;
607 dma-names = "tx", "rx", "tx", "rx";
83f18749 608 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
7c55747f 609 resets = <&cpg 310>;
83f18749
UH		 610 status = "disabled";
611 };
612
7c55747f
YK		 613 ohci0: usb@ee080000 {
614 compatible = "generic-ohci";
615 reg = <0 0xee080000 0 0x100>;
423254a1
YS		 616 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cpg CPG_MOD 703>;
618 phys = <&usb2_phy0>;
619 phy-names = "usb";
423254a1
YS		 620 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
621 resets = <&cpg 703>;
622 status = "disabled";
623 };
624
7c55747f
YK		 625 ehci0: usb@ee080100 {
626 compatible = "generic-ehci";
627 reg = <0 0xee080100 0 0x100>;
423254a1
YS		 628 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cpg CPG_MOD 703>;
630 phys = <&usb2_phy0>;
631 phy-names = "usb";
7c55747f 632 companion = <&ohci0>;
423254a1
YS		 633 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
634 resets = <&cpg 703>;
635 status = "disabled";
636 };
637
a0ea7fe8
YS		 638 usb2_phy0: usb-phy@ee080200 {
639 compatible = "renesas,usb2-phy-r8a77995",
640 "renesas,rcar-gen3-usb2-phy";
641 reg = <0 0xee080200 0 0x700>;
642 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cpg CPG_MOD 703>;
644 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
645 resets = <&cpg 703>;
646 #phy-cells = <0>;
647 status = "disabled";
648 };
d7ef367b 649
7c55747f
YK		 650 sdhi2: sd@ee140000 {
651 compatible = "renesas,sdhi-r8a77995",
652 "renesas,rcar-gen3-sdhi";
653 reg = <0 0xee140000 0 0x2000>;
654 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 312>;
656 max-frequency = <200000000>;
657 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
658 resets = <&cpg 312>;
659 status = "disabled";
660 };
661
662 gic: interrupt-controller@f1010000 {
663 compatible = "arm,gic-400";
664 #interrupt-cells = <3>;
665 #address-cells = <0>;
666 interrupt-controller;
667 reg = <0x0 0xf1010000 0 0x1000>,
668 <0x0 0xf1020000 0 0x20000>,
669 <0x0 0xf1040000 0 0x20000>,
670 <0x0 0xf1060000 0 0x20000>;
671 interrupts = <GIC_PPI 9
672 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
673 clocks = <&cpg CPG_MOD 408>;
674 clock-names = "clk";
675 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
676 resets = <&cpg 408>;
677 };
678
295952a1
KB		 679 vspbs: vsp@fe960000 {
680 compatible = "renesas,vsp2";
681 reg = <0 0xfe960000 0 0x8000>;
682 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cpg CPG_MOD 627>;
684 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
685 resets = <&cpg 627>;
686 renesas,fcp = <&fcpvb0>;
687 };
688
295952a1
KB		 689 vspd0: vsp@fea20000 {
690 compatible = "renesas,vsp2";
691 reg = <0 0xfea20000 0 0x8000>;
692 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&cpg CPG_MOD 623>;
694 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
695 resets = <&cpg 623>;
696 renesas,fcp = <&fcpvd0>;
697 };
698
295952a1
KB		 699 vspd1: vsp@fea28000 {
700 compatible = "renesas,vsp2";
701 reg = <0 0xfea28000 0 0x8000>;
702 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&cpg CPG_MOD 622>;
704 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
705 resets = <&cpg 622>;
706 renesas,fcp = <&fcpvd1>;
707 };
708
7c55747f
YK		 709 fcpvb0: fcp@fe96f000 {
710 compatible = "renesas,fcpv";
711 reg = <0 0xfe96f000 0 0x200>;
712 clocks = <&cpg CPG_MOD 607>;
713 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
714 resets = <&cpg 607>;
715 iommus = <&ipmmu_vp0 5>;
716 };
717
718 fcpvd0: fcp@fea27000 {
719 compatible = "renesas,fcpv";
720 reg = <0 0xfea27000 0 0x200>;
721 clocks = <&cpg CPG_MOD 603>;
722 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
723 resets = <&cpg 603>;
724 iommus = <&ipmmu_vi0 8>;
725 };
726
d7ef367b
KB		 727 fcpvd1: fcp@fea2f000 {
728 compatible = "renesas,fcpv";
729 reg = <0 0xfea2f000 0 0x200>;
730 clocks = <&cpg CPG_MOD 602>;
731 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
732 resets = <&cpg 602>;
733 iommus = <&ipmmu_vi0 9>;
734 };
18f1a773
KB		 735
736 du: display@feb00000 {
737 compatible = "renesas,du-r8a77995";
738 reg = <0 0xfeb00000 0 0x80000>;
739 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cpg CPG_MOD 724>,
742 <&cpg CPG_MOD 723>;
743 clock-names = "du.0", "du.1";
744 vsps = <&vspd0 0 &vspd1 0>;
745 status = "disabled";
746
747 ports {
748 #address-cells = <1>;
749 #size-cells = <0>;
750
751 port@0 {
752 reg = <0>;
753 du_out_rgb: endpoint {
754 };
755 };
756
757 port@1 {
758 reg = <1>;
759 du_out_lvds0: endpoint {
760 };
761 };
762
763 port@2 {
764 reg = <2>;
765 du_out_lvds1: endpoint {
766 };
767 };
768 };
769 };
7c55747f
YK		 770
771 prr: chipid@fff00044 {
772 compatible = "renesas,prr";
773 reg = <0 0xfff00044 0 4>;
774 };
d917e0b2 775 };
f320eead
SH		 776
777 timer {
778 compatible = "arm,armv8-timer";
779 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
780 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
781 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
782 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
783 };
d917e0b2 784};
Linux 6.x block layer and io_uring tree(s)