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arm64: dts: renesas: r8a77990: Add INTC-EX device node
[linux-2.6-block.git] / arch / arm64 / boot / dts / renesas / r8a77990.dtsi
CommitLineData
f37a7767
YS		 1/* SPDX-License-Identifier: GPL-2.0 */
2/*
e18a31a7 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
f37a7767
YS		 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
83e7d2ec 8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
f37a7767 9#include <dt-bindings/interrupt-controller/arm-gic.h>
55697cbb 10#include <dt-bindings/power/r8a77990-sysc.h>
f37a7767
YS		 11
12/ {
13 compatible = "renesas,r8a77990";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
bc011dfa
TK		 17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 i2c4 = &i2c4;
23 i2c5 = &i2c5;
24 i2c6 = &i2c6;
25 i2c7 = &i2c7;
26 };
27
f37a7767
YS		 28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
f37a7767
YS		 32 a53_0: cpu@0 {
33 compatible = "arm,cortex-a53", "arm,armv8";
7085f5d9 34 reg = <0>;
f37a7767 35 device_type = "cpu";
83e7d2ec 36 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
f37a7767
YS		 37 next-level-cache = <&L2_CA53>;
38 enable-method = "psci";
39 };
40
7085f5d9
GU		 41 a53_1: cpu@1 {
42 compatible = "arm,cortex-a53", "arm,armv8";
43 reg = <1>;
44 device_type = "cpu";
83e7d2ec 45 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
7085f5d9
GU		 46 next-level-cache = <&L2_CA53>;
47 enable-method = "psci";
48 };
49
de1eb23c 50 L2_CA53: cache-controller-0 {
f37a7767 51 compatible = "cache";
83e7d2ec 52 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
f37a7767
YS		 53 cache-unified;
54 cache-level = <2>;
55 };
56 };
57
58 extal_clk: extal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 /* This value must be overridden by the board */
62 clock-frequency = <0>;
63 };
64
65 pmu_a53 {
66 compatible = "arm,cortex-a53-pmu";
7085f5d9
GU		 67 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
68 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&a53_0>, <&a53_1>;
f37a7767
YS		 70 };
71
72 psci {
bc26b8f4 73 compatible = "arm,psci-1.0", "arm,psci-0.2";
f37a7767
YS		 74 method = "smc";
75 };
76
103db9b5
TK		 77 /* External SCIF clock - to be overridden by boards that provide it */
78 scif_clk: scif {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <0>;
82 };
83
f37a7767
YS		 84 soc: soc {
85 compatible = "simple-bus";
86 interrupt-parent = <&gic>;
87 #address-cells = <2>;
88 #size-cells = <2>;
89 ranges;
90
eb614d94
TK		 91 rwdt: watchdog@e6020000 {
92 compatible = "renesas,r8a77990-wdt",
93 "renesas,rcar-gen3-wdt";
94 reg = <0 0xe6020000 0 0x0c>;
95 clocks = <&cpg CPG_MOD 402>;
83e7d2ec 96 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
eb614d94
TK		 97 resets = <&cpg 402>;
98 status = "disabled";
99 };
100
0d292de1
YS		 101 gpio0: gpio@e6050000 {
102 compatible = "renesas,gpio-r8a77990",
103 "renesas,rcar-gen3-gpio";
104 reg = <0 0xe6050000 0 0x50>;
105 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
106 #gpio-cells = <2>;
107 gpio-controller;
108 gpio-ranges = <&pfc 0 0 18>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 clocks = <&cpg CPG_MOD 912>;
83e7d2ec 112 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
0d292de1
YS		 113 resets = <&cpg 912>;
114 };
115
116 gpio1: gpio@e6051000 {
117 compatible = "renesas,gpio-r8a77990",
118 "renesas,rcar-gen3-gpio";
119 reg = <0 0xe6051000 0 0x50>;
120 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 gpio-ranges = <&pfc 0 32 23>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&cpg CPG_MOD 911>;
83e7d2ec 127 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
0d292de1
YS		 128 resets = <&cpg 911>;
129 };
130
131 gpio2: gpio@e6052000 {
132 compatible = "renesas,gpio-r8a77990",
133 "renesas,rcar-gen3-gpio";
134 reg = <0 0xe6052000 0 0x50>;
135 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
136 #gpio-cells = <2>;
137 gpio-controller;
138 gpio-ranges = <&pfc 0 64 26>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&cpg CPG_MOD 910>;
83e7d2ec 142 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
0d292de1
YS		 143 resets = <&cpg 910>;
144 };
145
146 gpio3: gpio@e6053000 {
147 compatible = "renesas,gpio-r8a77990",
148 "renesas,rcar-gen3-gpio";
149 reg = <0 0xe6053000 0 0x50>;
150 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
151 #gpio-cells = <2>;
152 gpio-controller;
153 gpio-ranges = <&pfc 0 96 16>;
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 clocks = <&cpg CPG_MOD 909>;
83e7d2ec 157 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
0d292de1
YS		 158 resets = <&cpg 909>;
159 };
160
161 gpio4: gpio@e6054000 {
162 compatible = "renesas,gpio-r8a77990",
163 "renesas,rcar-gen3-gpio";
164 reg = <0 0xe6054000 0 0x50>;
165 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 128 11>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&cpg CPG_MOD 908>;
83e7d2ec 172 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
0d292de1
YS		 173 resets = <&cpg 908>;
174 };
175
176 gpio5: gpio@e6055000 {
177 compatible = "renesas,gpio-r8a77990",
178 "renesas,rcar-gen3-gpio";
179 reg = <0 0xe6055000 0 0x50>;
180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
181 #gpio-cells = <2>;
182 gpio-controller;
183 gpio-ranges = <&pfc 0 160 20>;
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 clocks = <&cpg CPG_MOD 907>;
83e7d2ec 187 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
0d292de1
YS		 188 resets = <&cpg 907>;
189 };
190
191 gpio6: gpio@e6055400 {
192 compatible = "renesas,gpio-r8a77990",
193 "renesas,rcar-gen3-gpio";
194 reg = <0 0xe6055400 0 0x50>;
195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 192 18>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&cpg CPG_MOD 906>;
83e7d2ec 202 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
0d292de1
YS		 203 resets = <&cpg 906>;
204 };
205
bc011dfa
TK		 206 i2c0: i2c@e6500000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "renesas,i2c-r8a77990",
210 "renesas,rcar-gen3-i2c";
211 reg = <0 0xe6500000 0 0x40>;
212 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&cpg CPG_MOD 931>;
214 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
215 resets = <&cpg 931>;
216 i2c-scl-internal-delay-ns = <110>;
217 status = "disabled";
218 };
219
220 i2c1: i2c@e6508000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "renesas,i2c-r8a77990",
224 "renesas,rcar-gen3-i2c";
225 reg = <0 0xe6508000 0 0x40>;
226 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cpg CPG_MOD 930>;
228 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
229 resets = <&cpg 930>;
230 i2c-scl-internal-delay-ns = <6>;
231 status = "disabled";
232 };
233
234 i2c2: i2c@e6510000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "renesas,i2c-r8a77990",
238 "renesas,rcar-gen3-i2c";
239 reg = <0 0xe6510000 0 0x40>;
240 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cpg CPG_MOD 929>;
242 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
243 resets = <&cpg 929>;
244 i2c-scl-internal-delay-ns = <6>;
245 status = "disabled";
246 };
247
248 i2c3: i2c@e66d0000 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "renesas,i2c-r8a77990",
252 "renesas,rcar-gen3-i2c";
253 reg = <0 0xe66d0000 0 0x40>;
254 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&cpg CPG_MOD 928>;
256 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
257 resets = <&cpg 928>;
258 i2c-scl-internal-delay-ns = <110>;
259 status = "disabled";
260 };
261
262 i2c4: i2c@e66d8000 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "renesas,i2c-r8a77990",
266 "renesas,rcar-gen3-i2c";
267 reg = <0 0xe66d8000 0 0x40>;
268 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cpg CPG_MOD 927>;
270 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
271 resets = <&cpg 927>;
272 i2c-scl-internal-delay-ns = <6>;
273 status = "disabled";
274 };
275
276 i2c5: i2c@e66e0000 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "renesas,i2c-r8a77990",
280 "renesas,rcar-gen3-i2c";
281 reg = <0 0xe66e0000 0 0x40>;
282 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&cpg CPG_MOD 919>;
284 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
285 resets = <&cpg 919>;
286 i2c-scl-internal-delay-ns = <6>;
287 status = "disabled";
288 };
289
290 i2c6: i2c@e66e8000 {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "renesas,i2c-r8a77990",
294 "renesas,rcar-gen3-i2c";
295 reg = <0 0xe66e8000 0 0x40>;
296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cpg CPG_MOD 918>;
298 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
299 resets = <&cpg 918>;
300 i2c-scl-internal-delay-ns = <6>;
301 status = "disabled";
302 };
303
304 i2c7: i2c@e6690000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "renesas,i2c-r8a77990",
308 "renesas,rcar-gen3-i2c";
309 reg = <0 0xe6690000 0 0x40>;
310 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&cpg CPG_MOD 1003>;
312 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
313 resets = <&cpg 1003>;
314 i2c-scl-internal-delay-ns = <6>;
315 status = "disabled";
316 };
317
4ab0df33
YS		 318 pfc: pin-controller@e6060000 {
319 compatible = "renesas,pfc-r8a77990";
320 reg = <0 0xe6060000 0 0x508>;
321 };
322
f37a7767
YS		 323 cpg: clock-controller@e6150000 {
324 compatible = "renesas,r8a77990-cpg-mssr";
325 reg = <0 0xe6150000 0 0x1000>;
326 clocks = <&extal_clk>;
327 clock-names = "extal";
328 #clock-cells = <2>;
329 #power-domain-cells = <0>;
330 #reset-cells = <1>;
331 };
332
333 rst: reset-controller@e6160000 {
334 compatible = "renesas,r8a77990-rst";
335 reg = <0 0xe6160000 0 0x0200>;
336 };
337
338 sysc: system-controller@e6180000 {
339 compatible = "renesas,r8a77990-sysc";
340 reg = <0 0xe6180000 0 0x0400>;
341 #power-domain-cells = <1>;
342 };
343
0c793a02
TK		 344 intc_ex: interrupt-controller@e61c0000 {
345 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
346 #interrupt-cells = <2>;
347 interrupt-controller;
348 reg = <0 0xe61c0000 0 0x200>;
349 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&cpg CPG_MOD 407>;
356 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
357 resets = <&cpg 407>;
358 };
359
3943e896
TK		 360 dmac0: dma-controller@e6700000 {
361 compatible = "renesas,dmac-r8a77990",
362 "renesas,rcar-dmac";
363 reg = <0 0xe6700000 0 0x10000>;
364 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
381 interrupt-names = "error",
382 "ch0", "ch1", "ch2", "ch3",
383 "ch4", "ch5", "ch6", "ch7",
384 "ch8", "ch9", "ch10", "ch11",
385 "ch12", "ch13", "ch14", "ch15";
386 clocks = <&cpg CPG_MOD 219>;
387 clock-names = "fck";
388 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
389 resets = <&cpg 219>;
390 #dma-cells = <1>;
391 dma-channels = <16>;
f0f9f7a6
MD		 392 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
393 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
394 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
395 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
396 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
397 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
398 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
399 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
3943e896
TK		 400 };
401
402 dmac1: dma-controller@e7300000 {
403 compatible = "renesas,dmac-r8a77990",
404 "renesas,rcar-dmac";
405 reg = <0 0xe7300000 0 0x10000>;
406 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
418 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
419 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
420 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
421 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
422 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
423 interrupt-names = "error",
424 "ch0", "ch1", "ch2", "ch3",
425 "ch4", "ch5", "ch6", "ch7",
426 "ch8", "ch9", "ch10", "ch11",
427 "ch12", "ch13", "ch14", "ch15";
428 clocks = <&cpg CPG_MOD 218>;
429 clock-names = "fck";
430 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
431 resets = <&cpg 218>;
432 #dma-cells = <1>;
433 dma-channels = <16>;
f0f9f7a6
MD		 434 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
435 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
436 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
437 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
438 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
439 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
440 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
441 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
3943e896
TK		 442 };
443
444 dmac2: dma-controller@e7310000 {
445 compatible = "renesas,dmac-r8a77990",
446 "renesas,rcar-dmac";
447 reg = <0 0xe7310000 0 0x10000>;
448 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
449 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
450 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
451 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
452 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
453 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
454 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
455 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
456 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
457 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
458 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
459 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
460 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
461 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
462 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
463 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
464 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "error",
466 "ch0", "ch1", "ch2", "ch3",
467 "ch4", "ch5", "ch6", "ch7",
468 "ch8", "ch9", "ch10", "ch11",
469 "ch12", "ch13", "ch14", "ch15";
470 clocks = <&cpg CPG_MOD 217>;
471 clock-names = "fck";
472 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
473 resets = <&cpg 217>;
474 #dma-cells = <1>;
475 dma-channels = <16>;
f0f9f7a6
MD		 476 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
477 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
478 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
479 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
480 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
481 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
482 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
483 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
3943e896
TK		 484 };
485
55697cbb
MD		 486 ipmmu_ds0: mmu@e6740000 {
487 compatible = "renesas,ipmmu-r8a77990";
488 reg = <0 0xe6740000 0 0x1000>;
489 renesas,ipmmu-main = <&ipmmu_mm 0>;
490 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
491 #iommu-cells = <1>;
492 };
493
494 ipmmu_ds1: mmu@e7740000 {
495 compatible = "renesas,ipmmu-r8a77990";
496 reg = <0 0xe7740000 0 0x1000>;
497 renesas,ipmmu-main = <&ipmmu_mm 1>;
498 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
499 #iommu-cells = <1>;
500 };
501
502 ipmmu_hc: mmu@e6570000 {
503 compatible = "renesas,ipmmu-r8a77990";
504 reg = <0 0xe6570000 0 0x1000>;
505 renesas,ipmmu-main = <&ipmmu_mm 2>;
506 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
507 #iommu-cells = <1>;
508 };
509
510 ipmmu_mm: mmu@e67b0000 {
511 compatible = "renesas,ipmmu-r8a77990";
512 reg = <0 0xe67b0000 0 0x1000>;
513 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
515 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
516 #iommu-cells = <1>;
517 };
518
519 ipmmu_mp: mmu@ec670000 {
520 compatible = "renesas,ipmmu-r8a77990";
521 reg = <0 0xec670000 0 0x1000>;
522 renesas,ipmmu-main = <&ipmmu_mm 4>;
523 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
524 #iommu-cells = <1>;
525 };
526
527 ipmmu_pv0: mmu@fd800000 {
528 compatible = "renesas,ipmmu-r8a77990";
529 reg = <0 0xfd800000 0 0x1000>;
530 renesas,ipmmu-main = <&ipmmu_mm 6>;
531 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
532 #iommu-cells = <1>;
533 };
534
535 ipmmu_rt: mmu@ffc80000 {
536 compatible = "renesas,ipmmu-r8a77990";
537 reg = <0 0xffc80000 0 0x1000>;
538 renesas,ipmmu-main = <&ipmmu_mm 10>;
539 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
540 #iommu-cells = <1>;
541 };
542
543 ipmmu_vc0: mmu@fe6b0000 {
544 compatible = "renesas,ipmmu-r8a77990";
545 reg = <0 0xfe6b0000 0 0x1000>;
546 renesas,ipmmu-main = <&ipmmu_mm 12>;
547 power-domains = <&sysc R8A77990_PD_A3VC>;
548 #iommu-cells = <1>;
549 };
550
551 ipmmu_vi0: mmu@febd0000 {
552 compatible = "renesas,ipmmu-r8a77990";
553 reg = <0 0xfebd0000 0 0x1000>;
554 renesas,ipmmu-main = <&ipmmu_mm 14>;
555 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
556 #iommu-cells = <1>;
557 };
558
559 ipmmu_vp0: mmu@fe990000 {
560 compatible = "renesas,ipmmu-r8a77990";
561 reg = <0 0xfe990000 0 0x1000>;
562 renesas,ipmmu-main = <&ipmmu_mm 16>;
563 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
564 #iommu-cells = <1>;
565 };
566
913a78b5
YS		 567 avb: ethernet@e6800000 {
568 compatible = "renesas,etheravb-r8a77990",
569 "renesas,etheravb-rcar-gen3";
4b03df5f 570 reg = <0 0xe6800000 0 0x800>;
913a78b5
YS		 571 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-names = "ch0", "ch1", "ch2", "ch3",
597 "ch4", "ch5", "ch6", "ch7",
598 "ch8", "ch9", "ch10", "ch11",
599 "ch12", "ch13", "ch14", "ch15",
600 "ch16", "ch17", "ch18", "ch19",
601 "ch20", "ch21", "ch22", "ch23",
602 "ch24";
603 clocks = <&cpg CPG_MOD 812>;
83e7d2ec 604 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
913a78b5
YS		 605 resets = <&cpg 812>;
606 phy-mode = "rgmii";
607 #address-cells = <1>;
608 #size-cells = <0>;
609 status = "disabled";
610 };
611
18048556
YS		 612 pwm0: pwm@e6e30000 {
613 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
614 reg = <0 0xe6e30000 0 0x8>;
615 clocks = <&cpg CPG_MOD 523>;
616 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
617 resets = <&cpg 523>;
618 #pwm-cells = <2>;
619 status = "disabled";
620 };
621
622 pwm1: pwm@e6e31000 {
623 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
624 reg = <0 0xe6e31000 0 0x8>;
625 clocks = <&cpg CPG_MOD 523>;
626 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
627 resets = <&cpg 523>;
628 #pwm-cells = <2>;
629 status = "disabled";
630 };
631
632 pwm2: pwm@e6e32000 {
633 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
634 reg = <0 0xe6e32000 0 0x8>;
635 clocks = <&cpg CPG_MOD 523>;
636 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
637 resets = <&cpg 523>;
638 #pwm-cells = <2>;
639 status = "disabled";
640 };
641
642 pwm3: pwm@e6e33000 {
643 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
644 reg = <0 0xe6e33000 0 0x8>;
645 clocks = <&cpg CPG_MOD 523>;
646 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
647 resets = <&cpg 523>;
648 #pwm-cells = <2>;
649 status = "disabled";
650 };
651
652 pwm4: pwm@e6e34000 {
653 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
654 reg = <0 0xe6e34000 0 0x8>;
655 clocks = <&cpg CPG_MOD 523>;
656 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
657 resets = <&cpg 523>;
658 #pwm-cells = <2>;
659 status = "disabled";
660 };
661
662 pwm5: pwm@e6e35000 {
663 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
664 reg = <0 0xe6e35000 0 0x8>;
665 clocks = <&cpg CPG_MOD 523>;
666 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
667 resets = <&cpg 523>;
668 #pwm-cells = <2>;
669 status = "disabled";
670 };
671
672 pwm6: pwm@e6e36000 {
673 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
674 reg = <0 0xe6e36000 0 0x8>;
675 clocks = <&cpg CPG_MOD 523>;
676 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
677 resets = <&cpg 523>;
678 #pwm-cells = <2>;
679 status = "disabled";
680 };
681
f37a7767
YS		 682 scif2: serial@e6e88000 {
683 compatible = "renesas,scif-r8a77990",
684 "renesas,rcar-gen3-scif", "renesas,scif";
685 reg = <0 0xe6e88000 0 64>;
686 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
103db9b5
TK		 687 clocks = <&cpg CPG_MOD 310>,
688 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
689 <&scif_clk>;
690 clock-names = "fck", "brg_int", "scif_clk";
691
83e7d2ec 692 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
f37a7767
YS		 693 resets = <&cpg 310>;
694 status = "disabled";
695 };
696
4b7e3ab1
GU		 697 msiof0: spi@e6e90000 {
698 compatible = "renesas,msiof-r8a77990",
699 "renesas,rcar-gen3-msiof";
700 reg = <0 0xe6e90000 0 0x0064>;
701 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&cpg CPG_MOD 211>;
703 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
704 resets = <&cpg 211>;
705 #address-cells = <1>;
706 #size-cells = <0>;
707 status = "disabled";
708 };
709
710 msiof1: spi@e6ea0000 {
711 compatible = "renesas,msiof-r8a77990",
712 "renesas,rcar-gen3-msiof";
713 reg = <0 0xe6ea0000 0 0x0064>;
714 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cpg CPG_MOD 210>;
716 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
717 resets = <&cpg 210>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720 status = "disabled";
721 };
722
723 msiof2: spi@e6c00000 {
724 compatible = "renesas,msiof-r8a77990",
725 "renesas,rcar-gen3-msiof";
726 reg = <0 0xe6c00000 0 0x0064>;
727 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&cpg CPG_MOD 209>;
729 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
730 resets = <&cpg 209>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 status = "disabled";
734 };
735
736 msiof3: spi@e6c10000 {
737 compatible = "renesas,msiof-r8a77990",
738 "renesas,rcar-gen3-msiof";
739 reg = <0 0xe6c10000 0 0x0064>;
740 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cpg CPG_MOD 208>;
742 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
743 resets = <&cpg 208>;
744 #address-cells = <1>;
745 #size-cells = <0>;
746 status = "disabled";
747 };
748
ec70407a
KM		 749 vin4: video@e6ef4000 {
750 compatible = "renesas,vin-r8a77990";
751 reg = <0 0xe6ef4000 0 0x1000>;
752 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cpg CPG_MOD 807>;
754 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
755 resets = <&cpg 807>;
756 renesas,id = <4>;
757 status = "disabled";
758
759 ports {
760 #address-cells = <1>;
761 #size-cells = <0>;
762
763 port@1 {
764 reg = <1>;
765
766 vin4csi40: endpoint {
767 remote-endpoint= <&csi40vin4>;
768 };
769 };
770 };
771 };
772
773 vin5: video@e6ef5000 {
774 compatible = "renesas,vin-r8a77990";
775 reg = <0 0xe6ef5000 0 0x1000>;
776 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&cpg CPG_MOD 806>;
778 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
779 resets = <&cpg 806>;
780 renesas,id = <5>;
781 status = "disabled";
782
783 ports {
784 #address-cells = <1>;
785 #size-cells = <0>;
786
787 port@1 {
788 reg = <1>;
789
790 vin5csi40: endpoint {
791 remote-endpoint= <&csi40vin5>;
792 };
793 };
794 };
795 };
796
fe1bc94a
YS		 797 xhci0: usb@ee000000 {
798 compatible = "renesas,xhci-r8a77990",
799 "renesas,rcar-gen3-xhci";
800 reg = <0 0xee000000 0 0xc00>;
801 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 328>;
803 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
804 resets = <&cpg 328>;
805 status = "disabled";
806 };
807
6dd72b4d
YS		 808 ohci0: usb@ee080000 {
809 compatible = "generic-ohci";
810 reg = <0 0xee080000 0 0x100>;
811 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 812 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
6dd72b4d
YS		 813 phys = <&usb2_phy0>;
814 phy-names = "usb";
83e7d2ec 815 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
737e05bf 816 resets = <&cpg 703>, <&cpg 704>;
6dd72b4d
YS		 817 status = "disabled";
818 };
819
820 ehci0: usb@ee080100 {
821 compatible = "generic-ehci";
822 reg = <0 0xee080100 0 0x100>;
823 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 824 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
6dd72b4d
YS		 825 phys = <&usb2_phy0>;
826 phy-names = "usb";
827 companion = <&ohci0>;
83e7d2ec 828 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
737e05bf 829 resets = <&cpg 703>, <&cpg 704>;
6dd72b4d
YS		 830 status = "disabled";
831 };
832
833 usb2_phy0: usb-phy@ee080200 {
834 compatible = "renesas,usb2-phy-r8a77990",
835 "renesas,rcar-gen3-usb2-phy";
836 reg = <0 0xee080200 0 0x700>;
837 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 838 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
83e7d2ec 839 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
737e05bf 840 resets = <&cpg 703>, <&cpg 704>;
6dd72b4d
YS		 841 #phy-cells = <0>;
842 status = "disabled";
843 };
844
f37a7767
YS		 845 gic: interrupt-controller@f1010000 {
846 compatible = "arm,gic-400";
847 #interrupt-cells = <3>;
848 #address-cells = <0>;
849 interrupt-controller;
850 reg = <0x0 0xf1010000 0 0x1000>,
851 <0x0 0xf1020000 0 0x20000>,
852 <0x0 0xf1040000 0 0x20000>,
853 <0x0 0xf1060000 0 0x20000>;
854 interrupts = <GIC_PPI 9
7085f5d9 855 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
f37a7767
YS		 856 clocks = <&cpg CPG_MOD 408>;
857 clock-names = "clk";
83e7d2ec 858 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
f37a7767
YS		 859 resets = <&cpg 408>;
860 };
861
13ee2bfc
LP		 862 vspb0: vsp@fe960000 {
863 compatible = "renesas,vsp2";
864 reg = <0 0xfe960000 0 0x8000>;
865 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&cpg CPG_MOD 626>;
867 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
868 resets = <&cpg 626>;
869 renesas,fcp = <&fcpvb0>;
870 };
871
872 fcpvb0: fcp@fe96f000 {
873 compatible = "renesas,fcpv";
874 reg = <0 0xfe96f000 0 0x200>;
875 clocks = <&cpg CPG_MOD 607>;
876 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
877 resets = <&cpg 607>;
878 iommus = <&ipmmu_vp0 5>;
879 };
880
881 vspi0: vsp@fe9a0000 {
882 compatible = "renesas,vsp2";
883 reg = <0 0xfe9a0000 0 0x8000>;
884 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&cpg CPG_MOD 631>;
886 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
887 resets = <&cpg 631>;
888 renesas,fcp = <&fcpvi0>;
889 };
890
891 fcpvi0: fcp@fe9af000 {
892 compatible = "renesas,fcpv";
893 reg = <0 0xfe9af000 0 0x200>;
894 clocks = <&cpg CPG_MOD 611>;
895 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
896 resets = <&cpg 611>;
897 iommus = <&ipmmu_vp0 8>;
898 };
899
900 vspd0: vsp@fea20000 {
901 compatible = "renesas,vsp2";
902 reg = <0 0xfea20000 0 0x7000>;
903 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&cpg CPG_MOD 623>;
905 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
906 resets = <&cpg 623>;
907 renesas,fcp = <&fcpvd0>;
908 };
909
910 fcpvd0: fcp@fea27000 {
911 compatible = "renesas,fcpv";
912 reg = <0 0xfea27000 0 0x200>;
913 clocks = <&cpg CPG_MOD 603>;
914 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
915 resets = <&cpg 603>;
916 iommus = <&ipmmu_vi0 8>;
917 };
918
919 vspd1: vsp@fea28000 {
920 compatible = "renesas,vsp2";
921 reg = <0 0xfea28000 0 0x7000>;
922 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&cpg CPG_MOD 622>;
924 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
925 resets = <&cpg 622>;
926 renesas,fcp = <&fcpvd1>;
927 };
928
929 fcpvd1: fcp@fea2f000 {
930 compatible = "renesas,fcpv";
931 reg = <0 0xfea2f000 0 0x200>;
932 clocks = <&cpg CPG_MOD 602>;
933 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
934 resets = <&cpg 602>;
935 iommus = <&ipmmu_vi0 9>;
936 };
937
ec70407a
KM		 938 csi40: csi2@feaa0000 {
939 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
940 reg = <0 0xfeaa0000 0 0x10000>;
941 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&cpg CPG_MOD 716>;
943 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
944 resets = <&cpg 716>;
945 status = "disabled";
946
947 ports {
948 #address-cells = <1>;
949 #size-cells = <0>;
950
951 port@1 {
952 #address-cells = <1>;
953 #size-cells = <0>;
954
955 reg = <1>;
956
957 csi40vin4: endpoint@0 {
958 reg = <0>;
959 remote-endpoint = <&vin4csi40>;
960 };
961 csi40vin5: endpoint@1 {
962 reg = <1>;
963 remote-endpoint = <&vin5csi40>;
964 };
965 };
966 };
967 };
968
13ee2bfc
LP		 969 du: display@feb00000 {
970 compatible = "renesas,du-r8a77990";
971 reg = <0 0xfeb00000 0 0x80000>;
972 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&cpg CPG_MOD 724>,
975 <&cpg CPG_MOD 723>;
976 clock-names = "du.0", "du.1";
977 vsps = <&vspd0 0 &vspd1 0>;
978 status = "disabled";
979
980 ports {
981 #address-cells = <1>;
982 #size-cells = <0>;
983
984 port@0 {
985 reg = <0>;
986 du_out_rgb: endpoint {
987 };
988 };
989
990 port@1 {
991 reg = <1>;
992 du_out_lvds0: endpoint {
993 remote-endpoint = <&lvds0_in>;
994 };
995 };
996
997 port@2 {
998 reg = <2>;
999 du_out_lvds1: endpoint {
1000 remote-endpoint = <&lvds1_in>;
1001 };
1002 };
1003 };
1004 };
1005
1006 lvds0: lvds-encoder@feb90000 {
1007 compatible = "renesas,r8a77990-lvds";
1008 reg = <0 0xfeb90000 0 0x20>;
1009 clocks = <&cpg CPG_MOD 727>;
1010 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1011 resets = <&cpg 727>;
1012 status = "disabled";
1013
1014 ports {
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017
1018 port@0 {
1019 reg = <0>;
1020 lvds0_in: endpoint {
1021 remote-endpoint = <&du_out_lvds0>;
1022 };
1023 };
1024
1025 port@1 {
1026 reg = <1>;
1027 lvds0_out: endpoint {
1028 };
1029 };
1030 };
1031 };
1032
1033 lvds1: lvds-encoder@feb90100 {
1034 compatible = "renesas,r8a77990-lvds";
1035 reg = <0 0xfeb90100 0 0x20>;
1036 clocks = <&cpg CPG_MOD 727>;
1037 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1038 resets = <&cpg 726>;
1039 status = "disabled";
1040
1041 ports {
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044
1045 port@0 {
1046 reg = <0>;
1047 lvds1_in: endpoint {
1048 remote-endpoint = <&du_out_lvds1>;
1049 };
1050 };
1051
1052 port@1 {
1053 reg = <1>;
1054 lvds1_out: endpoint {
1055 };
1056 };
1057 };
1058 };
1059
f37a7767
YS		 1060 prr: chipid@fff00044 {
1061 compatible = "renesas,prr";
1062 reg = <0 0xfff00044 0 4>;
1063 };
1064 };
1065
1066 timer {
1067 compatible = "arm,armv8-timer";
7085f5d9
GU		 1068 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1069 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1070 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1071 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
f37a7767
YS		 1072 };
1073};
Linux 6.x block layer and io_uring tree(s)