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ARM: dts: renesas: Add fck to etheravb-rcar-gen2 clock-names list
[linux-block.git] / arch / arm64 / boot / dts / renesas / r8a77951.dtsi
CommitLineData
cba59c25 1// SPDX-License-Identifier: GPL-2.0
26a7e06d 2/*
052e99db 3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
26a7e06d
SH		 4 *
5 * Copyright (C) 2015 Renesas Electronics Corp.
26a7e06d
SH		 6 */
7
49af46b4 8#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
26a7e06d 9#include <dt-bindings/interrupt-controller/arm-gic.h>
abbecab1 10#include <dt-bindings/power/r8a7795-sysc.h>
26a7e06d 11
6fad293d
GU		 12#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
13
26a7e06d
SH		 14/ {
15 compatible = "renesas,r8a7795";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
32bc0c51
KM		 19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 i2c5 = &i2c5;
26 i2c6 = &i2c6;
d7e0d64a 27 i2c7 = &i2c_dvfs;
32bc0c51
KM		 28 };
29
82cf1d15
SH		 30 /*
31 * The external audio clocks are configured as 0 Hz fixed frequency
32 * clocks by default.
33 * Boards that provide audio clocks should override them.
34 */
35 audio_clk_a: audio_clk_a {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
39 };
40
41 audio_clk_b: audio_clk_b {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 };
46
47 audio_clk_c: audio_clk_c {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <0>;
51 };
52
53 /* External CAN clock - to be overridden by boards that provide it */
54 can_clk: can {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
58 };
59
60 cluster0_opp: opp_table0 {
61 compatible = "operating-points-v2";
62 opp-shared;
63
64 opp-500000000 {
65 opp-hz = /bits/ 64 <500000000>;
66 opp-microvolt = <830000>;
67 clock-latency-ns = <300000>;
68 };
69 opp-1000000000 {
70 opp-hz = /bits/ 64 <1000000000>;
71 opp-microvolt = <830000>;
72 clock-latency-ns = <300000>;
73 };
74 opp-1500000000 {
75 opp-hz = /bits/ 64 <1500000000>;
76 opp-microvolt = <830000>;
77 clock-latency-ns = <300000>;
78 opp-suspend;
79 };
80 opp-1600000000 {
81 opp-hz = /bits/ 64 <1600000000>;
82 opp-microvolt = <900000>;
83 clock-latency-ns = <300000>;
84 turbo-mode;
85 };
86 opp-1700000000 {
87 opp-hz = /bits/ 64 <1700000000>;
88 opp-microvolt = <960000>;
89 clock-latency-ns = <300000>;
90 turbo-mode;
91 };
92 };
93
94 cluster1_opp: opp_table1 {
95 compatible = "operating-points-v2";
96 opp-shared;
97
98 opp-800000000 {
99 opp-hz = /bits/ 64 <800000000>;
100 opp-microvolt = <820000>;
101 clock-latency-ns = <300000>;
102 };
103 opp-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <820000>;
106 clock-latency-ns = <300000>;
107 };
108 opp-1200000000 {
109 opp-hz = /bits/ 64 <1200000000>;
110 opp-microvolt = <820000>;
111 clock-latency-ns = <300000>;
112 };
113 };
114
26a7e06d
SH		 115 cpus {
116 #address-cells = <1>;
117 #size-cells = <0>;
118
b380ae0d
GI		 119 cpu-map {
120 cluster0 {
121 core0 {
122 cpu = <&a57_0>;
123 };
124 core1 {
125 cpu = <&a57_1>;
126 };
127 core2 {
128 cpu = <&a57_2>;
129 };
130 core3 {
131 cpu = <&a57_3>;
132 };
133 };
134
135 cluster1 {
136 core0 {
137 cpu = <&a53_0>;
138 };
139 core1 {
140 cpu = <&a53_1>;
141 };
142 core2 {
143 cpu = <&a53_2>;
144 };
145 core3 {
146 cpu = <&a53_3>;
147 };
148 };
149 };
150
26a7e06d 151 a57_0: cpu@0 {
31af04cd 152 compatible = "arm,cortex-a57";
26a7e06d
SH		 153 reg = <0x0>;
154 device_type = "cpu";
abbecab1 155 power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
7b337e61 156 next-level-cache = <&L2_CA57>;
12e51557 157 enable-method = "psci";
a3ba1169 158 cpu-idle-states = <&CPU_SLEEP_0>;
47e1714a 159 dynamic-power-coefficient = <854>;
fced3a97 160 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
dd149e85 161 operating-points-v2 = <&cluster0_opp>;
2250d856 162 capacity-dmips-mhz = <1024>;
0c38c54e 163 #cooling-cells = <2>;
26a7e06d 164 };
0ed1a79e
GI		 165
166 a57_1: cpu@1 {
31af04cd 167 compatible = "arm,cortex-a57";
0ed1a79e
GI		 168 reg = <0x1>;
169 device_type = "cpu";
abbecab1 170 power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
7b337e61 171 next-level-cache = <&L2_CA57>;
0ed1a79e 172 enable-method = "psci";
a3ba1169 173 cpu-idle-states = <&CPU_SLEEP_0>;
fced3a97 174 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
dd149e85 175 operating-points-v2 = <&cluster0_opp>;
2250d856 176 capacity-dmips-mhz = <1024>;
0c38c54e 177 #cooling-cells = <2>;
0ed1a79e 178 };
a5547642 179
0ed1a79e 180 a57_2: cpu@2 {
31af04cd 181 compatible = "arm,cortex-a57";
0ed1a79e
GI		 182 reg = <0x2>;
183 device_type = "cpu";
abbecab1 184 power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
7b337e61 185 next-level-cache = <&L2_CA57>;
0ed1a79e 186 enable-method = "psci";
a3ba1169 187 cpu-idle-states = <&CPU_SLEEP_0>;
fced3a97 188 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
dd149e85 189 operating-points-v2 = <&cluster0_opp>;
2250d856 190 capacity-dmips-mhz = <1024>;
0c38c54e 191 #cooling-cells = <2>;
0ed1a79e 192 };
a5547642 193
0ed1a79e 194 a57_3: cpu@3 {
31af04cd 195 compatible = "arm,cortex-a57";
0ed1a79e
GI		 196 reg = <0x3>;
197 device_type = "cpu";
abbecab1 198 power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
7b337e61 199 next-level-cache = <&L2_CA57>;
0ed1a79e 200 enable-method = "psci";
a3ba1169 201 cpu-idle-states = <&CPU_SLEEP_0>;
fced3a97 202 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
dd149e85 203 operating-points-v2 = <&cluster0_opp>;
2250d856 204 capacity-dmips-mhz = <1024>;
0c38c54e 205 #cooling-cells = <2>;
0ed1a79e 206 };
26a7e06d 207
799a75ab 208 a53_0: cpu@100 {
31af04cd 209 compatible = "arm,cortex-a53";
799a75ab
GU		 210 reg = <0x100>;
211 device_type = "cpu";
212 power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
213 next-level-cache = <&L2_CA53>;
214 enable-method = "psci";
fe87bde8 215 cpu-idle-states = <&CPU_SLEEP_1>;
15d8cd83 216 #cooling-cells = <2>;
47e1714a 217 dynamic-power-coefficient = <277>;
fced3a97 218 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
dd149e85 219 operating-points-v2 = <&cluster1_opp>;
2250d856 220 capacity-dmips-mhz = <535>;
799a75ab
GU		 221 };
222
223 a53_1: cpu@101 {
31af04cd 224 compatible = "arm,cortex-a53";
799a75ab
GU		 225 reg = <0x101>;
226 device_type = "cpu";
227 power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
228 next-level-cache = <&L2_CA53>;
229 enable-method = "psci";
fe87bde8 230 cpu-idle-states = <&CPU_SLEEP_1>;
fced3a97 231 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
dd149e85 232 operating-points-v2 = <&cluster1_opp>;
2250d856 233 capacity-dmips-mhz = <535>;
799a75ab
GU		 234 };
235
236 a53_2: cpu@102 {
31af04cd 237 compatible = "arm,cortex-a53";
799a75ab
GU		 238 reg = <0x102>;
239 device_type = "cpu";
240 power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
241 next-level-cache = <&L2_CA53>;
242 enable-method = "psci";
fe87bde8 243 cpu-idle-states = <&CPU_SLEEP_1>;
fced3a97 244 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
dd149e85 245 operating-points-v2 = <&cluster1_opp>;
2250d856 246 capacity-dmips-mhz = <535>;
799a75ab
GU		 247 };
248
249 a53_3: cpu@103 {
31af04cd 250 compatible = "arm,cortex-a53";
799a75ab
GU		 251 reg = <0x103>;
252 device_type = "cpu";
253 power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
254 next-level-cache = <&L2_CA53>;
255 enable-method = "psci";
fe87bde8 256 cpu-idle-states = <&CPU_SLEEP_1>;
fced3a97 257 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
dd149e85 258 operating-points-v2 = <&cluster1_opp>;
2250d856 259 capacity-dmips-mhz = <535>;
799a75ab
GU		 260 };
261
d165856d 262 L2_CA57: cache-controller-0 {
6f7bf82c 263 compatible = "cache";
6f7bf82c
GU		 264 power-domains = <&sysc R8A7795_PD_CA57_SCU>;
265 cache-unified;
266 cache-level = <2>;
267 };
7b337e61 268
d165856d 269 L2_CA53: cache-controller-1 {
6f7bf82c 270 compatible = "cache";
6f7bf82c
GU		 271 power-domains = <&sysc R8A7795_PD_CA53_SCU>;
272 cache-unified;
273 cache-level = <2>;
274 };
a3ba1169
KN		 275
276 idle-states {
277 entry-method = "psci";
278
279 CPU_SLEEP_0: cpu-sleep-0 {
280 compatible = "arm,idle-state";
281 arm,psci-suspend-param = <0x0010000>;
282 local-timer-stop;
283 entry-latency-us = <400>;
284 exit-latency-us = <500>;
285 min-residency-us = <4000>;
286 };
fe87bde8
DP		 287
288 CPU_SLEEP_1: cpu-sleep-1 {
289 compatible = "arm,idle-state";
290 arm,psci-suspend-param = <0x0010000>;
291 local-timer-stop;
292 entry-latency-us = <700>;
293 exit-latency-us = <700>;
294 min-residency-us = <5000>;
295 };
a3ba1169 296 };
8e1c3aa3
GU		 297 };
298
26a7e06d
SH		 299 extal_clk: extal {
300 compatible = "fixed-clock";
301 #clock-cells = <0>;
302 /* This value must be overridden by the board */
303 clock-frequency = <0>;
304 };
305
306 extalr_clk: extalr {
307 compatible = "fixed-clock";
308 #clock-cells = <0>;
309 /* This value must be overridden by the board */
310 clock-frequency = <0>;
311 };
312
9251024a
PE		 313 /* External PCIe clock - can be overridden by the board */
314 pcie_bus_clk: pcie_bus {
315 compatible = "fixed-clock";
316 #clock-cells = <0>;
9f33a8a9 317 clock-frequency = <0>;
9251024a
PE		 318 };
319
4f5dc77b
SH		 320 pmu_a53 {
321 compatible = "arm,cortex-a53-pmu";
322 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
323 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
324 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
325 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
326 interrupt-affinity = <&a53_0>,
327 <&a53_1>,
328 <&a53_2>,
329 <&a53_3>;
330 };
331
82cf1d15
SH		 332 pmu_a57 {
333 compatible = "arm,cortex-a57-pmu";
334 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
399ec3ff 335 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
82cf1d15
SH		 336 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
337 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-affinity = <&a57_0>,
339 <&a57_1>,
340 <&a57_2>,
341 <&a57_3>;
342 };
343
86af5aac
SH		 344 psci {
345 compatible = "arm,psci-1.0", "arm,psci-0.2";
346 method = "smc";
347 };
348
1c6c924a
SH		 349 /* External SCIF clock - to be overridden by boards that provide it */
350 scif_clk: scif {
351 compatible = "fixed-clock";
352 #clock-cells = <0>;
353 clock-frequency = <0>;
354 };
355
291e0c49 356 soc: soc {
26a7e06d
SH		 357 compatible = "simple-bus";
358 interrupt-parent = <&gic>;
0ed1a79e 359
26a7e06d
SH		 360 #address-cells = <2>;
361 #size-cells = <2>;
362 ranges;
363
0b65a9ad 364 rwdt: watchdog@e6020000 {
3114815f
WS		 365 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
366 reg = <0 0xe6020000 0 0x0c>;
367 clocks = <&cpg CPG_MOD 402>;
b186fbb6 368 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 369 resets = <&cpg 402>;
3114815f
WS		 370 status = "disabled";
371 };
372
7b08623a
TK		 373 gpio0: gpio@e6050000 {
374 compatible = "renesas,gpio-r8a7795",
d6d7037c 375 "renesas,rcar-gen3-gpio";
7b08623a
TK		 376 reg = <0 0xe6050000 0 0x50>;
377 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
378 #gpio-cells = <2>;
379 gpio-controller;
380 gpio-ranges = <&pfc 0 0 16>;
381 #interrupt-cells = <2>;
382 interrupt-controller;
383 clocks = <&cpg CPG_MOD 912>;
38dbb45e 384 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 385 resets = <&cpg 912>;
7b08623a
TK		 386 };
387
388 gpio1: gpio@e6051000 {
389 compatible = "renesas,gpio-r8a7795",
d6d7037c 390 "renesas,rcar-gen3-gpio";
7b08623a
TK		 391 reg = <0 0xe6051000 0 0x50>;
392 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
393 #gpio-cells = <2>;
394 gpio-controller;
eb14ed1a 395 gpio-ranges = <&pfc 0 32 29>;
7b08623a
TK		 396 #interrupt-cells = <2>;
397 interrupt-controller;
398 clocks = <&cpg CPG_MOD 911>;
38dbb45e 399 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 400 resets = <&cpg 911>;
7b08623a
TK		 401 };
402
403 gpio2: gpio@e6052000 {
404 compatible = "renesas,gpio-r8a7795",
d6d7037c 405 "renesas,rcar-gen3-gpio";
7b08623a
TK		 406 reg = <0 0xe6052000 0 0x50>;
407 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
408 #gpio-cells = <2>;
409 gpio-controller;
410 gpio-ranges = <&pfc 0 64 15>;
411 #interrupt-cells = <2>;
412 interrupt-controller;
413 clocks = <&cpg CPG_MOD 910>;
38dbb45e 414 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 415 resets = <&cpg 910>;
7b08623a
TK		 416 };
417
418 gpio3: gpio@e6053000 {
419 compatible = "renesas,gpio-r8a7795",
d6d7037c 420 "renesas,rcar-gen3-gpio";
7b08623a
TK		 421 reg = <0 0xe6053000 0 0x50>;
422 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
423 #gpio-cells = <2>;
424 gpio-controller;
425 gpio-ranges = <&pfc 0 96 16>;
426 #interrupt-cells = <2>;
427 interrupt-controller;
428 clocks = <&cpg CPG_MOD 909>;
38dbb45e 429 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 430 resets = <&cpg 909>;
7b08623a
TK		 431 };
432
433 gpio4: gpio@e6054000 {
434 compatible = "renesas,gpio-r8a7795",
d6d7037c 435 "renesas,rcar-gen3-gpio";
7b08623a
TK		 436 reg = <0 0xe6054000 0 0x50>;
437 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
438 #gpio-cells = <2>;
439 gpio-controller;
440 gpio-ranges = <&pfc 0 128 18>;
441 #interrupt-cells = <2>;
442 interrupt-controller;
443 clocks = <&cpg CPG_MOD 908>;
38dbb45e 444 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 445 resets = <&cpg 908>;
7b08623a
TK		 446 };
447
448 gpio5: gpio@e6055000 {
449 compatible = "renesas,gpio-r8a7795",
d6d7037c 450 "renesas,rcar-gen3-gpio";
7b08623a
TK		 451 reg = <0 0xe6055000 0 0x50>;
452 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
453 #gpio-cells = <2>;
454 gpio-controller;
455 gpio-ranges = <&pfc 0 160 26>;
456 #interrupt-cells = <2>;
457 interrupt-controller;
458 clocks = <&cpg CPG_MOD 907>;
38dbb45e 459 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 460 resets = <&cpg 907>;
7b08623a
TK		 461 };
462
463 gpio6: gpio@e6055400 {
464 compatible = "renesas,gpio-r8a7795",
d6d7037c 465 "renesas,rcar-gen3-gpio";
7b08623a
TK		 466 reg = <0 0xe6055400 0 0x50>;
467 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
468 #gpio-cells = <2>;
469 gpio-controller;
470 gpio-ranges = <&pfc 0 192 32>;
471 #interrupt-cells = <2>;
472 interrupt-controller;
473 clocks = <&cpg CPG_MOD 906>;
38dbb45e 474 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 475 resets = <&cpg 906>;
7b08623a
TK		 476 };
477
478 gpio7: gpio@e6055800 {
479 compatible = "renesas,gpio-r8a7795",
d6d7037c 480 "renesas,rcar-gen3-gpio";
7b08623a
TK		 481 reg = <0 0xe6055800 0 0x50>;
482 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
483 #gpio-cells = <2>;
484 gpio-controller;
485 gpio-ranges = <&pfc 0 224 4>;
486 #interrupt-cells = <2>;
487 interrupt-controller;
488 clocks = <&cpg CPG_MOD 905>;
38dbb45e 489 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 490 resets = <&cpg 905>;
7b08623a
TK		 491 };
492
a2053990 493 pfc: pinctrl@e6060000 {
e0f0bda7
SH		 494 compatible = "renesas,pfc-r8a7795";
495 reg = <0 0xe6060000 0 0x50c>;
496 };
497
720066d1
CVD		 498 cmt0: timer@e60f0000 {
499 compatible = "renesas,r8a7795-cmt0",
500 "renesas,rcar-gen3-cmt0";
501 reg = <0 0xe60f0000 0 0x1004>;
502 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cpg CPG_MOD 303>;
505 clock-names = "fck";
506 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
507 resets = <&cpg 303>;
508 status = "disabled";
509 };
510
511 cmt1: timer@e6130000 {
512 compatible = "renesas,r8a7795-cmt1",
513 "renesas,rcar-gen3-cmt1";
514 reg = <0 0xe6130000 0 0x1004>;
515 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cpg CPG_MOD 302>;
524 clock-names = "fck";
525 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
526 resets = <&cpg 302>;
527 status = "disabled";
528 };
529
530 cmt2: timer@e6140000 {
531 compatible = "renesas,r8a7795-cmt1",
532 "renesas,rcar-gen3-cmt1";
533 reg = <0 0xe6140000 0 0x1004>;
534 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 301>;
543 clock-names = "fck";
544 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
545 resets = <&cpg 301>;
546 status = "disabled";
547 };
548
549 cmt3: timer@e6148000 {
550 compatible = "renesas,r8a7795-cmt1",
551 "renesas,rcar-gen3-cmt1";
552 reg = <0 0xe6148000 0 0x1004>;
553 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&cpg CPG_MOD 300>;
562 clock-names = "fck";
563 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
564 resets = <&cpg 300>;
565 status = "disabled";
566 };
567
26a7e06d
SH		 568 cpg: clock-controller@e6150000 {
569 compatible = "renesas,r8a7795-cpg-mssr";
570 reg = <0 0xe6150000 0 0x1000>;
571 clocks = <&extal_clk>, <&extalr_clk>;
572 clock-names = "extal", "extalr";
573 #clock-cells = <2>;
574 #power-domain-cells = <0>;
dcccc132 575 #reset-cells = <1>;
26a7e06d 576 };
d9202126 577
6ddbb4ce
GU		 578 rst: reset-controller@e6160000 {
579 compatible = "renesas,r8a7795-rst";
580 reg = <0 0xe6160000 0 0x0200>;
581 };
582
abbecab1
GU		 583 sysc: system-controller@e6180000 {
584 compatible = "renesas,r8a7795-sysc";
585 reg = <0 0xe6180000 0 0x0400>;
586 #power-domain-cells = <1>;
587 };
588
e0f0bda7
SH		 589 tsc: thermal@e6198000 {
590 compatible = "renesas,r8a7795-thermal";
591 reg = <0 0xe6198000 0 0x100>,
592 <0 0xe61a0000 0 0x100>,
593 <0 0xe61a8000 0 0x100>;
594 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cpg CPG_MOD 522>;
598 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
599 resets = <&cpg 522>;
600 #thermal-sensor-cells = <1>;
9241844a
KM		 601 };
602
9c6c053c
MD		 603 intc_ex: interrupt-controller@e61c0000 {
604 compatible = "renesas,intc-ex-r8a7795", "renesas,irqc";
605 #interrupt-cells = <2>;
606 interrupt-controller;
607 reg = <0 0xe61c0000 0 0x200>;
0aab5b91
GU		 608 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
9c6c053c 614 clocks = <&cpg CPG_MOD 407>;
38dbb45e 615 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 616 resets = <&cpg 407>;
9c6c053c
MD		 617 };
618
4e4c17c6
NS		 619 tmu0: timer@e61e0000 {
620 compatible = "renesas,tmu-r8a7795", "renesas,tmu";
621 reg = <0 0xe61e0000 0 0x30>;
622 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&cpg CPG_MOD 125>;
626 clock-names = "fck";
627 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
628 resets = <&cpg 125>;
629 status = "disabled";
630 };
631
632 tmu1: timer@e6fc0000 {
633 compatible = "renesas,tmu-r8a7795", "renesas,tmu";
634 reg = <0 0xe6fc0000 0 0x30>;
635 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&cpg CPG_MOD 124>;
639 clock-names = "fck";
640 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
641 resets = <&cpg 124>;
642 status = "disabled";
643 };
644
645 tmu2: timer@e6fd0000 {
646 compatible = "renesas,tmu-r8a7795", "renesas,tmu";
647 reg = <0 0xe6fd0000 0 0x30>;
648 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&cpg CPG_MOD 123>;
652 clock-names = "fck";
653 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
654 resets = <&cpg 123>;
655 status = "disabled";
656 };
657
658 tmu3: timer@e6fe0000 {
659 compatible = "renesas,tmu-r8a7795", "renesas,tmu";
660 reg = <0 0xe6fe0000 0 0x30>;
661 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cpg CPG_MOD 122>;
665 clock-names = "fck";
666 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
667 resets = <&cpg 122>;
668 status = "disabled";
669 };
670
671 tmu4: timer@ffc00000 {
672 compatible = "renesas,tmu-r8a7795", "renesas,tmu";
673 reg = <0 0xffc00000 0 0x30>;
674 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cpg CPG_MOD 121>;
678 clock-names = "fck";
679 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
680 resets = <&cpg 121>;
681 status = "disabled";
682 };
683
e0f0bda7
SH		 684 i2c0: i2c@e6500000 {
685 #address-cells = <1>;
686 #size-cells = <0>;
687 compatible = "renesas,i2c-r8a7795",
688 "renesas,rcar-gen3-i2c";
689 reg = <0 0xe6500000 0 0x40>;
690 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 931>;
3b7e7848 692 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 693 resets = <&cpg 931>;
694 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
695 <&dmac2 0x91>, <&dmac2 0x90>;
696 dma-names = "tx", "rx", "tx", "rx";
697 i2c-scl-internal-delay-ns = <110>;
698 status = "disabled";
3b7e7848
MD		 699 };
700
e0f0bda7
SH		 701 i2c1: i2c@e6508000 {
702 #address-cells = <1>;
703 #size-cells = <0>;
704 compatible = "renesas,i2c-r8a7795",
705 "renesas,rcar-gen3-i2c";
706 reg = <0 0xe6508000 0 0x40>;
707 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&cpg CPG_MOD 930>;
3b7e7848 709 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 710 resets = <&cpg 930>;
711 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
712 <&dmac2 0x93>, <&dmac2 0x92>;
713 dma-names = "tx", "rx", "tx", "rx";
714 i2c-scl-internal-delay-ns = <6>;
3b7e7848
MD		 715 status = "disabled";
716 };
717
e0f0bda7
SH		 718 i2c2: i2c@e6510000 {
719 #address-cells = <1>;
720 #size-cells = <0>;
721 compatible = "renesas,i2c-r8a7795",
722 "renesas,rcar-gen3-i2c";
723 reg = <0 0xe6510000 0 0x40>;
724 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cpg CPG_MOD 929>;
726 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
727 resets = <&cpg 929>;
728 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
729 <&dmac2 0x95>, <&dmac2 0x94>;
730 dma-names = "tx", "rx", "tx", "rx";
731 i2c-scl-internal-delay-ns = <6>;
3b7e7848
MD		 732 status = "disabled";
733 };
734
e0f0bda7
SH		 735 i2c3: i2c@e66d0000 {
736 #address-cells = <1>;
737 #size-cells = <0>;
738 compatible = "renesas,i2c-r8a7795",
739 "renesas,rcar-gen3-i2c";
740 reg = <0 0xe66d0000 0 0x40>;
741 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&cpg CPG_MOD 928>;
743 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
744 resets = <&cpg 928>;
745 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
746 dma-names = "tx", "rx";
747 i2c-scl-internal-delay-ns = <110>;
3b7e7848
MD		 748 status = "disabled";
749 };
750
e0f0bda7
SH		 751 i2c4: i2c@e66d8000 {
752 #address-cells = <1>;
753 #size-cells = <0>;
754 compatible = "renesas,i2c-r8a7795",
755 "renesas,rcar-gen3-i2c";
756 reg = <0 0xe66d8000 0 0x40>;
757 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cpg CPG_MOD 927>;
759 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
760 resets = <&cpg 927>;
761 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
762 dma-names = "tx", "rx";
763 i2c-scl-internal-delay-ns = <110>;
3b7e7848
MD		 764 status = "disabled";
765 };
766
e0f0bda7
SH		 767 i2c5: i2c@e66e0000 {
768 #address-cells = <1>;
769 #size-cells = <0>;
770 compatible = "renesas,i2c-r8a7795",
771 "renesas,rcar-gen3-i2c";
772 reg = <0 0xe66e0000 0 0x40>;
773 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cpg CPG_MOD 919>;
3b7e7848 775 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 776 resets = <&cpg 919>;
777 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
778 dma-names = "tx", "rx";
779 i2c-scl-internal-delay-ns = <110>;
3b7e7848
MD		 780 status = "disabled";
781 };
782
e0f0bda7
SH		 783 i2c6: i2c@e66e8000 {
784 #address-cells = <1>;
785 #size-cells = <0>;
786 compatible = "renesas,i2c-r8a7795",
787 "renesas,rcar-gen3-i2c";
788 reg = <0 0xe66e8000 0 0x40>;
789 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cpg CPG_MOD 918>;
9dd660eb 791 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 792 resets = <&cpg 918>;
793 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
794 dma-names = "tx", "rx";
795 i2c-scl-internal-delay-ns = <6>;
9dd660eb
SH		 796 status = "disabled";
797 };
798
e0f0bda7
SH		 799 i2c_dvfs: i2c@e60b0000 {
800 #address-cells = <1>;
801 #size-cells = <0>;
802 compatible = "renesas,iic-r8a7795",
803 "renesas,rcar-gen3-iic",
804 "renesas,rmobile-iic";
805 reg = <0 0xe60b0000 0 0x425>;
806 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&cpg CPG_MOD 926>;
3b7e7848 808 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 809 resets = <&cpg 926>;
810 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
811 dma-names = "tx", "rx";
3b7e7848
MD		 812 status = "disabled";
813 };
814
e0f0bda7
SH		 815 hscif0: serial@e6540000 {
816 compatible = "renesas,hscif-r8a7795",
817 "renesas,rcar-gen3-hscif",
818 "renesas,hscif";
819 reg = <0 0xe6540000 0 96>;
820 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cpg CPG_MOD 520>,
822 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
823 <&scif_clk>;
824 clock-names = "fck", "brg_int", "scif_clk";
825 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
826 <&dmac2 0x31>, <&dmac2 0x30>;
827 dma-names = "tx", "rx", "tx", "rx";
3b7e7848 828 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 829 resets = <&cpg 520>;
3b7e7848
MD		 830 status = "disabled";
831 };
832
e0f0bda7
SH		 833 hscif1: serial@e6550000 {
834 compatible = "renesas,hscif-r8a7795",
835 "renesas,rcar-gen3-hscif",
836 "renesas,hscif";
837 reg = <0 0xe6550000 0 96>;
838 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&cpg CPG_MOD 519>,
840 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
841 <&scif_clk>;
842 clock-names = "fck", "brg_int", "scif_clk";
843 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
844 <&dmac2 0x33>, <&dmac2 0x32>;
845 dma-names = "tx", "rx", "tx", "rx";
846 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
847 resets = <&cpg 519>;
3b7e7848
MD		 848 status = "disabled";
849 };
850
e0f0bda7
SH		 851 hscif2: serial@e6560000 {
852 compatible = "renesas,hscif-r8a7795",
853 "renesas,rcar-gen3-hscif",
854 "renesas,hscif";
855 reg = <0 0xe6560000 0 96>;
856 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&cpg CPG_MOD 518>,
858 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
859 <&scif_clk>;
860 clock-names = "fck", "brg_int", "scif_clk";
861 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
862 <&dmac2 0x35>, <&dmac2 0x34>;
aab7a241 863 dma-names = "tx", "rx", "tx", "rx";
3b7e7848 864 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 865 resets = <&cpg 518>;
3b7e7848
MD		 866 status = "disabled";
867 };
868
e0f0bda7
SH		 869 hscif3: serial@e66a0000 {
870 compatible = "renesas,hscif-r8a7795",
871 "renesas,rcar-gen3-hscif",
872 "renesas,hscif";
873 reg = <0 0xe66a0000 0 96>;
874 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&cpg CPG_MOD 517>,
876 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
877 <&scif_clk>;
878 clock-names = "fck", "brg_int", "scif_clk";
879 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
880 dma-names = "tx", "rx";
3b7e7848 881 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 882 resets = <&cpg 517>;
3b7e7848
MD		 883 status = "disabled";
884 };
885
e0f0bda7
SH		 886 hscif4: serial@e66b0000 {
887 compatible = "renesas,hscif-r8a7795",
888 "renesas,rcar-gen3-hscif",
889 "renesas,hscif";
890 reg = <0 0xe66b0000 0 96>;
891 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&cpg CPG_MOD 516>,
893 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
894 <&scif_clk>;
895 clock-names = "fck", "brg_int", "scif_clk";
896 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
897 dma-names = "tx", "rx";
3b7e7848 898 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 899 resets = <&cpg 516>;
3b7e7848
MD		 900 status = "disabled";
901 };
902
e0f0bda7
SH		 903 hsusb: usb@e6590000 {
904 compatible = "renesas,usbhs-r8a7795",
905 "renesas,rcar-gen3-usbhs";
e67898dc 906 reg = <0 0xe6590000 0 0x200>;
e0f0bda7 907 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 908 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
e0f0bda7
SH		 909 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
910 <&usb_dmac1 0>, <&usb_dmac1 1>;
911 dma-names = "ch0", "ch1", "ch2", "ch3";
912 renesas,buswait = <11>;
7794bd7e 913 phys = <&usb2_phy0 3>;
e0f0bda7 914 phy-names = "usb";
3b7e7848 915 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
737e05bf 916 resets = <&cpg 704>, <&cpg 703>;
e0f0bda7 917 status = "disabled";
3b7e7848
MD		 918 };
919
e0f0bda7
SH		 920 hsusb3: usb@e659c000 {
921 compatible = "renesas,usbhs-r8a7795",
922 "renesas,rcar-gen3-usbhs";
e67898dc 923 reg = <0 0xe659c000 0 0x200>;
e0f0bda7 924 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 925 clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>;
e0f0bda7
SH		 926 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
927 <&usb_dmac3 0>, <&usb_dmac3 1>;
928 dma-names = "ch0", "ch1", "ch2", "ch3";
929 renesas,buswait = <11>;
7794bd7e 930 phys = <&usb2_phy3 3>;
e0f0bda7 931 phy-names = "usb";
3b7e7848 932 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
737e05bf 933 resets = <&cpg 705>, <&cpg 700>;
e0f0bda7 934 status = "disabled";
3b7e7848
MD		 935 };
936
e0f0bda7
SH		 937 usb_dmac0: dma-controller@e65a0000 {
938 compatible = "renesas,r8a7795-usb-dmac",
939 "renesas,usb-dmac";
940 reg = <0 0xe65a0000 0 0x100>;
0aab5b91
GU		 941 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
e0f0bda7
SH		 943 interrupt-names = "ch0", "ch1";
944 clocks = <&cpg CPG_MOD 330>;
3b7e7848 945 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 946 resets = <&cpg 330>;
947 #dma-cells = <1>;
948 dma-channels = <2>;
949 };
950
951 usb_dmac1: dma-controller@e65b0000 {
952 compatible = "renesas,r8a7795-usb-dmac",
953 "renesas,usb-dmac";
954 reg = <0 0xe65b0000 0 0x100>;
0aab5b91
GU		 955 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e0f0bda7
SH		 957 interrupt-names = "ch0", "ch1";
958 clocks = <&cpg CPG_MOD 331>;
959 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
960 resets = <&cpg 331>;
961 #dma-cells = <1>;
962 dma-channels = <2>;
963 };
964
965 usb_dmac2: dma-controller@e6460000 {
966 compatible = "renesas,r8a7795-usb-dmac",
967 "renesas,usb-dmac";
968 reg = <0 0xe6460000 0 0x100>;
0aab5b91
GU		 969 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
e0f0bda7
SH		 971 interrupt-names = "ch0", "ch1";
972 clocks = <&cpg CPG_MOD 326>;
973 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
974 resets = <&cpg 326>;
975 #dma-cells = <1>;
976 dma-channels = <2>;
977 };
978
979 usb_dmac3: dma-controller@e6470000 {
980 compatible = "renesas,r8a7795-usb-dmac",
981 "renesas,usb-dmac";
982 reg = <0 0xe6470000 0 0x100>;
0aab5b91
GU		 983 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
e0f0bda7
SH		 985 interrupt-names = "ch0", "ch1";
986 clocks = <&cpg CPG_MOD 329>;
987 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
988 resets = <&cpg 329>;
989 #dma-cells = <1>;
990 dma-channels = <2>;
991 };
992
993 usb3_phy0: usb-phy@e65ee000 {
994 compatible = "renesas,r8a7795-usb3-phy",
995 "renesas,rcar-gen3-usb3-phy";
996 reg = <0 0xe65ee000 0 0x90>;
997 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
998 <&usb_extal_clk>;
999 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
1000 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1001 resets = <&cpg 328>;
1002 #phy-cells = <0>;
1003 status = "disabled";
3b7e7848
MD		 1004 };
1005
8db067d5
GU		 1006 arm_cc630p: crypto@e6601000 {
1007 compatible = "arm,cryptocell-630p-ree";
1008 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1009 reg = <0x0 0xe6601000 0 0x1000>;
1010 clocks = <&cpg CPG_MOD 229>;
1011 resets = <&cpg 229>;
1012 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1013 };
1014
d9202126 1015 dmac0: dma-controller@e6700000 {
e2102cea
GU		 1016 compatible = "renesas,dmac-r8a7795",
1017 "renesas,rcar-dmac";
1018 reg = <0 0xe6700000 0 0x10000>;
0aab5b91
GU		 1019 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1021 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
e2102cea
GU		 1036 interrupt-names = "error",
1037 "ch0", "ch1", "ch2", "ch3",
1038 "ch4", "ch5", "ch6", "ch7",
1039 "ch8", "ch9", "ch10", "ch11",
1040 "ch12", "ch13", "ch14", "ch15";
1041 clocks = <&cpg CPG_MOD 219>;
1042 clock-names = "fck";
38dbb45e 1043 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1044 resets = <&cpg 219>;
e2102cea
GU		 1045 #dma-cells = <1>;
1046 dma-channels = <16>;
bf2ca657
MD		 1047 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1048 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1049 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1050 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1051 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1052 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1053 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1054 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
d9202126
GU		 1055 };
1056
1057 dmac1: dma-controller@e7300000 {
e2102cea
GU		 1058 compatible = "renesas,dmac-r8a7795",
1059 "renesas,rcar-dmac";
1060 reg = <0 0xe7300000 0 0x10000>;
0aab5b91
GU		 1061 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1063 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1069 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
1070 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1071 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1073 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1074 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1075 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1076 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1077 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
e2102cea
GU		 1078 interrupt-names = "error",
1079 "ch0", "ch1", "ch2", "ch3",
1080 "ch4", "ch5", "ch6", "ch7",
1081 "ch8", "ch9", "ch10", "ch11",
1082 "ch12", "ch13", "ch14", "ch15";
1083 clocks = <&cpg CPG_MOD 218>;
1084 clock-names = "fck";
38dbb45e 1085 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1086 resets = <&cpg 218>;
e2102cea
GU		 1087 #dma-cells = <1>;
1088 dma-channels = <16>;
bf2ca657
MD		 1089 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1090 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1091 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1092 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1093 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1094 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1095 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1096 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
d9202126
GU		 1097 };
1098
1099 dmac2: dma-controller@e7310000 {
e2102cea
GU		 1100 compatible = "renesas,dmac-r8a7795",
1101 "renesas,rcar-dmac";
1102 reg = <0 0xe7310000 0 0x10000>;
0aab5b91
GU		 1103 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1115 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1117 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1118 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1119 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
e2102cea
GU		 1120 interrupt-names = "error",
1121 "ch0", "ch1", "ch2", "ch3",
1122 "ch4", "ch5", "ch6", "ch7",
1123 "ch8", "ch9", "ch10", "ch11",
1124 "ch12", "ch13", "ch14", "ch15";
1125 clocks = <&cpg CPG_MOD 217>;
1126 clock-names = "fck";
38dbb45e 1127 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1128 resets = <&cpg 217>;
769fa836
KM		 1129 #dma-cells = <1>;
1130 dma-channels = <16>;
bf2ca657
MD		 1131 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1132 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1133 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1134 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1135 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1136 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1137 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1138 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
769fa836
KM		 1139 };
1140
cf8ae446 1141 ipmmu_ds0: iommu@e6740000 {
e0f0bda7
SH		 1142 compatible = "renesas,ipmmu-r8a7795";
1143 reg = <0 0xe6740000 0 0x1000>;
1144 renesas,ipmmu-main = <&ipmmu_mm 0>;
769fa836 1145 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1146 #iommu-cells = <1>;
769fa836
KM		 1147 };
1148
cf8ae446 1149 ipmmu_ds1: iommu@e7740000 {
e0f0bda7
SH		 1150 compatible = "renesas,ipmmu-r8a7795";
1151 reg = <0 0xe7740000 0 0x1000>;
1152 renesas,ipmmu-main = <&ipmmu_mm 1>;
769fa836 1153 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1154 #iommu-cells = <1>;
d9202126 1155 };
49af46b4 1156
cf8ae446 1157 ipmmu_hc: iommu@e6570000 {
e0f0bda7
SH		 1158 compatible = "renesas,ipmmu-r8a7795";
1159 reg = <0 0xe6570000 0 0x1000>;
1160 renesas,ipmmu-main = <&ipmmu_mm 2>;
38dbb45e 1161 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1162 #iommu-cells = <1>;
a92843c8
KM		 1163 };
1164
cf8ae446 1165 ipmmu_ir: iommu@ff8b0000 {
e0f0bda7
SH		 1166 compatible = "renesas,ipmmu-r8a7795";
1167 reg = <0 0xff8b0000 0 0x1000>;
1168 renesas,ipmmu-main = <&ipmmu_mm 3>;
1169 power-domains = <&sysc R8A7795_PD_A3IR>;
1170 #iommu-cells = <1>;
308b7e4b
RS		 1171 };
1172
cf8ae446 1173 ipmmu_mm: iommu@e67b0000 {
e0f0bda7
SH		 1174 compatible = "renesas,ipmmu-r8a7795";
1175 reg = <0 0xe67b0000 0 0x1000>;
1176 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1177 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
38dbb45e 1178 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1179 #iommu-cells = <1>;
308b7e4b
RS		 1180 };
1181
cf8ae446 1182 ipmmu_mp0: iommu@ec670000 {
e0f0bda7
SH		 1183 compatible = "renesas,ipmmu-r8a7795";
1184 reg = <0 0xec670000 0 0x1000>;
1185 renesas,ipmmu-main = <&ipmmu_mm 4>;
162cd784 1186 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1187 #iommu-cells = <1>;
162cd784
RS		 1188 };
1189
cf8ae446 1190 ipmmu_pv0: iommu@fd800000 {
e0f0bda7
SH		 1191 compatible = "renesas,ipmmu-r8a7795";
1192 reg = <0 0xfd800000 0 0x1000>;
1193 renesas,ipmmu-main = <&ipmmu_mm 6>;
91662b1b 1194 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1195 #iommu-cells = <1>;
91662b1b
RS		 1196 };
1197
cf8ae446 1198 ipmmu_pv1: iommu@fd950000 {
e0f0bda7
SH		 1199 compatible = "renesas,ipmmu-r8a7795";
1200 reg = <0 0xfd950000 0 0x1000>;
1201 renesas,ipmmu-main = <&ipmmu_mm 7>;
91662b1b 1202 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1203 #iommu-cells = <1>;
91662b1b
RS		 1204 };
1205
cf8ae446 1206 ipmmu_pv2: iommu@fd960000 {
e0f0bda7
SH		 1207 compatible = "renesas,ipmmu-r8a7795";
1208 reg = <0 0xfd960000 0 0x1000>;
1209 renesas,ipmmu-main = <&ipmmu_mm 8>;
91662b1b 1210 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1211 #iommu-cells = <1>;
91662b1b
RS		 1212 };
1213
cf8ae446 1214 ipmmu_pv3: iommu@fd970000 {
e0f0bda7
SH		 1215 compatible = "renesas,ipmmu-r8a7795";
1216 reg = <0 0xfd970000 0 0x1000>;
1217 renesas,ipmmu-main = <&ipmmu_mm 9>;
91662b1b 1218 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1219 #iommu-cells = <1>;
91662b1b
RS		 1220 };
1221
cf8ae446 1222 ipmmu_rt: iommu@ffc80000 {
e0f0bda7
SH		 1223 compatible = "renesas,ipmmu-r8a7795";
1224 reg = <0 0xffc80000 0 0x1000>;
1225 renesas,ipmmu-main = <&ipmmu_mm 10>;
91662b1b 1226 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1227 #iommu-cells = <1>;
91662b1b
RS		 1228 };
1229
cf8ae446 1230 ipmmu_vc0: iommu@fe6b0000 {
e0f0bda7
SH		 1231 compatible = "renesas,ipmmu-r8a7795";
1232 reg = <0 0xfe6b0000 0 0x1000>;
1233 renesas,ipmmu-main = <&ipmmu_mm 12>;
1234 power-domains = <&sysc R8A7795_PD_A3VC>;
1235 #iommu-cells = <1>;
e0f0bda7
SH		 1236 };
1237
cf8ae446 1238 ipmmu_vc1: iommu@fe6f0000 {
e0f0bda7
SH		 1239 compatible = "renesas,ipmmu-r8a7795";
1240 reg = <0 0xfe6f0000 0 0x1000>;
1241 renesas,ipmmu-main = <&ipmmu_mm 13>;
1242 power-domains = <&sysc R8A7795_PD_A3VC>;
1243 #iommu-cells = <1>;
e0f0bda7
SH		 1244 };
1245
cf8ae446 1246 ipmmu_vi0: iommu@febd0000 {
e0f0bda7
SH		 1247 compatible = "renesas,ipmmu-r8a7795";
1248 reg = <0 0xfebd0000 0 0x1000>;
1249 renesas,ipmmu-main = <&ipmmu_mm 14>;
91662b1b 1250 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1251 #iommu-cells = <1>;
1252 };
1253
cf8ae446 1254 ipmmu_vi1: iommu@febe0000 {
e0f0bda7
SH		 1255 compatible = "renesas,ipmmu-r8a7795";
1256 reg = <0 0xfebe0000 0 0x1000>;
1257 renesas,ipmmu-main = <&ipmmu_mm 15>;
1258 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1259 #iommu-cells = <1>;
91662b1b
RS		 1260 };
1261
cf8ae446 1262 ipmmu_vp0: iommu@fe990000 {
e0f0bda7
SH		 1263 compatible = "renesas,ipmmu-r8a7795";
1264 reg = <0 0xfe990000 0 0x1000>;
1265 renesas,ipmmu-main = <&ipmmu_mm 16>;
1266 power-domains = <&sysc R8A7795_PD_A3VP>;
1267 #iommu-cells = <1>;
e0f0bda7
SH		 1268 };
1269
cf8ae446 1270 ipmmu_vp1: iommu@fe980000 {
e0f0bda7
SH		 1271 compatible = "renesas,ipmmu-r8a7795";
1272 reg = <0 0xfe980000 0 0x1000>;
1273 renesas,ipmmu-main = <&ipmmu_mm 17>;
1274 power-domains = <&sysc R8A7795_PD_A3VP>;
1275 #iommu-cells = <1>;
1276 };
1277
1278 avb: ethernet@e6800000 {
1279 compatible = "renesas,etheravb-r8a7795",
1280 "renesas,etheravb-rcar-gen3";
1281 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1282 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1285 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1286 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1288 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1295 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1296 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1298 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1299 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1300 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1302 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1305 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1306 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1307 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1308 "ch4", "ch5", "ch6", "ch7",
1309 "ch8", "ch9", "ch10", "ch11",
1310 "ch12", "ch13", "ch14", "ch15",
1311 "ch16", "ch17", "ch18", "ch19",
1312 "ch20", "ch21", "ch22", "ch23",
1313 "ch24";
1314 clocks = <&cpg CPG_MOD 812>;
91662b1b 1315 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1316 resets = <&cpg 812>;
1317 phy-mode = "rgmii";
9b810181
GU		 1318 rx-internal-delay-ps = <0>;
1319 tx-internal-delay-ps = <0>;
e0f0bda7
SH		 1320 iommus = <&ipmmu_ds0 16>;
1321 #address-cells = <1>;
1322 #size-cells = <0>;
91662b1b
RS		 1323 status = "disabled";
1324 };
1325
e0f0bda7
SH		 1326 can0: can@e6c30000 {
1327 compatible = "renesas,can-r8a7795",
1328 "renesas,rcar-gen3-can";
1329 reg = <0 0xe6c30000 0 0x1000>;
1330 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&cpg CPG_MOD 916>,
1332 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
1333 <&can_clk>;
1334 clock-names = "clkp1", "clkp2", "can_clk";
1335 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
1336 assigned-clock-rates = <40000000>;
91662b1b 1337 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1338 resets = <&cpg 916>;
91662b1b
RS		 1339 status = "disabled";
1340 };
1341
e0f0bda7
SH		 1342 can1: can@e6c38000 {
1343 compatible = "renesas,can-r8a7795",
1344 "renesas,rcar-gen3-can";
1345 reg = <0 0xe6c38000 0 0x1000>;
1346 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MOD 915>,
1348 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
1349 <&can_clk>;
1350 clock-names = "clkp1", "clkp2", "can_clk";
1351 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
1352 assigned-clock-rates = <40000000>;
38dbb45e 1353 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1354 resets = <&cpg 915>;
4fa04299
GU		 1355 status = "disabled";
1356 };
1357
e0f0bda7
SH		 1358 canfd: can@e66c0000 {
1359 compatible = "renesas,r8a7795-canfd",
1360 "renesas,rcar-gen3-canfd";
1361 reg = <0 0xe66c0000 0 0x8000>;
1362 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MOD 914>,
1365 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
1366 <&can_clk>;
1367 clock-names = "fck", "canfd", "can_clk";
1368 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
1369 assigned-clock-rates = <40000000>;
38dbb45e 1370 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1371 resets = <&cpg 914>;
4fa04299 1372 status = "disabled";
e0f0bda7
SH		 1373
1374 channel0 {
1375 status = "disabled";
1376 };
1377
1378 channel1 {
1379 status = "disabled";
1380 };
4fa04299
GU		 1381 };
1382
e0f0bda7
SH		 1383 pwm0: pwm@e6e30000 {
1384 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1385 reg = <0 0xe6e30000 0 0x8>;
1386 clocks = <&cpg CPG_MOD 523>;
38dbb45e 1387 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1388 resets = <&cpg 523>;
1389 #pwm-cells = <2>;
4fa04299
GU		 1390 status = "disabled";
1391 };
1392
e0f0bda7
SH		 1393 pwm1: pwm@e6e31000 {
1394 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1395 reg = <0 0xe6e31000 0 0x8>;
1396 clocks = <&cpg CPG_MOD 523>;
38dbb45e 1397 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1398 resets = <&cpg 523>;
1399 #pwm-cells = <2>;
4fa04299
GU		 1400 status = "disabled";
1401 };
1402
e0f0bda7
SH		 1403 pwm2: pwm@e6e32000 {
1404 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1405 reg = <0 0xe6e32000 0 0x8>;
1406 clocks = <&cpg CPG_MOD 523>;
38dbb45e 1407 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1408 resets = <&cpg 523>;
1409 #pwm-cells = <2>;
4fa04299
GU		 1410 status = "disabled";
1411 };
1412
e0f0bda7
SH		 1413 pwm3: pwm@e6e33000 {
1414 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1415 reg = <0 0xe6e33000 0 0x8>;
1416 clocks = <&cpg CPG_MOD 523>;
ecad187f 1417 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1418 resets = <&cpg 523>;
1419 #pwm-cells = <2>;
ecad187f
GU		 1420 status = "disabled";
1421 };
1422
e0f0bda7
SH		 1423 pwm4: pwm@e6e34000 {
1424 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1425 reg = <0 0xe6e34000 0 0x8>;
1426 clocks = <&cpg CPG_MOD 523>;
ecad187f 1427 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1428 resets = <&cpg 523>;
1429 #pwm-cells = <2>;
ecad187f
GU		 1430 status = "disabled";
1431 };
1432
e0f0bda7
SH		 1433 pwm5: pwm@e6e35000 {
1434 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1435 reg = <0 0xe6e35000 0 0x8>;
1436 clocks = <&cpg CPG_MOD 523>;
ecad187f 1437 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1438 resets = <&cpg 523>;
1439 #pwm-cells = <2>;
ecad187f
GU		 1440 status = "disabled";
1441 };
1442
e0f0bda7
SH		 1443 pwm6: pwm@e6e36000 {
1444 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1445 reg = <0 0xe6e36000 0 0x8>;
1446 clocks = <&cpg CPG_MOD 523>;
ecad187f 1447 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1448 resets = <&cpg 523>;
1449 #pwm-cells = <2>;
ecad187f
GU		 1450 status = "disabled";
1451 };
1452
49af46b4 1453 scif0: serial@e6e60000 {
653f502d
GU		 1454 compatible = "renesas,scif-r8a7795",
1455 "renesas,rcar-gen3-scif", "renesas,scif";
49af46b4
GU		 1456 reg = <0 0xe6e60000 0 64>;
1457 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
3da41e4c
GU		 1458 clocks = <&cpg CPG_MOD 207>,
1459 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1460 <&scif_clk>;
1461 clock-names = "fck", "brg_int", "scif_clk";
eb21089c
GU		 1462 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1463 <&dmac2 0x51>, <&dmac2 0x50>;
1464 dma-names = "tx", "rx", "tx", "rx";
38dbb45e 1465 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1466 resets = <&cpg 207>;
49af46b4
GU		 1467 status = "disabled";
1468 };
1469
1470 scif1: serial@e6e68000 {
653f502d
GU		 1471 compatible = "renesas,scif-r8a7795",
1472 "renesas,rcar-gen3-scif", "renesas,scif";
49af46b4
GU		 1473 reg = <0 0xe6e68000 0 64>;
1474 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
3da41e4c
GU		 1475 clocks = <&cpg CPG_MOD 206>,
1476 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1477 <&scif_clk>;
1478 clock-names = "fck", "brg_int", "scif_clk";
eb21089c
GU		 1479 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1480 <&dmac2 0x53>, <&dmac2 0x52>;
1481 dma-names = "tx", "rx", "tx", "rx";
38dbb45e 1482 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1483 resets = <&cpg 206>;
49af46b4
GU		 1484 status = "disabled";
1485 };
1486
1487 scif2: serial@e6e88000 {
653f502d
GU		 1488 compatible = "renesas,scif-r8a7795",
1489 "renesas,rcar-gen3-scif", "renesas,scif";
49af46b4
GU		 1490 reg = <0 0xe6e88000 0 64>;
1491 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3da41e4c
GU		 1492 clocks = <&cpg CPG_MOD 310>,
1493 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1494 <&scif_clk>;
1495 clock-names = "fck", "brg_int", "scif_clk";
eb21089c
GU		 1496 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1497 <&dmac2 0x13>, <&dmac2 0x12>;
1498 dma-names = "tx", "rx", "tx", "rx";
38dbb45e 1499 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1500 resets = <&cpg 310>;
49af46b4
GU		 1501 status = "disabled";
1502 };
1503
1504 scif3: serial@e6c50000 {
653f502d
GU		 1505 compatible = "renesas,scif-r8a7795",
1506 "renesas,rcar-gen3-scif", "renesas,scif";
49af46b4
GU		 1507 reg = <0 0xe6c50000 0 64>;
1508 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
3da41e4c
GU		 1509 clocks = <&cpg CPG_MOD 204>,
1510 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1511 <&scif_clk>;
1512 clock-names = "fck", "brg_int", "scif_clk";
49af46b4
GU		 1513 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1514 dma-names = "tx", "rx";
38dbb45e 1515 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1516 resets = <&cpg 204>;
49af46b4
GU		 1517 status = "disabled";
1518 };
1519
1520 scif4: serial@e6c40000 {
653f502d
GU		 1521 compatible = "renesas,scif-r8a7795",
1522 "renesas,rcar-gen3-scif", "renesas,scif";
49af46b4
GU		 1523 reg = <0 0xe6c40000 0 64>;
1524 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
3da41e4c
GU		 1525 clocks = <&cpg CPG_MOD 203>,
1526 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1527 <&scif_clk>;
1528 clock-names = "fck", "brg_int", "scif_clk";
49af46b4
GU		 1529 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1530 dma-names = "tx", "rx";
38dbb45e 1531 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1532 resets = <&cpg 203>;
49af46b4
GU		 1533 status = "disabled";
1534 };
1535
1536 scif5: serial@e6f30000 {
653f502d
GU		 1537 compatible = "renesas,scif-r8a7795",
1538 "renesas,rcar-gen3-scif", "renesas,scif";
49af46b4
GU		 1539 reg = <0 0xe6f30000 0 64>;
1540 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
3da41e4c
GU		 1541 clocks = <&cpg CPG_MOD 202>,
1542 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1543 <&scif_clk>;
1544 clock-names = "fck", "brg_int", "scif_clk";
eb21089c
GU		 1545 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1546 <&dmac2 0x5b>, <&dmac2 0x5a>;
1547 dma-names = "tx", "rx", "tx", "rx";
38dbb45e 1548 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 1549 resets = <&cpg 202>;
49af46b4
GU		 1550 status = "disabled";
1551 };
32bc0c51 1552
a461b5bf
CVD		 1553 tpu: pwm@e6e80000 {
1554 compatible = "renesas,tpu-r8a7795", "renesas,tpu";
1555 reg = <0 0xe6e80000 0 0x148>;
1556 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1557 clocks = <&cpg CPG_MOD 304>;
1558 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1559 resets = <&cpg 304>;
1560 #pwm-cells = <3>;
1561 status = "disabled";
1562 };
1563
e0f0bda7
SH		 1564 msiof0: spi@e6e90000 {
1565 compatible = "renesas,msiof-r8a7795",
1566 "renesas,rcar-gen3-msiof";
1567 reg = <0 0xe6e90000 0 0x0064>;
1568 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1569 clocks = <&cpg CPG_MOD 211>;
1570 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1571 <&dmac2 0x41>, <&dmac2 0x40>;
eb21089c 1572 dma-names = "tx", "rx", "tx", "rx";
38dbb45e 1573 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 1574 resets = <&cpg 211>;
32bc0c51
KM		 1575 #address-cells = <1>;
1576 #size-cells = <0>;
32bc0c51
KM		 1577 status = "disabled";
1578 };
1579
e0f0bda7
SH		 1580 msiof1: spi@e6ea0000 {
1581 compatible = "renesas,msiof-r8a7795",
1582 "renesas,rcar-gen3-msiof";
1583 reg = <0 0xe6ea0000 0 0x0064>;
1584 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1585 clocks = <&cpg CPG_MOD 210>;
1586 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1587 <&dmac2 0x43>, <&dmac2 0x42>;
1588 dma-names = "tx", "rx", "tx", "rx";
38dbb45e 1589 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1590 resets = <&cpg 210>;
1591 #address-cells = <1>;
1592 #size-cells = <0>;
32bc0c51
KM		 1593 status = "disabled";
1594 };
1595
e0f0bda7
SH		 1596 msiof2: spi@e6c00000 {
1597 compatible = "renesas,msiof-r8a7795",
1598 "renesas,rcar-gen3-msiof";
1599 reg = <0 0xe6c00000 0 0x0064>;
1600 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1601 clocks = <&cpg CPG_MOD 209>;
1602 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1603 dma-names = "tx", "rx";
1604 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1605 resets = <&cpg 209>;
32bc0c51
KM		 1606 #address-cells = <1>;
1607 #size-cells = <0>;
32bc0c51
KM		 1608 status = "disabled";
1609 };
1610
e0f0bda7
SH		 1611 msiof3: spi@e6c10000 {
1612 compatible = "renesas,msiof-r8a7795",
1613 "renesas,rcar-gen3-msiof";
1614 reg = <0 0xe6c10000 0 0x0064>;
1615 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1616 clocks = <&cpg CPG_MOD 208>;
1617 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1618 dma-names = "tx", "rx";
1619 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1620 resets = <&cpg 208>;
32bc0c51
KM		 1621 #address-cells = <1>;
1622 #size-cells = <0>;
32bc0c51
KM		 1623 status = "disabled";
1624 };
1625
15da7132
NS		 1626 vin0: video@e6ef0000 {
1627 compatible = "renesas,vin-r8a7795";
1628 reg = <0 0xe6ef0000 0 0x1000>;
1629 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&cpg CPG_MOD 811>;
1631 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1632 resets = <&cpg 811>;
1633 renesas,id = <0>;
1634 status = "disabled";
1635
1636 ports {
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1639
1640 port@1 {
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1643
1644 reg = <1>;
1645
1646 vin0csi20: endpoint@0 {
1647 reg = <0>;
fced3a97 1648 remote-endpoint = <&csi20vin0>;
15da7132
NS		 1649 };
1650 vin0csi40: endpoint@2 {
1651 reg = <2>;
fced3a97 1652 remote-endpoint = <&csi40vin0>;
15da7132
NS		 1653 };
1654 };
1655 };
1656 };
1657
1658 vin1: video@e6ef1000 {
1659 compatible = "renesas,vin-r8a7795";
1660 reg = <0 0xe6ef1000 0 0x1000>;
1661 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MOD 810>;
1663 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1664 resets = <&cpg 810>;
1665 renesas,id = <1>;
1666 status = "disabled";
1667
1668 ports {
1669 #address-cells = <1>;
1670 #size-cells = <0>;
1671
1672 port@1 {
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675
1676 reg = <1>;
1677
1678 vin1csi20: endpoint@0 {
1679 reg = <0>;
fced3a97 1680 remote-endpoint = <&csi20vin1>;
15da7132
NS		 1681 };
1682 vin1csi40: endpoint@2 {
1683 reg = <2>;
fced3a97 1684 remote-endpoint = <&csi40vin1>;
15da7132
NS		 1685 };
1686 };
1687 };
1688 };
1689
1690 vin2: video@e6ef2000 {
1691 compatible = "renesas,vin-r8a7795";
1692 reg = <0 0xe6ef2000 0 0x1000>;
1693 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MOD 809>;
1695 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1696 resets = <&cpg 809>;
1697 renesas,id = <2>;
1698 status = "disabled";
1699
1700 ports {
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1703
1704 port@1 {
1705 #address-cells = <1>;
1706 #size-cells = <0>;
1707
1708 reg = <1>;
1709
1710 vin2csi20: endpoint@0 {
1711 reg = <0>;
fced3a97 1712 remote-endpoint = <&csi20vin2>;
15da7132
NS		 1713 };
1714 vin2csi40: endpoint@2 {
1715 reg = <2>;
fced3a97 1716 remote-endpoint = <&csi40vin2>;
15da7132
NS		 1717 };
1718 };
1719 };
1720 };
1721
1722 vin3: video@e6ef3000 {
1723 compatible = "renesas,vin-r8a7795";
1724 reg = <0 0xe6ef3000 0 0x1000>;
1725 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1726 clocks = <&cpg CPG_MOD 808>;
1727 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1728 resets = <&cpg 808>;
1729 renesas,id = <3>;
1730 status = "disabled";
1731
1732 ports {
1733 #address-cells = <1>;
1734 #size-cells = <0>;
1735
1736 port@1 {
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1739
1740 reg = <1>;
1741
1742 vin3csi20: endpoint@0 {
1743 reg = <0>;
fced3a97 1744 remote-endpoint = <&csi20vin3>;
15da7132
NS		 1745 };
1746 vin3csi40: endpoint@2 {
1747 reg = <2>;
fced3a97 1748 remote-endpoint = <&csi40vin3>;
15da7132
NS		 1749 };
1750 };
1751 };
1752 };
1753
1754 vin4: video@e6ef4000 {
1755 compatible = "renesas,vin-r8a7795";
1756 reg = <0 0xe6ef4000 0 0x1000>;
1757 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1758 clocks = <&cpg CPG_MOD 807>;
1759 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1760 resets = <&cpg 807>;
1761 renesas,id = <4>;
1762 status = "disabled";
1763
1764 ports {
1765 #address-cells = <1>;
1766 #size-cells = <0>;
1767
1768 port@1 {
1769 #address-cells = <1>;
1770 #size-cells = <0>;
1771
1772 reg = <1>;
1773
1774 vin4csi20: endpoint@0 {
1775 reg = <0>;
fced3a97 1776 remote-endpoint = <&csi20vin4>;
15da7132
NS		 1777 };
1778 vin4csi41: endpoint@3 {
1779 reg = <3>;
fced3a97 1780 remote-endpoint = <&csi41vin4>;
15da7132
NS		 1781 };
1782 };
1783 };
1784 };
1785
1786 vin5: video@e6ef5000 {
1787 compatible = "renesas,vin-r8a7795";
1788 reg = <0 0xe6ef5000 0 0x1000>;
1789 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1790 clocks = <&cpg CPG_MOD 806>;
1791 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1792 resets = <&cpg 806>;
1793 renesas,id = <5>;
1794 status = "disabled";
1795
1796 ports {
1797 #address-cells = <1>;
1798 #size-cells = <0>;
1799
1800 port@1 {
1801 #address-cells = <1>;
1802 #size-cells = <0>;
1803
1804 reg = <1>;
1805
1806 vin5csi20: endpoint@0 {
1807 reg = <0>;
fced3a97 1808 remote-endpoint = <&csi20vin5>;
15da7132
NS		 1809 };
1810 vin5csi41: endpoint@3 {
1811 reg = <3>;
fced3a97 1812 remote-endpoint = <&csi41vin5>;
15da7132
NS		 1813 };
1814 };
1815 };
1816 };
1817
1818 vin6: video@e6ef6000 {
1819 compatible = "renesas,vin-r8a7795";
1820 reg = <0 0xe6ef6000 0 0x1000>;
1821 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1822 clocks = <&cpg CPG_MOD 805>;
1823 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1824 resets = <&cpg 805>;
1825 renesas,id = <6>;
1826 status = "disabled";
1827
1828 ports {
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1831
1832 port@1 {
1833 #address-cells = <1>;
1834 #size-cells = <0>;
1835
1836 reg = <1>;
1837
1838 vin6csi20: endpoint@0 {
1839 reg = <0>;
fced3a97 1840 remote-endpoint = <&csi20vin6>;
15da7132
NS		 1841 };
1842 vin6csi41: endpoint@3 {
1843 reg = <3>;
fced3a97 1844 remote-endpoint = <&csi41vin6>;
15da7132
NS		 1845 };
1846 };
1847 };
1848 };
1849
1850 vin7: video@e6ef7000 {
1851 compatible = "renesas,vin-r8a7795";
1852 reg = <0 0xe6ef7000 0 0x1000>;
1853 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1854 clocks = <&cpg CPG_MOD 804>;
1855 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1856 resets = <&cpg 804>;
1857 renesas,id = <7>;
1858 status = "disabled";
1859
1860 ports {
1861 #address-cells = <1>;
1862 #size-cells = <0>;
1863
1864 port@1 {
1865 #address-cells = <1>;
1866 #size-cells = <0>;
1867
1868 reg = <1>;
1869
1870 vin7csi20: endpoint@0 {
1871 reg = <0>;
fced3a97 1872 remote-endpoint = <&csi20vin7>;
15da7132
NS		 1873 };
1874 vin7csi41: endpoint@3 {
1875 reg = <3>;
fced3a97 1876 remote-endpoint = <&csi41vin7>;
15da7132
NS		 1877 };
1878 };
1879 };
1880 };
1881
e0f0bda7
SH		 1882 drif00: rif@e6f40000 {
1883 compatible = "renesas,r8a7795-drif",
1884 "renesas,rcar-gen3-drif";
1885 reg = <0 0xe6f40000 0 0x64>;
1886 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1887 clocks = <&cpg CPG_MOD 515>;
1888 clock-names = "fck";
1889 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1890 dma-names = "rx", "rx";
38dbb45e 1891 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1892 resets = <&cpg 515>;
1893 renesas,bonding = <&drif01>;
32bc0c51
KM		 1894 status = "disabled";
1895 };
623197b9 1896
e0f0bda7
SH		 1897 drif01: rif@e6f50000 {
1898 compatible = "renesas,r8a7795-drif",
1899 "renesas,rcar-gen3-drif";
1900 reg = <0 0xe6f50000 0 0x64>;
1901 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1902 clocks = <&cpg CPG_MOD 514>;
1903 clock-names = "fck";
1904 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1905 dma-names = "rx", "rx";
b2b9443b 1906 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1907 resets = <&cpg 514>;
1908 renesas,bonding = <&drif00>;
b2b9443b
LP		 1909 status = "disabled";
1910 };
1911
e0f0bda7
SH		 1912 drif10: rif@e6f60000 {
1913 compatible = "renesas,r8a7795-drif",
1914 "renesas,rcar-gen3-drif";
1915 reg = <0 0xe6f60000 0 0x64>;
1916 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1917 clocks = <&cpg CPG_MOD 513>;
1918 clock-names = "fck";
1919 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1920 dma-names = "rx", "rx";
b2b9443b 1921 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1922 resets = <&cpg 513>;
1923 renesas,bonding = <&drif11>;
b2b9443b
LP		 1924 status = "disabled";
1925 };
1926
e0f0bda7
SH		 1927 drif11: rif@e6f70000 {
1928 compatible = "renesas,r8a7795-drif",
1929 "renesas,rcar-gen3-drif";
1930 reg = <0 0xe6f70000 0 0x64>;
1931 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1932 clocks = <&cpg CPG_MOD 512>;
1933 clock-names = "fck";
1934 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1935 dma-names = "rx", "rx";
b2b9443b 1936 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1937 resets = <&cpg 512>;
1938 renesas,bonding = <&drif10>;
b2b9443b
LP		 1939 status = "disabled";
1940 };
1941
e0f0bda7
SH		 1942 drif20: rif@e6f80000 {
1943 compatible = "renesas,r8a7795-drif",
1944 "renesas,rcar-gen3-drif";
1945 reg = <0 0xe6f80000 0 0x64>;
1946 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1947 clocks = <&cpg CPG_MOD 511>;
1948 clock-names = "fck";
1949 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1950 dma-names = "rx", "rx";
b2b9443b 1951 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1952 resets = <&cpg 511>;
1953 renesas,bonding = <&drif21>;
b2b9443b
LP		 1954 status = "disabled";
1955 };
1956
e0f0bda7
SH		 1957 drif21: rif@e6f90000 {
1958 compatible = "renesas,r8a7795-drif",
1959 "renesas,rcar-gen3-drif";
1960 reg = <0 0xe6f90000 0 0x64>;
1961 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1962 clocks = <&cpg CPG_MOD 510>;
1963 clock-names = "fck";
1964 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1965 dma-names = "rx", "rx";
b2b9443b 1966 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1967 resets = <&cpg 510>;
1968 renesas,bonding = <&drif20>;
b2b9443b
LP		 1969 status = "disabled";
1970 };
1971
e0f0bda7
SH		 1972 drif30: rif@e6fa0000 {
1973 compatible = "renesas,r8a7795-drif",
1974 "renesas,rcar-gen3-drif";
1975 reg = <0 0xe6fa0000 0 0x64>;
1976 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1977 clocks = <&cpg CPG_MOD 509>;
1978 clock-names = "fck";
1979 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1980 dma-names = "rx", "rx";
b2b9443b 1981 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1982 resets = <&cpg 509>;
1983 renesas,bonding = <&drif31>;
b2b9443b
LP		 1984 status = "disabled";
1985 };
1986
e0f0bda7
SH		 1987 drif31: rif@e6fb0000 {
1988 compatible = "renesas,r8a7795-drif",
1989 "renesas,rcar-gen3-drif";
1990 reg = <0 0xe6fb0000 0 0x64>;
1991 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1992 clocks = <&cpg CPG_MOD 508>;
1993 clock-names = "fck";
1994 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1995 dma-names = "rx", "rx";
b2b9443b 1996 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 1997 resets = <&cpg 508>;
1998 renesas,bonding = <&drif30>;
b2b9443b
LP		 1999 status = "disabled";
2000 };
2001
623197b9
KM		 2002 rcar_sound: sound@ec500000 {
2003 /*
2004 * #sound-dai-cells is required
2005 *
2006 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
2007 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
2008 */
2009 /*
2010 * #clock-cells is required for audio_clkout0/1/2/3
2011 *
2012 * clkout : #clock-cells = <0>; <&rcar_sound>;
2013 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
2014 */
2015 compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
2016 reg = <0 0xec500000 0 0x1000>, /* SCU */
2017 <0 0xec5a0000 0 0x100>, /* ADG */
2018 <0 0xec540000 0 0x1000>, /* SSIU */
2019 <0 0xec541000 0 0x280>, /* SSI */
7a516e49 2020 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
623197b9
KM		 2021 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
2022
2023 clocks = <&cpg CPG_MOD 1005>,
2024 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
2025 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
2026 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
2027 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
2028 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
b868ff51
KM		 2029 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
2030 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
2031 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
2032 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
2033 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
c9293d78 2034 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
ad5805f3 2035 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
b9dd9450 2036 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
623197b9
KM		 2037 <&audio_clk_a>, <&audio_clk_b>,
2038 <&audio_clk_c>,
2039 <&cpg CPG_CORE R8A7795_CLK_S0D4>;
2040 clock-names = "ssi-all",
2041 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
2042 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
2043 "ssi.1", "ssi.0",
b868ff51
KM		 2044 "src.9", "src.8", "src.7", "src.6",
2045 "src.5", "src.4", "src.3", "src.2",
2046 "src.1", "src.0",
ad5805f3 2047 "mix.1", "mix.0",
c9293d78 2048 "ctu.1", "ctu.0",
b9dd9450 2049 "dvc.0", "dvc.1",
623197b9 2050 "clk_a", "clk_b", "clk_c", "clk_i";
38dbb45e 2051 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
161a1910
GU		 2052 resets = <&cpg 1005>,
2053 <&cpg 1006>, <&cpg 1007>,
2054 <&cpg 1008>, <&cpg 1009>,
2055 <&cpg 1010>, <&cpg 1011>,
2056 <&cpg 1012>, <&cpg 1013>,
2057 <&cpg 1014>, <&cpg 1015>;
2058 reset-names = "ssi-all",
2059 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
2060 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
2061 "ssi.1", "ssi.0";
623197b9
KM		 2062 status = "disabled";
2063
b9dd9450 2064 rcar_sound,dvc {
6f7bf82c 2065 dvc0: dvc-0 {
b5a8ffad 2066 dmas = <&audma1 0xbc>;
b9dd9450
KM		 2067 dma-names = "tx";
2068 };
6f7bf82c 2069 dvc1: dvc-1 {
b5a8ffad 2070 dmas = <&audma1 0xbe>;
b9dd9450
KM		 2071 dma-names = "tx";
2072 };
2073 };
2074
ad5805f3
KM		 2075 rcar_sound,mix {
2076 mix0: mix-0 { };
2077 mix1: mix-1 { };
2078 };
2079
c9293d78
KM		 2080 rcar_sound,ctu {
2081 ctu00: ctu-0 { };
2082 ctu01: ctu-1 { };
2083 ctu02: ctu-2 { };
2084 ctu03: ctu-3 { };
2085 ctu10: ctu-4 { };
2086 ctu11: ctu-5 { };
2087 ctu12: ctu-6 { };
2088 ctu13: ctu-7 { };
2089 };
2090
b868ff51 2091 rcar_sound,src {
6f7bf82c 2092 src0: src-0 {
52b541ab 2093 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2094 dmas = <&audma0 0x85>, <&audma1 0x9a>;
2095 dma-names = "rx", "tx";
2096 };
6f7bf82c 2097 src1: src-1 {
52b541ab 2098 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2099 dmas = <&audma0 0x87>, <&audma1 0x9c>;
2100 dma-names = "rx", "tx";
2101 };
6f7bf82c 2102 src2: src-2 {
52b541ab 2103 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2104 dmas = <&audma0 0x89>, <&audma1 0x9e>;
2105 dma-names = "rx", "tx";
2106 };
6f7bf82c 2107 src3: src-3 {
52b541ab 2108 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2109 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
2110 dma-names = "rx", "tx";
2111 };
6f7bf82c 2112 src4: src-4 {
52b541ab 2113 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2114 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
2115 dma-names = "rx", "tx";
2116 };
6f7bf82c 2117 src5: src-5 {
52b541ab 2118 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2119 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
2120 dma-names = "rx", "tx";
2121 };
6f7bf82c 2122 src6: src-6 {
52b541ab 2123 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2124 dmas = <&audma0 0x91>, <&audma1 0xb4>;
2125 dma-names = "rx", "tx";
2126 };
6f7bf82c 2127 src7: src-7 {
52b541ab 2128 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2129 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2130 dma-names = "rx", "tx";
2131 };
6f7bf82c 2132 src8: src-8 {
52b541ab 2133 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2134 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2135 dma-names = "rx", "tx";
2136 };
6f7bf82c 2137 src9: src-9 {
52b541ab 2138 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
b868ff51
KM		 2139 dmas = <&audma0 0x97>, <&audma1 0xba>;
2140 dma-names = "rx", "tx";
2141 };
2142 };
2143
da90dd84
KM		 2144 rcar_sound,ssiu {
2145 ssiu00: ssiu-0 {
2146 dmas = <&audma0 0x15>, <&audma1 0x16>;
2147 dma-names = "rx", "tx";
2148 };
2149 ssiu01: ssiu-1 {
2150 dmas = <&audma0 0x35>, <&audma1 0x36>;
2151 dma-names = "rx", "tx";
2152 };
2153 ssiu02: ssiu-2 {
2154 dmas = <&audma0 0x37>, <&audma1 0x38>;
2155 dma-names = "rx", "tx";
2156 };
2157 ssiu03: ssiu-3 {
2158 dmas = <&audma0 0x47>, <&audma1 0x48>;
2159 dma-names = "rx", "tx";
2160 };
2161 ssiu04: ssiu-4 {
2162 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2163 dma-names = "rx", "tx";
2164 };
2165 ssiu05: ssiu-5 {
2166 dmas = <&audma0 0x43>, <&audma1 0x44>;
2167 dma-names = "rx", "tx";
2168 };
2169 ssiu06: ssiu-6 {
2170 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2171 dma-names = "rx", "tx";
2172 };
2173 ssiu07: ssiu-7 {
2174 dmas = <&audma0 0x53>, <&audma1 0x54>;
2175 dma-names = "rx", "tx";
2176 };
2177 ssiu10: ssiu-8 {
2178 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2179 dma-names = "rx", "tx";
2180 };
2181 ssiu11: ssiu-9 {
2182 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2183 dma-names = "rx", "tx";
2184 };
2185 ssiu12: ssiu-10 {
2186 dmas = <&audma0 0x57>, <&audma1 0x58>;
2187 dma-names = "rx", "tx";
2188 };
2189 ssiu13: ssiu-11 {
2190 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2191 dma-names = "rx", "tx";
2192 };
2193 ssiu14: ssiu-12 {
2194 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2195 dma-names = "rx", "tx";
2196 };
2197 ssiu15: ssiu-13 {
2198 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2199 dma-names = "rx", "tx";
2200 };
2201 ssiu16: ssiu-14 {
2202 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2203 dma-names = "rx", "tx";
2204 };
2205 ssiu17: ssiu-15 {
2206 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2207 dma-names = "rx", "tx";
2208 };
2209 ssiu20: ssiu-16 {
2210 dmas = <&audma0 0x63>, <&audma1 0x64>;
2211 dma-names = "rx", "tx";
2212 };
2213 ssiu21: ssiu-17 {
2214 dmas = <&audma0 0x67>, <&audma1 0x68>;
2215 dma-names = "rx", "tx";
2216 };
2217 ssiu22: ssiu-18 {
2218 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2219 dma-names = "rx", "tx";
2220 };
2221 ssiu23: ssiu-19 {
2222 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2223 dma-names = "rx", "tx";
2224 };
2225 ssiu24: ssiu-20 {
2226 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2227 dma-names = "rx", "tx";
2228 };
2229 ssiu25: ssiu-21 {
2230 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2231 dma-names = "rx", "tx";
2232 };
2233 ssiu26: ssiu-22 {
2234 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2235 dma-names = "rx", "tx";
2236 };
2237 ssiu27: ssiu-23 {
2238 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2239 dma-names = "rx", "tx";
2240 };
2241 ssiu30: ssiu-24 {
2242 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2243 dma-names = "rx", "tx";
2244 };
2245 ssiu31: ssiu-25 {
2246 dmas = <&audma0 0x21>, <&audma1 0x22>;
2247 dma-names = "rx", "tx";
2248 };
2249 ssiu32: ssiu-26 {
2250 dmas = <&audma0 0x23>, <&audma1 0x24>;
2251 dma-names = "rx", "tx";
2252 };
2253 ssiu33: ssiu-27 {
2254 dmas = <&audma0 0x25>, <&audma1 0x26>;
2255 dma-names = "rx", "tx";
2256 };
2257 ssiu34: ssiu-28 {
2258 dmas = <&audma0 0x27>, <&audma1 0x28>;
2259 dma-names = "rx", "tx";
2260 };
2261 ssiu35: ssiu-29 {
2262 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2263 dma-names = "rx", "tx";
2264 };
2265 ssiu36: ssiu-30 {
2266 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2267 dma-names = "rx", "tx";
2268 };
2269 ssiu37: ssiu-31 {
2270 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2271 dma-names = "rx", "tx";
2272 };
2273 ssiu40: ssiu-32 {
2274 dmas = <&audma0 0x71>, <&audma1 0x72>;
2275 dma-names = "rx", "tx";
2276 };
2277 ssiu41: ssiu-33 {
2278 dmas = <&audma0 0x17>, <&audma1 0x18>;
2279 dma-names = "rx", "tx";
2280 };
2281 ssiu42: ssiu-34 {
2282 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2283 dma-names = "rx", "tx";
2284 };
2285 ssiu43: ssiu-35 {
2286 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2287 dma-names = "rx", "tx";
2288 };
2289 ssiu44: ssiu-36 {
2290 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2291 dma-names = "rx", "tx";
2292 };
2293 ssiu45: ssiu-37 {
2294 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2295 dma-names = "rx", "tx";
2296 };
2297 ssiu46: ssiu-38 {
2298 dmas = <&audma0 0x31>, <&audma1 0x32>;
2299 dma-names = "rx", "tx";
2300 };
2301 ssiu47: ssiu-39 {
2302 dmas = <&audma0 0x33>, <&audma1 0x34>;
2303 dma-names = "rx", "tx";
2304 };
2305 ssiu50: ssiu-40 {
2306 dmas = <&audma0 0x73>, <&audma1 0x74>;
2307 dma-names = "rx", "tx";
2308 };
2309 ssiu60: ssiu-41 {
2310 dmas = <&audma0 0x75>, <&audma1 0x76>;
2311 dma-names = "rx", "tx";
2312 };
2313 ssiu70: ssiu-42 {
2314 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2315 dma-names = "rx", "tx";
2316 };
2317 ssiu80: ssiu-43 {
2318 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2319 dma-names = "rx", "tx";
2320 };
2321 ssiu90: ssiu-44 {
2322 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2323 dma-names = "rx", "tx";
2324 };
2325 ssiu91: ssiu-45 {
2326 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2327 dma-names = "rx", "tx";
2328 };
2329 ssiu92: ssiu-46 {
2330 dmas = <&audma0 0x81>, <&audma1 0x82>;
2331 dma-names = "rx", "tx";
2332 };
2333 ssiu93: ssiu-47 {
2334 dmas = <&audma0 0x83>, <&audma1 0x84>;
2335 dma-names = "rx", "tx";
2336 };
2337 ssiu94: ssiu-48 {
2338 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2339 dma-names = "rx", "tx";
2340 };
2341 ssiu95: ssiu-49 {
2342 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2343 dma-names = "rx", "tx";
2344 };
2345 ssiu96: ssiu-50 {
2346 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2347 dma-names = "rx", "tx";
2348 };
2349 ssiu97: ssiu-51 {
2350 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2351 dma-names = "rx", "tx";
2352 };
2353 };
2354
623197b9 2355 rcar_sound,ssi {
6f7bf82c 2356 ssi0: ssi-0 {
52b541ab 2357 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2358 dmas = <&audma0 0x01>, <&audma1 0x02>;
2359 dma-names = "rx", "tx";
623197b9 2360 };
6f7bf82c 2361 ssi1: ssi-1 {
52b541ab 2362 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2363 dmas = <&audma0 0x03>, <&audma1 0x04>;
2364 dma-names = "rx", "tx";
623197b9 2365 };
6f7bf82c 2366 ssi2: ssi-2 {
52b541ab 2367 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2368 dmas = <&audma0 0x05>, <&audma1 0x06>;
2369 dma-names = "rx", "tx";
623197b9 2370 };
6f7bf82c 2371 ssi3: ssi-3 {
52b541ab 2372 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2373 dmas = <&audma0 0x07>, <&audma1 0x08>;
2374 dma-names = "rx", "tx";
623197b9 2375 };
6f7bf82c 2376 ssi4: ssi-4 {
52b541ab 2377 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2378 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2379 dma-names = "rx", "tx";
623197b9 2380 };
6f7bf82c 2381 ssi5: ssi-5 {
52b541ab 2382 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2383 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2384 dma-names = "rx", "tx";
623197b9 2385 };
6f7bf82c 2386 ssi6: ssi-6 {
52b541ab 2387 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2388 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2389 dma-names = "rx", "tx";
623197b9 2390 };
6f7bf82c 2391 ssi7: ssi-7 {
52b541ab 2392 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2393 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2394 dma-names = "rx", "tx";
623197b9 2395 };
6f7bf82c 2396 ssi8: ssi-8 {
52b541ab 2397 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2398 dmas = <&audma0 0x11>, <&audma1 0x12>;
2399 dma-names = "rx", "tx";
623197b9 2400 };
6f7bf82c 2401 ssi9: ssi-9 {
52b541ab 2402 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
0ec8e0a8
KM		 2403 dmas = <&audma0 0x13>, <&audma1 0x14>;
2404 dma-names = "rx", "tx";
623197b9
KM		 2405 };
2406 };
2407 };
4c13472b 2408
e0f0bda7
SH		 2409 audma0: dma-controller@ec700000 {
2410 compatible = "renesas,dmac-r8a7795",
2411 "renesas,rcar-dmac";
2412 reg = <0 0xec700000 0 0x10000>;
0aab5b91
GU		 2413 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2414 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2415 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2416 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2417 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2418 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2421 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2422 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2423 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2424 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2425 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2426 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2427 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2428 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2429 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
e0f0bda7
SH		 2430 interrupt-names = "error",
2431 "ch0", "ch1", "ch2", "ch3",
2432 "ch4", "ch5", "ch6", "ch7",
2433 "ch8", "ch9", "ch10", "ch11",
2434 "ch12", "ch13", "ch14", "ch15";
2435 clocks = <&cpg CPG_MOD 502>;
2436 clock-names = "fck";
2cab226c 2437 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 2438 resets = <&cpg 502>;
2439 #dma-cells = <1>;
2440 dma-channels = <16>;
2441 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2442 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
2443 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
2444 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
2445 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
2446 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
2447 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
2448 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
4c13472b 2449 };
171f2ef8 2450
e0f0bda7
SH		 2451 audma1: dma-controller@ec720000 {
2452 compatible = "renesas,dmac-r8a7795",
2453 "renesas,rcar-dmac";
2454 reg = <0 0xec720000 0 0x10000>;
0aab5b91
GU		 2455 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2456 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2457 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2458 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2459 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2460 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2461 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2462 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2463 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2464 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2465 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2466 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2467 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2468 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2469 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2470 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2471 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
e0f0bda7
SH		 2472 interrupt-names = "error",
2473 "ch0", "ch1", "ch2", "ch3",
2474 "ch4", "ch5", "ch6", "ch7",
2475 "ch8", "ch9", "ch10", "ch11",
2476 "ch12", "ch13", "ch14", "ch15";
2477 clocks = <&cpg CPG_MOD 501>;
2478 clock-names = "fck";
7c1e5ea6 2479 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7
SH		 2480 resets = <&cpg 501>;
2481 #dma-cells = <1>;
2482 dma-channels = <16>;
2483 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
2484 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
2485 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
2486 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
2487 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
2488 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
2489 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
2490 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
7c1e5ea6
YS		 2491 };
2492
171f2ef8 2493 xhci0: usb@ee000000 {
81ae0ac3 2494 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
171f2ef8
YS		 2495 reg = <0 0xee000000 0 0xc00>;
2496 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2497 clocks = <&cpg CPG_MOD 328>;
38dbb45e 2498 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 2499 resets = <&cpg 328>;
171f2ef8
YS		 2500 status = "disabled";
2501 };
2502
3bdba1b2
YS		 2503 usb3_peri0: usb@ee020000 {
2504 compatible = "renesas,r8a7795-usb3-peri",
2505 "renesas,rcar-gen3-usb3-peri";
2506 reg = <0 0xee020000 0 0x400>;
2507 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2508 clocks = <&cpg CPG_MOD 328>;
2509 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2510 resets = <&cpg 328>;
2511 status = "disabled";
2512 };
2513
e0f0bda7
SH		 2514 ohci0: usb@ee080000 {
2515 compatible = "generic-ohci";
2516 reg = <0 0xee080000 0 0x100>;
5923bb52 2517 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 2518 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
7794bd7e 2519 phys = <&usb2_phy0 1>;
e0f0bda7 2520 phy-names = "usb";
38dbb45e 2521 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
737e05bf 2522 resets = <&cpg 703>, <&cpg 704>;
5923bb52
YS		 2523 status = "disabled";
2524 };
2525
e0f0bda7
SH		 2526 ohci1: usb@ee0a0000 {
2527 compatible = "generic-ohci";
2528 reg = <0 0xee0a0000 0 0x100>;
2529 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
5923bb52 2530 clocks = <&cpg CPG_MOD 702>;
7794bd7e 2531 phys = <&usb2_phy1 1>;
e0f0bda7 2532 phy-names = "usb";
38dbb45e 2533 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 2534 resets = <&cpg 702>;
5923bb52
YS		 2535 status = "disabled";
2536 };
2537
e0f0bda7
SH		 2538 ohci2: usb@ee0c0000 {
2539 compatible = "generic-ohci";
2540 reg = <0 0xee0c0000 0 0x100>;
2541 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
5923bb52 2542 clocks = <&cpg CPG_MOD 701>;
7794bd7e 2543 phys = <&usb2_phy2 1>;
e0f0bda7 2544 phy-names = "usb";
38dbb45e 2545 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 2546 resets = <&cpg 701>;
5923bb52
YS		 2547 status = "disabled";
2548 };
a2bcdc28 2549
e0f0bda7
SH		 2550 ohci3: usb@ee0e0000 {
2551 compatible = "generic-ohci";
2552 reg = <0 0xee0e0000 0 0x100>;
ac29cc44 2553 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 2554 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
7794bd7e 2555 phys = <&usb2_phy3 1>;
e0f0bda7 2556 phy-names = "usb";
ac29cc44 2557 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
737e05bf 2558 resets = <&cpg 700>, <&cpg 705>;
ac29cc44
YS		 2559 status = "disabled";
2560 };
2561
a2bcdc28
YS		 2562 ehci0: usb@ee080100 {
2563 compatible = "generic-ehci";
2564 reg = <0 0xee080100 0 0x100>;
2565 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 2566 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
7794bd7e 2567 phys = <&usb2_phy0 2>;
a2bcdc28 2568 phy-names = "usb";
c3a937bb 2569 companion = <&ohci0>;
38dbb45e 2570 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
737e05bf 2571 resets = <&cpg 703>, <&cpg 704>;
a2bcdc28
YS		 2572 status = "disabled";
2573 };
2574
2575 ehci1: usb@ee0a0100 {
2576 compatible = "generic-ehci";
2577 reg = <0 0xee0a0100 0 0x100>;
2578 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2579 clocks = <&cpg CPG_MOD 702>;
7794bd7e 2580 phys = <&usb2_phy1 2>;
a2bcdc28 2581 phy-names = "usb";
c3a937bb 2582 companion = <&ohci1>;
38dbb45e 2583 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 2584 resets = <&cpg 702>;
a2bcdc28
YS		 2585 status = "disabled";
2586 };
2587
2588 ehci2: usb@ee0c0100 {
2589 compatible = "generic-ehci";
2590 reg = <0 0xee0c0100 0 0x100>;
2591 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
2592 clocks = <&cpg CPG_MOD 701>;
7794bd7e 2593 phys = <&usb2_phy2 2>;
a2bcdc28 2594 phy-names = "usb";
c3a937bb 2595 companion = <&ohci2>;
38dbb45e 2596 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 2597 resets = <&cpg 701>;
a2bcdc28
YS		 2598 status = "disabled";
2599 };
2600
4dad6dcd
YS		 2601 ehci3: usb@ee0e0100 {
2602 compatible = "generic-ehci";
2603 reg = <0 0xee0e0100 0 0x100>;
2604 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 2605 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
7794bd7e 2606 phys = <&usb2_phy3 2>;
4dad6dcd 2607 phy-names = "usb";
c3a937bb 2608 companion = <&ohci3>;
4dad6dcd 2609 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
737e05bf 2610 resets = <&cpg 700>, <&cpg 705>;
4dad6dcd
YS		 2611 status = "disabled";
2612 };
2613
e0f0bda7
SH		 2614 usb2_phy0: usb-phy@ee080200 {
2615 compatible = "renesas,usb2-phy-r8a7795",
2616 "renesas,rcar-gen3-usb2-phy";
2617 reg = <0 0xee080200 0 0x700>;
a2bcdc28 2618 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 2619 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
38dbb45e 2620 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
737e05bf 2621 resets = <&cpg 703>, <&cpg 704>;
7794bd7e 2622 #phy-cells = <1>;
a2bcdc28
YS		 2623 status = "disabled";
2624 };
2625
e0f0bda7
SH		 2626 usb2_phy1: usb-phy@ee0a0200 {
2627 compatible = "renesas,usb2-phy-r8a7795",
2628 "renesas,rcar-gen3-usb2-phy";
2629 reg = <0 0xee0a0200 0 0x700>;
a2bcdc28 2630 clocks = <&cpg CPG_MOD 702>;
38dbb45e 2631 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 2632 resets = <&cpg 702>;
7794bd7e 2633 #phy-cells = <1>;
a2bcdc28
YS		 2634 status = "disabled";
2635 };
2636
e0f0bda7
SH		 2637 usb2_phy2: usb-phy@ee0c0200 {
2638 compatible = "renesas,usb2-phy-r8a7795",
2639 "renesas,rcar-gen3-usb2-phy";
2640 reg = <0 0xee0c0200 0 0x700>;
a2bcdc28 2641 clocks = <&cpg CPG_MOD 701>;
38dbb45e 2642 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 2643 resets = <&cpg 701>;
7794bd7e 2644 #phy-cells = <1>;
e0f0bda7
SH		 2645 status = "disabled";
2646 };
2647
2648 usb2_phy3: usb-phy@ee0e0200 {
2649 compatible = "renesas,usb2-phy-r8a7795",
2650 "renesas,rcar-gen3-usb2-phy";
2651 reg = <0 0xee0e0200 0 0x700>;
2652 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
737e05bf 2653 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
e0f0bda7 2654 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
737e05bf 2655 resets = <&cpg 700>, <&cpg 705>;
7794bd7e 2656 #phy-cells = <1>;
e0f0bda7
SH		 2657 status = "disabled";
2658 };
2659
a6cb262a 2660 sdhi0: mmc@ee100000 {
e0f0bda7
SH		 2661 compatible = "renesas,sdhi-r8a7795",
2662 "renesas,rcar-gen3-sdhi";
2663 reg = <0 0xee100000 0 0x2000>;
2664 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2665 clocks = <&cpg CPG_MOD 314>;
2666 max-frequency = <200000000>;
2667 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2668 resets = <&cpg 314>;
8292f5eb 2669 iommus = <&ipmmu_ds1 32>;
e0f0bda7
SH		 2670 status = "disabled";
2671 };
2672
a6cb262a 2673 sdhi1: mmc@ee120000 {
e0f0bda7
SH		 2674 compatible = "renesas,sdhi-r8a7795",
2675 "renesas,rcar-gen3-sdhi";
2676 reg = <0 0xee120000 0 0x2000>;
2677 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2678 clocks = <&cpg CPG_MOD 313>;
2679 max-frequency = <200000000>;
2680 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2681 resets = <&cpg 313>;
8292f5eb 2682 iommus = <&ipmmu_ds1 33>;
e0f0bda7
SH		 2683 status = "disabled";
2684 };
2685
a6cb262a 2686 sdhi2: mmc@ee140000 {
e0f0bda7
SH		 2687 compatible = "renesas,sdhi-r8a7795",
2688 "renesas,rcar-gen3-sdhi";
2689 reg = <0 0xee140000 0 0x2000>;
2690 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2691 clocks = <&cpg CPG_MOD 312>;
2692 max-frequency = <200000000>;
2693 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2694 resets = <&cpg 312>;
8292f5eb 2695 iommus = <&ipmmu_ds1 34>;
a2bcdc28
YS		 2696 status = "disabled";
2697 };
d2422e10 2698
a6cb262a 2699 sdhi3: mmc@ee160000 {
e0f0bda7
SH		 2700 compatible = "renesas,sdhi-r8a7795",
2701 "renesas,rcar-gen3-sdhi";
2702 reg = <0 0xee160000 0 0x2000>;
2703 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2704 clocks = <&cpg CPG_MOD 311>;
2705 max-frequency = <200000000>;
4dad6dcd 2706 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 2707 resets = <&cpg 311>;
8292f5eb 2708 iommus = <&ipmmu_ds1 35>;
4dad6dcd
YS		 2709 status = "disabled";
2710 };
2711
e0f0bda7
SH		 2712 sata: sata@ee300000 {
2713 compatible = "renesas,sata-r8a7795",
2714 "renesas,rcar-gen3-sata";
2715 reg = <0 0xee300000 0 0x200000>;
2716 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2717 clocks = <&cpg CPG_MOD 815>;
d2422e10 2718 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 2719 resets = <&cpg 815>;
d2422e10 2720 status = "disabled";
e0f0bda7 2721 iommus = <&ipmmu_hc 2>;
d2422e10
YS		 2722 };
2723
e0f0bda7
SH		 2724 gic: interrupt-controller@f1010000 {
2725 compatible = "arm,gic-400";
2726 #interrupt-cells = <3>;
2727 #address-cells = <0>;
2728 interrupt-controller;
2729 reg = <0x0 0xf1010000 0 0x1000>,
2730 <0x0 0xf1020000 0 0x20000>,
2731 <0x0 0xf1040000 0 0x20000>,
2732 <0x0 0xf1060000 0 0x20000>;
2733 interrupts = <GIC_PPI 9
2734 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2735 clocks = <&cpg CPG_MOD 408>;
2736 clock-names = "clk";
4725f2b8 2737 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
e0f0bda7 2738 resets = <&cpg 408>;
4725f2b8
YS		 2739 };
2740
9251024a 2741 pciec0: pcie@fe000000 {
fb04f4b8
SH		 2742 compatible = "renesas,pcie-r8a7795",
2743 "renesas,pcie-rcar-gen3";
9251024a
PE		 2744 reg = <0 0xfe000000 0 0x80000>;
2745 #address-cells = <3>;
2746 #size-cells = <2>;
2747 bus-range = <0x00 0xff>;
2748 device_type = "pci";
9504a9f2
GU		 2749 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2750 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2751 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2752 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
9251024a
PE		 2753 /* Map all possible DDR as inbound ranges */
2754 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2755 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2756 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2757 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2758 #interrupt-cells = <1>;
2759 interrupt-map-mask = <0 0 0 0>;
2760 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2761 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2762 clock-names = "pcie", "pcie_bus";
38dbb45e 2763 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 2764 resets = <&cpg 319>;
9251024a
PE		 2765 status = "disabled";
2766 };
2767
2768 pciec1: pcie@ee800000 {
fb04f4b8
SH		 2769 compatible = "renesas,pcie-r8a7795",
2770 "renesas,pcie-rcar-gen3";
9251024a
PE		 2771 reg = <0 0xee800000 0 0x80000>;
2772 #address-cells = <3>;
2773 #size-cells = <2>;
2774 bus-range = <0x00 0xff>;
2775 device_type = "pci";
9504a9f2
GU		 2776 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2777 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2778 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2779 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
9251024a
PE		 2780 /* Map all possible DDR as inbound ranges */
2781 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2782 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2783 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2784 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2785 #interrupt-cells = <1>;
2786 interrupt-map-mask = <0 0 0 0>;
2787 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2788 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2789 clock-names = "pcie", "pcie_bus";
38dbb45e 2790 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dcccc132 2791 resets = <&cpg 318>;
9251024a 2792 status = "disabled";
0f80b9b8
YH		 2793 };
2794
2795 pciec0_ep: pcie-ep@fe000000 {
2796 compatible = "renesas,r8a7795-pcie-ep",
2797 "renesas,rcar-gen3-pcie-ep";
2798 reg = <0x0 0xfe000000 0 0x80000>,
2799 <0x0 0xfe100000 0 0x100000>,
2800 <0x0 0xfe200000 0 0x200000>,
2801 <0x0 0x30000000 0 0x8000000>,
2802 <0x0 0x38000000 0 0x8000000>;
2803 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2804 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2805 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2806 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2807 clocks = <&cpg CPG_MOD 319>;
2808 clock-names = "pcie";
2809 resets = <&cpg 319>;
2810 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2811 status = "disabled";
2812 };
2813
2814 pciec1_ep: pcie-ep@ee800000 {
2815 compatible = "renesas,r8a7795-pcie-ep",
2816 "renesas,rcar-gen3-pcie-ep";
2817 reg = <0x0 0xee800000 0 0x80000>,
2818 <0x0 0xee900000 0 0x100000>,
2819 <0x0 0xeea00000 0 0x200000>,
2820 <0x0 0xc0000000 0 0x8000000>,
2821 <0x0 0xc8000000 0 0x8000000>;
2822 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2823 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2824 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2825 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2826 clocks = <&cpg CPG_MOD 318>;
2827 clock-names = "pcie";
2828 resets = <&cpg 318>;
2829 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2830 status = "disabled";
9251024a 2831 };
28fc8131 2832
24604cd3
SS		 2833 imr-lx4@fe860000 {
2834 compatible = "renesas,r8a7795-imr-lx4",
2835 "renesas,imr-lx4";
2836 reg = <0 0xfe860000 0 0x2000>;
2837 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2838 clocks = <&cpg CPG_MOD 823>;
2839 power-domains = <&sysc R8A7795_PD_A3VC>;
2840 resets = <&cpg 823>;
2841 };
2842
2843 imr-lx4@fe870000 {
2844 compatible = "renesas,r8a7795-imr-lx4",
2845 "renesas,imr-lx4";
2846 reg = <0 0xfe870000 0 0x2000>;
2847 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2848 clocks = <&cpg CPG_MOD 822>;
2849 power-domains = <&sysc R8A7795_PD_A3VC>;
2850 resets = <&cpg 822>;
2851 };
2852
2853 imr-lx4@fe880000 {
2854 compatible = "renesas,r8a7795-imr-lx4",
2855 "renesas,imr-lx4";
2856 reg = <0 0xfe880000 0 0x2000>;
2857 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
2858 clocks = <&cpg CPG_MOD 821>;
2859 power-domains = <&sysc R8A7795_PD_A3VC>;
2860 resets = <&cpg 821>;
2861 };
2862
2863 imr-lx4@fe890000 {
2864 compatible = "renesas,r8a7795-imr-lx4",
2865 "renesas,imr-lx4";
2866 reg = <0 0xfe890000 0 0x2000>;
2867 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
2868 clocks = <&cpg CPG_MOD 820>;
2869 power-domains = <&sysc R8A7795_PD_A3VC>;
2870 resets = <&cpg 820>;
2871 };
2872
c7a895fc
YK		 2873 vspbc: vsp@fe920000 {
2874 compatible = "renesas,vsp2";
2875 reg = <0 0xfe920000 0 0x8000>;
2876 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
2877 clocks = <&cpg CPG_MOD 624>;
2878 power-domains = <&sysc R8A7795_PD_A3VP>;
2879 resets = <&cpg 624>;
2880
2881 renesas,fcp = <&fcpvb1>;
2882 };
2883
2884 vspbd: vsp@fe960000 {
2885 compatible = "renesas,vsp2";
2886 reg = <0 0xfe960000 0 0x8000>;
2887 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2888 clocks = <&cpg CPG_MOD 626>;
2889 power-domains = <&sysc R8A7795_PD_A3VP>;
2890 resets = <&cpg 626>;
2891
2892 renesas,fcp = <&fcpvb0>;
2893 };
2894
2895 vspd0: vsp@fea20000 {
2896 compatible = "renesas,vsp2";
2897 reg = <0 0xfea20000 0 0x5000>;
2898 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2899 clocks = <&cpg CPG_MOD 623>;
2900 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2901 resets = <&cpg 623>;
2902
2903 renesas,fcp = <&fcpvd0>;
2904 };
2905
2906 vspd1: vsp@fea28000 {
2907 compatible = "renesas,vsp2";
2908 reg = <0 0xfea28000 0 0x5000>;
2909 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2910 clocks = <&cpg CPG_MOD 622>;
2911 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2912 resets = <&cpg 622>;
2913
2914 renesas,fcp = <&fcpvd1>;
2915 };
2916
2917 vspd2: vsp@fea30000 {
2918 compatible = "renesas,vsp2";
2919 reg = <0 0xfea30000 0 0x5000>;
2920 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2921 clocks = <&cpg CPG_MOD 621>;
2922 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2923 resets = <&cpg 621>;
2924
2925 renesas,fcp = <&fcpvd2>;
2926 };
2927
2928 vspi0: vsp@fe9a0000 {
2929 compatible = "renesas,vsp2";
2930 reg = <0 0xfe9a0000 0 0x8000>;
2931 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2932 clocks = <&cpg CPG_MOD 631>;
2933 power-domains = <&sysc R8A7795_PD_A3VP>;
2934 resets = <&cpg 631>;
2935
2936 renesas,fcp = <&fcpvi0>;
2937 };
2938
2939 vspi1: vsp@fe9b0000 {
2940 compatible = "renesas,vsp2";
2941 reg = <0 0xfe9b0000 0 0x8000>;
2942 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
2943 clocks = <&cpg CPG_MOD 630>;
2944 power-domains = <&sysc R8A7795_PD_A3VP>;
2945 resets = <&cpg 630>;
2946
2947 renesas,fcp = <&fcpvi1>;
2948 };
2949
e0f0bda7
SH		 2950 fdp1@fe940000 {
2951 compatible = "renesas,fdp1";
2952 reg = <0 0xfe940000 0 0x2400>;
2953 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2954 clocks = <&cpg CPG_MOD 119>;
9f8573e3 2955 power-domains = <&sysc R8A7795_PD_A3VP>;
e0f0bda7
SH		 2956 resets = <&cpg 119>;
2957 renesas,fcp = <&fcpf0>;
9f8573e3
LP		 2958 };
2959
e0f0bda7
SH		 2960 fdp1@fe944000 {
2961 compatible = "renesas,fdp1";
2962 reg = <0 0xfe944000 0 0x2400>;
2963 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2964 clocks = <&cpg CPG_MOD 118>;
52cd0783 2965 power-domains = <&sysc R8A7795_PD_A3VP>;
e0f0bda7
SH		 2966 resets = <&cpg 118>;
2967 renesas,fcp = <&fcpf1>;
52cd0783
LP		 2968 };
2969
28fc8131 2970 fcpf0: fcp@fe950000 {
ab33da0b 2971 compatible = "renesas,fcpf";
28fc8131
KB		 2972 reg = <0 0xfe950000 0 0x200>;
2973 clocks = <&cpg CPG_MOD 615>;
2974 power-domains = <&sysc R8A7795_PD_A3VP>;
dcccc132 2975 resets = <&cpg 615>;
afdeb149 2976 iommus = <&ipmmu_vp0 0>;
28fc8131
KB		 2977 };
2978
2979 fcpf1: fcp@fe951000 {
ab33da0b 2980 compatible = "renesas,fcpf";
28fc8131
KB		 2981 reg = <0 0xfe951000 0 0x200>;
2982 clocks = <&cpg CPG_MOD 614>;
2983 power-domains = <&sysc R8A7795_PD_A3VP>;
dcccc132 2984 resets = <&cpg 614>;
afdeb149 2985 iommus = <&ipmmu_vp1 1>;
28fc8131
KB		 2986 };
2987
52cd0783 2988 fcpvb0: fcp@fe96f000 {
ab33da0b 2989 compatible = "renesas,fcpv";
52cd0783
LP		 2990 reg = <0 0xfe96f000 0 0x200>;
2991 clocks = <&cpg CPG_MOD 607>;
2992 power-domains = <&sysc R8A7795_PD_A3VP>;
dcccc132 2993 resets = <&cpg 607>;
cdd919ba 2994 iommus = <&ipmmu_vp0 5>;
52cd0783
LP		 2995 };
2996
e0f0bda7
SH		 2997 fcpvb1: fcp@fe92f000 {
2998 compatible = "renesas,fcpv";
2999 reg = <0 0xfe92f000 0 0x200>;
3000 clocks = <&cpg CPG_MOD 606>;
9f8573e3 3001 power-domains = <&sysc R8A7795_PD_A3VP>;
e0f0bda7
SH		 3002 resets = <&cpg 606>;
3003 iommus = <&ipmmu_vp1 7>;
9f8573e3
LP		 3004 };
3005
52cd0783 3006 fcpvi0: fcp@fe9af000 {
ab33da0b 3007 compatible = "renesas,fcpv";
52cd0783
LP		 3008 reg = <0 0xfe9af000 0 0x200>;
3009 clocks = <&cpg CPG_MOD 611>;
3010 power-domains = <&sysc R8A7795_PD_A3VP>;
dcccc132 3011 resets = <&cpg 611>;
a02aac48 3012 iommus = <&ipmmu_vp0 8>;
52cd0783
LP		 3013 };
3014
3015 fcpvi1: fcp@fe9bf000 {
ab33da0b 3016 compatible = "renesas,fcpv";
52cd0783
LP		 3017 reg = <0 0xfe9bf000 0 0x200>;
3018 clocks = <&cpg CPG_MOD 610>;
3019 power-domains = <&sysc R8A7795_PD_A3VP>;
dcccc132 3020 resets = <&cpg 610>;
a02aac48 3021 iommus = <&ipmmu_vp1 9>;
52cd0783
LP		 3022 };
3023
e0f0bda7
SH		 3024 fcpvd0: fcp@fea27000 {
3025 compatible = "renesas,fcpv";
3026 reg = <0 0xfea27000 0 0x200>;
3027 clocks = <&cpg CPG_MOD 603>;
3028 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3029 resets = <&cpg 603>;
3030 iommus = <&ipmmu_vi0 8>;
3031 };
3032
3033 fcpvd1: fcp@fea2f000 {
3034 compatible = "renesas,fcpv";
3035 reg = <0 0xfea2f000 0 0x200>;
3036 clocks = <&cpg CPG_MOD 602>;
3037 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3038 resets = <&cpg 602>;
3039 iommus = <&ipmmu_vi0 9>;
3040 };
3041
3042 fcpvd2: fcp@fea37000 {
3043 compatible = "renesas,fcpv";
3044 reg = <0 0xfea37000 0 0x200>;
3045 clocks = <&cpg CPG_MOD 601>;
3046 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3047 resets = <&cpg 601>;
3048 iommus = <&ipmmu_vi1 10>;
3049 };
3050
948c59dd
JM		 3051 cmm0: cmm@fea40000 {
3052 compatible = "renesas,r8a7795-cmm",
3053 "renesas,rcar-gen3-cmm";
3054 reg = <0 0xfea40000 0 0x1000>;
3055 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3056 clocks = <&cpg CPG_MOD 711>;
3057 resets = <&cpg 711>;
3058 };
3059
3060 cmm1: cmm@fea50000 {
3061 compatible = "renesas,r8a7795-cmm",
3062 "renesas,rcar-gen3-cmm";
3063 reg = <0 0xfea50000 0 0x1000>;
3064 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3065 clocks = <&cpg CPG_MOD 710>;
3066 resets = <&cpg 710>;
3067 };
3068
3069 cmm2: cmm@fea60000 {
3070 compatible = "renesas,r8a7795-cmm",
3071 "renesas,rcar-gen3-cmm";
3072 reg = <0 0xfea60000 0 0x1000>;
3073 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3074 clocks = <&cpg CPG_MOD 709>;
3075 resets = <&cpg 709>;
3076 };
3077
3078 cmm3: cmm@fea70000 {
3079 compatible = "renesas,r8a7795-cmm",
3080 "renesas,rcar-gen3-cmm";
3081 reg = <0 0xfea70000 0 0x1000>;
3082 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3083 clocks = <&cpg CPG_MOD 708>;
3084 resets = <&cpg 708>;
3085 };
3086
15da7132
NS		 3087 csi20: csi2@fea80000 {
3088 compatible = "renesas,r8a7795-csi2";
3089 reg = <0 0xfea80000 0 0x10000>;
3090 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
3091 clocks = <&cpg CPG_MOD 714>;
3092 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3093 resets = <&cpg 714>;
3094 status = "disabled";
3095
3096 ports {
3097 #address-cells = <1>;
3098 #size-cells = <0>;
3099
0a96c059
NS		 3100 port@0 {
3101 reg = <0>;
3102 };
3103
15da7132
NS		 3104 port@1 {
3105 #address-cells = <1>;
3106 #size-cells = <0>;
3107
3108 reg = <1>;
3109
3110 csi20vin0: endpoint@0 {
3111 reg = <0>;
3112 remote-endpoint = <&vin0csi20>;
3113 };
3114 csi20vin1: endpoint@1 {
3115 reg = <1>;
3116 remote-endpoint = <&vin1csi20>;
3117 };
3118 csi20vin2: endpoint@2 {
3119 reg = <2>;
3120 remote-endpoint = <&vin2csi20>;
3121 };
3122 csi20vin3: endpoint@3 {
3123 reg = <3>;
3124 remote-endpoint = <&vin3csi20>;
3125 };
3126 csi20vin4: endpoint@4 {
3127 reg = <4>;
3128 remote-endpoint = <&vin4csi20>;
3129 };
3130 csi20vin5: endpoint@5 {
3131 reg = <5>;
3132 remote-endpoint = <&vin5csi20>;
3133 };
3134 csi20vin6: endpoint@6 {
3135 reg = <6>;
3136 remote-endpoint = <&vin6csi20>;
3137 };
3138 csi20vin7: endpoint@7 {
3139 reg = <7>;
3140 remote-endpoint = <&vin7csi20>;
3141 };
3142 };
3143 };
3144 };
3145
3146 csi40: csi2@feaa0000 {
3147 compatible = "renesas,r8a7795-csi2";
3148 reg = <0 0xfeaa0000 0 0x10000>;
3149 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
3150 clocks = <&cpg CPG_MOD 716>;
3151 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3152 resets = <&cpg 716>;
3153 status = "disabled";
3154
3155 ports {
3156 #address-cells = <1>;
3157 #size-cells = <0>;
3158
0a96c059
NS		 3159 port@0 {
3160 reg = <0>;
3161 };
3162
15da7132
NS		 3163 port@1 {
3164 #address-cells = <1>;
3165 #size-cells = <0>;
3166
3167 reg = <1>;
3168
3169 csi40vin0: endpoint@0 {
3170 reg = <0>;
3171 remote-endpoint = <&vin0csi40>;
3172 };
3173 csi40vin1: endpoint@1 {
3174 reg = <1>;
3175 remote-endpoint = <&vin1csi40>;
3176 };
3177 csi40vin2: endpoint@2 {
3178 reg = <2>;
3179 remote-endpoint = <&vin2csi40>;
3180 };
3181 csi40vin3: endpoint@3 {
3182 reg = <3>;
3183 remote-endpoint = <&vin3csi40>;
3184 };
3185 };
3186 };
3187 };
3188
3189 csi41: csi2@feab0000 {
3190 compatible = "renesas,r8a7795-csi2";
3191 reg = <0 0xfeab0000 0 0x10000>;
3192 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
3193 clocks = <&cpg CPG_MOD 715>;
3194 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3195 resets = <&cpg 715>;
3196 status = "disabled";
3197
3198 ports {
3199 #address-cells = <1>;
3200 #size-cells = <0>;
3201
0a96c059
NS		 3202 port@0 {
3203 reg = <0>;
3204 };
3205
15da7132
NS		 3206 port@1 {
3207 #address-cells = <1>;
3208 #size-cells = <0>;
3209
3210 reg = <1>;
3211
3212 csi41vin4: endpoint@0 {
3213 reg = <0>;
3214 remote-endpoint = <&vin4csi41>;
3215 };
3216 csi41vin5: endpoint@1 {
3217 reg = <1>;
3218 remote-endpoint = <&vin5csi41>;
3219 };
3220 csi41vin6: endpoint@2 {
3221 reg = <2>;
3222 remote-endpoint = <&vin6csi41>;
3223 };
3224 csi41vin7: endpoint@3 {
3225 reg = <3>;
3226 remote-endpoint = <&vin7csi41>;
3227 };
3228 };
3229 };
3230 };
3231
6b5ac2f1 3232 hdmi0: hdmi@fead0000 {
12daaf78
UH		 3233 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
3234 reg = <0 0xfead0000 0 0x10000>;
3235 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
3236 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
3237 clock-names = "iahb", "isfr";
3238 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3239 resets = <&cpg 729>;
3240 status = "disabled";
3241
3242 ports {
3243 #address-cells = <1>;
3244 #size-cells = <0>;
3245 port@0 {
3246 reg = <0>;
3247 dw_hdmi0_in: endpoint {
3248 remote-endpoint = <&du_out_hdmi0>;
3249 };
3250 };
3251 port@1 {
3252 reg = <1>;
3253 };
5a0d8a6f
KM		 3254 port@2 {
3255 /* HDMI sound */
3256 reg = <2>;
3257 };
12daaf78
UH		 3258 };
3259 };
3260
6b5ac2f1 3261 hdmi1: hdmi@feae0000 {
12daaf78
UH		 3262 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
3263 reg = <0 0xfeae0000 0 0x10000>;
3264 interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
3265 clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
3266 clock-names = "iahb", "isfr";
3267 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3268 resets = <&cpg 728>;
3269 status = "disabled";
3270
3271 ports {
3272 #address-cells = <1>;
3273 #size-cells = <0>;
3274 port@0 {
3275 reg = <0>;
3276 dw_hdmi1_in: endpoint {
3277 remote-endpoint = <&du_out_hdmi1>;
3278 };
3279 };
3280 port@1 {
3281 reg = <1>;
3282 };
5a0d8a6f
KM		 3283 port@2 {
3284 /* HDMI sound */
3285 reg = <2>;
3286 };
12daaf78
UH		 3287 };
3288 };
3289
a001a07f 3290 du: display@feb00000 {
f0499b9f 3291 compatible = "renesas,du-r8a7795";
58e8ed2e 3292 reg = <0 0xfeb00000 0 0x80000>;
a001a07f
LP		 3293 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3294 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3295 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3296 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
d745c72d
GU		 3297 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
3298 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>;
58e8ed2e 3299 clock-names = "du.0", "du.1", "du.2", "du.3";
d745c72d
GU		 3300 resets = <&cpg 724>, <&cpg 722>;
3301 reset-names = "du.0", "du.2";
948c59dd
JM		 3302
3303 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
03abfdd3
GU		 3304 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>,
3305 <&vspd0 1>;
948c59dd 3306
a001a07f
LP		 3307 status = "disabled";
3308
a001a07f
LP		 3309 ports {
3310 #address-cells = <1>;
3311 #size-cells = <0>;
3312
3313 port@0 {
3314 reg = <0>;
3315 du_out_rgb: endpoint {
3316 };
3317 };
3318 port@1 {
3319 reg = <1>;
3320 du_out_hdmi0: endpoint {
12daaf78 3321 remote-endpoint = <&dw_hdmi0_in>;
a001a07f
LP		 3322 };
3323 };
3324 port@2 {
3325 reg = <2>;
3326 du_out_hdmi1: endpoint {
12daaf78 3327 remote-endpoint = <&dw_hdmi1_in>;
a001a07f
LP		 3328 };
3329 };
3330 port@3 {
3331 reg = <3>;
3332 du_out_lvds0: endpoint {
58e8ed2e
LP		 3333 remote-endpoint = <&lvds0_in>;
3334 };
3335 };
3336 };
3337 };
3338
3339 lvds0: lvds@feb90000 {
3340 compatible = "renesas,r8a7795-lvds";
3341 reg = <0 0xfeb90000 0 0x14>;
3342 clocks = <&cpg CPG_MOD 727>;
3343 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3344 resets = <&cpg 727>;
3345 status = "disabled";
3346
3347 ports {
3348 #address-cells = <1>;
3349 #size-cells = <0>;
3350
3351 port@0 {
3352 reg = <0>;
3353 lvds0_in: endpoint {
3354 remote-endpoint = <&du_out_lvds0>;
3355 };
3356 };
3357 port@1 {
3358 reg = <1>;
3359 lvds0_out: endpoint {
a001a07f
LP		 3360 };
3361 };
3362 };
3363 };
b443cd17 3364
e0f0bda7
SH		 3365 prr: chipid@fff00044 {
3366 compatible = "renesas,prr";
3367 reg = <0 0xfff00044 0 4>;
b443cd17 3368 };
4f5dc77b 3369 };
b443cd17 3370
4f5dc77b
SH		 3371 thermal-zones {
3372 sensor_thermal1: sensor-thermal1 {
3373 polling-delay-passive = <250>;
3374 polling-delay = <1000>;
3375 thermal-sensors = <&tsc 0>;
15d8cd83 3376 sustainable-power = <6313>;
4f5dc77b
SH		 3377
3378 trips {
3379 sensor1_crit: sensor1-crit {
3380 temperature = <120000>;
02f15e4b 3381 hysteresis = <1000>;
4f5dc77b 3382 type = "critical";
b443cd17
WS		 3383 };
3384 };
4f5dc77b 3385 };
b443cd17 3386
4f5dc77b
SH		 3387 sensor_thermal2: sensor-thermal2 {
3388 polling-delay-passive = <250>;
3389 polling-delay = <1000>;
3390 thermal-sensors = <&tsc 1>;
15d8cd83 3391 sustainable-power = <6313>;
b443cd17 3392
4f5dc77b
SH		 3393 trips {
3394 sensor2_crit: sensor2-crit {
3395 temperature = <120000>;
02f15e4b 3396 hysteresis = <1000>;
4f5dc77b 3397 type = "critical";
b443cd17
WS		 3398 };
3399 };
4f5dc77b 3400 };
b443cd17 3401
4f5dc77b
SH		 3402 sensor_thermal3: sensor-thermal3 {
3403 polling-delay-passive = <250>;
3404 polling-delay = <1000>;
3405 thermal-sensors = <&tsc 2>;
b443cd17 3406
4f5dc77b 3407 trips {
15d8cd83
DP		 3408 target: trip-point1 {
3409 temperature = <100000>;
02f15e4b 3410 hysteresis = <1000>;
0c38c54e
NS		 3411 type = "passive";
3412 };
15d8cd83 3413
4f5dc77b
SH		 3414 sensor3_crit: sensor3-crit {
3415 temperature = <120000>;
02f15e4b 3416 hysteresis = <1000>;
4f5dc77b 3417 type = "critical";
b443cd17
WS		 3418 };
3419 };
0c38c54e
NS		 3420
3421 cooling-maps {
3422 map0 {
15d8cd83
DP		 3423 trip = <&target>;
3424 cooling-device = <&a57_0 2 4>;
3425 contribution = <1024>;
3426 };
3427
3428 map1 {
3429 trip = <&target>;
3430 cooling-device = <&a53_0 0 2>;
3431 contribution = <1024>;
0c38c54e
NS		 3432 };
3433 };
b443cd17 3434 };
26a7e06d 3435 };
7c1e5ea6 3436
82cf1d15
SH		 3437 timer {
3438 compatible = "arm,armv8-timer";
3439 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3440 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3441 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3442 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3443 };
3444
7c1e5ea6
YS		 3445 /* External USB clocks - can be overridden by the board */
3446 usb3s0_clk: usb3s0 {
3447 compatible = "fixed-clock";
3448 #clock-cells = <0>;
3449 clock-frequency = <0>;
3450 };
3451
3452 usb_extal_clk: usb_extal {
3453 compatible = "fixed-clock";
3454 #clock-cells = <0>;
3455 clock-frequency = <0>;
3456 };
26a7e06d 3457};
Linux 6.x block layer and io_uring tree(s)