Commit | Line | Data |
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26a7e06d SH |
1 | /* |
2 | * Device Tree Source for the r8a7795 SoC | |
3 | * | |
4 | * Copyright (C) 2015 Renesas Electronics Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
49af46b4 | 11 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
26a7e06d SH |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
13 | ||
14 | / { | |
15 | compatible = "renesas,r8a7795"; | |
16 | #address-cells = <2>; | |
17 | #size-cells = <2>; | |
18 | ||
32bc0c51 KM |
19 | aliases { |
20 | i2c0 = &i2c0; | |
21 | i2c1 = &i2c1; | |
22 | i2c2 = &i2c2; | |
23 | i2c3 = &i2c3; | |
24 | i2c4 = &i2c4; | |
25 | i2c5 = &i2c5; | |
26 | i2c6 = &i2c6; | |
27 | }; | |
28 | ||
12e51557 GI |
29 | psci { |
30 | compatible = "arm,psci-0.2"; | |
31 | method = "smc"; | |
32 | }; | |
33 | ||
26a7e06d SH |
34 | cpus { |
35 | #address-cells = <1>; | |
36 | #size-cells = <0>; | |
37 | ||
26a7e06d SH |
38 | a57_0: cpu@0 { |
39 | compatible = "arm,cortex-a57", "arm,armv8"; | |
40 | reg = <0x0>; | |
41 | device_type = "cpu"; | |
12e51557 | 42 | enable-method = "psci"; |
26a7e06d | 43 | }; |
0ed1a79e GI |
44 | |
45 | a57_1: cpu@1 { | |
46 | compatible = "arm,cortex-a57","arm,armv8"; | |
47 | reg = <0x1>; | |
48 | device_type = "cpu"; | |
49 | enable-method = "psci"; | |
50 | }; | |
51 | a57_2: cpu@2 { | |
52 | compatible = "arm,cortex-a57","arm,armv8"; | |
53 | reg = <0x2>; | |
54 | device_type = "cpu"; | |
55 | enable-method = "psci"; | |
56 | }; | |
57 | a57_3: cpu@3 { | |
58 | compatible = "arm,cortex-a57","arm,armv8"; | |
59 | reg = <0x3>; | |
60 | device_type = "cpu"; | |
61 | enable-method = "psci"; | |
62 | }; | |
26a7e06d SH |
63 | }; |
64 | ||
65 | extal_clk: extal { | |
66 | compatible = "fixed-clock"; | |
67 | #clock-cells = <0>; | |
68 | /* This value must be overridden by the board */ | |
69 | clock-frequency = <0>; | |
70 | }; | |
71 | ||
72 | extalr_clk: extalr { | |
73 | compatible = "fixed-clock"; | |
74 | #clock-cells = <0>; | |
75 | /* This value must be overridden by the board */ | |
76 | clock-frequency = <0>; | |
77 | }; | |
78 | ||
623197b9 KM |
79 | /* |
80 | * The external audio clocks are configured as 0 Hz fixed frequency | |
81 | * clocks by default. | |
82 | * Boards that provide audio clocks should override them. | |
83 | */ | |
84 | audio_clk_a: audio_clk_a { | |
85 | compatible = "fixed-clock"; | |
86 | #clock-cells = <0>; | |
87 | clock-frequency = <0>; | |
88 | }; | |
89 | ||
90 | audio_clk_b: audio_clk_b { | |
91 | compatible = "fixed-clock"; | |
92 | #clock-cells = <0>; | |
93 | clock-frequency = <0>; | |
94 | }; | |
95 | ||
96 | audio_clk_c: audio_clk_c { | |
97 | compatible = "fixed-clock"; | |
98 | #clock-cells = <0>; | |
99 | clock-frequency = <0>; | |
100 | }; | |
101 | ||
26a7e06d SH |
102 | soc { |
103 | compatible = "simple-bus"; | |
104 | interrupt-parent = <&gic>; | |
0ed1a79e | 105 | |
26a7e06d SH |
106 | #address-cells = <2>; |
107 | #size-cells = <2>; | |
108 | ranges; | |
109 | ||
110 | gic: interrupt-controller@0xf1010000 { | |
111 | compatible = "arm,gic-400"; | |
112 | #interrupt-cells = <3>; | |
113 | #address-cells = <0>; | |
114 | interrupt-controller; | |
115 | reg = <0x0 0xf1010000 0 0x1000>, | |
116 | <0x0 0xf1020000 0 0x2000>; | |
117 | interrupts = <GIC_PPI 9 | |
0ed1a79e | 118 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
26a7e06d SH |
119 | }; |
120 | ||
7b08623a TK |
121 | gpio0: gpio@e6050000 { |
122 | compatible = "renesas,gpio-r8a7795", | |
123 | "renesas,gpio-rcar"; | |
124 | reg = <0 0xe6050000 0 0x50>; | |
125 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
126 | #gpio-cells = <2>; | |
127 | gpio-controller; | |
128 | gpio-ranges = <&pfc 0 0 16>; | |
129 | #interrupt-cells = <2>; | |
130 | interrupt-controller; | |
131 | clocks = <&cpg CPG_MOD 912>; | |
132 | power-domains = <&cpg>; | |
133 | }; | |
134 | ||
135 | gpio1: gpio@e6051000 { | |
136 | compatible = "renesas,gpio-r8a7795", | |
137 | "renesas,gpio-rcar"; | |
138 | reg = <0 0xe6051000 0 0x50>; | |
139 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
140 | #gpio-cells = <2>; | |
141 | gpio-controller; | |
142 | gpio-ranges = <&pfc 0 32 28>; | |
143 | #interrupt-cells = <2>; | |
144 | interrupt-controller; | |
145 | clocks = <&cpg CPG_MOD 911>; | |
146 | power-domains = <&cpg>; | |
147 | }; | |
148 | ||
149 | gpio2: gpio@e6052000 { | |
150 | compatible = "renesas,gpio-r8a7795", | |
151 | "renesas,gpio-rcar"; | |
152 | reg = <0 0xe6052000 0 0x50>; | |
153 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
154 | #gpio-cells = <2>; | |
155 | gpio-controller; | |
156 | gpio-ranges = <&pfc 0 64 15>; | |
157 | #interrupt-cells = <2>; | |
158 | interrupt-controller; | |
159 | clocks = <&cpg CPG_MOD 910>; | |
160 | power-domains = <&cpg>; | |
161 | }; | |
162 | ||
163 | gpio3: gpio@e6053000 { | |
164 | compatible = "renesas,gpio-r8a7795", | |
165 | "renesas,gpio-rcar"; | |
166 | reg = <0 0xe6053000 0 0x50>; | |
167 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
168 | #gpio-cells = <2>; | |
169 | gpio-controller; | |
170 | gpio-ranges = <&pfc 0 96 16>; | |
171 | #interrupt-cells = <2>; | |
172 | interrupt-controller; | |
173 | clocks = <&cpg CPG_MOD 909>; | |
174 | power-domains = <&cpg>; | |
175 | }; | |
176 | ||
177 | gpio4: gpio@e6054000 { | |
178 | compatible = "renesas,gpio-r8a7795", | |
179 | "renesas,gpio-rcar"; | |
180 | reg = <0 0xe6054000 0 0x50>; | |
181 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
182 | #gpio-cells = <2>; | |
183 | gpio-controller; | |
184 | gpio-ranges = <&pfc 0 128 18>; | |
185 | #interrupt-cells = <2>; | |
186 | interrupt-controller; | |
187 | clocks = <&cpg CPG_MOD 908>; | |
188 | power-domains = <&cpg>; | |
189 | }; | |
190 | ||
191 | gpio5: gpio@e6055000 { | |
192 | compatible = "renesas,gpio-r8a7795", | |
193 | "renesas,gpio-rcar"; | |
194 | reg = <0 0xe6055000 0 0x50>; | |
195 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
196 | #gpio-cells = <2>; | |
197 | gpio-controller; | |
198 | gpio-ranges = <&pfc 0 160 26>; | |
199 | #interrupt-cells = <2>; | |
200 | interrupt-controller; | |
201 | clocks = <&cpg CPG_MOD 907>; | |
202 | power-domains = <&cpg>; | |
203 | }; | |
204 | ||
205 | gpio6: gpio@e6055400 { | |
206 | compatible = "renesas,gpio-r8a7795", | |
207 | "renesas,gpio-rcar"; | |
208 | reg = <0 0xe6055400 0 0x50>; | |
209 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
210 | #gpio-cells = <2>; | |
211 | gpio-controller; | |
212 | gpio-ranges = <&pfc 0 192 32>; | |
213 | #interrupt-cells = <2>; | |
214 | interrupt-controller; | |
215 | clocks = <&cpg CPG_MOD 906>; | |
216 | power-domains = <&cpg>; | |
217 | }; | |
218 | ||
219 | gpio7: gpio@e6055800 { | |
220 | compatible = "renesas,gpio-r8a7795", | |
221 | "renesas,gpio-rcar"; | |
222 | reg = <0 0xe6055800 0 0x50>; | |
223 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
224 | #gpio-cells = <2>; | |
225 | gpio-controller; | |
226 | gpio-ranges = <&pfc 0 224 4>; | |
227 | #interrupt-cells = <2>; | |
228 | interrupt-controller; | |
229 | clocks = <&cpg CPG_MOD 905>; | |
230 | power-domains = <&cpg>; | |
231 | }; | |
232 | ||
a6b6b478 YH |
233 | pmu { |
234 | compatible = "arm,armv8-pmuv3"; | |
235 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
236 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
237 | <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
238 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
239 | interrupt-affinity = <&a57_0>, | |
240 | <&a57_1>, | |
241 | <&a57_2>, | |
242 | <&a57_3>; | |
243 | }; | |
244 | ||
26a7e06d SH |
245 | timer { |
246 | compatible = "arm,armv8-timer"; | |
247 | interrupts = <GIC_PPI 13 | |
0ed1a79e | 248 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
26a7e06d | 249 | <GIC_PPI 14 |
0ed1a79e | 250 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
26a7e06d | 251 | <GIC_PPI 11 |
0ed1a79e | 252 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
26a7e06d | 253 | <GIC_PPI 10 |
0ed1a79e | 254 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
26a7e06d SH |
255 | }; |
256 | ||
257 | cpg: clock-controller@e6150000 { | |
258 | compatible = "renesas,r8a7795-cpg-mssr"; | |
259 | reg = <0 0xe6150000 0 0x1000>; | |
260 | clocks = <&extal_clk>, <&extalr_clk>; | |
261 | clock-names = "extal", "extalr"; | |
262 | #clock-cells = <2>; | |
263 | #power-domain-cells = <0>; | |
264 | }; | |
d9202126 | 265 | |
b281f4c8 KM |
266 | audma0: dma-controller@ec700000 { |
267 | compatible = "renesas,rcar-dmac"; | |
268 | reg = <0 0xec700000 0 0x10000>; | |
269 | interrupts = <0 350 IRQ_TYPE_LEVEL_HIGH | |
270 | 0 320 IRQ_TYPE_LEVEL_HIGH | |
271 | 0 321 IRQ_TYPE_LEVEL_HIGH | |
272 | 0 322 IRQ_TYPE_LEVEL_HIGH | |
273 | 0 323 IRQ_TYPE_LEVEL_HIGH | |
274 | 0 324 IRQ_TYPE_LEVEL_HIGH | |
275 | 0 325 IRQ_TYPE_LEVEL_HIGH | |
276 | 0 326 IRQ_TYPE_LEVEL_HIGH | |
277 | 0 327 IRQ_TYPE_LEVEL_HIGH | |
278 | 0 328 IRQ_TYPE_LEVEL_HIGH | |
279 | 0 329 IRQ_TYPE_LEVEL_HIGH | |
280 | 0 330 IRQ_TYPE_LEVEL_HIGH | |
281 | 0 331 IRQ_TYPE_LEVEL_HIGH | |
282 | 0 332 IRQ_TYPE_LEVEL_HIGH | |
283 | 0 333 IRQ_TYPE_LEVEL_HIGH | |
284 | 0 334 IRQ_TYPE_LEVEL_HIGH | |
285 | 0 335 IRQ_TYPE_LEVEL_HIGH>; | |
286 | interrupt-names = "error", | |
287 | "ch0", "ch1", "ch2", "ch3", | |
288 | "ch4", "ch5", "ch6", "ch7", | |
289 | "ch8", "ch9", "ch10", "ch11", | |
290 | "ch12", "ch13", "ch14", "ch15"; | |
291 | clocks = <&cpg CPG_MOD 502>; | |
292 | clock-names = "fck"; | |
293 | power-domains = <&cpg>; | |
294 | #dma-cells = <1>; | |
295 | dma-channels = <16>; | |
296 | }; | |
297 | ||
298 | audma1: dma-controller@ec720000 { | |
299 | compatible = "renesas,rcar-dmac"; | |
300 | reg = <0 0xec720000 0 0x10000>; | |
301 | interrupts = <0 351 IRQ_TYPE_LEVEL_HIGH | |
302 | 0 336 IRQ_TYPE_LEVEL_HIGH | |
303 | 0 337 IRQ_TYPE_LEVEL_HIGH | |
304 | 0 338 IRQ_TYPE_LEVEL_HIGH | |
305 | 0 339 IRQ_TYPE_LEVEL_HIGH | |
306 | 0 340 IRQ_TYPE_LEVEL_HIGH | |
307 | 0 341 IRQ_TYPE_LEVEL_HIGH | |
308 | 0 342 IRQ_TYPE_LEVEL_HIGH | |
309 | 0 343 IRQ_TYPE_LEVEL_HIGH | |
310 | 0 344 IRQ_TYPE_LEVEL_HIGH | |
311 | 0 345 IRQ_TYPE_LEVEL_HIGH | |
312 | 0 346 IRQ_TYPE_LEVEL_HIGH | |
313 | 0 347 IRQ_TYPE_LEVEL_HIGH | |
314 | 0 348 IRQ_TYPE_LEVEL_HIGH | |
315 | 0 349 IRQ_TYPE_LEVEL_HIGH | |
316 | 0 382 IRQ_TYPE_LEVEL_HIGH | |
317 | 0 383 IRQ_TYPE_LEVEL_HIGH>; | |
318 | interrupt-names = "error", | |
319 | "ch0", "ch1", "ch2", "ch3", | |
320 | "ch4", "ch5", "ch6", "ch7", | |
321 | "ch8", "ch9", "ch10", "ch11", | |
322 | "ch12", "ch13", "ch14", "ch15"; | |
323 | clocks = <&cpg CPG_MOD 501>; | |
324 | clock-names = "fck"; | |
325 | power-domains = <&cpg>; | |
326 | #dma-cells = <1>; | |
327 | dma-channels = <16>; | |
328 | }; | |
329 | ||
9241844a KM |
330 | pfc: pfc@e6060000 { |
331 | compatible = "renesas,pfc-r8a7795"; | |
332 | reg = <0 0xe6060000 0 0x50c>; | |
333 | }; | |
334 | ||
d9202126 GU |
335 | dmac0: dma-controller@e6700000 { |
336 | /* Empty node for now */ | |
337 | }; | |
338 | ||
339 | dmac1: dma-controller@e7300000 { | |
340 | /* Empty node for now */ | |
341 | }; | |
342 | ||
343 | dmac2: dma-controller@e7310000 { | |
344 | /* Empty node for now */ | |
345 | }; | |
49af46b4 | 346 | |
a92843c8 KM |
347 | avb: ethernet@e6800000 { |
348 | compatible = "renesas,etheravb-r8a7795"; | |
349 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; | |
350 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
351 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
352 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
353 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
354 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
355 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
356 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
357 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
358 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
359 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
360 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
361 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
362 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
363 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
364 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
365 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
366 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
367 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
368 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
369 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
370 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
371 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
372 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
373 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
374 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
375 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
376 | "ch4", "ch5", "ch6", "ch7", | |
377 | "ch8", "ch9", "ch10", "ch11", | |
378 | "ch12", "ch13", "ch14", "ch15", | |
379 | "ch16", "ch17", "ch18", "ch19", | |
380 | "ch20", "ch21", "ch22", "ch23", | |
381 | "ch24"; | |
382 | clocks = <&cpg CPG_MOD 812>; | |
383 | power-domains = <&cpg>; | |
384 | phy-mode = "rgmii-id"; | |
385 | #address-cells = <1>; | |
386 | #size-cells = <0>; | |
387 | }; | |
388 | ||
4fa04299 GU |
389 | hscif0: serial@e6540000 { |
390 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
391 | reg = <0 0xe6540000 0 96>; | |
392 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
393 | clocks = <&cpg CPG_MOD 520>; | |
394 | clock-names = "sci_ick"; | |
395 | dmas = <&dmac1 0x31>, <&dmac1 0x30>; | |
396 | dma-names = "tx", "rx"; | |
397 | power-domains = <&cpg>; | |
398 | status = "disabled"; | |
399 | }; | |
400 | ||
401 | hscif1: serial@e6550000 { | |
402 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
403 | reg = <0 0xe6550000 0 96>; | |
404 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
405 | clocks = <&cpg CPG_MOD 519>; | |
406 | clock-names = "sci_ick"; | |
407 | dmas = <&dmac1 0x33>, <&dmac1 0x32>; | |
408 | dma-names = "tx", "rx"; | |
409 | power-domains = <&cpg>; | |
410 | status = "disabled"; | |
411 | }; | |
412 | ||
413 | hscif2: serial@e6560000 { | |
414 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
415 | reg = <0 0xe6560000 0 96>; | |
416 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
417 | clocks = <&cpg CPG_MOD 518>; | |
418 | clock-names = "sci_ick"; | |
419 | dmas = <&dmac1 0x35>, <&dmac1 0x34>; | |
420 | dma-names = "tx", "rx"; | |
421 | power-domains = <&cpg>; | |
422 | status = "disabled"; | |
423 | }; | |
424 | ||
425 | hscif3: serial@e66a0000 { | |
426 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
427 | reg = <0 0xe66a0000 0 96>; | |
428 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
429 | clocks = <&cpg CPG_MOD 517>; | |
430 | clock-names = "sci_ick"; | |
431 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; | |
432 | dma-names = "tx", "rx"; | |
433 | power-domains = <&cpg>; | |
434 | status = "disabled"; | |
435 | }; | |
436 | ||
437 | hscif4: serial@e66b0000 { | |
438 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
439 | reg = <0 0xe66b0000 0 96>; | |
440 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
441 | clocks = <&cpg CPG_MOD 516>; | |
442 | clock-names = "sci_ick"; | |
443 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; | |
444 | dma-names = "tx", "rx"; | |
445 | power-domains = <&cpg>; | |
446 | status = "disabled"; | |
447 | }; | |
448 | ||
49af46b4 GU |
449 | scif0: serial@e6e60000 { |
450 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
451 | reg = <0 0xe6e60000 0 64>; | |
452 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
453 | clocks = <&cpg CPG_MOD 207>; | |
454 | clock-names = "sci_ick"; | |
455 | dmas = <&dmac1 0x51>, <&dmac1 0x50>; | |
456 | dma-names = "tx", "rx"; | |
457 | power-domains = <&cpg>; | |
458 | status = "disabled"; | |
459 | }; | |
460 | ||
461 | scif1: serial@e6e68000 { | |
462 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
463 | reg = <0 0xe6e68000 0 64>; | |
464 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
465 | clocks = <&cpg CPG_MOD 206>; | |
466 | clock-names = "sci_ick"; | |
467 | dmas = <&dmac1 0x53>, <&dmac1 0x52>; | |
468 | dma-names = "tx", "rx"; | |
469 | power-domains = <&cpg>; | |
470 | status = "disabled"; | |
471 | }; | |
472 | ||
473 | scif2: serial@e6e88000 { | |
474 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
475 | reg = <0 0xe6e88000 0 64>; | |
476 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
477 | clocks = <&cpg CPG_MOD 310>; | |
478 | clock-names = "sci_ick"; | |
479 | dmas = <&dmac1 0x13>, <&dmac1 0x12>; | |
480 | dma-names = "tx", "rx"; | |
481 | power-domains = <&cpg>; | |
482 | status = "disabled"; | |
483 | }; | |
484 | ||
485 | scif3: serial@e6c50000 { | |
486 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
487 | reg = <0 0xe6c50000 0 64>; | |
488 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
489 | clocks = <&cpg CPG_MOD 204>; | |
490 | clock-names = "sci_ick"; | |
491 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
492 | dma-names = "tx", "rx"; | |
493 | power-domains = <&cpg>; | |
494 | status = "disabled"; | |
495 | }; | |
496 | ||
497 | scif4: serial@e6c40000 { | |
498 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
499 | reg = <0 0xe6c40000 0 64>; | |
500 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
501 | clocks = <&cpg CPG_MOD 203>; | |
502 | clock-names = "sci_ick"; | |
503 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
504 | dma-names = "tx", "rx"; | |
505 | power-domains = <&cpg>; | |
506 | status = "disabled"; | |
507 | }; | |
508 | ||
509 | scif5: serial@e6f30000 { | |
510 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
511 | reg = <0 0xe6f30000 0 64>; | |
512 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
513 | clocks = <&cpg CPG_MOD 202>; | |
514 | clock-names = "sci_ick"; | |
515 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; | |
516 | dma-names = "tx", "rx"; | |
517 | power-domains = <&cpg>; | |
518 | status = "disabled"; | |
519 | }; | |
32bc0c51 KM |
520 | |
521 | i2c0: i2c@e6500000 { | |
522 | #address-cells = <1>; | |
523 | #size-cells = <0>; | |
524 | compatible = "renesas,i2c-r8a7795"; | |
525 | reg = <0 0xe6500000 0 0x40>; | |
526 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
527 | clocks = <&cpg CPG_MOD 931>; | |
528 | power-domains = <&cpg>; | |
9036a730 | 529 | i2c-scl-internal-delay-ns = <110>; |
32bc0c51 KM |
530 | status = "disabled"; |
531 | }; | |
532 | ||
533 | i2c1: i2c@e6508000 { | |
534 | #address-cells = <1>; | |
535 | #size-cells = <0>; | |
536 | compatible = "renesas,i2c-r8a7795"; | |
537 | reg = <0 0xe6508000 0 0x40>; | |
538 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
539 | clocks = <&cpg CPG_MOD 930>; | |
540 | power-domains = <&cpg>; | |
9036a730 | 541 | i2c-scl-internal-delay-ns = <6>; |
32bc0c51 KM |
542 | status = "disabled"; |
543 | }; | |
544 | ||
545 | i2c2: i2c@e6510000 { | |
546 | #address-cells = <1>; | |
547 | #size-cells = <0>; | |
548 | compatible = "renesas,i2c-r8a7795"; | |
549 | reg = <0 0xe6510000 0 0x40>; | |
550 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
551 | clocks = <&cpg CPG_MOD 929>; | |
552 | power-domains = <&cpg>; | |
9036a730 | 553 | i2c-scl-internal-delay-ns = <6>; |
32bc0c51 KM |
554 | status = "disabled"; |
555 | }; | |
556 | ||
557 | i2c3: i2c@e66d0000 { | |
558 | #address-cells = <1>; | |
559 | #size-cells = <0>; | |
560 | compatible = "renesas,i2c-r8a7795"; | |
561 | reg = <0 0xe66d0000 0 0x40>; | |
562 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
563 | clocks = <&cpg CPG_MOD 928>; | |
564 | power-domains = <&cpg>; | |
9036a730 | 565 | i2c-scl-internal-delay-ns = <110>; |
32bc0c51 KM |
566 | status = "disabled"; |
567 | }; | |
568 | ||
569 | i2c4: i2c@e66d8000 { | |
570 | #address-cells = <1>; | |
571 | #size-cells = <0>; | |
572 | compatible = "renesas,i2c-r8a7795"; | |
573 | reg = <0 0xe66d8000 0 0x40>; | |
574 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
575 | clocks = <&cpg CPG_MOD 927>; | |
576 | power-domains = <&cpg>; | |
9036a730 | 577 | i2c-scl-internal-delay-ns = <110>; |
32bc0c51 KM |
578 | status = "disabled"; |
579 | }; | |
580 | ||
581 | i2c5: i2c@e66e0000 { | |
582 | #address-cells = <1>; | |
583 | #size-cells = <0>; | |
584 | compatible = "renesas,i2c-r8a7795"; | |
585 | reg = <0 0xe66e0000 0 0x40>; | |
586 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
587 | clocks = <&cpg CPG_MOD 919>; | |
588 | power-domains = <&cpg>; | |
9036a730 | 589 | i2c-scl-internal-delay-ns = <110>; |
32bc0c51 KM |
590 | status = "disabled"; |
591 | }; | |
592 | ||
593 | i2c6: i2c@e66e8000 { | |
594 | #address-cells = <1>; | |
595 | #size-cells = <0>; | |
596 | compatible = "renesas,i2c-r8a7795"; | |
597 | reg = <0 0xe66e8000 0 0x40>; | |
598 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
599 | clocks = <&cpg CPG_MOD 918>; | |
600 | power-domains = <&cpg>; | |
9036a730 | 601 | i2c-scl-internal-delay-ns = <6>; |
32bc0c51 KM |
602 | status = "disabled"; |
603 | }; | |
623197b9 KM |
604 | |
605 | rcar_sound: sound@ec500000 { | |
606 | /* | |
607 | * #sound-dai-cells is required | |
608 | * | |
609 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
610 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
611 | */ | |
612 | /* | |
613 | * #clock-cells is required for audio_clkout0/1/2/3 | |
614 | * | |
615 | * clkout : #clock-cells = <0>; <&rcar_sound>; | |
616 | * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; | |
617 | */ | |
618 | compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; | |
619 | reg = <0 0xec500000 0 0x1000>, /* SCU */ | |
620 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
621 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
622 | <0 0xec541000 0 0x280>, /* SSI */ | |
623 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ | |
624 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; | |
625 | ||
626 | clocks = <&cpg CPG_MOD 1005>, | |
627 | <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, | |
628 | <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, | |
629 | <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, | |
630 | <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, | |
631 | <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, | |
b868ff51 KM |
632 | <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, |
633 | <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, | |
634 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | |
635 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | |
636 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | |
b9dd9450 | 637 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
623197b9 KM |
638 | <&audio_clk_a>, <&audio_clk_b>, |
639 | <&audio_clk_c>, | |
640 | <&cpg CPG_CORE R8A7795_CLK_S0D4>; | |
641 | clock-names = "ssi-all", | |
642 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
643 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
644 | "ssi.1", "ssi.0", | |
b868ff51 KM |
645 | "src.9", "src.8", "src.7", "src.6", |
646 | "src.5", "src.4", "src.3", "src.2", | |
647 | "src.1", "src.0", | |
b9dd9450 | 648 | "dvc.0", "dvc.1", |
623197b9 KM |
649 | "clk_a", "clk_b", "clk_c", "clk_i"; |
650 | power-domains = <&cpg>; | |
651 | status = "disabled"; | |
652 | ||
b9dd9450 KM |
653 | rcar_sound,dvc { |
654 | dvc0: dvc@0 { | |
655 | dmas = <&audma0 0xbc>; | |
656 | dma-names = "tx"; | |
657 | }; | |
658 | dvc1: dvc@1 { | |
659 | dmas = <&audma0 0xbe>; | |
660 | dma-names = "tx"; | |
661 | }; | |
662 | }; | |
663 | ||
b868ff51 KM |
664 | rcar_sound,src { |
665 | src0: src@0 { | |
666 | interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; | |
667 | dmas = <&audma0 0x85>, <&audma1 0x9a>; | |
668 | dma-names = "rx", "tx"; | |
669 | }; | |
670 | src1: src@1 { | |
671 | interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; | |
672 | dmas = <&audma0 0x87>, <&audma1 0x9c>; | |
673 | dma-names = "rx", "tx"; | |
674 | }; | |
675 | src2: src@2 { | |
676 | interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; | |
677 | dmas = <&audma0 0x89>, <&audma1 0x9e>; | |
678 | dma-names = "rx", "tx"; | |
679 | }; | |
680 | src3: src@3 { | |
681 | interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; | |
682 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; | |
683 | dma-names = "rx", "tx"; | |
684 | }; | |
685 | src4: src@4 { | |
686 | interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; | |
687 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; | |
688 | dma-names = "rx", "tx"; | |
689 | }; | |
690 | src5: src@5 { | |
691 | interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; | |
692 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; | |
693 | dma-names = "rx", "tx"; | |
694 | }; | |
695 | src6: src@6 { | |
696 | interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; | |
697 | dmas = <&audma0 0x91>, <&audma1 0xb4>; | |
698 | dma-names = "rx", "tx"; | |
699 | }; | |
700 | src7: src@7 { | |
701 | interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; | |
702 | dmas = <&audma0 0x93>, <&audma1 0xb6>; | |
703 | dma-names = "rx", "tx"; | |
704 | }; | |
705 | src8: src@8 { | |
706 | interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; | |
707 | dmas = <&audma0 0x95>, <&audma1 0xb8>; | |
708 | dma-names = "rx", "tx"; | |
709 | }; | |
710 | src9: src@9 { | |
711 | interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; | |
712 | dmas = <&audma0 0x97>, <&audma1 0xba>; | |
713 | dma-names = "rx", "tx"; | |
714 | }; | |
715 | }; | |
716 | ||
623197b9 KM |
717 | rcar_sound,ssi { |
718 | ssi0: ssi@0 { | |
719 | interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
720 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; |
721 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
722 | }; |
723 | ssi1: ssi@1 { | |
724 | interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
725 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; |
726 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
727 | }; |
728 | ssi2: ssi@2 { | |
729 | interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
730 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; |
731 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
732 | }; |
733 | ssi3: ssi@3 { | |
734 | interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
735 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; |
736 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
737 | }; |
738 | ssi4: ssi@4 { | |
739 | interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
740 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; |
741 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
742 | }; |
743 | ssi5: ssi@5 { | |
744 | interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
745 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; |
746 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
747 | }; |
748 | ssi6: ssi@6 { | |
749 | interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
750 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; |
751 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
752 | }; |
753 | ssi7: ssi@7 { | |
754 | interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
755 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; |
756 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
757 | }; |
758 | ssi8: ssi@8 { | |
759 | interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
760 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; |
761 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
762 | }; |
763 | ssi9: ssi@9 { | |
764 | interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; | |
10d18ab8 KM |
765 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; |
766 | dma-names = "rx", "tx", "rxu", "txu"; | |
623197b9 KM |
767 | }; |
768 | }; | |
769 | }; | |
26a7e06d SH |
770 | }; |
771 | }; |