projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| cba59c25 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 26a7e06d | 2 | /* |
| e18a31a7 | 3 | * Device Tree Source for the R-Car H3 (R8A77950) SoC |
| 26a7e06d SH |
4 | * |
| 5 | * Copyright (C) 2015 Renesas Electronics Corp. | |
| 26a7e06d SH |
6 | */ |
| 7 | ||
| 49af46b4 | 8 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
| 26a7e06d | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| abbecab1 | 10 | #include <dt-bindings/power/r8a7795-sysc.h> |
| 26a7e06d | 11 | |
| 6fad293d GU |
12 | #define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 |
| 13 | ||
| 26a7e06d SH |
14 | / { |
| 15 | compatible = "renesas,r8a7795"; | |
| 16 | #address-cells = <2>; | |
| 17 | #size-cells = <2>; | |
| 18 | ||
| 32bc0c51 KM |
19 | aliases { |
| 20 | i2c0 = &i2c0; | |
| 21 | i2c1 = &i2c1; | |
| 22 | i2c2 = &i2c2; | |
| 23 | i2c3 = &i2c3; | |
| 24 | i2c4 = &i2c4; | |
| 25 | i2c5 = &i2c5; | |
| 26 | i2c6 = &i2c6; | |
| d7e0d64a | 27 | i2c7 = &i2c_dvfs; |
| 32bc0c51 KM |
28 | }; |
| 29 | ||
| 82cf1d15 SH |
30 | /* |
| 31 | * The external audio clocks are configured as 0 Hz fixed frequency | |
| 32 | * clocks by default. | |
| 33 | * Boards that provide audio clocks should override them. | |
| 34 | */ | |
| 35 | audio_clk_a: audio_clk_a { | |
| 36 | compatible = "fixed-clock"; | |
| 37 | #clock-cells = <0>; | |
| 38 | clock-frequency = <0>; | |
| 39 | }; | |
| 40 | ||
| 41 | audio_clk_b: audio_clk_b { | |
| 42 | compatible = "fixed-clock"; | |
| 43 | #clock-cells = <0>; | |
| 44 | clock-frequency = <0>; | |
| 45 | }; | |
| 46 | ||
| 47 | audio_clk_c: audio_clk_c { | |
| 48 | compatible = "fixed-clock"; | |
| 49 | #clock-cells = <0>; | |
| 50 | clock-frequency = <0>; | |
| 51 | }; | |
| 52 | ||
| 53 | /* External CAN clock - to be overridden by boards that provide it */ | |
| 54 | can_clk: can { | |
| 55 | compatible = "fixed-clock"; | |
| 56 | #clock-cells = <0>; | |
| 57 | clock-frequency = <0>; | |
| 58 | }; | |
| 59 | ||
| 60 | cluster0_opp: opp_table0 { | |
| 61 | compatible = "operating-points-v2"; | |
| 62 | opp-shared; | |
| 63 | ||
| 64 | opp-500000000 { | |
| 65 | opp-hz = /bits/ 64 <500000000>; | |
| 66 | opp-microvolt = <830000>; | |
| 67 | clock-latency-ns = <300000>; | |
| 68 | }; | |
| 69 | opp-1000000000 { | |
| 70 | opp-hz = /bits/ 64 <1000000000>; | |
| 71 | opp-microvolt = <830000>; | |
| 72 | clock-latency-ns = <300000>; | |
| 73 | }; | |
| 74 | opp-1500000000 { | |
| 75 | opp-hz = /bits/ 64 <1500000000>; | |
| 76 | opp-microvolt = <830000>; | |
| 77 | clock-latency-ns = <300000>; | |
| 78 | opp-suspend; | |
| 79 | }; | |
| 80 | opp-1600000000 { | |
| 81 | opp-hz = /bits/ 64 <1600000000>; | |
| 82 | opp-microvolt = <900000>; | |
| 83 | clock-latency-ns = <300000>; | |
| 84 | turbo-mode; | |
| 85 | }; | |
| 86 | opp-1700000000 { | |
| 87 | opp-hz = /bits/ 64 <1700000000>; | |
| 88 | opp-microvolt = <960000>; | |
| 89 | clock-latency-ns = <300000>; | |
| 90 | turbo-mode; | |
| 91 | }; | |
| 92 | }; | |
| 93 | ||
| 94 | cluster1_opp: opp_table1 { | |
| 95 | compatible = "operating-points-v2"; | |
| 96 | opp-shared; | |
| 97 | ||
| 98 | opp-800000000 { | |
| 99 | opp-hz = /bits/ 64 <800000000>; | |
| 100 | opp-microvolt = <820000>; | |
| 101 | clock-latency-ns = <300000>; | |
| 102 | }; | |
| 103 | opp-1000000000 { | |
| 104 | opp-hz = /bits/ 64 <1000000000>; | |
| 105 | opp-microvolt = <820000>; | |
| 106 | clock-latency-ns = <300000>; | |
| 107 | }; | |
| 108 | opp-1200000000 { | |
| 109 | opp-hz = /bits/ 64 <1200000000>; | |
| 110 | opp-microvolt = <820000>; | |
| 111 | clock-latency-ns = <300000>; | |
| 112 | }; | |
| 113 | }; | |
| 114 | ||
| 26a7e06d SH |
115 | cpus { |
| 116 | #address-cells = <1>; | |
| 117 | #size-cells = <0>; | |
| 118 | ||
| b380ae0d GI |
119 | cpu-map { |
| 120 | cluster0 { | |
| 121 | core0 { | |
| 122 | cpu = <&a57_0>; | |
| 123 | }; | |
| 124 | core1 { | |
| 125 | cpu = <&a57_1>; | |
| 126 | }; | |
| 127 | core2 { | |
| 128 | cpu = <&a57_2>; | |
| 129 | }; | |
| 130 | core3 { | |
| 131 | cpu = <&a57_3>; | |
| 132 | }; | |
| 133 | }; | |
| 134 | ||
| 135 | cluster1 { | |
| 136 | core0 { | |
| 137 | cpu = <&a53_0>; | |
| 138 | }; | |
| 139 | core1 { | |
| 140 | cpu = <&a53_1>; | |
| 141 | }; | |
| 142 | core2 { | |
| 143 | cpu = <&a53_2>; | |
| 144 | }; | |
| 145 | core3 { | |
| 146 | cpu = <&a53_3>; | |
| 147 | }; | |
| 148 | }; | |
| 149 | }; | |
| 150 | ||
| 26a7e06d | 151 | a57_0: cpu@0 { |
| 31af04cd | 152 | compatible = "arm,cortex-a57"; |
| 26a7e06d SH |
153 | reg = <0x0>; |
| 154 | device_type = "cpu"; | |
| abbecab1 | 155 | power-domains = <&sysc R8A7795_PD_CA57_CPU0>; |
| 7b337e61 | 156 | next-level-cache = <&L2_CA57>; |
| 12e51557 | 157 | enable-method = "psci"; |
| a3ba1169 | 158 | cpu-idle-states = <&CPU_SLEEP_0>; |
| 47e1714a | 159 | dynamic-power-coefficient = <854>; |
| fced3a97 | 160 | clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; |
| dd149e85 | 161 | operating-points-v2 = <&cluster0_opp>; |
| 2250d856 | 162 | capacity-dmips-mhz = <1024>; |
| 0c38c54e | 163 | #cooling-cells = <2>; |
| 26a7e06d | 164 | }; |
| 0ed1a79e GI |
165 | |
| 166 | a57_1: cpu@1 { | |
| 31af04cd | 167 | compatible = "arm,cortex-a57"; |
| 0ed1a79e GI |
168 | reg = <0x1>; |
| 169 | device_type = "cpu"; | |
| abbecab1 | 170 | power-domains = <&sysc R8A7795_PD_CA57_CPU1>; |
| 7b337e61 | 171 | next-level-cache = <&L2_CA57>; |
| 0ed1a79e | 172 | enable-method = "psci"; |
| a3ba1169 | 173 | cpu-idle-states = <&CPU_SLEEP_0>; |
| fced3a97 | 174 | clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; |
| dd149e85 | 175 | operating-points-v2 = <&cluster0_opp>; |
| 2250d856 | 176 | capacity-dmips-mhz = <1024>; |
| 0c38c54e | 177 | #cooling-cells = <2>; |
| 0ed1a79e | 178 | }; |
| a5547642 | 179 | |
| 0ed1a79e | 180 | a57_2: cpu@2 { |
| 31af04cd | 181 | compatible = "arm,cortex-a57"; |
| 0ed1a79e GI |
182 | reg = <0x2>; |
| 183 | device_type = "cpu"; | |
| abbecab1 | 184 | power-domains = <&sysc R8A7795_PD_CA57_CPU2>; |
| 7b337e61 | 185 | next-level-cache = <&L2_CA57>; |
| 0ed1a79e | 186 | enable-method = "psci"; |
| a3ba1169 | 187 | cpu-idle-states = <&CPU_SLEEP_0>; |
| fced3a97 | 188 | clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; |
| dd149e85 | 189 | operating-points-v2 = <&cluster0_opp>; |
| 2250d856 | 190 | capacity-dmips-mhz = <1024>; |
| 0c38c54e | 191 | #cooling-cells = <2>; |
| 0ed1a79e | 192 | }; |
| a5547642 | 193 | |
| 0ed1a79e | 194 | a57_3: cpu@3 { |
| 31af04cd | 195 | compatible = "arm,cortex-a57"; |
| 0ed1a79e GI |
196 | reg = <0x3>; |
| 197 | device_type = "cpu"; | |
| abbecab1 | 198 | power-domains = <&sysc R8A7795_PD_CA57_CPU3>; |
| 7b337e61 | 199 | next-level-cache = <&L2_CA57>; |
| 0ed1a79e | 200 | enable-method = "psci"; |
| a3ba1169 | 201 | cpu-idle-states = <&CPU_SLEEP_0>; |
| fced3a97 | 202 | clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; |
| dd149e85 | 203 | operating-points-v2 = <&cluster0_opp>; |
| 2250d856 | 204 | capacity-dmips-mhz = <1024>; |
| 0c38c54e | 205 | #cooling-cells = <2>; |
| 0ed1a79e | 206 | }; |
| 26a7e06d | 207 | |
| 799a75ab | 208 | a53_0: cpu@100 { |
| 31af04cd | 209 | compatible = "arm,cortex-a53"; |
| 799a75ab GU |
210 | reg = <0x100>; |
| 211 | device_type = "cpu"; | |
| 212 | power-domains = <&sysc R8A7795_PD_CA53_CPU0>; | |
| 213 | next-level-cache = <&L2_CA53>; | |
| 214 | enable-method = "psci"; | |
| fe87bde8 | 215 | cpu-idle-states = <&CPU_SLEEP_1>; |
| 15d8cd83 | 216 | #cooling-cells = <2>; |
| 47e1714a | 217 | dynamic-power-coefficient = <277>; |
| fced3a97 | 218 | clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; |
| dd149e85 | 219 | operating-points-v2 = <&cluster1_opp>; |
| 2250d856 | 220 | capacity-dmips-mhz = <535>; |
| 799a75ab GU |
221 | }; |
| 222 | ||
| 223 | a53_1: cpu@101 { | |
| 31af04cd | 224 | compatible = "arm,cortex-a53"; |
| 799a75ab GU |
225 | reg = <0x101>; |
| 226 | device_type = "cpu"; | |
| 227 | power-domains = <&sysc R8A7795_PD_CA53_CPU1>; | |
| 228 | next-level-cache = <&L2_CA53>; | |
| 229 | enable-method = "psci"; | |
| fe87bde8 | 230 | cpu-idle-states = <&CPU_SLEEP_1>; |
| fced3a97 | 231 | clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; |
| dd149e85 | 232 | operating-points-v2 = <&cluster1_opp>; |
| 2250d856 | 233 | capacity-dmips-mhz = <535>; |
| 799a75ab GU |
234 | }; |
| 235 | ||
| 236 | a53_2: cpu@102 { | |
| 31af04cd | 237 | compatible = "arm,cortex-a53"; |
| 799a75ab GU |
238 | reg = <0x102>; |
| 239 | device_type = "cpu"; | |
| 240 | power-domains = <&sysc R8A7795_PD_CA53_CPU2>; | |
| 241 | next-level-cache = <&L2_CA53>; | |
| 242 | enable-method = "psci"; | |
| fe87bde8 | 243 | cpu-idle-states = <&CPU_SLEEP_1>; |
| fced3a97 | 244 | clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; |
| dd149e85 | 245 | operating-points-v2 = <&cluster1_opp>; |
| 2250d856 | 246 | capacity-dmips-mhz = <535>; |
| 799a75ab GU |
247 | }; |
| 248 | ||
| 249 | a53_3: cpu@103 { | |
| 31af04cd | 250 | compatible = "arm,cortex-a53"; |
| 799a75ab GU |
251 | reg = <0x103>; |
| 252 | device_type = "cpu"; | |
| 253 | power-domains = <&sysc R8A7795_PD_CA53_CPU3>; | |
| 254 | next-level-cache = <&L2_CA53>; | |
| 255 | enable-method = "psci"; | |
| fe87bde8 | 256 | cpu-idle-states = <&CPU_SLEEP_1>; |
| fced3a97 | 257 | clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; |
| dd149e85 | 258 | operating-points-v2 = <&cluster1_opp>; |
| 2250d856 | 259 | capacity-dmips-mhz = <535>; |
| 799a75ab GU |
260 | }; |
| 261 | ||
| d165856d | 262 | L2_CA57: cache-controller-0 { |
| 6f7bf82c | 263 | compatible = "cache"; |
| 6f7bf82c GU |
264 | power-domains = <&sysc R8A7795_PD_CA57_SCU>; |
| 265 | cache-unified; | |
| 266 | cache-level = <2>; | |
| 267 | }; | |
| 7b337e61 | 268 | |
| d165856d | 269 | L2_CA53: cache-controller-1 { |
| 6f7bf82c | 270 | compatible = "cache"; |
| 6f7bf82c GU |
271 | power-domains = <&sysc R8A7795_PD_CA53_SCU>; |
| 272 | cache-unified; | |
| 273 | cache-level = <2>; | |
| 274 | }; | |
| a3ba1169 KN |
275 | |
| 276 | idle-states { | |
| 277 | entry-method = "psci"; | |
| 278 | ||
| 279 | CPU_SLEEP_0: cpu-sleep-0 { | |
| 280 | compatible = "arm,idle-state"; | |
| 281 | arm,psci-suspend-param = <0x0010000>; | |
| 282 | local-timer-stop; | |
| 283 | entry-latency-us = <400>; | |
| 284 | exit-latency-us = <500>; | |
| 285 | min-residency-us = <4000>; | |
| 286 | }; | |
| fe87bde8 DP |
287 | |
| 288 | CPU_SLEEP_1: cpu-sleep-1 { | |
| 289 | compatible = "arm,idle-state"; | |
| 290 | arm,psci-suspend-param = <0x0010000>; | |
| 291 | local-timer-stop; | |
| 292 | entry-latency-us = <700>; | |
| 293 | exit-latency-us = <700>; | |
| 294 | min-residency-us = <5000>; | |
| 295 | }; | |
| a3ba1169 | 296 | }; |
| 8e1c3aa3 GU |
297 | }; |
| 298 | ||
| 26a7e06d SH |
299 | extal_clk: extal { |
| 300 | compatible = "fixed-clock"; | |
| 301 | #clock-cells = <0>; | |
| 302 | /* This value must be overridden by the board */ | |
| 303 | clock-frequency = <0>; | |
| 304 | }; | |
| 305 | ||
| 306 | extalr_clk: extalr { | |
| 307 | compatible = "fixed-clock"; | |
| 308 | #clock-cells = <0>; | |
| 309 | /* This value must be overridden by the board */ | |
| 310 | clock-frequency = <0>; | |
| 311 | }; | |
| 312 | ||
| 9251024a PE |
313 | /* External PCIe clock - can be overridden by the board */ |
| 314 | pcie_bus_clk: pcie_bus { | |
| 315 | compatible = "fixed-clock"; | |
| 316 | #clock-cells = <0>; | |
| 9f33a8a9 | 317 | clock-frequency = <0>; |
| 9251024a PE |
318 | }; |
| 319 | ||
| 4f5dc77b SH |
320 | pmu_a53 { |
| 321 | compatible = "arm,cortex-a53-pmu"; | |
| 322 | interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, | |
| 323 | <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
| 324 | <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, | |
| 325 | <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 326 | interrupt-affinity = <&a53_0>, | |
| 327 | <&a53_1>, | |
| 328 | <&a53_2>, | |
| 329 | <&a53_3>; | |
| 330 | }; | |
| 331 | ||
| 82cf1d15 SH |
332 | pmu_a57 { |
| 333 | compatible = "arm,cortex-a57-pmu"; | |
| 334 | interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
| 399ec3ff | 335 | <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| 82cf1d15 SH |
336 | <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, |
| 337 | <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 338 | interrupt-affinity = <&a57_0>, | |
| 339 | <&a57_1>, | |
| 340 | <&a57_2>, | |
| 341 | <&a57_3>; | |
| 342 | }; | |
| 343 | ||
| 86af5aac SH |
344 | psci { |
| 345 | compatible = "arm,psci-1.0", "arm,psci-0.2"; | |
| 346 | method = "smc"; | |
| 347 | }; | |
| 348 | ||
| 1c6c924a SH |
349 | /* External SCIF clock - to be overridden by boards that provide it */ |
| 350 | scif_clk: scif { | |
| 351 | compatible = "fixed-clock"; | |
| 352 | #clock-cells = <0>; | |
| 353 | clock-frequency = <0>; | |
| 354 | }; | |
| 355 | ||
| 291e0c49 | 356 | soc: soc { |
| 26a7e06d SH |
357 | compatible = "simple-bus"; |
| 358 | interrupt-parent = <&gic>; | |
| 0ed1a79e | 359 | |
| 26a7e06d SH |
360 | #address-cells = <2>; |
| 361 | #size-cells = <2>; | |
| 362 | ranges; | |
| 363 | ||
| 0b65a9ad | 364 | rwdt: watchdog@e6020000 { |
| 3114815f WS |
365 | compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; |
| 366 | reg = <0 0xe6020000 0 0x0c>; | |
| 367 | clocks = <&cpg CPG_MOD 402>; | |
| b186fbb6 | 368 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 369 | resets = <&cpg 402>; |
| 3114815f WS |
370 | status = "disabled"; |
| 371 | }; | |
| 372 | ||
| 7b08623a TK |
373 | gpio0: gpio@e6050000 { |
| 374 | compatible = "renesas,gpio-r8a7795", | |
| d6d7037c | 375 | "renesas,rcar-gen3-gpio"; |
| 7b08623a TK |
376 | reg = <0 0xe6050000 0 0x50>; |
| 377 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| 378 | #gpio-cells = <2>; | |
| 379 | gpio-controller; | |
| 380 | gpio-ranges = <&pfc 0 0 16>; | |
| 381 | #interrupt-cells = <2>; | |
| 382 | interrupt-controller; | |
| 383 | clocks = <&cpg CPG_MOD 912>; | |
| 38dbb45e | 384 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 385 | resets = <&cpg 912>; |
| 7b08623a TK |
386 | }; |
| 387 | ||
| 388 | gpio1: gpio@e6051000 { | |
| 389 | compatible = "renesas,gpio-r8a7795", | |
| d6d7037c | 390 | "renesas,rcar-gen3-gpio"; |
| 7b08623a TK |
391 | reg = <0 0xe6051000 0 0x50>; |
| 392 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 393 | #gpio-cells = <2>; | |
| 394 | gpio-controller; | |
| eb14ed1a | 395 | gpio-ranges = <&pfc 0 32 29>; |
| 7b08623a TK |
396 | #interrupt-cells = <2>; |
| 397 | interrupt-controller; | |
| 398 | clocks = <&cpg CPG_MOD 911>; | |
| 38dbb45e | 399 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 400 | resets = <&cpg 911>; |
| 7b08623a TK |
401 | }; |
| 402 | ||
| 403 | gpio2: gpio@e6052000 { | |
| 404 | compatible = "renesas,gpio-r8a7795", | |
| d6d7037c | 405 | "renesas,rcar-gen3-gpio"; |
| 7b08623a TK |
406 | reg = <0 0xe6052000 0 0x50>; |
| 407 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 408 | #gpio-cells = <2>; | |
| 409 | gpio-controller; | |
| 410 | gpio-ranges = <&pfc 0 64 15>; | |
| 411 | #interrupt-cells = <2>; | |
| 412 | interrupt-controller; | |
| 413 | clocks = <&cpg CPG_MOD 910>; | |
| 38dbb45e | 414 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 415 | resets = <&cpg 910>; |
| 7b08623a TK |
416 | }; |
| 417 | ||
| 418 | gpio3: gpio@e6053000 { | |
| 419 | compatible = "renesas,gpio-r8a7795", | |
| d6d7037c | 420 | "renesas,rcar-gen3-gpio"; |
| 7b08623a TK |
421 | reg = <0 0xe6053000 0 0x50>; |
| 422 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 423 | #gpio-cells = <2>; | |
| 424 | gpio-controller; | |
| 425 | gpio-ranges = <&pfc 0 96 16>; | |
| 426 | #interrupt-cells = <2>; | |
| 427 | interrupt-controller; | |
| 428 | clocks = <&cpg CPG_MOD 909>; | |
| 38dbb45e | 429 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 430 | resets = <&cpg 909>; |
| 7b08623a TK |
431 | }; |
| 432 | ||
| 433 | gpio4: gpio@e6054000 { | |
| 434 | compatible = "renesas,gpio-r8a7795", | |
| d6d7037c | 435 | "renesas,rcar-gen3-gpio"; |
| 7b08623a TK |
436 | reg = <0 0xe6054000 0 0x50>; |
| 437 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 438 | #gpio-cells = <2>; | |
| 439 | gpio-controller; | |
| 440 | gpio-ranges = <&pfc 0 128 18>; | |
| 441 | #interrupt-cells = <2>; | |
| 442 | interrupt-controller; | |
| 443 | clocks = <&cpg CPG_MOD 908>; | |
| 38dbb45e | 444 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 445 | resets = <&cpg 908>; |
| 7b08623a TK |
446 | }; |
| 447 | ||
| 448 | gpio5: gpio@e6055000 { | |
| 449 | compatible = "renesas,gpio-r8a7795", | |
| d6d7037c | 450 | "renesas,rcar-gen3-gpio"; |
| 7b08623a TK |
451 | reg = <0 0xe6055000 0 0x50>; |
| 452 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 453 | #gpio-cells = <2>; | |
| 454 | gpio-controller; | |
| 455 | gpio-ranges = <&pfc 0 160 26>; | |
| 456 | #interrupt-cells = <2>; | |
| 457 | interrupt-controller; | |
| 458 | clocks = <&cpg CPG_MOD 907>; | |
| 38dbb45e | 459 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 460 | resets = <&cpg 907>; |
| 7b08623a TK |
461 | }; |
| 462 | ||
| 463 | gpio6: gpio@e6055400 { | |
| 464 | compatible = "renesas,gpio-r8a7795", | |
| d6d7037c | 465 | "renesas,rcar-gen3-gpio"; |
| 7b08623a TK |
466 | reg = <0 0xe6055400 0 0x50>; |
| 467 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 468 | #gpio-cells = <2>; | |
| 469 | gpio-controller; | |
| 470 | gpio-ranges = <&pfc 0 192 32>; | |
| 471 | #interrupt-cells = <2>; | |
| 472 | interrupt-controller; | |
| 473 | clocks = <&cpg CPG_MOD 906>; | |
| 38dbb45e | 474 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 475 | resets = <&cpg 906>; |
| 7b08623a TK |
476 | }; |
| 477 | ||
| 478 | gpio7: gpio@e6055800 { | |
| 479 | compatible = "renesas,gpio-r8a7795", | |
| d6d7037c | 480 | "renesas,rcar-gen3-gpio"; |
| 7b08623a TK |
481 | reg = <0 0xe6055800 0 0x50>; |
| 482 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 483 | #gpio-cells = <2>; | |
| 484 | gpio-controller; | |
| 485 | gpio-ranges = <&pfc 0 224 4>; | |
| 486 | #interrupt-cells = <2>; | |
| 487 | interrupt-controller; | |
| 488 | clocks = <&cpg CPG_MOD 905>; | |
| 38dbb45e | 489 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 490 | resets = <&cpg 905>; |
| 7b08623a TK |
491 | }; |
| 492 | ||
| e0f0bda7 SH |
493 | pfc: pin-controller@e6060000 { |
| 494 | compatible = "renesas,pfc-r8a7795"; | |
| 495 | reg = <0 0xe6060000 0 0x50c>; | |
| 496 | }; | |
| 497 | ||
| 720066d1 CVD |
498 | cmt0: timer@e60f0000 { |
| 499 | compatible = "renesas,r8a7795-cmt0", | |
| 500 | "renesas,rcar-gen3-cmt0"; | |
| 501 | reg = <0 0xe60f0000 0 0x1004>; | |
| 502 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
| 503 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
| 504 | clocks = <&cpg CPG_MOD 303>; | |
| 505 | clock-names = "fck"; | |
| 506 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 507 | resets = <&cpg 303>; | |
| 508 | status = "disabled"; | |
| 509 | }; | |
| 510 | ||
| 511 | cmt1: timer@e6130000 { | |
| 512 | compatible = "renesas,r8a7795-cmt1", | |
| 513 | "renesas,rcar-gen3-cmt1"; | |
| 514 | reg = <0 0xe6130000 0 0x1004>; | |
| 515 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, | |
| 516 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 517 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
| 518 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
| 519 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
| 520 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
| 521 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
| 522 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
| 523 | clocks = <&cpg CPG_MOD 302>; | |
| 524 | clock-names = "fck"; | |
| 525 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 526 | resets = <&cpg 302>; | |
| 527 | status = "disabled"; | |
| 528 | }; | |
| 529 | ||
| 530 | cmt2: timer@e6140000 { | |
| 531 | compatible = "renesas,r8a7795-cmt1", | |
| 532 | "renesas,rcar-gen3-cmt1"; | |
| 533 | reg = <0 0xe6140000 0 0x1004>; | |
| 534 | interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
| 535 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
| 536 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
| 537 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
| 538 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
| 539 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, | |
| 540 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
| 541 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; | |
| 542 | clocks = <&cpg CPG_MOD 301>; | |
| 543 | clock-names = "fck"; | |
| 544 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 545 | resets = <&cpg 301>; | |
| 546 | status = "disabled"; | |
| 547 | }; | |
| 548 | ||
| 549 | cmt3: timer@e6148000 { | |
| 550 | compatible = "renesas,r8a7795-cmt1", | |
| 551 | "renesas,rcar-gen3-cmt1"; | |
| 552 | reg = <0 0xe6148000 0 0x1004>; | |
| 553 | interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, | |
| 554 | <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, | |
| 555 | <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, | |
| 556 | <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, | |
| 557 | <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, | |
| 558 | <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, | |
| 559 | <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, | |
| 560 | <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; | |
| 561 | clocks = <&cpg CPG_MOD 300>; | |
| 562 | clock-names = "fck"; | |
| 563 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 564 | resets = <&cpg 300>; | |
| 565 | status = "disabled"; | |
| 566 | }; | |
| 567 | ||
| 26a7e06d SH |
568 | cpg: clock-controller@e6150000 { |
| 569 | compatible = "renesas,r8a7795-cpg-mssr"; | |
| 570 | reg = <0 0xe6150000 0 0x1000>; | |
| 571 | clocks = <&extal_clk>, <&extalr_clk>; | |
| 572 | clock-names = "extal", "extalr"; | |
| 573 | #clock-cells = <2>; | |
| 574 | #power-domain-cells = <0>; | |
| dcccc132 | 575 | #reset-cells = <1>; |
| 26a7e06d | 576 | }; |
| d9202126 | 577 | |
| 6ddbb4ce GU |
578 | rst: reset-controller@e6160000 { |
| 579 | compatible = "renesas,r8a7795-rst"; | |
| 580 | reg = <0 0xe6160000 0 0x0200>; | |
| 581 | }; | |
| 582 | ||
| abbecab1 GU |
583 | sysc: system-controller@e6180000 { |
| 584 | compatible = "renesas,r8a7795-sysc"; | |
| 585 | reg = <0 0xe6180000 0 0x0400>; | |
| 586 | #power-domain-cells = <1>; | |
| 587 | }; | |
| 588 | ||
| e0f0bda7 SH |
589 | tsc: thermal@e6198000 { |
| 590 | compatible = "renesas,r8a7795-thermal"; | |
| 591 | reg = <0 0xe6198000 0 0x100>, | |
| 592 | <0 0xe61a0000 0 0x100>, | |
| 593 | <0 0xe61a8000 0 0x100>; | |
| 594 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
| 595 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
| 596 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 597 | clocks = <&cpg CPG_MOD 522>; | |
| 598 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 599 | resets = <&cpg 522>; | |
| 600 | #thermal-sensor-cells = <1>; | |
| 9241844a KM |
601 | }; |
| 602 | ||
| 9c6c053c MD |
603 | intc_ex: interrupt-controller@e61c0000 { |
| 604 | compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; | |
| 605 | #interrupt-cells = <2>; | |
| 606 | interrupt-controller; | |
| 607 | reg = <0 0xe61c0000 0 0x200>; | |
| 608 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH | |
| 609 | GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH | |
| 610 | GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH | |
| 611 | GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH | |
| 612 | GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH | |
| 613 | GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; | |
| 614 | clocks = <&cpg CPG_MOD 407>; | |
| 38dbb45e | 615 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 616 | resets = <&cpg 407>; |
| 9c6c053c MD |
617 | }; |
| 618 | ||
| e0f0bda7 SH |
619 | i2c0: i2c@e6500000 { |
| 620 | #address-cells = <1>; | |
| 621 | #size-cells = <0>; | |
| 622 | compatible = "renesas,i2c-r8a7795", | |
| 623 | "renesas,rcar-gen3-i2c"; | |
| 624 | reg = <0 0xe6500000 0 0x40>; | |
| 625 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
| 626 | clocks = <&cpg CPG_MOD 931>; | |
| 3b7e7848 | 627 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
628 | resets = <&cpg 931>; |
| 629 | dmas = <&dmac1 0x91>, <&dmac1 0x90>, | |
| 630 | <&dmac2 0x91>, <&dmac2 0x90>; | |
| 631 | dma-names = "tx", "rx", "tx", "rx"; | |
| 632 | i2c-scl-internal-delay-ns = <110>; | |
| 633 | status = "disabled"; | |
| 3b7e7848 MD |
634 | }; |
| 635 | ||
| e0f0bda7 SH |
636 | i2c1: i2c@e6508000 { |
| 637 | #address-cells = <1>; | |
| 638 | #size-cells = <0>; | |
| 639 | compatible = "renesas,i2c-r8a7795", | |
| 640 | "renesas,rcar-gen3-i2c"; | |
| 641 | reg = <0 0xe6508000 0 0x40>; | |
| 642 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
| 643 | clocks = <&cpg CPG_MOD 930>; | |
| 3b7e7848 | 644 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
645 | resets = <&cpg 930>; |
| 646 | dmas = <&dmac1 0x93>, <&dmac1 0x92>, | |
| 647 | <&dmac2 0x93>, <&dmac2 0x92>; | |
| 648 | dma-names = "tx", "rx", "tx", "rx"; | |
| 649 | i2c-scl-internal-delay-ns = <6>; | |
| 3b7e7848 MD |
650 | status = "disabled"; |
| 651 | }; | |
| 652 | ||
| e0f0bda7 SH |
653 | i2c2: i2c@e6510000 { |
| 654 | #address-cells = <1>; | |
| 655 | #size-cells = <0>; | |
| 656 | compatible = "renesas,i2c-r8a7795", | |
| 657 | "renesas,rcar-gen3-i2c"; | |
| 658 | reg = <0 0xe6510000 0 0x40>; | |
| 659 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
| 660 | clocks = <&cpg CPG_MOD 929>; | |
| 661 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 662 | resets = <&cpg 929>; | |
| 663 | dmas = <&dmac1 0x95>, <&dmac1 0x94>, | |
| 664 | <&dmac2 0x95>, <&dmac2 0x94>; | |
| 665 | dma-names = "tx", "rx", "tx", "rx"; | |
| 666 | i2c-scl-internal-delay-ns = <6>; | |
| 3b7e7848 MD |
667 | status = "disabled"; |
| 668 | }; | |
| 669 | ||
| e0f0bda7 SH |
670 | i2c3: i2c@e66d0000 { |
| 671 | #address-cells = <1>; | |
| 672 | #size-cells = <0>; | |
| 673 | compatible = "renesas,i2c-r8a7795", | |
| 674 | "renesas,rcar-gen3-i2c"; | |
| 675 | reg = <0 0xe66d0000 0 0x40>; | |
| 676 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
| 677 | clocks = <&cpg CPG_MOD 928>; | |
| 678 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 679 | resets = <&cpg 928>; | |
| 680 | dmas = <&dmac0 0x97>, <&dmac0 0x96>; | |
| 681 | dma-names = "tx", "rx"; | |
| 682 | i2c-scl-internal-delay-ns = <110>; | |
| 3b7e7848 MD |
683 | status = "disabled"; |
| 684 | }; | |
| 685 | ||
| e0f0bda7 SH |
686 | i2c4: i2c@e66d8000 { |
| 687 | #address-cells = <1>; | |
| 688 | #size-cells = <0>; | |
| 689 | compatible = "renesas,i2c-r8a7795", | |
| 690 | "renesas,rcar-gen3-i2c"; | |
| 691 | reg = <0 0xe66d8000 0 0x40>; | |
| 692 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
| 693 | clocks = <&cpg CPG_MOD 927>; | |
| 694 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 695 | resets = <&cpg 927>; | |
| 696 | dmas = <&dmac0 0x99>, <&dmac0 0x98>; | |
| 697 | dma-names = "tx", "rx"; | |
| 698 | i2c-scl-internal-delay-ns = <110>; | |
| 3b7e7848 MD |
699 | status = "disabled"; |
| 700 | }; | |
| 701 | ||
| e0f0bda7 SH |
702 | i2c5: i2c@e66e0000 { |
| 703 | #address-cells = <1>; | |
| 704 | #size-cells = <0>; | |
| 705 | compatible = "renesas,i2c-r8a7795", | |
| 706 | "renesas,rcar-gen3-i2c"; | |
| 707 | reg = <0 0xe66e0000 0 0x40>; | |
| 708 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 709 | clocks = <&cpg CPG_MOD 919>; | |
| 3b7e7848 | 710 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
711 | resets = <&cpg 919>; |
| 712 | dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; | |
| 713 | dma-names = "tx", "rx"; | |
| 714 | i2c-scl-internal-delay-ns = <110>; | |
| 3b7e7848 MD |
715 | status = "disabled"; |
| 716 | }; | |
| 717 | ||
| e0f0bda7 SH |
718 | i2c6: i2c@e66e8000 { |
| 719 | #address-cells = <1>; | |
| 720 | #size-cells = <0>; | |
| 721 | compatible = "renesas,i2c-r8a7795", | |
| 722 | "renesas,rcar-gen3-i2c"; | |
| 723 | reg = <0 0xe66e8000 0 0x40>; | |
| 724 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
| 725 | clocks = <&cpg CPG_MOD 918>; | |
| 9dd660eb | 726 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
727 | resets = <&cpg 918>; |
| 728 | dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; | |
| 729 | dma-names = "tx", "rx"; | |
| 730 | i2c-scl-internal-delay-ns = <6>; | |
| 9dd660eb SH |
731 | status = "disabled"; |
| 732 | }; | |
| 733 | ||
| e0f0bda7 SH |
734 | i2c_dvfs: i2c@e60b0000 { |
| 735 | #address-cells = <1>; | |
| 736 | #size-cells = <0>; | |
| 737 | compatible = "renesas,iic-r8a7795", | |
| 738 | "renesas,rcar-gen3-iic", | |
| 739 | "renesas,rmobile-iic"; | |
| 740 | reg = <0 0xe60b0000 0 0x425>; | |
| 741 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; | |
| 742 | clocks = <&cpg CPG_MOD 926>; | |
| 3b7e7848 | 743 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
744 | resets = <&cpg 926>; |
| 745 | dmas = <&dmac0 0x11>, <&dmac0 0x10>; | |
| 746 | dma-names = "tx", "rx"; | |
| 3b7e7848 MD |
747 | status = "disabled"; |
| 748 | }; | |
| 749 | ||
| e0f0bda7 SH |
750 | hscif0: serial@e6540000 { |
| 751 | compatible = "renesas,hscif-r8a7795", | |
| 752 | "renesas,rcar-gen3-hscif", | |
| 753 | "renesas,hscif"; | |
| 754 | reg = <0 0xe6540000 0 96>; | |
| 755 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
| 756 | clocks = <&cpg CPG_MOD 520>, | |
| 757 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 758 | <&scif_clk>; | |
| 759 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 760 | dmas = <&dmac1 0x31>, <&dmac1 0x30>, | |
| 761 | <&dmac2 0x31>, <&dmac2 0x30>; | |
| 762 | dma-names = "tx", "rx", "tx", "rx"; | |
| 3b7e7848 | 763 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 764 | resets = <&cpg 520>; |
| 3b7e7848 MD |
765 | status = "disabled"; |
| 766 | }; | |
| 767 | ||
| e0f0bda7 SH |
768 | hscif1: serial@e6550000 { |
| 769 | compatible = "renesas,hscif-r8a7795", | |
| 770 | "renesas,rcar-gen3-hscif", | |
| 771 | "renesas,hscif"; | |
| 772 | reg = <0 0xe6550000 0 96>; | |
| 773 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
| 774 | clocks = <&cpg CPG_MOD 519>, | |
| 775 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 776 | <&scif_clk>; | |
| 777 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 778 | dmas = <&dmac1 0x33>, <&dmac1 0x32>, | |
| 779 | <&dmac2 0x33>, <&dmac2 0x32>; | |
| 780 | dma-names = "tx", "rx", "tx", "rx"; | |
| 781 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 782 | resets = <&cpg 519>; | |
| 3b7e7848 MD |
783 | status = "disabled"; |
| 784 | }; | |
| 785 | ||
| e0f0bda7 SH |
786 | hscif2: serial@e6560000 { |
| 787 | compatible = "renesas,hscif-r8a7795", | |
| 788 | "renesas,rcar-gen3-hscif", | |
| 789 | "renesas,hscif"; | |
| 790 | reg = <0 0xe6560000 0 96>; | |
| 791 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
| 792 | clocks = <&cpg CPG_MOD 518>, | |
| 793 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 794 | <&scif_clk>; | |
| 795 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 796 | dmas = <&dmac1 0x35>, <&dmac1 0x34>, | |
| 797 | <&dmac2 0x35>, <&dmac2 0x34>; | |
| aab7a241 | 798 | dma-names = "tx", "rx", "tx", "rx"; |
| 3b7e7848 | 799 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 800 | resets = <&cpg 518>; |
| 3b7e7848 MD |
801 | status = "disabled"; |
| 802 | }; | |
| 803 | ||
| e0f0bda7 SH |
804 | hscif3: serial@e66a0000 { |
| 805 | compatible = "renesas,hscif-r8a7795", | |
| 806 | "renesas,rcar-gen3-hscif", | |
| 807 | "renesas,hscif"; | |
| 808 | reg = <0 0xe66a0000 0 96>; | |
| 809 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
| 810 | clocks = <&cpg CPG_MOD 517>, | |
| 811 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 812 | <&scif_clk>; | |
| 813 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 814 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; | |
| 815 | dma-names = "tx", "rx"; | |
| 3b7e7848 | 816 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 817 | resets = <&cpg 517>; |
| 3b7e7848 MD |
818 | status = "disabled"; |
| 819 | }; | |
| 820 | ||
| e0f0bda7 SH |
821 | hscif4: serial@e66b0000 { |
| 822 | compatible = "renesas,hscif-r8a7795", | |
| 823 | "renesas,rcar-gen3-hscif", | |
| 824 | "renesas,hscif"; | |
| 825 | reg = <0 0xe66b0000 0 96>; | |
| 826 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
| 827 | clocks = <&cpg CPG_MOD 516>, | |
| 828 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 829 | <&scif_clk>; | |
| 830 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 831 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; | |
| 832 | dma-names = "tx", "rx"; | |
| 3b7e7848 | 833 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 834 | resets = <&cpg 516>; |
| 3b7e7848 MD |
835 | status = "disabled"; |
| 836 | }; | |
| 837 | ||
| e0f0bda7 SH |
838 | hsusb: usb@e6590000 { |
| 839 | compatible = "renesas,usbhs-r8a7795", | |
| 840 | "renesas,rcar-gen3-usbhs"; | |
| e67898dc | 841 | reg = <0 0xe6590000 0 0x200>; |
| e0f0bda7 | 842 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 737e05bf | 843 | clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; |
| e0f0bda7 SH |
844 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, |
| 845 | <&usb_dmac1 0>, <&usb_dmac1 1>; | |
| 846 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
| 847 | renesas,buswait = <11>; | |
| 7794bd7e | 848 | phys = <&usb2_phy0 3>; |
| e0f0bda7 | 849 | phy-names = "usb"; |
| 3b7e7848 | 850 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 737e05bf | 851 | resets = <&cpg 704>, <&cpg 703>; |
| e0f0bda7 | 852 | status = "disabled"; |
| 3b7e7848 MD |
853 | }; |
| 854 | ||
| e0f0bda7 SH |
855 | hsusb3: usb@e659c000 { |
| 856 | compatible = "renesas,usbhs-r8a7795", | |
| 857 | "renesas,rcar-gen3-usbhs"; | |
| e67898dc | 858 | reg = <0 0xe659c000 0 0x200>; |
| e0f0bda7 | 859 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 737e05bf | 860 | clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; |
| e0f0bda7 SH |
861 | dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, |
| 862 | <&usb_dmac3 0>, <&usb_dmac3 1>; | |
| 863 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
| 864 | renesas,buswait = <11>; | |
| 7794bd7e | 865 | phys = <&usb2_phy3 3>; |
| e0f0bda7 | 866 | phy-names = "usb"; |
| 3b7e7848 | 867 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 737e05bf | 868 | resets = <&cpg 705>, <&cpg 700>; |
| e0f0bda7 | 869 | status = "disabled"; |
| 3b7e7848 MD |
870 | }; |
| 871 | ||
| e0f0bda7 SH |
872 | usb_dmac0: dma-controller@e65a0000 { |
| 873 | compatible = "renesas,r8a7795-usb-dmac", | |
| 874 | "renesas,usb-dmac"; | |
| 875 | reg = <0 0xe65a0000 0 0x100>; | |
| 876 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH | |
| 877 | GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
| 878 | interrupt-names = "ch0", "ch1"; | |
| 879 | clocks = <&cpg CPG_MOD 330>; | |
| 3b7e7848 | 880 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
881 | resets = <&cpg 330>; |
| 882 | #dma-cells = <1>; | |
| 883 | dma-channels = <2>; | |
| 884 | }; | |
| 885 | ||
| 886 | usb_dmac1: dma-controller@e65b0000 { | |
| 887 | compatible = "renesas,r8a7795-usb-dmac", | |
| 888 | "renesas,usb-dmac"; | |
| 889 | reg = <0 0xe65b0000 0 0x100>; | |
| 890 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH | |
| 891 | GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
| 892 | interrupt-names = "ch0", "ch1"; | |
| 893 | clocks = <&cpg CPG_MOD 331>; | |
| 894 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 895 | resets = <&cpg 331>; | |
| 896 | #dma-cells = <1>; | |
| 897 | dma-channels = <2>; | |
| 898 | }; | |
| 899 | ||
| 900 | usb_dmac2: dma-controller@e6460000 { | |
| 901 | compatible = "renesas,r8a7795-usb-dmac", | |
| 902 | "renesas,usb-dmac"; | |
| 903 | reg = <0 0xe6460000 0 0x100>; | |
| 904 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH | |
| 905 | GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| 906 | interrupt-names = "ch0", "ch1"; | |
| 907 | clocks = <&cpg CPG_MOD 326>; | |
| 908 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 909 | resets = <&cpg 326>; | |
| 910 | #dma-cells = <1>; | |
| 911 | dma-channels = <2>; | |
| 912 | }; | |
| 913 | ||
| 914 | usb_dmac3: dma-controller@e6470000 { | |
| 915 | compatible = "renesas,r8a7795-usb-dmac", | |
| 916 | "renesas,usb-dmac"; | |
| 917 | reg = <0 0xe6470000 0 0x100>; | |
| 918 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH | |
| 919 | GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| 920 | interrupt-names = "ch0", "ch1"; | |
| 921 | clocks = <&cpg CPG_MOD 329>; | |
| 922 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 923 | resets = <&cpg 329>; | |
| 924 | #dma-cells = <1>; | |
| 925 | dma-channels = <2>; | |
| 926 | }; | |
| 927 | ||
| 928 | usb3_phy0: usb-phy@e65ee000 { | |
| 929 | compatible = "renesas,r8a7795-usb3-phy", | |
| 930 | "renesas,rcar-gen3-usb3-phy"; | |
| 931 | reg = <0 0xe65ee000 0 0x90>; | |
| 932 | clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, | |
| 933 | <&usb_extal_clk>; | |
| 934 | clock-names = "usb3-if", "usb3s_clk", "usb_extal"; | |
| 935 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 936 | resets = <&cpg 328>; | |
| 937 | #phy-cells = <0>; | |
| 938 | status = "disabled"; | |
| 3b7e7848 MD |
939 | }; |
| 940 | ||
| 8db067d5 GU |
941 | arm_cc630p: crypto@e6601000 { |
| 942 | compatible = "arm,cryptocell-630p-ree"; | |
| 943 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| 944 | reg = <0x0 0xe6601000 0 0x1000>; | |
| 945 | clocks = <&cpg CPG_MOD 229>; | |
| 946 | resets = <&cpg 229>; | |
| 947 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 948 | }; | |
| 949 | ||
| d9202126 | 950 | dmac0: dma-controller@e6700000 { |
| e2102cea GU |
951 | compatible = "renesas,dmac-r8a7795", |
| 952 | "renesas,rcar-dmac"; | |
| 953 | reg = <0 0xe6700000 0 0x10000>; | |
| 954 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH | |
| 955 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
| 956 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
| 957 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
| 958 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
| 959 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
| 960 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
| 961 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
| 962 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
| 963 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
| 964 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
| 965 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
| 966 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
| 967 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
| 968 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
| 969 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH | |
| 970 | GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; | |
| 971 | interrupt-names = "error", | |
| 972 | "ch0", "ch1", "ch2", "ch3", | |
| 973 | "ch4", "ch5", "ch6", "ch7", | |
| 974 | "ch8", "ch9", "ch10", "ch11", | |
| 975 | "ch12", "ch13", "ch14", "ch15"; | |
| 976 | clocks = <&cpg CPG_MOD 219>; | |
| 977 | clock-names = "fck"; | |
| 38dbb45e | 978 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 979 | resets = <&cpg 219>; |
| e2102cea GU |
980 | #dma-cells = <1>; |
| 981 | dma-channels = <16>; | |
| bf2ca657 MD |
982 | iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, |
| 983 | <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, | |
| 984 | <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, | |
| 985 | <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, | |
| 986 | <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, | |
| 987 | <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, | |
| 988 | <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, | |
| 989 | <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; | |
| d9202126 GU |
990 | }; |
| 991 | ||
| 992 | dmac1: dma-controller@e7300000 { | |
| e2102cea GU |
993 | compatible = "renesas,dmac-r8a7795", |
| 994 | "renesas,rcar-dmac"; | |
| 995 | reg = <0 0xe7300000 0 0x10000>; | |
| 996 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH | |
| 997 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
| 998 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
| 999 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
| 1000 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
| 1001 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
| 1002 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
| 1003 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
| 1004 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
| 1005 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
| 1006 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
| 1007 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
| 1008 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
| 1009 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
| 1010 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
| 1011 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH | |
| 1012 | GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; | |
| 1013 | interrupt-names = "error", | |
| 1014 | "ch0", "ch1", "ch2", "ch3", | |
| 1015 | "ch4", "ch5", "ch6", "ch7", | |
| 1016 | "ch8", "ch9", "ch10", "ch11", | |
| 1017 | "ch12", "ch13", "ch14", "ch15"; | |
| 1018 | clocks = <&cpg CPG_MOD 218>; | |
| 1019 | clock-names = "fck"; | |
| 38dbb45e | 1020 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1021 | resets = <&cpg 218>; |
| e2102cea GU |
1022 | #dma-cells = <1>; |
| 1023 | dma-channels = <16>; | |
| bf2ca657 MD |
1024 | iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, |
| 1025 | <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, | |
| 1026 | <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, | |
| 1027 | <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, | |
| 1028 | <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, | |
| 1029 | <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, | |
| 1030 | <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, | |
| 1031 | <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; | |
| d9202126 GU |
1032 | }; |
| 1033 | ||
| 1034 | dmac2: dma-controller@e7310000 { | |
| e2102cea GU |
1035 | compatible = "renesas,dmac-r8a7795", |
| 1036 | "renesas,rcar-dmac"; | |
| 1037 | reg = <0 0xe7310000 0 0x10000>; | |
| 1038 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH | |
| 1039 | GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH | |
| 1040 | GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH | |
| 1041 | GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH | |
| 1042 | GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH | |
| 1043 | GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH | |
| 1044 | GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH | |
| 1045 | GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH | |
| 1046 | GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH | |
| 1047 | GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH | |
| 1048 | GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH | |
| 1049 | GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH | |
| 1050 | GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH | |
| 1051 | GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH | |
| 1052 | GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH | |
| 1053 | GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH | |
| 1054 | GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; | |
| 1055 | interrupt-names = "error", | |
| 1056 | "ch0", "ch1", "ch2", "ch3", | |
| 1057 | "ch4", "ch5", "ch6", "ch7", | |
| 1058 | "ch8", "ch9", "ch10", "ch11", | |
| 1059 | "ch12", "ch13", "ch14", "ch15"; | |
| 1060 | clocks = <&cpg CPG_MOD 217>; | |
| 1061 | clock-names = "fck"; | |
| 38dbb45e | 1062 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1063 | resets = <&cpg 217>; |
| 769fa836 KM |
1064 | #dma-cells = <1>; |
| 1065 | dma-channels = <16>; | |
| bf2ca657 MD |
1066 | iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, |
| 1067 | <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, | |
| 1068 | <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, | |
| 1069 | <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, | |
| 1070 | <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, | |
| 1071 | <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, | |
| 1072 | <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, | |
| 1073 | <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; | |
| 769fa836 KM |
1074 | }; |
| 1075 | ||
| e0f0bda7 SH |
1076 | ipmmu_ds0: mmu@e6740000 { |
| 1077 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1078 | reg = <0 0xe6740000 0 0x1000>; | |
| 1079 | renesas,ipmmu-main = <&ipmmu_mm 0>; | |
| 769fa836 | 1080 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1081 | #iommu-cells = <1>; |
| 769fa836 KM |
1082 | }; |
| 1083 | ||
| e0f0bda7 SH |
1084 | ipmmu_ds1: mmu@e7740000 { |
| 1085 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1086 | reg = <0 0xe7740000 0 0x1000>; | |
| 1087 | renesas,ipmmu-main = <&ipmmu_mm 1>; | |
| 769fa836 | 1088 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1089 | #iommu-cells = <1>; |
| d9202126 | 1090 | }; |
| 49af46b4 | 1091 | |
| e0f0bda7 SH |
1092 | ipmmu_hc: mmu@e6570000 { |
| 1093 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1094 | reg = <0 0xe6570000 0 0x1000>; | |
| 1095 | renesas,ipmmu-main = <&ipmmu_mm 2>; | |
| 38dbb45e | 1096 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1097 | #iommu-cells = <1>; |
| a92843c8 KM |
1098 | }; |
| 1099 | ||
| e0f0bda7 SH |
1100 | ipmmu_ir: mmu@ff8b0000 { |
| 1101 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1102 | reg = <0 0xff8b0000 0 0x1000>; | |
| 1103 | renesas,ipmmu-main = <&ipmmu_mm 3>; | |
| 1104 | power-domains = <&sysc R8A7795_PD_A3IR>; | |
| 1105 | #iommu-cells = <1>; | |
| 308b7e4b RS |
1106 | }; |
| 1107 | ||
| e0f0bda7 SH |
1108 | ipmmu_mm: mmu@e67b0000 { |
| 1109 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1110 | reg = <0 0xe67b0000 0 0x1000>; | |
| 1111 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, | |
| 1112 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | |
| 38dbb45e | 1113 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1114 | #iommu-cells = <1>; |
| 308b7e4b RS |
1115 | }; |
| 1116 | ||
| e0f0bda7 SH |
1117 | ipmmu_mp0: mmu@ec670000 { |
| 1118 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1119 | reg = <0 0xec670000 0 0x1000>; | |
| 1120 | renesas,ipmmu-main = <&ipmmu_mm 4>; | |
| 162cd784 | 1121 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1122 | #iommu-cells = <1>; |
| 162cd784 RS |
1123 | }; |
| 1124 | ||
| e0f0bda7 SH |
1125 | ipmmu_pv0: mmu@fd800000 { |
| 1126 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1127 | reg = <0 0xfd800000 0 0x1000>; | |
| 1128 | renesas,ipmmu-main = <&ipmmu_mm 6>; | |
| 91662b1b | 1129 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1130 | #iommu-cells = <1>; |
| 91662b1b RS |
1131 | }; |
| 1132 | ||
| e0f0bda7 SH |
1133 | ipmmu_pv1: mmu@fd950000 { |
| 1134 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1135 | reg = <0 0xfd950000 0 0x1000>; | |
| 1136 | renesas,ipmmu-main = <&ipmmu_mm 7>; | |
| 91662b1b | 1137 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1138 | #iommu-cells = <1>; |
| 91662b1b RS |
1139 | }; |
| 1140 | ||
| e0f0bda7 SH |
1141 | ipmmu_pv2: mmu@fd960000 { |
| 1142 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1143 | reg = <0 0xfd960000 0 0x1000>; | |
| 1144 | renesas,ipmmu-main = <&ipmmu_mm 8>; | |
| 91662b1b | 1145 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1146 | #iommu-cells = <1>; |
| 91662b1b RS |
1147 | }; |
| 1148 | ||
| e0f0bda7 SH |
1149 | ipmmu_pv3: mmu@fd970000 { |
| 1150 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1151 | reg = <0 0xfd970000 0 0x1000>; | |
| 1152 | renesas,ipmmu-main = <&ipmmu_mm 9>; | |
| 91662b1b | 1153 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1154 | #iommu-cells = <1>; |
| 91662b1b RS |
1155 | }; |
| 1156 | ||
| e0f0bda7 SH |
1157 | ipmmu_rt: mmu@ffc80000 { |
| 1158 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1159 | reg = <0 0xffc80000 0 0x1000>; | |
| 1160 | renesas,ipmmu-main = <&ipmmu_mm 10>; | |
| 91662b1b | 1161 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1162 | #iommu-cells = <1>; |
| 91662b1b RS |
1163 | }; |
| 1164 | ||
| e0f0bda7 SH |
1165 | ipmmu_vc0: mmu@fe6b0000 { |
| 1166 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1167 | reg = <0 0xfe6b0000 0 0x1000>; | |
| 1168 | renesas,ipmmu-main = <&ipmmu_mm 12>; | |
| 1169 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
| 1170 | #iommu-cells = <1>; | |
| e0f0bda7 SH |
1171 | }; |
| 1172 | ||
| 1173 | ipmmu_vc1: mmu@fe6f0000 { | |
| 1174 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1175 | reg = <0 0xfe6f0000 0 0x1000>; | |
| 1176 | renesas,ipmmu-main = <&ipmmu_mm 13>; | |
| 1177 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
| 1178 | #iommu-cells = <1>; | |
| e0f0bda7 SH |
1179 | }; |
| 1180 | ||
| 1181 | ipmmu_vi0: mmu@febd0000 { | |
| 1182 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1183 | reg = <0 0xfebd0000 0 0x1000>; | |
| 1184 | renesas,ipmmu-main = <&ipmmu_mm 14>; | |
| 91662b1b | 1185 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1186 | #iommu-cells = <1>; |
| 1187 | }; | |
| 1188 | ||
| 1189 | ipmmu_vi1: mmu@febe0000 { | |
| 1190 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1191 | reg = <0 0xfebe0000 0 0x1000>; | |
| 1192 | renesas,ipmmu-main = <&ipmmu_mm 15>; | |
| 1193 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1194 | #iommu-cells = <1>; | |
| 91662b1b RS |
1195 | }; |
| 1196 | ||
| e0f0bda7 SH |
1197 | ipmmu_vp0: mmu@fe990000 { |
| 1198 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1199 | reg = <0 0xfe990000 0 0x1000>; | |
| 1200 | renesas,ipmmu-main = <&ipmmu_mm 16>; | |
| 1201 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| 1202 | #iommu-cells = <1>; | |
| e0f0bda7 SH |
1203 | }; |
| 1204 | ||
| 1205 | ipmmu_vp1: mmu@fe980000 { | |
| 1206 | compatible = "renesas,ipmmu-r8a7795"; | |
| 1207 | reg = <0 0xfe980000 0 0x1000>; | |
| 1208 | renesas,ipmmu-main = <&ipmmu_mm 17>; | |
| 1209 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| 1210 | #iommu-cells = <1>; | |
| 1211 | }; | |
| 1212 | ||
| 1213 | avb: ethernet@e6800000 { | |
| 1214 | compatible = "renesas,etheravb-r8a7795", | |
| 1215 | "renesas,etheravb-rcar-gen3"; | |
| 1216 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; | |
| 1217 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
| 1218 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
| 1219 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 1220 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
| 1221 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
| 1222 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
| 1223 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
| 1224 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
| 1225 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
| 1226 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
| 1227 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
| 1228 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
| 1229 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
| 1230 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
| 1231 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
| 1232 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
| 1233 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
| 1234 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
| 1235 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
| 1236 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
| 1237 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
| 1238 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
| 1239 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
| 1240 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
| 1241 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
| 1242 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
| 1243 | "ch4", "ch5", "ch6", "ch7", | |
| 1244 | "ch8", "ch9", "ch10", "ch11", | |
| 1245 | "ch12", "ch13", "ch14", "ch15", | |
| 1246 | "ch16", "ch17", "ch18", "ch19", | |
| 1247 | "ch20", "ch21", "ch22", "ch23", | |
| 1248 | "ch24"; | |
| 1249 | clocks = <&cpg CPG_MOD 812>; | |
| 91662b1b | 1250 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1251 | resets = <&cpg 812>; |
| 1252 | phy-mode = "rgmii"; | |
| 1253 | iommus = <&ipmmu_ds0 16>; | |
| 1254 | #address-cells = <1>; | |
| 1255 | #size-cells = <0>; | |
| 91662b1b RS |
1256 | status = "disabled"; |
| 1257 | }; | |
| 1258 | ||
| e0f0bda7 SH |
1259 | can0: can@e6c30000 { |
| 1260 | compatible = "renesas,can-r8a7795", | |
| 1261 | "renesas,rcar-gen3-can"; | |
| 1262 | reg = <0 0xe6c30000 0 0x1000>; | |
| 1263 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
| 1264 | clocks = <&cpg CPG_MOD 916>, | |
| 1265 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
| 1266 | <&can_clk>; | |
| 1267 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 1268 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
| 1269 | assigned-clock-rates = <40000000>; | |
| 91662b1b | 1270 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1271 | resets = <&cpg 916>; |
| 91662b1b RS |
1272 | status = "disabled"; |
| 1273 | }; | |
| 1274 | ||
| e0f0bda7 SH |
1275 | can1: can@e6c38000 { |
| 1276 | compatible = "renesas,can-r8a7795", | |
| 1277 | "renesas,rcar-gen3-can"; | |
| 1278 | reg = <0 0xe6c38000 0 0x1000>; | |
| 1279 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
| 1280 | clocks = <&cpg CPG_MOD 915>, | |
| 1281 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
| 1282 | <&can_clk>; | |
| 1283 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 1284 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
| 1285 | assigned-clock-rates = <40000000>; | |
| 38dbb45e | 1286 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1287 | resets = <&cpg 915>; |
| 4fa04299 GU |
1288 | status = "disabled"; |
| 1289 | }; | |
| 1290 | ||
| e0f0bda7 SH |
1291 | canfd: can@e66c0000 { |
| 1292 | compatible = "renesas,r8a7795-canfd", | |
| 1293 | "renesas,rcar-gen3-canfd"; | |
| 1294 | reg = <0 0xe66c0000 0 0x8000>; | |
| 1295 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, | |
| 1296 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 1297 | clocks = <&cpg CPG_MOD 914>, | |
| 1298 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
| 1299 | <&can_clk>; | |
| 1300 | clock-names = "fck", "canfd", "can_clk"; | |
| 1301 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
| 1302 | assigned-clock-rates = <40000000>; | |
| 38dbb45e | 1303 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1304 | resets = <&cpg 914>; |
| 4fa04299 | 1305 | status = "disabled"; |
| e0f0bda7 SH |
1306 | |
| 1307 | channel0 { | |
| 1308 | status = "disabled"; | |
| 1309 | }; | |
| 1310 | ||
| 1311 | channel1 { | |
| 1312 | status = "disabled"; | |
| 1313 | }; | |
| 4fa04299 GU |
1314 | }; |
| 1315 | ||
| e0f0bda7 SH |
1316 | pwm0: pwm@e6e30000 { |
| 1317 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1318 | reg = <0 0xe6e30000 0 0x8>; | |
| 1319 | clocks = <&cpg CPG_MOD 523>; | |
| 38dbb45e | 1320 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1321 | resets = <&cpg 523>; |
| 1322 | #pwm-cells = <2>; | |
| 4fa04299 GU |
1323 | status = "disabled"; |
| 1324 | }; | |
| 1325 | ||
| e0f0bda7 SH |
1326 | pwm1: pwm@e6e31000 { |
| 1327 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1328 | reg = <0 0xe6e31000 0 0x8>; | |
| 1329 | clocks = <&cpg CPG_MOD 523>; | |
| 38dbb45e | 1330 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1331 | resets = <&cpg 523>; |
| 1332 | #pwm-cells = <2>; | |
| 4fa04299 GU |
1333 | status = "disabled"; |
| 1334 | }; | |
| 1335 | ||
| e0f0bda7 SH |
1336 | pwm2: pwm@e6e32000 { |
| 1337 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1338 | reg = <0 0xe6e32000 0 0x8>; | |
| 1339 | clocks = <&cpg CPG_MOD 523>; | |
| 38dbb45e | 1340 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1341 | resets = <&cpg 523>; |
| 1342 | #pwm-cells = <2>; | |
| 4fa04299 GU |
1343 | status = "disabled"; |
| 1344 | }; | |
| 1345 | ||
| e0f0bda7 SH |
1346 | pwm3: pwm@e6e33000 { |
| 1347 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1348 | reg = <0 0xe6e33000 0 0x8>; | |
| 1349 | clocks = <&cpg CPG_MOD 523>; | |
| ecad187f | 1350 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1351 | resets = <&cpg 523>; |
| 1352 | #pwm-cells = <2>; | |
| ecad187f GU |
1353 | status = "disabled"; |
| 1354 | }; | |
| 1355 | ||
| e0f0bda7 SH |
1356 | pwm4: pwm@e6e34000 { |
| 1357 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1358 | reg = <0 0xe6e34000 0 0x8>; | |
| 1359 | clocks = <&cpg CPG_MOD 523>; | |
| ecad187f | 1360 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1361 | resets = <&cpg 523>; |
| 1362 | #pwm-cells = <2>; | |
| ecad187f GU |
1363 | status = "disabled"; |
| 1364 | }; | |
| 1365 | ||
| e0f0bda7 SH |
1366 | pwm5: pwm@e6e35000 { |
| 1367 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1368 | reg = <0 0xe6e35000 0 0x8>; | |
| 1369 | clocks = <&cpg CPG_MOD 523>; | |
| ecad187f | 1370 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1371 | resets = <&cpg 523>; |
| 1372 | #pwm-cells = <2>; | |
| ecad187f GU |
1373 | status = "disabled"; |
| 1374 | }; | |
| 1375 | ||
| e0f0bda7 SH |
1376 | pwm6: pwm@e6e36000 { |
| 1377 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1378 | reg = <0 0xe6e36000 0 0x8>; | |
| 1379 | clocks = <&cpg CPG_MOD 523>; | |
| ecad187f | 1380 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1381 | resets = <&cpg 523>; |
| 1382 | #pwm-cells = <2>; | |
| ecad187f GU |
1383 | status = "disabled"; |
| 1384 | }; | |
| 1385 | ||
| 49af46b4 | 1386 | scif0: serial@e6e60000 { |
| 653f502d GU |
1387 | compatible = "renesas,scif-r8a7795", |
| 1388 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
1389 | reg = <0 0xe6e60000 0 64>; |
| 1390 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
1391 | clocks = <&cpg CPG_MOD 207>, |
| 1392 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 1393 | <&scif_clk>; | |
| 1394 | clock-names = "fck", "brg_int", "scif_clk"; | |
| eb21089c GU |
1395 | dmas = <&dmac1 0x51>, <&dmac1 0x50>, |
| 1396 | <&dmac2 0x51>, <&dmac2 0x50>; | |
| 1397 | dma-names = "tx", "rx", "tx", "rx"; | |
| 38dbb45e | 1398 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1399 | resets = <&cpg 207>; |
| 49af46b4 GU |
1400 | status = "disabled"; |
| 1401 | }; | |
| 1402 | ||
| 1403 | scif1: serial@e6e68000 { | |
| 653f502d GU |
1404 | compatible = "renesas,scif-r8a7795", |
| 1405 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
1406 | reg = <0 0xe6e68000 0 64>; |
| 1407 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
1408 | clocks = <&cpg CPG_MOD 206>, |
| 1409 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 1410 | <&scif_clk>; | |
| 1411 | clock-names = "fck", "brg_int", "scif_clk"; | |
| eb21089c GU |
1412 | dmas = <&dmac1 0x53>, <&dmac1 0x52>, |
| 1413 | <&dmac2 0x53>, <&dmac2 0x52>; | |
| 1414 | dma-names = "tx", "rx", "tx", "rx"; | |
| 38dbb45e | 1415 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1416 | resets = <&cpg 206>; |
| 49af46b4 GU |
1417 | status = "disabled"; |
| 1418 | }; | |
| 1419 | ||
| 1420 | scif2: serial@e6e88000 { | |
| 653f502d GU |
1421 | compatible = "renesas,scif-r8a7795", |
| 1422 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
1423 | reg = <0 0xe6e88000 0 64>; |
| 1424 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
1425 | clocks = <&cpg CPG_MOD 310>, |
| 1426 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 1427 | <&scif_clk>; | |
| 1428 | clock-names = "fck", "brg_int", "scif_clk"; | |
| eb21089c GU |
1429 | dmas = <&dmac1 0x13>, <&dmac1 0x12>, |
| 1430 | <&dmac2 0x13>, <&dmac2 0x12>; | |
| 1431 | dma-names = "tx", "rx", "tx", "rx"; | |
| 38dbb45e | 1432 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1433 | resets = <&cpg 310>; |
| 49af46b4 GU |
1434 | status = "disabled"; |
| 1435 | }; | |
| 1436 | ||
| 1437 | scif3: serial@e6c50000 { | |
| 653f502d GU |
1438 | compatible = "renesas,scif-r8a7795", |
| 1439 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
1440 | reg = <0 0xe6c50000 0 64>; |
| 1441 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
1442 | clocks = <&cpg CPG_MOD 204>, |
| 1443 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 1444 | <&scif_clk>; | |
| 1445 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 49af46b4 GU |
1446 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; |
| 1447 | dma-names = "tx", "rx"; | |
| 38dbb45e | 1448 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1449 | resets = <&cpg 204>; |
| 49af46b4 GU |
1450 | status = "disabled"; |
| 1451 | }; | |
| 1452 | ||
| 1453 | scif4: serial@e6c40000 { | |
| 653f502d GU |
1454 | compatible = "renesas,scif-r8a7795", |
| 1455 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
1456 | reg = <0 0xe6c40000 0 64>; |
| 1457 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
1458 | clocks = <&cpg CPG_MOD 203>, |
| 1459 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 1460 | <&scif_clk>; | |
| 1461 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 49af46b4 GU |
1462 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; |
| 1463 | dma-names = "tx", "rx"; | |
| 38dbb45e | 1464 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1465 | resets = <&cpg 203>; |
| 49af46b4 GU |
1466 | status = "disabled"; |
| 1467 | }; | |
| 1468 | ||
| 1469 | scif5: serial@e6f30000 { | |
| 653f502d GU |
1470 | compatible = "renesas,scif-r8a7795", |
| 1471 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
1472 | reg = <0 0xe6f30000 0 64>; |
| 1473 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
1474 | clocks = <&cpg CPG_MOD 202>, |
| 1475 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 1476 | <&scif_clk>; | |
| 1477 | clock-names = "fck", "brg_int", "scif_clk"; | |
| eb21089c GU |
1478 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, |
| 1479 | <&dmac2 0x5b>, <&dmac2 0x5a>; | |
| 1480 | dma-names = "tx", "rx", "tx", "rx"; | |
| 38dbb45e | 1481 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1482 | resets = <&cpg 202>; |
| 49af46b4 GU |
1483 | status = "disabled"; |
| 1484 | }; | |
| 32bc0c51 | 1485 | |
| a461b5bf CVD |
1486 | tpu: pwm@e6e80000 { |
| 1487 | compatible = "renesas,tpu-r8a7795", "renesas,tpu"; | |
| 1488 | reg = <0 0xe6e80000 0 0x148>; | |
| 1489 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
| 1490 | clocks = <&cpg CPG_MOD 304>; | |
| 1491 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1492 | resets = <&cpg 304>; | |
| 1493 | #pwm-cells = <3>; | |
| 1494 | status = "disabled"; | |
| 1495 | }; | |
| 1496 | ||
| e0f0bda7 SH |
1497 | msiof0: spi@e6e90000 { |
| 1498 | compatible = "renesas,msiof-r8a7795", | |
| 1499 | "renesas,rcar-gen3-msiof"; | |
| 1500 | reg = <0 0xe6e90000 0 0x0064>; | |
| 1501 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
| 1502 | clocks = <&cpg CPG_MOD 211>; | |
| 1503 | dmas = <&dmac1 0x41>, <&dmac1 0x40>, | |
| 1504 | <&dmac2 0x41>, <&dmac2 0x40>; | |
| eb21089c | 1505 | dma-names = "tx", "rx", "tx", "rx"; |
| 38dbb45e | 1506 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 1507 | resets = <&cpg 211>; |
| 32bc0c51 KM |
1508 | #address-cells = <1>; |
| 1509 | #size-cells = <0>; | |
| 32bc0c51 KM |
1510 | status = "disabled"; |
| 1511 | }; | |
| 1512 | ||
| e0f0bda7 SH |
1513 | msiof1: spi@e6ea0000 { |
| 1514 | compatible = "renesas,msiof-r8a7795", | |
| 1515 | "renesas,rcar-gen3-msiof"; | |
| 1516 | reg = <0 0xe6ea0000 0 0x0064>; | |
| 1517 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; | |
| 1518 | clocks = <&cpg CPG_MOD 210>; | |
| 1519 | dmas = <&dmac1 0x43>, <&dmac1 0x42>, | |
| 1520 | <&dmac2 0x43>, <&dmac2 0x42>; | |
| 1521 | dma-names = "tx", "rx", "tx", "rx"; | |
| 38dbb45e | 1522 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1523 | resets = <&cpg 210>; |
| 1524 | #address-cells = <1>; | |
| 1525 | #size-cells = <0>; | |
| 32bc0c51 KM |
1526 | status = "disabled"; |
| 1527 | }; | |
| 1528 | ||
| e0f0bda7 SH |
1529 | msiof2: spi@e6c00000 { |
| 1530 | compatible = "renesas,msiof-r8a7795", | |
| 1531 | "renesas,rcar-gen3-msiof"; | |
| 1532 | reg = <0 0xe6c00000 0 0x0064>; | |
| 1533 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 1534 | clocks = <&cpg CPG_MOD 209>; | |
| 1535 | dmas = <&dmac0 0x45>, <&dmac0 0x44>; | |
| 1536 | dma-names = "tx", "rx"; | |
| 1537 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1538 | resets = <&cpg 209>; | |
| 32bc0c51 KM |
1539 | #address-cells = <1>; |
| 1540 | #size-cells = <0>; | |
| 32bc0c51 KM |
1541 | status = "disabled"; |
| 1542 | }; | |
| 1543 | ||
| e0f0bda7 SH |
1544 | msiof3: spi@e6c10000 { |
| 1545 | compatible = "renesas,msiof-r8a7795", | |
| 1546 | "renesas,rcar-gen3-msiof"; | |
| 1547 | reg = <0 0xe6c10000 0 0x0064>; | |
| 1548 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; | |
| 1549 | clocks = <&cpg CPG_MOD 208>; | |
| 1550 | dmas = <&dmac0 0x47>, <&dmac0 0x46>; | |
| 1551 | dma-names = "tx", "rx"; | |
| 1552 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1553 | resets = <&cpg 208>; | |
| 32bc0c51 KM |
1554 | #address-cells = <1>; |
| 1555 | #size-cells = <0>; | |
| 32bc0c51 KM |
1556 | status = "disabled"; |
| 1557 | }; | |
| 1558 | ||
| 15da7132 NS |
1559 | vin0: video@e6ef0000 { |
| 1560 | compatible = "renesas,vin-r8a7795"; | |
| 1561 | reg = <0 0xe6ef0000 0 0x1000>; | |
| 1562 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | |
| 1563 | clocks = <&cpg CPG_MOD 811>; | |
| 1564 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1565 | resets = <&cpg 811>; | |
| 1566 | renesas,id = <0>; | |
| 1567 | status = "disabled"; | |
| 1568 | ||
| 1569 | ports { | |
| 1570 | #address-cells = <1>; | |
| 1571 | #size-cells = <0>; | |
| 1572 | ||
| 1573 | port@1 { | |
| 1574 | #address-cells = <1>; | |
| 1575 | #size-cells = <0>; | |
| 1576 | ||
| 1577 | reg = <1>; | |
| 1578 | ||
| 1579 | vin0csi20: endpoint@0 { | |
| 1580 | reg = <0>; | |
| fced3a97 | 1581 | remote-endpoint = <&csi20vin0>; |
| 15da7132 NS |
1582 | }; |
| 1583 | vin0csi40: endpoint@2 { | |
| 1584 | reg = <2>; | |
| fced3a97 | 1585 | remote-endpoint = <&csi40vin0>; |
| 15da7132 NS |
1586 | }; |
| 1587 | }; | |
| 1588 | }; | |
| 1589 | }; | |
| 1590 | ||
| 1591 | vin1: video@e6ef1000 { | |
| 1592 | compatible = "renesas,vin-r8a7795"; | |
| 1593 | reg = <0 0xe6ef1000 0 0x1000>; | |
| 1594 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; | |
| 1595 | clocks = <&cpg CPG_MOD 810>; | |
| 1596 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1597 | resets = <&cpg 810>; | |
| 1598 | renesas,id = <1>; | |
| 1599 | status = "disabled"; | |
| 1600 | ||
| 1601 | ports { | |
| 1602 | #address-cells = <1>; | |
| 1603 | #size-cells = <0>; | |
| 1604 | ||
| 1605 | port@1 { | |
| 1606 | #address-cells = <1>; | |
| 1607 | #size-cells = <0>; | |
| 1608 | ||
| 1609 | reg = <1>; | |
| 1610 | ||
| 1611 | vin1csi20: endpoint@0 { | |
| 1612 | reg = <0>; | |
| fced3a97 | 1613 | remote-endpoint = <&csi20vin1>; |
| 15da7132 NS |
1614 | }; |
| 1615 | vin1csi40: endpoint@2 { | |
| 1616 | reg = <2>; | |
| fced3a97 | 1617 | remote-endpoint = <&csi40vin1>; |
| 15da7132 NS |
1618 | }; |
| 1619 | }; | |
| 1620 | }; | |
| 1621 | }; | |
| 1622 | ||
| 1623 | vin2: video@e6ef2000 { | |
| 1624 | compatible = "renesas,vin-r8a7795"; | |
| 1625 | reg = <0 0xe6ef2000 0 0x1000>; | |
| 1626 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | |
| 1627 | clocks = <&cpg CPG_MOD 809>; | |
| 1628 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1629 | resets = <&cpg 809>; | |
| 1630 | renesas,id = <2>; | |
| 1631 | status = "disabled"; | |
| 1632 | ||
| 1633 | ports { | |
| 1634 | #address-cells = <1>; | |
| 1635 | #size-cells = <0>; | |
| 1636 | ||
| 1637 | port@1 { | |
| 1638 | #address-cells = <1>; | |
| 1639 | #size-cells = <0>; | |
| 1640 | ||
| 1641 | reg = <1>; | |
| 1642 | ||
| 1643 | vin2csi20: endpoint@0 { | |
| 1644 | reg = <0>; | |
| fced3a97 | 1645 | remote-endpoint = <&csi20vin2>; |
| 15da7132 NS |
1646 | }; |
| 1647 | vin2csi40: endpoint@2 { | |
| 1648 | reg = <2>; | |
| fced3a97 | 1649 | remote-endpoint = <&csi40vin2>; |
| 15da7132 NS |
1650 | }; |
| 1651 | }; | |
| 1652 | }; | |
| 1653 | }; | |
| 1654 | ||
| 1655 | vin3: video@e6ef3000 { | |
| 1656 | compatible = "renesas,vin-r8a7795"; | |
| 1657 | reg = <0 0xe6ef3000 0 0x1000>; | |
| 1658 | interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; | |
| 1659 | clocks = <&cpg CPG_MOD 808>; | |
| 1660 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1661 | resets = <&cpg 808>; | |
| 1662 | renesas,id = <3>; | |
| 1663 | status = "disabled"; | |
| 1664 | ||
| 1665 | ports { | |
| 1666 | #address-cells = <1>; | |
| 1667 | #size-cells = <0>; | |
| 1668 | ||
| 1669 | port@1 { | |
| 1670 | #address-cells = <1>; | |
| 1671 | #size-cells = <0>; | |
| 1672 | ||
| 1673 | reg = <1>; | |
| 1674 | ||
| 1675 | vin3csi20: endpoint@0 { | |
| 1676 | reg = <0>; | |
| fced3a97 | 1677 | remote-endpoint = <&csi20vin3>; |
| 15da7132 NS |
1678 | }; |
| 1679 | vin3csi40: endpoint@2 { | |
| 1680 | reg = <2>; | |
| fced3a97 | 1681 | remote-endpoint = <&csi40vin3>; |
| 15da7132 NS |
1682 | }; |
| 1683 | }; | |
| 1684 | }; | |
| 1685 | }; | |
| 1686 | ||
| 1687 | vin4: video@e6ef4000 { | |
| 1688 | compatible = "renesas,vin-r8a7795"; | |
| 1689 | reg = <0 0xe6ef4000 0 0x1000>; | |
| 1690 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; | |
| 1691 | clocks = <&cpg CPG_MOD 807>; | |
| 1692 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1693 | resets = <&cpg 807>; | |
| 1694 | renesas,id = <4>; | |
| 1695 | status = "disabled"; | |
| 1696 | ||
| 1697 | ports { | |
| 1698 | #address-cells = <1>; | |
| 1699 | #size-cells = <0>; | |
| 1700 | ||
| 1701 | port@1 { | |
| 1702 | #address-cells = <1>; | |
| 1703 | #size-cells = <0>; | |
| 1704 | ||
| 1705 | reg = <1>; | |
| 1706 | ||
| 1707 | vin4csi20: endpoint@0 { | |
| 1708 | reg = <0>; | |
| fced3a97 | 1709 | remote-endpoint = <&csi20vin4>; |
| 15da7132 NS |
1710 | }; |
| 1711 | vin4csi41: endpoint@3 { | |
| 1712 | reg = <3>; | |
| fced3a97 | 1713 | remote-endpoint = <&csi41vin4>; |
| 15da7132 NS |
1714 | }; |
| 1715 | }; | |
| 1716 | }; | |
| 1717 | }; | |
| 1718 | ||
| 1719 | vin5: video@e6ef5000 { | |
| 1720 | compatible = "renesas,vin-r8a7795"; | |
| 1721 | reg = <0 0xe6ef5000 0 0x1000>; | |
| 1722 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; | |
| 1723 | clocks = <&cpg CPG_MOD 806>; | |
| 1724 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1725 | resets = <&cpg 806>; | |
| 1726 | renesas,id = <5>; | |
| 1727 | status = "disabled"; | |
| 1728 | ||
| 1729 | ports { | |
| 1730 | #address-cells = <1>; | |
| 1731 | #size-cells = <0>; | |
| 1732 | ||
| 1733 | port@1 { | |
| 1734 | #address-cells = <1>; | |
| 1735 | #size-cells = <0>; | |
| 1736 | ||
| 1737 | reg = <1>; | |
| 1738 | ||
| 1739 | vin5csi20: endpoint@0 { | |
| 1740 | reg = <0>; | |
| fced3a97 | 1741 | remote-endpoint = <&csi20vin5>; |
| 15da7132 NS |
1742 | }; |
| 1743 | vin5csi41: endpoint@3 { | |
| 1744 | reg = <3>; | |
| fced3a97 | 1745 | remote-endpoint = <&csi41vin5>; |
| 15da7132 NS |
1746 | }; |
| 1747 | }; | |
| 1748 | }; | |
| 1749 | }; | |
| 1750 | ||
| 1751 | vin6: video@e6ef6000 { | |
| 1752 | compatible = "renesas,vin-r8a7795"; | |
| 1753 | reg = <0 0xe6ef6000 0 0x1000>; | |
| 1754 | interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; | |
| 1755 | clocks = <&cpg CPG_MOD 805>; | |
| 1756 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1757 | resets = <&cpg 805>; | |
| 1758 | renesas,id = <6>; | |
| 1759 | status = "disabled"; | |
| 1760 | ||
| 1761 | ports { | |
| 1762 | #address-cells = <1>; | |
| 1763 | #size-cells = <0>; | |
| 1764 | ||
| 1765 | port@1 { | |
| 1766 | #address-cells = <1>; | |
| 1767 | #size-cells = <0>; | |
| 1768 | ||
| 1769 | reg = <1>; | |
| 1770 | ||
| 1771 | vin6csi20: endpoint@0 { | |
| 1772 | reg = <0>; | |
| fced3a97 | 1773 | remote-endpoint = <&csi20vin6>; |
| 15da7132 NS |
1774 | }; |
| 1775 | vin6csi41: endpoint@3 { | |
| 1776 | reg = <3>; | |
| fced3a97 | 1777 | remote-endpoint = <&csi41vin6>; |
| 15da7132 NS |
1778 | }; |
| 1779 | }; | |
| 1780 | }; | |
| 1781 | }; | |
| 1782 | ||
| 1783 | vin7: video@e6ef7000 { | |
| 1784 | compatible = "renesas,vin-r8a7795"; | |
| 1785 | reg = <0 0xe6ef7000 0 0x1000>; | |
| 1786 | interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; | |
| 1787 | clocks = <&cpg CPG_MOD 804>; | |
| 1788 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1789 | resets = <&cpg 804>; | |
| 1790 | renesas,id = <7>; | |
| 1791 | status = "disabled"; | |
| 1792 | ||
| 1793 | ports { | |
| 1794 | #address-cells = <1>; | |
| 1795 | #size-cells = <0>; | |
| 1796 | ||
| 1797 | port@1 { | |
| 1798 | #address-cells = <1>; | |
| 1799 | #size-cells = <0>; | |
| 1800 | ||
| 1801 | reg = <1>; | |
| 1802 | ||
| 1803 | vin7csi20: endpoint@0 { | |
| 1804 | reg = <0>; | |
| fced3a97 | 1805 | remote-endpoint = <&csi20vin7>; |
| 15da7132 NS |
1806 | }; |
| 1807 | vin7csi41: endpoint@3 { | |
| 1808 | reg = <3>; | |
| fced3a97 | 1809 | remote-endpoint = <&csi41vin7>; |
| 15da7132 NS |
1810 | }; |
| 1811 | }; | |
| 1812 | }; | |
| 1813 | }; | |
| 1814 | ||
| e0f0bda7 SH |
1815 | drif00: rif@e6f40000 { |
| 1816 | compatible = "renesas,r8a7795-drif", | |
| 1817 | "renesas,rcar-gen3-drif"; | |
| 1818 | reg = <0 0xe6f40000 0 0x64>; | |
| 1819 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 1820 | clocks = <&cpg CPG_MOD 515>; | |
| 1821 | clock-names = "fck"; | |
| 1822 | dmas = <&dmac1 0x20>, <&dmac2 0x20>; | |
| 1823 | dma-names = "rx", "rx"; | |
| 38dbb45e | 1824 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1825 | resets = <&cpg 515>; |
| 1826 | renesas,bonding = <&drif01>; | |
| 32bc0c51 KM |
1827 | status = "disabled"; |
| 1828 | }; | |
| 623197b9 | 1829 | |
| e0f0bda7 SH |
1830 | drif01: rif@e6f50000 { |
| 1831 | compatible = "renesas,r8a7795-drif", | |
| 1832 | "renesas,rcar-gen3-drif"; | |
| 1833 | reg = <0 0xe6f50000 0 0x64>; | |
| 1834 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| 1835 | clocks = <&cpg CPG_MOD 514>; | |
| 1836 | clock-names = "fck"; | |
| 1837 | dmas = <&dmac1 0x22>, <&dmac2 0x22>; | |
| 1838 | dma-names = "rx", "rx"; | |
| b2b9443b | 1839 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1840 | resets = <&cpg 514>; |
| 1841 | renesas,bonding = <&drif00>; | |
| b2b9443b LP |
1842 | status = "disabled"; |
| 1843 | }; | |
| 1844 | ||
| e0f0bda7 SH |
1845 | drif10: rif@e6f60000 { |
| 1846 | compatible = "renesas,r8a7795-drif", | |
| 1847 | "renesas,rcar-gen3-drif"; | |
| 1848 | reg = <0 0xe6f60000 0 0x64>; | |
| 1849 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 1850 | clocks = <&cpg CPG_MOD 513>; | |
| 1851 | clock-names = "fck"; | |
| 1852 | dmas = <&dmac1 0x24>, <&dmac2 0x24>; | |
| 1853 | dma-names = "rx", "rx"; | |
| b2b9443b | 1854 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1855 | resets = <&cpg 513>; |
| 1856 | renesas,bonding = <&drif11>; | |
| b2b9443b LP |
1857 | status = "disabled"; |
| 1858 | }; | |
| 1859 | ||
| e0f0bda7 SH |
1860 | drif11: rif@e6f70000 { |
| 1861 | compatible = "renesas,r8a7795-drif", | |
| 1862 | "renesas,rcar-gen3-drif"; | |
| 1863 | reg = <0 0xe6f70000 0 0x64>; | |
| 1864 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
| 1865 | clocks = <&cpg CPG_MOD 512>; | |
| 1866 | clock-names = "fck"; | |
| 1867 | dmas = <&dmac1 0x26>, <&dmac2 0x26>; | |
| 1868 | dma-names = "rx", "rx"; | |
| b2b9443b | 1869 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1870 | resets = <&cpg 512>; |
| 1871 | renesas,bonding = <&drif10>; | |
| b2b9443b LP |
1872 | status = "disabled"; |
| 1873 | }; | |
| 1874 | ||
| e0f0bda7 SH |
1875 | drif20: rif@e6f80000 { |
| 1876 | compatible = "renesas,r8a7795-drif", | |
| 1877 | "renesas,rcar-gen3-drif"; | |
| 1878 | reg = <0 0xe6f80000 0 0x64>; | |
| 1879 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 1880 | clocks = <&cpg CPG_MOD 511>; | |
| 1881 | clock-names = "fck"; | |
| 1882 | dmas = <&dmac1 0x28>, <&dmac2 0x28>; | |
| 1883 | dma-names = "rx", "rx"; | |
| b2b9443b | 1884 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1885 | resets = <&cpg 511>; |
| 1886 | renesas,bonding = <&drif21>; | |
| b2b9443b LP |
1887 | status = "disabled"; |
| 1888 | }; | |
| 1889 | ||
| e0f0bda7 SH |
1890 | drif21: rif@e6f90000 { |
| 1891 | compatible = "renesas,r8a7795-drif", | |
| 1892 | "renesas,rcar-gen3-drif"; | |
| 1893 | reg = <0 0xe6f90000 0 0x64>; | |
| 1894 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
| 1895 | clocks = <&cpg CPG_MOD 510>; | |
| 1896 | clock-names = "fck"; | |
| 1897 | dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; | |
| 1898 | dma-names = "rx", "rx"; | |
| b2b9443b | 1899 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1900 | resets = <&cpg 510>; |
| 1901 | renesas,bonding = <&drif20>; | |
| b2b9443b LP |
1902 | status = "disabled"; |
| 1903 | }; | |
| 1904 | ||
| e0f0bda7 SH |
1905 | drif30: rif@e6fa0000 { |
| 1906 | compatible = "renesas,r8a7795-drif", | |
| 1907 | "renesas,rcar-gen3-drif"; | |
| 1908 | reg = <0 0xe6fa0000 0 0x64>; | |
| 1909 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| 1910 | clocks = <&cpg CPG_MOD 509>; | |
| 1911 | clock-names = "fck"; | |
| 1912 | dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; | |
| 1913 | dma-names = "rx", "rx"; | |
| b2b9443b | 1914 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1915 | resets = <&cpg 509>; |
| 1916 | renesas,bonding = <&drif31>; | |
| b2b9443b LP |
1917 | status = "disabled"; |
| 1918 | }; | |
| 1919 | ||
| e0f0bda7 SH |
1920 | drif31: rif@e6fb0000 { |
| 1921 | compatible = "renesas,r8a7795-drif", | |
| 1922 | "renesas,rcar-gen3-drif"; | |
| 1923 | reg = <0 0xe6fb0000 0 0x64>; | |
| 1924 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
| 1925 | clocks = <&cpg CPG_MOD 508>; | |
| 1926 | clock-names = "fck"; | |
| 1927 | dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; | |
| 1928 | dma-names = "rx", "rx"; | |
| b2b9443b | 1929 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
1930 | resets = <&cpg 508>; |
| 1931 | renesas,bonding = <&drif30>; | |
| b2b9443b LP |
1932 | status = "disabled"; |
| 1933 | }; | |
| 1934 | ||
| 623197b9 KM |
1935 | rcar_sound: sound@ec500000 { |
| 1936 | /* | |
| 1937 | * #sound-dai-cells is required | |
| 1938 | * | |
| 1939 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
| 1940 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
| 1941 | */ | |
| 1942 | /* | |
| 1943 | * #clock-cells is required for audio_clkout0/1/2/3 | |
| 1944 | * | |
| 1945 | * clkout : #clock-cells = <0>; <&rcar_sound>; | |
| 1946 | * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; | |
| 1947 | */ | |
| 1948 | compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; | |
| 1949 | reg = <0 0xec500000 0 0x1000>, /* SCU */ | |
| 1950 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
| 1951 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
| 1952 | <0 0xec541000 0 0x280>, /* SSI */ | |
| 7a516e49 | 1953 | <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ |
| 623197b9 KM |
1954 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; |
| 1955 | ||
| 1956 | clocks = <&cpg CPG_MOD 1005>, | |
| 1957 | <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, | |
| 1958 | <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, | |
| 1959 | <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, | |
| 1960 | <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, | |
| 1961 | <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, | |
| b868ff51 KM |
1962 | <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, |
| 1963 | <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, | |
| 1964 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | |
| 1965 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | |
| 1966 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | |
| c9293d78 | 1967 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
| ad5805f3 | 1968 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
| b9dd9450 | 1969 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
| 623197b9 KM |
1970 | <&audio_clk_a>, <&audio_clk_b>, |
| 1971 | <&audio_clk_c>, | |
| 1972 | <&cpg CPG_CORE R8A7795_CLK_S0D4>; | |
| 1973 | clock-names = "ssi-all", | |
| 1974 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
| 1975 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
| 1976 | "ssi.1", "ssi.0", | |
| b868ff51 KM |
1977 | "src.9", "src.8", "src.7", "src.6", |
| 1978 | "src.5", "src.4", "src.3", "src.2", | |
| 1979 | "src.1", "src.0", | |
| ad5805f3 | 1980 | "mix.1", "mix.0", |
| c9293d78 | 1981 | "ctu.1", "ctu.0", |
| b9dd9450 | 1982 | "dvc.0", "dvc.1", |
| 623197b9 | 1983 | "clk_a", "clk_b", "clk_c", "clk_i"; |
| 38dbb45e | 1984 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 161a1910 GU |
1985 | resets = <&cpg 1005>, |
| 1986 | <&cpg 1006>, <&cpg 1007>, | |
| 1987 | <&cpg 1008>, <&cpg 1009>, | |
| 1988 | <&cpg 1010>, <&cpg 1011>, | |
| 1989 | <&cpg 1012>, <&cpg 1013>, | |
| 1990 | <&cpg 1014>, <&cpg 1015>; | |
| 1991 | reset-names = "ssi-all", | |
| 1992 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
| 1993 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
| 1994 | "ssi.1", "ssi.0"; | |
| 623197b9 KM |
1995 | status = "disabled"; |
| 1996 | ||
| b9dd9450 | 1997 | rcar_sound,dvc { |
| 6f7bf82c | 1998 | dvc0: dvc-0 { |
| b5a8ffad | 1999 | dmas = <&audma1 0xbc>; |
| b9dd9450 KM |
2000 | dma-names = "tx"; |
| 2001 | }; | |
| 6f7bf82c | 2002 | dvc1: dvc-1 { |
| b5a8ffad | 2003 | dmas = <&audma1 0xbe>; |
| b9dd9450 KM |
2004 | dma-names = "tx"; |
| 2005 | }; | |
| 2006 | }; | |
| 2007 | ||
| ad5805f3 KM |
2008 | rcar_sound,mix { |
| 2009 | mix0: mix-0 { }; | |
| 2010 | mix1: mix-1 { }; | |
| 2011 | }; | |
| 2012 | ||
| c9293d78 KM |
2013 | rcar_sound,ctu { |
| 2014 | ctu00: ctu-0 { }; | |
| 2015 | ctu01: ctu-1 { }; | |
| 2016 | ctu02: ctu-2 { }; | |
| 2017 | ctu03: ctu-3 { }; | |
| 2018 | ctu10: ctu-4 { }; | |
| 2019 | ctu11: ctu-5 { }; | |
| 2020 | ctu12: ctu-6 { }; | |
| 2021 | ctu13: ctu-7 { }; | |
| 2022 | }; | |
| 2023 | ||
| b868ff51 | 2024 | rcar_sound,src { |
| 6f7bf82c | 2025 | src0: src-0 { |
| 52b541ab | 2026 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2027 | dmas = <&audma0 0x85>, <&audma1 0x9a>; |
| 2028 | dma-names = "rx", "tx"; | |
| 2029 | }; | |
| 6f7bf82c | 2030 | src1: src-1 { |
| 52b541ab | 2031 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2032 | dmas = <&audma0 0x87>, <&audma1 0x9c>; |
| 2033 | dma-names = "rx", "tx"; | |
| 2034 | }; | |
| 6f7bf82c | 2035 | src2: src-2 { |
| 52b541ab | 2036 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2037 | dmas = <&audma0 0x89>, <&audma1 0x9e>; |
| 2038 | dma-names = "rx", "tx"; | |
| 2039 | }; | |
| 6f7bf82c | 2040 | src3: src-3 { |
| 52b541ab | 2041 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2042 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; |
| 2043 | dma-names = "rx", "tx"; | |
| 2044 | }; | |
| 6f7bf82c | 2045 | src4: src-4 { |
| 52b541ab | 2046 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2047 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; |
| 2048 | dma-names = "rx", "tx"; | |
| 2049 | }; | |
| 6f7bf82c | 2050 | src5: src-5 { |
| 52b541ab | 2051 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2052 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; |
| 2053 | dma-names = "rx", "tx"; | |
| 2054 | }; | |
| 6f7bf82c | 2055 | src6: src-6 { |
| 52b541ab | 2056 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2057 | dmas = <&audma0 0x91>, <&audma1 0xb4>; |
| 2058 | dma-names = "rx", "tx"; | |
| 2059 | }; | |
| 6f7bf82c | 2060 | src7: src-7 { |
| 52b541ab | 2061 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2062 | dmas = <&audma0 0x93>, <&audma1 0xb6>; |
| 2063 | dma-names = "rx", "tx"; | |
| 2064 | }; | |
| 6f7bf82c | 2065 | src8: src-8 { |
| 52b541ab | 2066 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2067 | dmas = <&audma0 0x95>, <&audma1 0xb8>; |
| 2068 | dma-names = "rx", "tx"; | |
| 2069 | }; | |
| 6f7bf82c | 2070 | src9: src-9 { |
| 52b541ab | 2071 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
2072 | dmas = <&audma0 0x97>, <&audma1 0xba>; |
| 2073 | dma-names = "rx", "tx"; | |
| 2074 | }; | |
| 2075 | }; | |
| 2076 | ||
| da90dd84 KM |
2077 | rcar_sound,ssiu { |
| 2078 | ssiu00: ssiu-0 { | |
| 2079 | dmas = <&audma0 0x15>, <&audma1 0x16>; | |
| 2080 | dma-names = "rx", "tx"; | |
| 2081 | }; | |
| 2082 | ssiu01: ssiu-1 { | |
| 2083 | dmas = <&audma0 0x35>, <&audma1 0x36>; | |
| 2084 | dma-names = "rx", "tx"; | |
| 2085 | }; | |
| 2086 | ssiu02: ssiu-2 { | |
| 2087 | dmas = <&audma0 0x37>, <&audma1 0x38>; | |
| 2088 | dma-names = "rx", "tx"; | |
| 2089 | }; | |
| 2090 | ssiu03: ssiu-3 { | |
| 2091 | dmas = <&audma0 0x47>, <&audma1 0x48>; | |
| 2092 | dma-names = "rx", "tx"; | |
| 2093 | }; | |
| 2094 | ssiu04: ssiu-4 { | |
| 2095 | dmas = <&audma0 0x3F>, <&audma1 0x40>; | |
| 2096 | dma-names = "rx", "tx"; | |
| 2097 | }; | |
| 2098 | ssiu05: ssiu-5 { | |
| 2099 | dmas = <&audma0 0x43>, <&audma1 0x44>; | |
| 2100 | dma-names = "rx", "tx"; | |
| 2101 | }; | |
| 2102 | ssiu06: ssiu-6 { | |
| 2103 | dmas = <&audma0 0x4F>, <&audma1 0x50>; | |
| 2104 | dma-names = "rx", "tx"; | |
| 2105 | }; | |
| 2106 | ssiu07: ssiu-7 { | |
| 2107 | dmas = <&audma0 0x53>, <&audma1 0x54>; | |
| 2108 | dma-names = "rx", "tx"; | |
| 2109 | }; | |
| 2110 | ssiu10: ssiu-8 { | |
| 2111 | dmas = <&audma0 0x49>, <&audma1 0x4a>; | |
| 2112 | dma-names = "rx", "tx"; | |
| 2113 | }; | |
| 2114 | ssiu11: ssiu-9 { | |
| 2115 | dmas = <&audma0 0x4B>, <&audma1 0x4C>; | |
| 2116 | dma-names = "rx", "tx"; | |
| 2117 | }; | |
| 2118 | ssiu12: ssiu-10 { | |
| 2119 | dmas = <&audma0 0x57>, <&audma1 0x58>; | |
| 2120 | dma-names = "rx", "tx"; | |
| 2121 | }; | |
| 2122 | ssiu13: ssiu-11 { | |
| 2123 | dmas = <&audma0 0x59>, <&audma1 0x5A>; | |
| 2124 | dma-names = "rx", "tx"; | |
| 2125 | }; | |
| 2126 | ssiu14: ssiu-12 { | |
| 2127 | dmas = <&audma0 0x5F>, <&audma1 0x60>; | |
| 2128 | dma-names = "rx", "tx"; | |
| 2129 | }; | |
| 2130 | ssiu15: ssiu-13 { | |
| 2131 | dmas = <&audma0 0xC3>, <&audma1 0xC4>; | |
| 2132 | dma-names = "rx", "tx"; | |
| 2133 | }; | |
| 2134 | ssiu16: ssiu-14 { | |
| 2135 | dmas = <&audma0 0xC7>, <&audma1 0xC8>; | |
| 2136 | dma-names = "rx", "tx"; | |
| 2137 | }; | |
| 2138 | ssiu17: ssiu-15 { | |
| 2139 | dmas = <&audma0 0xCB>, <&audma1 0xCC>; | |
| 2140 | dma-names = "rx", "tx"; | |
| 2141 | }; | |
| 2142 | ssiu20: ssiu-16 { | |
| 2143 | dmas = <&audma0 0x63>, <&audma1 0x64>; | |
| 2144 | dma-names = "rx", "tx"; | |
| 2145 | }; | |
| 2146 | ssiu21: ssiu-17 { | |
| 2147 | dmas = <&audma0 0x67>, <&audma1 0x68>; | |
| 2148 | dma-names = "rx", "tx"; | |
| 2149 | }; | |
| 2150 | ssiu22: ssiu-18 { | |
| 2151 | dmas = <&audma0 0x6B>, <&audma1 0x6C>; | |
| 2152 | dma-names = "rx", "tx"; | |
| 2153 | }; | |
| 2154 | ssiu23: ssiu-19 { | |
| 2155 | dmas = <&audma0 0x6D>, <&audma1 0x6E>; | |
| 2156 | dma-names = "rx", "tx"; | |
| 2157 | }; | |
| 2158 | ssiu24: ssiu-20 { | |
| 2159 | dmas = <&audma0 0xCF>, <&audma1 0xCE>; | |
| 2160 | dma-names = "rx", "tx"; | |
| 2161 | }; | |
| 2162 | ssiu25: ssiu-21 { | |
| 2163 | dmas = <&audma0 0xEB>, <&audma1 0xEC>; | |
| 2164 | dma-names = "rx", "tx"; | |
| 2165 | }; | |
| 2166 | ssiu26: ssiu-22 { | |
| 2167 | dmas = <&audma0 0xED>, <&audma1 0xEE>; | |
| 2168 | dma-names = "rx", "tx"; | |
| 2169 | }; | |
| 2170 | ssiu27: ssiu-23 { | |
| 2171 | dmas = <&audma0 0xEF>, <&audma1 0xF0>; | |
| 2172 | dma-names = "rx", "tx"; | |
| 2173 | }; | |
| 2174 | ssiu30: ssiu-24 { | |
| 2175 | dmas = <&audma0 0x6f>, <&audma1 0x70>; | |
| 2176 | dma-names = "rx", "tx"; | |
| 2177 | }; | |
| 2178 | ssiu31: ssiu-25 { | |
| 2179 | dmas = <&audma0 0x21>, <&audma1 0x22>; | |
| 2180 | dma-names = "rx", "tx"; | |
| 2181 | }; | |
| 2182 | ssiu32: ssiu-26 { | |
| 2183 | dmas = <&audma0 0x23>, <&audma1 0x24>; | |
| 2184 | dma-names = "rx", "tx"; | |
| 2185 | }; | |
| 2186 | ssiu33: ssiu-27 { | |
| 2187 | dmas = <&audma0 0x25>, <&audma1 0x26>; | |
| 2188 | dma-names = "rx", "tx"; | |
| 2189 | }; | |
| 2190 | ssiu34: ssiu-28 { | |
| 2191 | dmas = <&audma0 0x27>, <&audma1 0x28>; | |
| 2192 | dma-names = "rx", "tx"; | |
| 2193 | }; | |
| 2194 | ssiu35: ssiu-29 { | |
| 2195 | dmas = <&audma0 0x29>, <&audma1 0x2A>; | |
| 2196 | dma-names = "rx", "tx"; | |
| 2197 | }; | |
| 2198 | ssiu36: ssiu-30 { | |
| 2199 | dmas = <&audma0 0x2B>, <&audma1 0x2C>; | |
| 2200 | dma-names = "rx", "tx"; | |
| 2201 | }; | |
| 2202 | ssiu37: ssiu-31 { | |
| 2203 | dmas = <&audma0 0x2D>, <&audma1 0x2E>; | |
| 2204 | dma-names = "rx", "tx"; | |
| 2205 | }; | |
| 2206 | ssiu40: ssiu-32 { | |
| 2207 | dmas = <&audma0 0x71>, <&audma1 0x72>; | |
| 2208 | dma-names = "rx", "tx"; | |
| 2209 | }; | |
| 2210 | ssiu41: ssiu-33 { | |
| 2211 | dmas = <&audma0 0x17>, <&audma1 0x18>; | |
| 2212 | dma-names = "rx", "tx"; | |
| 2213 | }; | |
| 2214 | ssiu42: ssiu-34 { | |
| 2215 | dmas = <&audma0 0x19>, <&audma1 0x1A>; | |
| 2216 | dma-names = "rx", "tx"; | |
| 2217 | }; | |
| 2218 | ssiu43: ssiu-35 { | |
| 2219 | dmas = <&audma0 0x1B>, <&audma1 0x1C>; | |
| 2220 | dma-names = "rx", "tx"; | |
| 2221 | }; | |
| 2222 | ssiu44: ssiu-36 { | |
| 2223 | dmas = <&audma0 0x1D>, <&audma1 0x1E>; | |
| 2224 | dma-names = "rx", "tx"; | |
| 2225 | }; | |
| 2226 | ssiu45: ssiu-37 { | |
| 2227 | dmas = <&audma0 0x1F>, <&audma1 0x20>; | |
| 2228 | dma-names = "rx", "tx"; | |
| 2229 | }; | |
| 2230 | ssiu46: ssiu-38 { | |
| 2231 | dmas = <&audma0 0x31>, <&audma1 0x32>; | |
| 2232 | dma-names = "rx", "tx"; | |
| 2233 | }; | |
| 2234 | ssiu47: ssiu-39 { | |
| 2235 | dmas = <&audma0 0x33>, <&audma1 0x34>; | |
| 2236 | dma-names = "rx", "tx"; | |
| 2237 | }; | |
| 2238 | ssiu50: ssiu-40 { | |
| 2239 | dmas = <&audma0 0x73>, <&audma1 0x74>; | |
| 2240 | dma-names = "rx", "tx"; | |
| 2241 | }; | |
| 2242 | ssiu60: ssiu-41 { | |
| 2243 | dmas = <&audma0 0x75>, <&audma1 0x76>; | |
| 2244 | dma-names = "rx", "tx"; | |
| 2245 | }; | |
| 2246 | ssiu70: ssiu-42 { | |
| 2247 | dmas = <&audma0 0x79>, <&audma1 0x7a>; | |
| 2248 | dma-names = "rx", "tx"; | |
| 2249 | }; | |
| 2250 | ssiu80: ssiu-43 { | |
| 2251 | dmas = <&audma0 0x7b>, <&audma1 0x7c>; | |
| 2252 | dma-names = "rx", "tx"; | |
| 2253 | }; | |
| 2254 | ssiu90: ssiu-44 { | |
| 2255 | dmas = <&audma0 0x7d>, <&audma1 0x7e>; | |
| 2256 | dma-names = "rx", "tx"; | |
| 2257 | }; | |
| 2258 | ssiu91: ssiu-45 { | |
| 2259 | dmas = <&audma0 0x7F>, <&audma1 0x80>; | |
| 2260 | dma-names = "rx", "tx"; | |
| 2261 | }; | |
| 2262 | ssiu92: ssiu-46 { | |
| 2263 | dmas = <&audma0 0x81>, <&audma1 0x82>; | |
| 2264 | dma-names = "rx", "tx"; | |
| 2265 | }; | |
| 2266 | ssiu93: ssiu-47 { | |
| 2267 | dmas = <&audma0 0x83>, <&audma1 0x84>; | |
| 2268 | dma-names = "rx", "tx"; | |
| 2269 | }; | |
| 2270 | ssiu94: ssiu-48 { | |
| 2271 | dmas = <&audma0 0xA3>, <&audma1 0xA4>; | |
| 2272 | dma-names = "rx", "tx"; | |
| 2273 | }; | |
| 2274 | ssiu95: ssiu-49 { | |
| 2275 | dmas = <&audma0 0xA5>, <&audma1 0xA6>; | |
| 2276 | dma-names = "rx", "tx"; | |
| 2277 | }; | |
| 2278 | ssiu96: ssiu-50 { | |
| 2279 | dmas = <&audma0 0xA7>, <&audma1 0xA8>; | |
| 2280 | dma-names = "rx", "tx"; | |
| 2281 | }; | |
| 2282 | ssiu97: ssiu-51 { | |
| 2283 | dmas = <&audma0 0xA9>, <&audma1 0xAA>; | |
| 2284 | dma-names = "rx", "tx"; | |
| 2285 | }; | |
| 2286 | }; | |
| 2287 | ||
| 623197b9 | 2288 | rcar_sound,ssi { |
| 6f7bf82c | 2289 | ssi0: ssi-0 { |
| 52b541ab | 2290 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2291 | dmas = <&audma0 0x01>, <&audma1 0x02>; |
| 2292 | dma-names = "rx", "tx"; | |
| 623197b9 | 2293 | }; |
| 6f7bf82c | 2294 | ssi1: ssi-1 { |
| 52b541ab | 2295 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2296 | dmas = <&audma0 0x03>, <&audma1 0x04>; |
| 2297 | dma-names = "rx", "tx"; | |
| 623197b9 | 2298 | }; |
| 6f7bf82c | 2299 | ssi2: ssi-2 { |
| 52b541ab | 2300 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2301 | dmas = <&audma0 0x05>, <&audma1 0x06>; |
| 2302 | dma-names = "rx", "tx"; | |
| 623197b9 | 2303 | }; |
| 6f7bf82c | 2304 | ssi3: ssi-3 { |
| 52b541ab | 2305 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2306 | dmas = <&audma0 0x07>, <&audma1 0x08>; |
| 2307 | dma-names = "rx", "tx"; | |
| 623197b9 | 2308 | }; |
| 6f7bf82c | 2309 | ssi4: ssi-4 { |
| 52b541ab | 2310 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2311 | dmas = <&audma0 0x09>, <&audma1 0x0a>; |
| 2312 | dma-names = "rx", "tx"; | |
| 623197b9 | 2313 | }; |
| 6f7bf82c | 2314 | ssi5: ssi-5 { |
| 52b541ab | 2315 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2316 | dmas = <&audma0 0x0b>, <&audma1 0x0c>; |
| 2317 | dma-names = "rx", "tx"; | |
| 623197b9 | 2318 | }; |
| 6f7bf82c | 2319 | ssi6: ssi-6 { |
| 52b541ab | 2320 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2321 | dmas = <&audma0 0x0d>, <&audma1 0x0e>; |
| 2322 | dma-names = "rx", "tx"; | |
| 623197b9 | 2323 | }; |
| 6f7bf82c | 2324 | ssi7: ssi-7 { |
| 52b541ab | 2325 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2326 | dmas = <&audma0 0x0f>, <&audma1 0x10>; |
| 2327 | dma-names = "rx", "tx"; | |
| 623197b9 | 2328 | }; |
| 6f7bf82c | 2329 | ssi8: ssi-8 { |
| 52b541ab | 2330 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2331 | dmas = <&audma0 0x11>, <&audma1 0x12>; |
| 2332 | dma-names = "rx", "tx"; | |
| 623197b9 | 2333 | }; |
| 6f7bf82c | 2334 | ssi9: ssi-9 { |
| 52b541ab | 2335 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
| 0ec8e0a8 KM |
2336 | dmas = <&audma0 0x13>, <&audma1 0x14>; |
| 2337 | dma-names = "rx", "tx"; | |
| 623197b9 KM |
2338 | }; |
| 2339 | }; | |
| 2340 | }; | |
| 4c13472b | 2341 | |
| e0f0bda7 SH |
2342 | audma0: dma-controller@ec700000 { |
| 2343 | compatible = "renesas,dmac-r8a7795", | |
| 2344 | "renesas,rcar-dmac"; | |
| 2345 | reg = <0 0xec700000 0 0x10000>; | |
| 2346 | interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH | |
| 2347 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH | |
| 2348 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH | |
| 2349 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH | |
| 2350 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH | |
| 2351 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH | |
| 2352 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH | |
| 2353 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH | |
| 2354 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH | |
| 2355 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH | |
| 2356 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH | |
| 2357 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH | |
| 2358 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH | |
| 2359 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH | |
| 2360 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH | |
| 2361 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH | |
| 2362 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; | |
| 2363 | interrupt-names = "error", | |
| 2364 | "ch0", "ch1", "ch2", "ch3", | |
| 2365 | "ch4", "ch5", "ch6", "ch7", | |
| 2366 | "ch8", "ch9", "ch10", "ch11", | |
| 2367 | "ch12", "ch13", "ch14", "ch15"; | |
| 2368 | clocks = <&cpg CPG_MOD 502>; | |
| 2369 | clock-names = "fck"; | |
| 2cab226c | 2370 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
2371 | resets = <&cpg 502>; |
| 2372 | #dma-cells = <1>; | |
| 2373 | dma-channels = <16>; | |
| 2374 | iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, | |
| 2375 | <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, | |
| 2376 | <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, | |
| 2377 | <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, | |
| 2378 | <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, | |
| 2379 | <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, | |
| 2380 | <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, | |
| 2381 | <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; | |
| 4c13472b | 2382 | }; |
| 171f2ef8 | 2383 | |
| e0f0bda7 SH |
2384 | audma1: dma-controller@ec720000 { |
| 2385 | compatible = "renesas,dmac-r8a7795", | |
| 2386 | "renesas,rcar-dmac"; | |
| 2387 | reg = <0 0xec720000 0 0x10000>; | |
| 2388 | interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH | |
| 2389 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH | |
| 2390 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH | |
| 2391 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH | |
| 2392 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH | |
| 2393 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH | |
| 2394 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH | |
| 2395 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH | |
| 2396 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH | |
| 2397 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH | |
| 2398 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH | |
| 2399 | GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH | |
| 2400 | GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH | |
| 2401 | GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH | |
| 2402 | GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH | |
| 2403 | GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH | |
| 2404 | GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; | |
| 2405 | interrupt-names = "error", | |
| 2406 | "ch0", "ch1", "ch2", "ch3", | |
| 2407 | "ch4", "ch5", "ch6", "ch7", | |
| 2408 | "ch8", "ch9", "ch10", "ch11", | |
| 2409 | "ch12", "ch13", "ch14", "ch15"; | |
| 2410 | clocks = <&cpg CPG_MOD 501>; | |
| 2411 | clock-names = "fck"; | |
| 7c1e5ea6 | 2412 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 SH |
2413 | resets = <&cpg 501>; |
| 2414 | #dma-cells = <1>; | |
| 2415 | dma-channels = <16>; | |
| 2416 | iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, | |
| 2417 | <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, | |
| 2418 | <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, | |
| 2419 | <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, | |
| 2420 | <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, | |
| 2421 | <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, | |
| 2422 | <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, | |
| 2423 | <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; | |
| 7c1e5ea6 YS |
2424 | }; |
| 2425 | ||
| 171f2ef8 | 2426 | xhci0: usb@ee000000 { |
| 81ae0ac3 | 2427 | compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; |
| 171f2ef8 YS |
2428 | reg = <0 0xee000000 0 0xc00>; |
| 2429 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
| 2430 | clocks = <&cpg CPG_MOD 328>; | |
| 38dbb45e | 2431 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 2432 | resets = <&cpg 328>; |
| 171f2ef8 YS |
2433 | status = "disabled"; |
| 2434 | }; | |
| 2435 | ||
| 3bdba1b2 YS |
2436 | usb3_peri0: usb@ee020000 { |
| 2437 | compatible = "renesas,r8a7795-usb3-peri", | |
| 2438 | "renesas,rcar-gen3-usb3-peri"; | |
| 2439 | reg = <0 0xee020000 0 0x400>; | |
| 2440 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
| 2441 | clocks = <&cpg CPG_MOD 328>; | |
| 2442 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2443 | resets = <&cpg 328>; | |
| 2444 | status = "disabled"; | |
| 2445 | }; | |
| 2446 | ||
| e0f0bda7 SH |
2447 | ohci0: usb@ee080000 { |
| 2448 | compatible = "generic-ohci"; | |
| 2449 | reg = <0 0xee080000 0 0x100>; | |
| 5923bb52 | 2450 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 737e05bf | 2451 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| 7794bd7e | 2452 | phys = <&usb2_phy0 1>; |
| e0f0bda7 | 2453 | phy-names = "usb"; |
| 38dbb45e | 2454 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 737e05bf | 2455 | resets = <&cpg 703>, <&cpg 704>; |
| 5923bb52 YS |
2456 | status = "disabled"; |
| 2457 | }; | |
| 2458 | ||
| e0f0bda7 SH |
2459 | ohci1: usb@ee0a0000 { |
| 2460 | compatible = "generic-ohci"; | |
| 2461 | reg = <0 0xee0a0000 0 0x100>; | |
| 2462 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
| 5923bb52 | 2463 | clocks = <&cpg CPG_MOD 702>; |
| 7794bd7e | 2464 | phys = <&usb2_phy1 1>; |
| e0f0bda7 | 2465 | phy-names = "usb"; |
| 38dbb45e | 2466 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 2467 | resets = <&cpg 702>; |
| 5923bb52 YS |
2468 | status = "disabled"; |
| 2469 | }; | |
| 2470 | ||
| e0f0bda7 SH |
2471 | ohci2: usb@ee0c0000 { |
| 2472 | compatible = "generic-ohci"; | |
| 2473 | reg = <0 0xee0c0000 0 0x100>; | |
| 2474 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 5923bb52 | 2475 | clocks = <&cpg CPG_MOD 701>; |
| 7794bd7e | 2476 | phys = <&usb2_phy2 1>; |
| e0f0bda7 | 2477 | phy-names = "usb"; |
| 38dbb45e | 2478 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 2479 | resets = <&cpg 701>; |
| 5923bb52 YS |
2480 | status = "disabled"; |
| 2481 | }; | |
| a2bcdc28 | 2482 | |
| e0f0bda7 SH |
2483 | ohci3: usb@ee0e0000 { |
| 2484 | compatible = "generic-ohci"; | |
| 2485 | reg = <0 0xee0e0000 0 0x100>; | |
| ac29cc44 | 2486 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 737e05bf | 2487 | clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; |
| 7794bd7e | 2488 | phys = <&usb2_phy3 1>; |
| e0f0bda7 | 2489 | phy-names = "usb"; |
| ac29cc44 | 2490 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 737e05bf | 2491 | resets = <&cpg 700>, <&cpg 705>; |
| ac29cc44 YS |
2492 | status = "disabled"; |
| 2493 | }; | |
| 2494 | ||
| a2bcdc28 YS |
2495 | ehci0: usb@ee080100 { |
| 2496 | compatible = "generic-ehci"; | |
| 2497 | reg = <0 0xee080100 0 0x100>; | |
| 2498 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 737e05bf | 2499 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| 7794bd7e | 2500 | phys = <&usb2_phy0 2>; |
| a2bcdc28 | 2501 | phy-names = "usb"; |
| c3a937bb | 2502 | companion = <&ohci0>; |
| 38dbb45e | 2503 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 737e05bf | 2504 | resets = <&cpg 703>, <&cpg 704>; |
| a2bcdc28 YS |
2505 | status = "disabled"; |
| 2506 | }; | |
| 2507 | ||
| 2508 | ehci1: usb@ee0a0100 { | |
| 2509 | compatible = "generic-ehci"; | |
| 2510 | reg = <0 0xee0a0100 0 0x100>; | |
| 2511 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
| 2512 | clocks = <&cpg CPG_MOD 702>; | |
| 7794bd7e | 2513 | phys = <&usb2_phy1 2>; |
| a2bcdc28 | 2514 | phy-names = "usb"; |
| c3a937bb | 2515 | companion = <&ohci1>; |
| 38dbb45e | 2516 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 2517 | resets = <&cpg 702>; |
| a2bcdc28 YS |
2518 | status = "disabled"; |
| 2519 | }; | |
| 2520 | ||
| 2521 | ehci2: usb@ee0c0100 { | |
| 2522 | compatible = "generic-ehci"; | |
| 2523 | reg = <0 0xee0c0100 0 0x100>; | |
| 2524 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 2525 | clocks = <&cpg CPG_MOD 701>; | |
| 7794bd7e | 2526 | phys = <&usb2_phy2 2>; |
| a2bcdc28 | 2527 | phy-names = "usb"; |
| c3a937bb | 2528 | companion = <&ohci2>; |
| 38dbb45e | 2529 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 2530 | resets = <&cpg 701>; |
| a2bcdc28 YS |
2531 | status = "disabled"; |
| 2532 | }; | |
| 2533 | ||
| 4dad6dcd YS |
2534 | ehci3: usb@ee0e0100 { |
| 2535 | compatible = "generic-ehci"; | |
| 2536 | reg = <0 0xee0e0100 0 0x100>; | |
| 2537 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 737e05bf | 2538 | clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; |
| 7794bd7e | 2539 | phys = <&usb2_phy3 2>; |
| 4dad6dcd | 2540 | phy-names = "usb"; |
| c3a937bb | 2541 | companion = <&ohci3>; |
| 4dad6dcd | 2542 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 737e05bf | 2543 | resets = <&cpg 700>, <&cpg 705>; |
| 4dad6dcd YS |
2544 | status = "disabled"; |
| 2545 | }; | |
| 2546 | ||
| e0f0bda7 SH |
2547 | usb2_phy0: usb-phy@ee080200 { |
| 2548 | compatible = "renesas,usb2-phy-r8a7795", | |
| 2549 | "renesas,rcar-gen3-usb2-phy"; | |
| 2550 | reg = <0 0xee080200 0 0x700>; | |
| a2bcdc28 | 2551 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 737e05bf | 2552 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| 38dbb45e | 2553 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 737e05bf | 2554 | resets = <&cpg 703>, <&cpg 704>; |
| 7794bd7e | 2555 | #phy-cells = <1>; |
| a2bcdc28 YS |
2556 | status = "disabled"; |
| 2557 | }; | |
| 2558 | ||
| e0f0bda7 SH |
2559 | usb2_phy1: usb-phy@ee0a0200 { |
| 2560 | compatible = "renesas,usb2-phy-r8a7795", | |
| 2561 | "renesas,rcar-gen3-usb2-phy"; | |
| 2562 | reg = <0 0xee0a0200 0 0x700>; | |
| a2bcdc28 | 2563 | clocks = <&cpg CPG_MOD 702>; |
| 38dbb45e | 2564 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 2565 | resets = <&cpg 702>; |
| 7794bd7e | 2566 | #phy-cells = <1>; |
| a2bcdc28 YS |
2567 | status = "disabled"; |
| 2568 | }; | |
| 2569 | ||
| e0f0bda7 SH |
2570 | usb2_phy2: usb-phy@ee0c0200 { |
| 2571 | compatible = "renesas,usb2-phy-r8a7795", | |
| 2572 | "renesas,rcar-gen3-usb2-phy"; | |
| 2573 | reg = <0 0xee0c0200 0 0x700>; | |
| a2bcdc28 | 2574 | clocks = <&cpg CPG_MOD 701>; |
| 38dbb45e | 2575 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 2576 | resets = <&cpg 701>; |
| 7794bd7e | 2577 | #phy-cells = <1>; |
| e0f0bda7 SH |
2578 | status = "disabled"; |
| 2579 | }; | |
| 2580 | ||
| 2581 | usb2_phy3: usb-phy@ee0e0200 { | |
| 2582 | compatible = "renesas,usb2-phy-r8a7795", | |
| 2583 | "renesas,rcar-gen3-usb2-phy"; | |
| 2584 | reg = <0 0xee0e0200 0 0x700>; | |
| 2585 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 737e05bf | 2586 | clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; |
| e0f0bda7 | 2587 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 737e05bf | 2588 | resets = <&cpg 700>, <&cpg 705>; |
| 7794bd7e | 2589 | #phy-cells = <1>; |
| e0f0bda7 SH |
2590 | status = "disabled"; |
| 2591 | }; | |
| 2592 | ||
| 2593 | sdhi0: sd@ee100000 { | |
| 2594 | compatible = "renesas,sdhi-r8a7795", | |
| 2595 | "renesas,rcar-gen3-sdhi"; | |
| 2596 | reg = <0 0xee100000 0 0x2000>; | |
| 2597 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; | |
| 2598 | clocks = <&cpg CPG_MOD 314>; | |
| 2599 | max-frequency = <200000000>; | |
| 2600 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2601 | resets = <&cpg 314>; | |
| 2602 | status = "disabled"; | |
| 2603 | }; | |
| 2604 | ||
| 2605 | sdhi1: sd@ee120000 { | |
| 2606 | compatible = "renesas,sdhi-r8a7795", | |
| 2607 | "renesas,rcar-gen3-sdhi"; | |
| 2608 | reg = <0 0xee120000 0 0x2000>; | |
| 2609 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; | |
| 2610 | clocks = <&cpg CPG_MOD 313>; | |
| 2611 | max-frequency = <200000000>; | |
| 2612 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2613 | resets = <&cpg 313>; | |
| 2614 | status = "disabled"; | |
| 2615 | }; | |
| 2616 | ||
| 2617 | sdhi2: sd@ee140000 { | |
| 2618 | compatible = "renesas,sdhi-r8a7795", | |
| 2619 | "renesas,rcar-gen3-sdhi"; | |
| 2620 | reg = <0 0xee140000 0 0x2000>; | |
| 2621 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; | |
| 2622 | clocks = <&cpg CPG_MOD 312>; | |
| 2623 | max-frequency = <200000000>; | |
| 2624 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2625 | resets = <&cpg 312>; | |
| a2bcdc28 YS |
2626 | status = "disabled"; |
| 2627 | }; | |
| d2422e10 | 2628 | |
| e0f0bda7 SH |
2629 | sdhi3: sd@ee160000 { |
| 2630 | compatible = "renesas,sdhi-r8a7795", | |
| 2631 | "renesas,rcar-gen3-sdhi"; | |
| 2632 | reg = <0 0xee160000 0 0x2000>; | |
| 2633 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; | |
| 2634 | clocks = <&cpg CPG_MOD 311>; | |
| 2635 | max-frequency = <200000000>; | |
| 4dad6dcd | 2636 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 2637 | resets = <&cpg 311>; |
| 4dad6dcd YS |
2638 | status = "disabled"; |
| 2639 | }; | |
| 2640 | ||
| e0f0bda7 SH |
2641 | sata: sata@ee300000 { |
| 2642 | compatible = "renesas,sata-r8a7795", | |
| 2643 | "renesas,rcar-gen3-sata"; | |
| 2644 | reg = <0 0xee300000 0 0x200000>; | |
| 2645 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
| 2646 | clocks = <&cpg CPG_MOD 815>; | |
| d2422e10 | 2647 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 2648 | resets = <&cpg 815>; |
| d2422e10 | 2649 | status = "disabled"; |
| e0f0bda7 | 2650 | iommus = <&ipmmu_hc 2>; |
| d2422e10 YS |
2651 | }; |
| 2652 | ||
| e0f0bda7 SH |
2653 | gic: interrupt-controller@f1010000 { |
| 2654 | compatible = "arm,gic-400"; | |
| 2655 | #interrupt-cells = <3>; | |
| 2656 | #address-cells = <0>; | |
| 2657 | interrupt-controller; | |
| 2658 | reg = <0x0 0xf1010000 0 0x1000>, | |
| 2659 | <0x0 0xf1020000 0 0x20000>, | |
| 2660 | <0x0 0xf1040000 0 0x20000>, | |
| 2661 | <0x0 0xf1060000 0 0x20000>; | |
| 2662 | interrupts = <GIC_PPI 9 | |
| 2663 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 2664 | clocks = <&cpg CPG_MOD 408>; | |
| 2665 | clock-names = "clk"; | |
| 4725f2b8 | 2666 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| e0f0bda7 | 2667 | resets = <&cpg 408>; |
| 4725f2b8 YS |
2668 | }; |
| 2669 | ||
| 9251024a | 2670 | pciec0: pcie@fe000000 { |
| fb04f4b8 SH |
2671 | compatible = "renesas,pcie-r8a7795", |
| 2672 | "renesas,pcie-rcar-gen3"; | |
| 9251024a PE |
2673 | reg = <0 0xfe000000 0 0x80000>; |
| 2674 | #address-cells = <3>; | |
| 2675 | #size-cells = <2>; | |
| 2676 | bus-range = <0x00 0xff>; | |
| 2677 | device_type = "pci"; | |
| 2678 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
| 2679 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
| 2680 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
| 2681 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
| 2682 | /* Map all possible DDR as inbound ranges */ | |
| 2683 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; | |
| 2684 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 2685 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 2686 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
| 2687 | #interrupt-cells = <1>; | |
| 2688 | interrupt-map-mask = <0 0 0 0>; | |
| 2689 | interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
| 2690 | clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; | |
| 2691 | clock-names = "pcie", "pcie_bus"; | |
| 38dbb45e | 2692 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 2693 | resets = <&cpg 319>; |
| 9251024a PE |
2694 | status = "disabled"; |
| 2695 | }; | |
| 2696 | ||
| 2697 | pciec1: pcie@ee800000 { | |
| fb04f4b8 SH |
2698 | compatible = "renesas,pcie-r8a7795", |
| 2699 | "renesas,pcie-rcar-gen3"; | |
| 9251024a PE |
2700 | reg = <0 0xee800000 0 0x80000>; |
| 2701 | #address-cells = <3>; | |
| 2702 | #size-cells = <2>; | |
| 2703 | bus-range = <0x00 0xff>; | |
| 2704 | device_type = "pci"; | |
| 2705 | ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 | |
| 2706 | 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 | |
| 2707 | 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 | |
| 2708 | 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; | |
| 2709 | /* Map all possible DDR as inbound ranges */ | |
| 2710 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; | |
| 2711 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, | |
| 2712 | <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
| 2713 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
| 2714 | #interrupt-cells = <1>; | |
| 2715 | interrupt-map-mask = <0 0 0 0>; | |
| 2716 | interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
| 2717 | clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; | |
| 2718 | clock-names = "pcie", "pcie_bus"; | |
| 38dbb45e | 2719 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 2720 | resets = <&cpg 318>; |
| 9251024a PE |
2721 | status = "disabled"; |
| 2722 | }; | |
| 28fc8131 | 2723 | |
| 24604cd3 SS |
2724 | imr-lx4@fe860000 { |
| 2725 | compatible = "renesas,r8a7795-imr-lx4", | |
| 2726 | "renesas,imr-lx4"; | |
| 2727 | reg = <0 0xfe860000 0 0x2000>; | |
| 2728 | interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; | |
| 2729 | clocks = <&cpg CPG_MOD 823>; | |
| 2730 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
| 2731 | resets = <&cpg 823>; | |
| 2732 | }; | |
| 2733 | ||
| 2734 | imr-lx4@fe870000 { | |
| 2735 | compatible = "renesas,r8a7795-imr-lx4", | |
| 2736 | "renesas,imr-lx4"; | |
| 2737 | reg = <0 0xfe870000 0 0x2000>; | |
| 2738 | interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; | |
| 2739 | clocks = <&cpg CPG_MOD 822>; | |
| 2740 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
| 2741 | resets = <&cpg 822>; | |
| 2742 | }; | |
| 2743 | ||
| 2744 | imr-lx4@fe880000 { | |
| 2745 | compatible = "renesas,r8a7795-imr-lx4", | |
| 2746 | "renesas,imr-lx4"; | |
| 2747 | reg = <0 0xfe880000 0 0x2000>; | |
| 2748 | interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; | |
| 2749 | clocks = <&cpg CPG_MOD 821>; | |
| 2750 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
| 2751 | resets = <&cpg 821>; | |
| 2752 | }; | |
| 2753 | ||
| 2754 | imr-lx4@fe890000 { | |
| 2755 | compatible = "renesas,r8a7795-imr-lx4", | |
| 2756 | "renesas,imr-lx4"; | |
| 2757 | reg = <0 0xfe890000 0 0x2000>; | |
| 2758 | interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; | |
| 2759 | clocks = <&cpg CPG_MOD 820>; | |
| 2760 | power-domains = <&sysc R8A7795_PD_A3VC>; | |
| 2761 | resets = <&cpg 820>; | |
| 2762 | }; | |
| 2763 | ||
| c7a895fc YK |
2764 | vspbc: vsp@fe920000 { |
| 2765 | compatible = "renesas,vsp2"; | |
| 2766 | reg = <0 0xfe920000 0 0x8000>; | |
| 2767 | interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; | |
| 2768 | clocks = <&cpg CPG_MOD 624>; | |
| 2769 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| 2770 | resets = <&cpg 624>; | |
| 2771 | ||
| 2772 | renesas,fcp = <&fcpvb1>; | |
| 2773 | }; | |
| 2774 | ||
| 2775 | vspbd: vsp@fe960000 { | |
| 2776 | compatible = "renesas,vsp2"; | |
| 2777 | reg = <0 0xfe960000 0 0x8000>; | |
| 2778 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; | |
| 2779 | clocks = <&cpg CPG_MOD 626>; | |
| 2780 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| 2781 | resets = <&cpg 626>; | |
| 2782 | ||
| 2783 | renesas,fcp = <&fcpvb0>; | |
| 2784 | }; | |
| 2785 | ||
| 2786 | vspd0: vsp@fea20000 { | |
| 2787 | compatible = "renesas,vsp2"; | |
| 2788 | reg = <0 0xfea20000 0 0x5000>; | |
| 2789 | interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; | |
| 2790 | clocks = <&cpg CPG_MOD 623>; | |
| 2791 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2792 | resets = <&cpg 623>; | |
| 2793 | ||
| 2794 | renesas,fcp = <&fcpvd0>; | |
| 2795 | }; | |
| 2796 | ||
| 2797 | vspd1: vsp@fea28000 { | |
| 2798 | compatible = "renesas,vsp2"; | |
| 2799 | reg = <0 0xfea28000 0 0x5000>; | |
| 2800 | interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; | |
| 2801 | clocks = <&cpg CPG_MOD 622>; | |
| 2802 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2803 | resets = <&cpg 622>; | |
| 2804 | ||
| 2805 | renesas,fcp = <&fcpvd1>; | |
| 2806 | }; | |
| 2807 | ||
| 2808 | vspd2: vsp@fea30000 { | |
| 2809 | compatible = "renesas,vsp2"; | |
| 2810 | reg = <0 0xfea30000 0 0x5000>; | |
| 2811 | interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; | |
| 2812 | clocks = <&cpg CPG_MOD 621>; | |
| 2813 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2814 | resets = <&cpg 621>; | |
| 2815 | ||
| 2816 | renesas,fcp = <&fcpvd2>; | |
| 2817 | }; | |
| 2818 | ||
| 2819 | vspi0: vsp@fe9a0000 { | |
| 2820 | compatible = "renesas,vsp2"; | |
| 2821 | reg = <0 0xfe9a0000 0 0x8000>; | |
| 2822 | interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; | |
| 2823 | clocks = <&cpg CPG_MOD 631>; | |
| 2824 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| 2825 | resets = <&cpg 631>; | |
| 2826 | ||
| 2827 | renesas,fcp = <&fcpvi0>; | |
| 2828 | }; | |
| 2829 | ||
| 2830 | vspi1: vsp@fe9b0000 { | |
| 2831 | compatible = "renesas,vsp2"; | |
| 2832 | reg = <0 0xfe9b0000 0 0x8000>; | |
| 2833 | interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; | |
| 2834 | clocks = <&cpg CPG_MOD 630>; | |
| 2835 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| 2836 | resets = <&cpg 630>; | |
| 2837 | ||
| 2838 | renesas,fcp = <&fcpvi1>; | |
| 2839 | }; | |
| 2840 | ||
| e0f0bda7 SH |
2841 | fdp1@fe940000 { |
| 2842 | compatible = "renesas,fdp1"; | |
| 2843 | reg = <0 0xfe940000 0 0x2400>; | |
| 2844 | interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; | |
| 2845 | clocks = <&cpg CPG_MOD 119>; | |
| 9f8573e3 | 2846 | power-domains = <&sysc R8A7795_PD_A3VP>; |
| e0f0bda7 SH |
2847 | resets = <&cpg 119>; |
| 2848 | renesas,fcp = <&fcpf0>; | |
| 9f8573e3 LP |
2849 | }; |
| 2850 | ||
| e0f0bda7 SH |
2851 | fdp1@fe944000 { |
| 2852 | compatible = "renesas,fdp1"; | |
| 2853 | reg = <0 0xfe944000 0 0x2400>; | |
| 2854 | interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; | |
| 2855 | clocks = <&cpg CPG_MOD 118>; | |
| 52cd0783 | 2856 | power-domains = <&sysc R8A7795_PD_A3VP>; |
| e0f0bda7 SH |
2857 | resets = <&cpg 118>; |
| 2858 | renesas,fcp = <&fcpf1>; | |
| 52cd0783 LP |
2859 | }; |
| 2860 | ||
| 28fc8131 | 2861 | fcpf0: fcp@fe950000 { |
| ab33da0b | 2862 | compatible = "renesas,fcpf"; |
| 28fc8131 KB |
2863 | reg = <0 0xfe950000 0 0x200>; |
| 2864 | clocks = <&cpg CPG_MOD 615>; | |
| 2865 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 2866 | resets = <&cpg 615>; |
| afdeb149 | 2867 | iommus = <&ipmmu_vp0 0>; |
| 28fc8131 KB |
2868 | }; |
| 2869 | ||
| 2870 | fcpf1: fcp@fe951000 { | |
| ab33da0b | 2871 | compatible = "renesas,fcpf"; |
| 28fc8131 KB |
2872 | reg = <0 0xfe951000 0 0x200>; |
| 2873 | clocks = <&cpg CPG_MOD 614>; | |
| 2874 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 2875 | resets = <&cpg 614>; |
| afdeb149 | 2876 | iommus = <&ipmmu_vp1 1>; |
| 28fc8131 KB |
2877 | }; |
| 2878 | ||
| 52cd0783 | 2879 | fcpvb0: fcp@fe96f000 { |
| ab33da0b | 2880 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
2881 | reg = <0 0xfe96f000 0 0x200>; |
| 2882 | clocks = <&cpg CPG_MOD 607>; | |
| 2883 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 2884 | resets = <&cpg 607>; |
| cdd919ba | 2885 | iommus = <&ipmmu_vp0 5>; |
| 52cd0783 LP |
2886 | }; |
| 2887 | ||
| e0f0bda7 SH |
2888 | fcpvb1: fcp@fe92f000 { |
| 2889 | compatible = "renesas,fcpv"; | |
| 2890 | reg = <0 0xfe92f000 0 0x200>; | |
| 2891 | clocks = <&cpg CPG_MOD 606>; | |
| 9f8573e3 | 2892 | power-domains = <&sysc R8A7795_PD_A3VP>; |
| e0f0bda7 SH |
2893 | resets = <&cpg 606>; |
| 2894 | iommus = <&ipmmu_vp1 7>; | |
| 9f8573e3 LP |
2895 | }; |
| 2896 | ||
| 52cd0783 | 2897 | fcpvi0: fcp@fe9af000 { |
| ab33da0b | 2898 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
2899 | reg = <0 0xfe9af000 0 0x200>; |
| 2900 | clocks = <&cpg CPG_MOD 611>; | |
| 2901 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 2902 | resets = <&cpg 611>; |
| a02aac48 | 2903 | iommus = <&ipmmu_vp0 8>; |
| 52cd0783 LP |
2904 | }; |
| 2905 | ||
| 2906 | fcpvi1: fcp@fe9bf000 { | |
| ab33da0b | 2907 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
2908 | reg = <0 0xfe9bf000 0 0x200>; |
| 2909 | clocks = <&cpg CPG_MOD 610>; | |
| 2910 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 2911 | resets = <&cpg 610>; |
| a02aac48 | 2912 | iommus = <&ipmmu_vp1 9>; |
| 52cd0783 LP |
2913 | }; |
| 2914 | ||
| e0f0bda7 SH |
2915 | fcpvd0: fcp@fea27000 { |
| 2916 | compatible = "renesas,fcpv"; | |
| 2917 | reg = <0 0xfea27000 0 0x200>; | |
| 2918 | clocks = <&cpg CPG_MOD 603>; | |
| 2919 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2920 | resets = <&cpg 603>; | |
| 2921 | iommus = <&ipmmu_vi0 8>; | |
| 2922 | }; | |
| 2923 | ||
| 2924 | fcpvd1: fcp@fea2f000 { | |
| 2925 | compatible = "renesas,fcpv"; | |
| 2926 | reg = <0 0xfea2f000 0 0x200>; | |
| 2927 | clocks = <&cpg CPG_MOD 602>; | |
| 2928 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2929 | resets = <&cpg 602>; | |
| 2930 | iommus = <&ipmmu_vi0 9>; | |
| 2931 | }; | |
| 2932 | ||
| 2933 | fcpvd2: fcp@fea37000 { | |
| 2934 | compatible = "renesas,fcpv"; | |
| 2935 | reg = <0 0xfea37000 0 0x200>; | |
| 2936 | clocks = <&cpg CPG_MOD 601>; | |
| 2937 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2938 | resets = <&cpg 601>; | |
| 2939 | iommus = <&ipmmu_vi1 10>; | |
| 2940 | }; | |
| 2941 | ||
| 15da7132 NS |
2942 | csi20: csi2@fea80000 { |
| 2943 | compatible = "renesas,r8a7795-csi2"; | |
| 2944 | reg = <0 0xfea80000 0 0x10000>; | |
| 2945 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; | |
| 2946 | clocks = <&cpg CPG_MOD 714>; | |
| 2947 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 2948 | resets = <&cpg 714>; | |
| 2949 | status = "disabled"; | |
| 2950 | ||
| 2951 | ports { | |
| 2952 | #address-cells = <1>; | |
| 2953 | #size-cells = <0>; | |
| 2954 | ||
| 2955 | port@1 { | |
| 2956 | #address-cells = <1>; | |
| 2957 | #size-cells = <0>; | |
| 2958 | ||
| 2959 | reg = <1>; | |
| 2960 | ||
| 2961 | csi20vin0: endpoint@0 { | |
| 2962 | reg = <0>; | |
| 2963 | remote-endpoint = <&vin0csi20>; | |
| 2964 | }; | |
| 2965 | csi20vin1: endpoint@1 { | |
| 2966 | reg = <1>; | |
| 2967 | remote-endpoint = <&vin1csi20>; | |
| 2968 | }; | |
| 2969 | csi20vin2: endpoint@2 { | |
| 2970 | reg = <2>; | |
| 2971 | remote-endpoint = <&vin2csi20>; | |
| 2972 | }; | |
| 2973 | csi20vin3: endpoint@3 { | |
| 2974 | reg = <3>; | |
| 2975 | remote-endpoint = <&vin3csi20>; | |
| 2976 | }; | |
| 2977 | csi20vin4: endpoint@4 { | |
| 2978 | reg = <4>; | |
| 2979 | remote-endpoint = <&vin4csi20>; | |
| 2980 | }; | |
| 2981 | csi20vin5: endpoint@5 { | |
| 2982 | reg = <5>; | |
| 2983 | remote-endpoint = <&vin5csi20>; | |
| 2984 | }; | |
| 2985 | csi20vin6: endpoint@6 { | |
| 2986 | reg = <6>; | |
| 2987 | remote-endpoint = <&vin6csi20>; | |
| 2988 | }; | |
| 2989 | csi20vin7: endpoint@7 { | |
| 2990 | reg = <7>; | |
| 2991 | remote-endpoint = <&vin7csi20>; | |
| 2992 | }; | |
| 2993 | }; | |
| 2994 | }; | |
| 2995 | }; | |
| 2996 | ||
| 2997 | csi40: csi2@feaa0000 { | |
| 2998 | compatible = "renesas,r8a7795-csi2"; | |
| 2999 | reg = <0 0xfeaa0000 0 0x10000>; | |
| 3000 | interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; | |
| 3001 | clocks = <&cpg CPG_MOD 716>; | |
| 3002 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 3003 | resets = <&cpg 716>; | |
| 3004 | status = "disabled"; | |
| 3005 | ||
| 3006 | ports { | |
| 3007 | #address-cells = <1>; | |
| 3008 | #size-cells = <0>; | |
| 3009 | ||
| 3010 | port@1 { | |
| 3011 | #address-cells = <1>; | |
| 3012 | #size-cells = <0>; | |
| 3013 | ||
| 3014 | reg = <1>; | |
| 3015 | ||
| 3016 | csi40vin0: endpoint@0 { | |
| 3017 | reg = <0>; | |
| 3018 | remote-endpoint = <&vin0csi40>; | |
| 3019 | }; | |
| 3020 | csi40vin1: endpoint@1 { | |
| 3021 | reg = <1>; | |
| 3022 | remote-endpoint = <&vin1csi40>; | |
| 3023 | }; | |
| 3024 | csi40vin2: endpoint@2 { | |
| 3025 | reg = <2>; | |
| 3026 | remote-endpoint = <&vin2csi40>; | |
| 3027 | }; | |
| 3028 | csi40vin3: endpoint@3 { | |
| 3029 | reg = <3>; | |
| 3030 | remote-endpoint = <&vin3csi40>; | |
| 3031 | }; | |
| 3032 | }; | |
| 3033 | }; | |
| 3034 | }; | |
| 3035 | ||
| 3036 | csi41: csi2@feab0000 { | |
| 3037 | compatible = "renesas,r8a7795-csi2"; | |
| 3038 | reg = <0 0xfeab0000 0 0x10000>; | |
| 3039 | interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; | |
| 3040 | clocks = <&cpg CPG_MOD 715>; | |
| 3041 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 3042 | resets = <&cpg 715>; | |
| 3043 | status = "disabled"; | |
| 3044 | ||
| 3045 | ports { | |
| 3046 | #address-cells = <1>; | |
| 3047 | #size-cells = <0>; | |
| 3048 | ||
| 3049 | port@1 { | |
| 3050 | #address-cells = <1>; | |
| 3051 | #size-cells = <0>; | |
| 3052 | ||
| 3053 | reg = <1>; | |
| 3054 | ||
| 3055 | csi41vin4: endpoint@0 { | |
| 3056 | reg = <0>; | |
| 3057 | remote-endpoint = <&vin4csi41>; | |
| 3058 | }; | |
| 3059 | csi41vin5: endpoint@1 { | |
| 3060 | reg = <1>; | |
| 3061 | remote-endpoint = <&vin5csi41>; | |
| 3062 | }; | |
| 3063 | csi41vin6: endpoint@2 { | |
| 3064 | reg = <2>; | |
| 3065 | remote-endpoint = <&vin6csi41>; | |
| 3066 | }; | |
| 3067 | csi41vin7: endpoint@3 { | |
| 3068 | reg = <3>; | |
| 3069 | remote-endpoint = <&vin7csi41>; | |
| 3070 | }; | |
| 3071 | }; | |
| 3072 | }; | |
| 3073 | }; | |
| 3074 | ||
| 6b5ac2f1 | 3075 | hdmi0: hdmi@fead0000 { |
| 12daaf78 UH |
3076 | compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; |
| 3077 | reg = <0 0xfead0000 0 0x10000>; | |
| 3078 | interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; | |
| 3079 | clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; | |
| 3080 | clock-names = "iahb", "isfr"; | |
| 3081 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 3082 | resets = <&cpg 729>; | |
| 3083 | status = "disabled"; | |
| 3084 | ||
| 3085 | ports { | |
| 3086 | #address-cells = <1>; | |
| 3087 | #size-cells = <0>; | |
| 3088 | port@0 { | |
| 3089 | reg = <0>; | |
| 3090 | dw_hdmi0_in: endpoint { | |
| 3091 | remote-endpoint = <&du_out_hdmi0>; | |
| 3092 | }; | |
| 3093 | }; | |
| 3094 | port@1 { | |
| 3095 | reg = <1>; | |
| 3096 | }; | |
| 5a0d8a6f KM |
3097 | port@2 { |
| 3098 | /* HDMI sound */ | |
| 3099 | reg = <2>; | |
| 3100 | }; | |
| 12daaf78 UH |
3101 | }; |
| 3102 | }; | |
| 3103 | ||
| 6b5ac2f1 | 3104 | hdmi1: hdmi@feae0000 { |
| 12daaf78 UH |
3105 | compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; |
| 3106 | reg = <0 0xfeae0000 0 0x10000>; | |
| 3107 | interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; | |
| 3108 | clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; | |
| 3109 | clock-names = "iahb", "isfr"; | |
| 3110 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 3111 | resets = <&cpg 728>; | |
| 3112 | status = "disabled"; | |
| 3113 | ||
| 3114 | ports { | |
| 3115 | #address-cells = <1>; | |
| 3116 | #size-cells = <0>; | |
| 3117 | port@0 { | |
| 3118 | reg = <0>; | |
| 3119 | dw_hdmi1_in: endpoint { | |
| 3120 | remote-endpoint = <&du_out_hdmi1>; | |
| 3121 | }; | |
| 3122 | }; | |
| 3123 | port@1 { | |
| 3124 | reg = <1>; | |
| 3125 | }; | |
| 5a0d8a6f KM |
3126 | port@2 { |
| 3127 | /* HDMI sound */ | |
| 3128 | reg = <2>; | |
| 3129 | }; | |
| 12daaf78 UH |
3130 | }; |
| 3131 | }; | |
| 3132 | ||
| a001a07f | 3133 | du: display@feb00000 { |
| f0499b9f | 3134 | compatible = "renesas,du-r8a7795"; |
| 58e8ed2e | 3135 | reg = <0 0xfeb00000 0 0x80000>; |
| a001a07f LP |
3136 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| 3137 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, | |
| 3138 | <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, | |
| 3139 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; | |
| 3140 | clocks = <&cpg CPG_MOD 724>, | |
| 3141 | <&cpg CPG_MOD 723>, | |
| 3142 | <&cpg CPG_MOD 722>, | |
| 58e8ed2e LP |
3143 | <&cpg CPG_MOD 721>; |
| 3144 | clock-names = "du.0", "du.1", "du.2", "du.3"; | |
| 38290431 | 3145 | vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; |
| a001a07f LP |
3146 | status = "disabled"; |
| 3147 | ||
| a001a07f LP |
3148 | ports { |
| 3149 | #address-cells = <1>; | |
| 3150 | #size-cells = <0>; | |
| 3151 | ||
| 3152 | port@0 { | |
| 3153 | reg = <0>; | |
| 3154 | du_out_rgb: endpoint { | |
| 3155 | }; | |
| 3156 | }; | |
| 3157 | port@1 { | |
| 3158 | reg = <1>; | |
| 3159 | du_out_hdmi0: endpoint { | |
| 12daaf78 | 3160 | remote-endpoint = <&dw_hdmi0_in>; |
| a001a07f LP |
3161 | }; |
| 3162 | }; | |
| 3163 | port@2 { | |
| 3164 | reg = <2>; | |
| 3165 | du_out_hdmi1: endpoint { | |
| 12daaf78 | 3166 | remote-endpoint = <&dw_hdmi1_in>; |
| a001a07f LP |
3167 | }; |
| 3168 | }; | |
| 3169 | port@3 { | |
| 3170 | reg = <3>; | |
| 3171 | du_out_lvds0: endpoint { | |
| 58e8ed2e LP |
3172 | remote-endpoint = <&lvds0_in>; |
| 3173 | }; | |
| 3174 | }; | |
| 3175 | }; | |
| 3176 | }; | |
| 3177 | ||
| 3178 | lvds0: lvds@feb90000 { | |
| 3179 | compatible = "renesas,r8a7795-lvds"; | |
| 3180 | reg = <0 0xfeb90000 0 0x14>; | |
| 3181 | clocks = <&cpg CPG_MOD 727>; | |
| 3182 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 3183 | resets = <&cpg 727>; | |
| 3184 | status = "disabled"; | |
| 3185 | ||
| 3186 | ports { | |
| 3187 | #address-cells = <1>; | |
| 3188 | #size-cells = <0>; | |
| 3189 | ||
| 3190 | port@0 { | |
| 3191 | reg = <0>; | |
| 3192 | lvds0_in: endpoint { | |
| 3193 | remote-endpoint = <&du_out_lvds0>; | |
| 3194 | }; | |
| 3195 | }; | |
| 3196 | port@1 { | |
| 3197 | reg = <1>; | |
| 3198 | lvds0_out: endpoint { | |
| a001a07f LP |
3199 | }; |
| 3200 | }; | |
| 3201 | }; | |
| 3202 | }; | |
| b443cd17 | 3203 | |
| e0f0bda7 SH |
3204 | prr: chipid@fff00044 { |
| 3205 | compatible = "renesas,prr"; | |
| 3206 | reg = <0 0xfff00044 0 4>; | |
| b443cd17 | 3207 | }; |
| 4f5dc77b | 3208 | }; |
| b443cd17 | 3209 | |
| 4f5dc77b SH |
3210 | thermal-zones { |
| 3211 | sensor_thermal1: sensor-thermal1 { | |
| 3212 | polling-delay-passive = <250>; | |
| 3213 | polling-delay = <1000>; | |
| 3214 | thermal-sensors = <&tsc 0>; | |
| 15d8cd83 | 3215 | sustainable-power = <6313>; |
| 4f5dc77b SH |
3216 | |
| 3217 | trips { | |
| 3218 | sensor1_crit: sensor1-crit { | |
| 3219 | temperature = <120000>; | |
| 02f15e4b | 3220 | hysteresis = <1000>; |
| 4f5dc77b | 3221 | type = "critical"; |
| b443cd17 WS |
3222 | }; |
| 3223 | }; | |
| 4f5dc77b | 3224 | }; |
| b443cd17 | 3225 | |
| 4f5dc77b SH |
3226 | sensor_thermal2: sensor-thermal2 { |
| 3227 | polling-delay-passive = <250>; | |
| 3228 | polling-delay = <1000>; | |
| 3229 | thermal-sensors = <&tsc 1>; | |
| 15d8cd83 | 3230 | sustainable-power = <6313>; |
| b443cd17 | 3231 | |
| 4f5dc77b SH |
3232 | trips { |
| 3233 | sensor2_crit: sensor2-crit { | |
| 3234 | temperature = <120000>; | |
| 02f15e4b | 3235 | hysteresis = <1000>; |
| 4f5dc77b | 3236 | type = "critical"; |
| b443cd17 WS |
3237 | }; |
| 3238 | }; | |
| 4f5dc77b | 3239 | }; |
| b443cd17 | 3240 | |
| 4f5dc77b SH |
3241 | sensor_thermal3: sensor-thermal3 { |
| 3242 | polling-delay-passive = <250>; | |
| 3243 | polling-delay = <1000>; | |
| 3244 | thermal-sensors = <&tsc 2>; | |
| b443cd17 | 3245 | |
| 4f5dc77b | 3246 | trips { |
| 15d8cd83 DP |
3247 | target: trip-point1 { |
| 3248 | temperature = <100000>; | |
| 02f15e4b | 3249 | hysteresis = <1000>; |
| 0c38c54e NS |
3250 | type = "passive"; |
| 3251 | }; | |
| 15d8cd83 | 3252 | |
| 4f5dc77b SH |
3253 | sensor3_crit: sensor3-crit { |
| 3254 | temperature = <120000>; | |
| 02f15e4b | 3255 | hysteresis = <1000>; |
| 4f5dc77b | 3256 | type = "critical"; |
| b443cd17 WS |
3257 | }; |
| 3258 | }; | |
| 0c38c54e NS |
3259 | |
| 3260 | cooling-maps { | |
| 3261 | map0 { | |
| 15d8cd83 DP |
3262 | trip = <&target>; |
| 3263 | cooling-device = <&a57_0 2 4>; | |
| 3264 | contribution = <1024>; | |
| 3265 | }; | |
| 3266 | ||
| 3267 | map1 { | |
| 3268 | trip = <&target>; | |
| 3269 | cooling-device = <&a53_0 0 2>; | |
| 3270 | contribution = <1024>; | |
| 0c38c54e NS |
3271 | }; |
| 3272 | }; | |
| b443cd17 | 3273 | }; |
| 26a7e06d | 3274 | }; |
| 7c1e5ea6 | 3275 | |
| 82cf1d15 SH |
3276 | timer { |
| 3277 | compatible = "arm,armv8-timer"; | |
| 3278 | interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 3279 | <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 3280 | <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 3281 | <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; | |
| 3282 | }; | |
| 3283 | ||
| 7c1e5ea6 YS |
3284 | /* External USB clocks - can be overridden by the board */ |
| 3285 | usb3s0_clk: usb3s0 { | |
| 3286 | compatible = "fixed-clock"; | |
| 3287 | #clock-cells = <0>; | |
| 3288 | clock-frequency = <0>; | |
| 3289 | }; | |
| 3290 | ||
| 3291 | usb_extal_clk: usb_extal { | |
| 3292 | compatible = "fixed-clock"; | |
| 3293 | #clock-cells = <0>; | |
| 3294 | clock-frequency = <0>; | |
| 3295 | }; | |
| 26a7e06d | 3296 | }; |