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Merge tag 'soc-drivers-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[linux-block.git] / arch / arm64 / boot / dts / renesas / r8a774e1.dtsi
CommitLineData
4dd61a52
MCR		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11#include <dt-bindings/power/r8a774e1-sysc.h>
12
4dd61a52
MCR		 13/ {
14 compatible = "renesas,r8a774e1";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 /*
19 * The external audio clocks are configured as 0 Hz fixed frequency
20 * clocks by default.
21 * Boards that provide audio clocks should override them.
22 */
23 audio_clk_a: audio_clk_a {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
27 };
28
7de8bfaa
LP		 29 audio_clk_b: audio_clk_b {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
33 };
34
4dd61a52
MCR		 35 audio_clk_c: audio_clk_c {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
39 };
40
8e340e75
LP		 41 /* External CAN clock - to be overridden by boards that provide it */
42 can_clk: can {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <0>;
46 };
47
7744b393 48 cluster0_opp: opp-table-0 {
d18dbce4
MCR		 49 compatible = "operating-points-v2";
50 opp-shared;
51
52 opp-500000000 {
53 opp-hz = /bits/ 64 <500000000>;
54 opp-microvolt = <820000>;
55 clock-latency-ns = <300000>;
56 };
57 opp-1000000000 {
58 opp-hz = /bits/ 64 <1000000000>;
59 opp-microvolt = <820000>;
60 clock-latency-ns = <300000>;
61 };
62 opp-1500000000 {
63 opp-hz = /bits/ 64 <1500000000>;
64 opp-microvolt = <820000>;
65 clock-latency-ns = <300000>;
66 opp-suspend;
67 };
68 };
69
7744b393 70 cluster1_opp: opp-table-1 {
d18dbce4
MCR		 71 compatible = "operating-points-v2";
72 opp-shared;
73
74 opp-800000000 {
75 opp-hz = /bits/ 64 <800000000>;
76 opp-microvolt = <820000>;
77 clock-latency-ns = <300000>;
78 };
79 opp-1000000000 {
80 opp-hz = /bits/ 64 <1000000000>;
81 opp-microvolt = <820000>;
82 clock-latency-ns = <300000>;
83 };
84 opp-1200000000 {
85 opp-hz = /bits/ 64 <1200000000>;
86 opp-microvolt = <820000>;
87 clock-latency-ns = <300000>;
88 };
89 };
90
4dd61a52
MCR		 91 cpus {
92 #address-cells = <1>;
93 #size-cells = <0>;
94
95 cpu-map {
96 cluster0 {
97 core0 {
98 cpu = <&a57_0>;
99 };
100 core1 {
101 cpu = <&a57_1>;
102 };
103 core2 {
104 cpu = <&a57_2>;
105 };
106 core3 {
107 cpu = <&a57_3>;
108 };
109 };
110
111 cluster1 {
112 core0 {
113 cpu = <&a53_0>;
114 };
115 core1 {
116 cpu = <&a53_1>;
117 };
118 core2 {
119 cpu = <&a53_2>;
120 };
121 core3 {
122 cpu = <&a53_3>;
123 };
124 };
125 };
126
127 a57_0: cpu@0 {
128 compatible = "arm,cortex-a57";
129 reg = <0x0>;
130 device_type = "cpu";
131 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
132 next-level-cache = <&L2_CA57>;
133 enable-method = "psci";
912d3c53 134 cpu-idle-states = <&CPU_SLEEP_0>;
4dd61a52
MCR		 135 dynamic-power-coefficient = <854>;
136 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
d18dbce4 137 operating-points-v2 = <&cluster0_opp>;
4dd61a52
MCR		 138 capacity-dmips-mhz = <1024>;
139 #cooling-cells = <2>;
140 };
141
142 a57_1: cpu@1 {
143 compatible = "arm,cortex-a57";
144 reg = <0x1>;
145 device_type = "cpu";
146 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
147 next-level-cache = <&L2_CA57>;
148 enable-method = "psci";
912d3c53 149 cpu-idle-states = <&CPU_SLEEP_0>;
4dd61a52 150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
d18dbce4 151 operating-points-v2 = <&cluster0_opp>;
4dd61a52
MCR		 152 capacity-dmips-mhz = <1024>;
153 #cooling-cells = <2>;
154 };
155
156 a57_2: cpu@2 {
157 compatible = "arm,cortex-a57";
158 reg = <0x2>;
159 device_type = "cpu";
160 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
161 next-level-cache = <&L2_CA57>;
162 enable-method = "psci";
912d3c53 163 cpu-idle-states = <&CPU_SLEEP_0>;
4dd61a52 164 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
d18dbce4 165 operating-points-v2 = <&cluster0_opp>;
4dd61a52
MCR		 166 capacity-dmips-mhz = <1024>;
167 #cooling-cells = <2>;
168 };
169
170 a57_3: cpu@3 {
171 compatible = "arm,cortex-a57";
172 reg = <0x3>;
173 device_type = "cpu";
174 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
175 next-level-cache = <&L2_CA57>;
176 enable-method = "psci";
912d3c53 177 cpu-idle-states = <&CPU_SLEEP_0>;
4dd61a52 178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
d18dbce4 179 operating-points-v2 = <&cluster0_opp>;
4dd61a52
MCR		 180 capacity-dmips-mhz = <1024>;
181 #cooling-cells = <2>;
182 };
183
184 a53_0: cpu@100 {
185 compatible = "arm,cortex-a53";
186 reg = <0x100>;
187 device_type = "cpu";
188 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
189 next-level-cache = <&L2_CA53>;
190 enable-method = "psci";
912d3c53 191 cpu-idle-states = <&CPU_SLEEP_1>;
4dd61a52
MCR		 192 #cooling-cells = <2>;
193 dynamic-power-coefficient = <277>;
194 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
d18dbce4 195 operating-points-v2 = <&cluster1_opp>;
4dd61a52
MCR		 196 capacity-dmips-mhz = <535>;
197 };
198
199 a53_1: cpu@101 {
200 compatible = "arm,cortex-a53";
201 reg = <0x101>;
202 device_type = "cpu";
203 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
204 next-level-cache = <&L2_CA53>;
205 enable-method = "psci";
912d3c53 206 cpu-idle-states = <&CPU_SLEEP_1>;
4dd61a52 207 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
d18dbce4 208 operating-points-v2 = <&cluster1_opp>;
4dd61a52
MCR		 209 capacity-dmips-mhz = <535>;
210 };
211
212 a53_2: cpu@102 {
213 compatible = "arm,cortex-a53";
214 reg = <0x102>;
215 device_type = "cpu";
216 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
217 next-level-cache = <&L2_CA53>;
218 enable-method = "psci";
912d3c53 219 cpu-idle-states = <&CPU_SLEEP_1>;
4dd61a52 220 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
d18dbce4 221 operating-points-v2 = <&cluster1_opp>;
4dd61a52
MCR		 222 capacity-dmips-mhz = <535>;
223 };
224
225 a53_3: cpu@103 {
226 compatible = "arm,cortex-a53";
227 reg = <0x103>;
228 device_type = "cpu";
229 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
230 next-level-cache = <&L2_CA53>;
231 enable-method = "psci";
912d3c53 232 cpu-idle-states = <&CPU_SLEEP_1>;
4dd61a52 233 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
d18dbce4 234 operating-points-v2 = <&cluster1_opp>;
4dd61a52
MCR		 235 capacity-dmips-mhz = <535>;
236 };
237
238 L2_CA57: cache-controller-0 {
239 compatible = "cache";
240 power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
241 cache-unified;
242 cache-level = <2>;
243 };
244
245 L2_CA53: cache-controller-1 {
246 compatible = "cache";
247 power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
248 cache-unified;
249 cache-level = <2>;
250 };
912d3c53
LP		 251
252 idle-states {
253 entry-method = "psci";
254
255 CPU_SLEEP_0: cpu-sleep-0 {
256 compatible = "arm,idle-state";
257 arm,psci-suspend-param = <0x0010000>;
258 local-timer-stop;
259 entry-latency-us = <400>;
260 exit-latency-us = <500>;
261 min-residency-us = <4000>;
262 };
263
264 CPU_SLEEP_1: cpu-sleep-1 {
265 compatible = "arm,idle-state";
266 arm,psci-suspend-param = <0x0010000>;
267 local-timer-stop;
268 entry-latency-us = <700>;
269 exit-latency-us = <700>;
270 min-residency-us = <5000>;
271 };
272 };
4dd61a52
MCR		 273 };
274
275 extal_clk: extal {
276 compatible = "fixed-clock";
277 #clock-cells = <0>;
278 /* This value must be overridden by the board */
279 clock-frequency = <0>;
280 };
281
282 extalr_clk: extalr {
283 compatible = "fixed-clock";
284 #clock-cells = <0>;
285 /* This value must be overridden by the board */
286 clock-frequency = <0>;
287 };
288
289 /* External PCIe clock - can be overridden by the board */
290 pcie_bus_clk: pcie_bus {
291 compatible = "fixed-clock";
292 #clock-cells = <0>;
293 clock-frequency = <0>;
294 };
295
296 pmu_a53 {
297 compatible = "arm,cortex-a53-pmu";
298 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
299 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
300 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
301 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
303 };
304
305 pmu_a57 {
306 compatible = "arm,cortex-a57-pmu";
307 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
308 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
309 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
310 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
311 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
312 };
313
314 psci {
315 compatible = "arm,psci-1.0", "arm,psci-0.2";
316 method = "smc";
317 };
318
319 /* External SCIF clock - to be overridden by boards that provide it */
320 scif_clk: scif {
321 compatible = "fixed-clock";
322 #clock-cells = <0>;
323 clock-frequency = <0>;
324 };
325
326 soc {
327 compatible = "simple-bus";
328 interrupt-parent = <&gic>;
329 #address-cells = <2>;
330 #size-cells = <2>;
331 ranges;
332
333 rwdt: watchdog@e6020000 {
96ebdb7a
LP		 334 compatible = "renesas,r8a774e1-wdt",
335 "renesas,rcar-gen3-wdt";
4dd61a52 336 reg = <0 0xe6020000 0 0x0c>;
96ebdb7a
LP		 337 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cpg CPG_MOD 402>;
339 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
340 resets = <&cpg 402>;
4dd61a52 341 status = "disabled";
4dd61a52
MCR		 342 };
343
344 gpio0: gpio@e6050000 {
43b0c905
MCR		 345 compatible = "renesas,gpio-r8a774e1",
346 "renesas,rcar-gen3-gpio";
4dd61a52 347 reg = <0 0xe6050000 0 0x50>;
43b0c905 348 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
4dd61a52
MCR		 349 #gpio-cells = <2>;
350 gpio-controller;
43b0c905 351 gpio-ranges = <&pfc 0 0 16>;
4dd61a52
MCR		 352 #interrupt-cells = <2>;
353 interrupt-controller;
43b0c905
MCR		 354 clocks = <&cpg CPG_MOD 912>;
355 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
356 resets = <&cpg 912>;
4dd61a52
MCR		 357 };
358
359 gpio1: gpio@e6051000 {
43b0c905
MCR		 360 compatible = "renesas,gpio-r8a774e1",
361 "renesas,rcar-gen3-gpio";
4dd61a52 362 reg = <0 0xe6051000 0 0x50>;
43b0c905 363 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4dd61a52
MCR		 364 #gpio-cells = <2>;
365 gpio-controller;
43b0c905 366 gpio-ranges = <&pfc 0 32 29>;
4dd61a52
MCR		 367 #interrupt-cells = <2>;
368 interrupt-controller;
43b0c905
MCR		 369 clocks = <&cpg CPG_MOD 911>;
370 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
371 resets = <&cpg 911>;
4dd61a52
MCR		 372 };
373
374 gpio2: gpio@e6052000 {
43b0c905
MCR		 375 compatible = "renesas,gpio-r8a774e1",
376 "renesas,rcar-gen3-gpio";
4dd61a52 377 reg = <0 0xe6052000 0 0x50>;
43b0c905 378 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4dd61a52
MCR		 379 #gpio-cells = <2>;
380 gpio-controller;
43b0c905 381 gpio-ranges = <&pfc 0 64 15>;
4dd61a52
MCR		 382 #interrupt-cells = <2>;
383 interrupt-controller;
43b0c905
MCR		 384 clocks = <&cpg CPG_MOD 910>;
385 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
386 resets = <&cpg 910>;
4dd61a52
MCR		 387 };
388
389 gpio3: gpio@e6053000 {
43b0c905
MCR		 390 compatible = "renesas,gpio-r8a774e1",
391 "renesas,rcar-gen3-gpio";
4dd61a52 392 reg = <0 0xe6053000 0 0x50>;
43b0c905 393 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
4dd61a52
MCR		 394 #gpio-cells = <2>;
395 gpio-controller;
43b0c905 396 gpio-ranges = <&pfc 0 96 16>;
4dd61a52
MCR		 397 #interrupt-cells = <2>;
398 interrupt-controller;
43b0c905
MCR		 399 clocks = <&cpg CPG_MOD 909>;
400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
401 resets = <&cpg 909>;
4dd61a52
MCR		 402 };
403
404 gpio4: gpio@e6054000 {
43b0c905
MCR		 405 compatible = "renesas,gpio-r8a774e1",
406 "renesas,rcar-gen3-gpio";
4dd61a52 407 reg = <0 0xe6054000 0 0x50>;
43b0c905 408 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
4dd61a52
MCR		 409 #gpio-cells = <2>;
410 gpio-controller;
43b0c905 411 gpio-ranges = <&pfc 0 128 18>;
4dd61a52
MCR		 412 #interrupt-cells = <2>;
413 interrupt-controller;
43b0c905
MCR		 414 clocks = <&cpg CPG_MOD 908>;
415 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
416 resets = <&cpg 908>;
4dd61a52
MCR		 417 };
418
419 gpio5: gpio@e6055000 {
43b0c905
MCR		 420 compatible = "renesas,gpio-r8a774e1",
421 "renesas,rcar-gen3-gpio";
4dd61a52 422 reg = <0 0xe6055000 0 0x50>;
43b0c905 423 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4dd61a52
MCR		 424 #gpio-cells = <2>;
425 gpio-controller;
43b0c905 426 gpio-ranges = <&pfc 0 160 26>;
4dd61a52
MCR		 427 #interrupt-cells = <2>;
428 interrupt-controller;
43b0c905
MCR		 429 clocks = <&cpg CPG_MOD 907>;
430 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
431 resets = <&cpg 907>;
4dd61a52
MCR		 432 };
433
434 gpio6: gpio@e6055400 {
43b0c905
MCR		 435 compatible = "renesas,gpio-r8a774e1",
436 "renesas,rcar-gen3-gpio";
4dd61a52 437 reg = <0 0xe6055400 0 0x50>;
43b0c905 438 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4dd61a52
MCR		 439 #gpio-cells = <2>;
440 gpio-controller;
43b0c905 441 gpio-ranges = <&pfc 0 192 32>;
4dd61a52
MCR		 442 #interrupt-cells = <2>;
443 interrupt-controller;
43b0c905
MCR		 444 clocks = <&cpg CPG_MOD 906>;
445 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
446 resets = <&cpg 906>;
4dd61a52
MCR		 447 };
448
449 gpio7: gpio@e6055800 {
43b0c905
MCR		 450 compatible = "renesas,gpio-r8a774e1",
451 "renesas,rcar-gen3-gpio";
4dd61a52 452 reg = <0 0xe6055800 0 0x50>;
43b0c905 453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4dd61a52
MCR		 454 #gpio-cells = <2>;
455 gpio-controller;
43b0c905 456 gpio-ranges = <&pfc 0 224 4>;
4dd61a52
MCR		 457 #interrupt-cells = <2>;
458 interrupt-controller;
43b0c905
MCR		 459 clocks = <&cpg CPG_MOD 905>;
460 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
461 resets = <&cpg 905>;
4dd61a52
MCR		 462 };
463
a2053990 464 pfc: pinctrl@e6060000 {
4dd61a52
MCR		 465 compatible = "renesas,pfc-r8a774e1";
466 reg = <0 0xe6060000 0 0x50c>;
467 };
468
c6c4b7de
MCR		 469 cmt0: timer@e60f0000 {
470 compatible = "renesas,r8a774e1-cmt0",
471 "renesas,rcar-gen3-cmt0";
472 reg = <0 0xe60f0000 0 0x1004>;
473 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&cpg CPG_MOD 303>;
476 clock-names = "fck";
477 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
478 resets = <&cpg 303>;
479 status = "disabled";
480 };
481
482 cmt1: timer@e6130000 {
483 compatible = "renesas,r8a774e1-cmt1",
484 "renesas,rcar-gen3-cmt1";
485 reg = <0 0xe6130000 0 0x1004>;
486 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 302>;
495 clock-names = "fck";
496 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
497 resets = <&cpg 302>;
498 status = "disabled";
499 };
500
501 cmt2: timer@e6140000 {
502 compatible = "renesas,r8a774e1-cmt1",
503 "renesas,rcar-gen3-cmt1";
504 reg = <0 0xe6140000 0 0x1004>;
505 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cpg CPG_MOD 301>;
514 clock-names = "fck";
515 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
516 resets = <&cpg 301>;
517 status = "disabled";
518 };
519
520 cmt3: timer@e6148000 {
521 compatible = "renesas,r8a774e1-cmt1",
522 "renesas,rcar-gen3-cmt1";
523 reg = <0 0xe6148000 0 0x1004>;
524 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cpg CPG_MOD 300>;
533 clock-names = "fck";
534 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
535 resets = <&cpg 300>;
536 status = "disabled";
537 };
538
4dd61a52
MCR		 539 cpg: clock-controller@e6150000 {
540 compatible = "renesas,r8a774e1-cpg-mssr";
541 reg = <0 0xe6150000 0 0x1000>;
542 clocks = <&extal_clk>, <&extalr_clk>;
543 clock-names = "extal", "extalr";
544 #clock-cells = <2>;
545 #power-domain-cells = <0>;
546 #reset-cells = <1>;
547 };
548
549 rst: reset-controller@e6160000 {
550 compatible = "renesas,r8a774e1-rst";
551 reg = <0 0xe6160000 0 0x0200>;
552 };
553
554 sysc: system-controller@e6180000 {
555 compatible = "renesas,r8a774e1-sysc";
556 reg = <0 0xe6180000 0 0x0400>;
557 #power-domain-cells = <1>;
558 };
559
6dd73367
MCR		 560 tsc: thermal@e6198000 {
561 compatible = "renesas,r8a774e1-thermal";
562 reg = <0 0xe6198000 0 0x100>,
563 <0 0xe61a0000 0 0x100>,
564 <0 0xe61a8000 0 0x100>;
565 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cpg CPG_MOD 522>;
569 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
570 resets = <&cpg 522>;
571 #thermal-sensor-cells = <1>;
572 };
573
4dd61a52
MCR		 574 intc_ex: interrupt-controller@e61c0000 {
575 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
576 #interrupt-cells = <2>;
577 interrupt-controller;
578 reg = <0 0xe61c0000 0 0x200>;
579 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&cpg CPG_MOD 407>;
586 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
587 resets = <&cpg 407>;
588 };
589
58eb575c
MCR		 590 tmu0: timer@e61e0000 {
591 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
592 reg = <0 0xe61e0000 0 0x30>;
593 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
c53866cb 596 interrupt-names = "tuni0", "tuni1", "tuni2";
58eb575c
MCR		 597 clocks = <&cpg CPG_MOD 125>;
598 clock-names = "fck";
599 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
600 resets = <&cpg 125>;
601 status = "disabled";
602 };
603
604 tmu1: timer@e6fc0000 {
605 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
606 reg = <0 0xe6fc0000 0 0x30>;
607 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
c53866cb
GU		 609 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
611 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
58eb575c
MCR		 612 clocks = <&cpg CPG_MOD 124>;
613 clock-names = "fck";
614 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
615 resets = <&cpg 124>;
616 status = "disabled";
617 };
618
619 tmu2: timer@e6fd0000 {
620 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
621 reg = <0 0xe6fd0000 0 0x30>;
622 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
c53866cb
GU		 624 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
626 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
58eb575c
MCR		 627 clocks = <&cpg CPG_MOD 123>;
628 clock-names = "fck";
629 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
630 resets = <&cpg 123>;
631 status = "disabled";
632 };
633
634 tmu3: timer@e6fe0000 {
635 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
636 reg = <0 0xe6fe0000 0 0x30>;
637 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
c53866cb 640 interrupt-names = "tuni0", "tuni1", "tuni2";
58eb575c
MCR		 641 clocks = <&cpg CPG_MOD 122>;
642 clock-names = "fck";
643 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
644 resets = <&cpg 122>;
645 status = "disabled";
646 };
647
648 tmu4: timer@ffc00000 {
649 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
650 reg = <0 0xffc00000 0 0x30>;
651 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
c53866cb 654 interrupt-names = "tuni0", "tuni1", "tuni2";
58eb575c
MCR		 655 clocks = <&cpg CPG_MOD 121>;
656 clock-names = "fck";
657 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
658 resets = <&cpg 121>;
659 status = "disabled";
660 };
661
950a3a79
LP		 662 i2c0: i2c@e6500000 {
663 #address-cells = <1>;
664 #size-cells = <0>;
665 compatible = "renesas,i2c-r8a774e1",
666 "renesas,rcar-gen3-i2c";
667 reg = <0 0xe6500000 0 0x40>;
668 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cpg CPG_MOD 931>;
670 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
671 resets = <&cpg 931>;
672 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
673 <&dmac2 0x91>, <&dmac2 0x90>;
674 dma-names = "tx", "rx", "tx", "rx";
675 i2c-scl-internal-delay-ns = <110>;
676 status = "disabled";
677 };
678
679 i2c1: i2c@e6508000 {
680 #address-cells = <1>;
681 #size-cells = <0>;
682 compatible = "renesas,i2c-r8a774e1",
683 "renesas,rcar-gen3-i2c";
684 reg = <0 0xe6508000 0 0x40>;
685 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&cpg CPG_MOD 930>;
687 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
688 resets = <&cpg 930>;
689 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
690 <&dmac2 0x93>, <&dmac2 0x92>;
691 dma-names = "tx", "rx", "tx", "rx";
692 i2c-scl-internal-delay-ns = <6>;
693 status = "disabled";
694 };
695
4dd61a52 696 i2c2: i2c@e6510000 {
4dd61a52
MCR		 697 #address-cells = <1>;
698 #size-cells = <0>;
950a3a79
LP		 699 compatible = "renesas,i2c-r8a774e1",
700 "renesas,rcar-gen3-i2c";
701 reg = <0 0xe6510000 0 0x40>;
702 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&cpg CPG_MOD 929>;
704 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
705 resets = <&cpg 929>;
706 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
707 <&dmac2 0x95>, <&dmac2 0x94>;
708 dma-names = "tx", "rx", "tx", "rx";
709 i2c-scl-internal-delay-ns = <6>;
4dd61a52 710 status = "disabled";
950a3a79 711 };
4dd61a52 712
950a3a79
LP		 713 i2c3: i2c@e66d0000 {
714 #address-cells = <1>;
715 #size-cells = <0>;
716 compatible = "renesas,i2c-r8a774e1",
717 "renesas,rcar-gen3-i2c";
718 reg = <0 0xe66d0000 0 0x40>;
719 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&cpg CPG_MOD 928>;
721 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
722 resets = <&cpg 928>;
723 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
724 dma-names = "tx", "rx";
725 i2c-scl-internal-delay-ns = <110>;
726 status = "disabled";
4dd61a52
MCR		 727 };
728
729 i2c4: i2c@e66d8000 {
730 #address-cells = <1>;
731 #size-cells = <0>;
950a3a79
LP		 732 compatible = "renesas,i2c-r8a774e1",
733 "renesas,rcar-gen3-i2c";
4dd61a52 734 reg = <0 0xe66d8000 0 0x40>;
950a3a79
LP		 735 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&cpg CPG_MOD 927>;
737 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
738 resets = <&cpg 927>;
739 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
740 dma-names = "tx", "rx";
741 i2c-scl-internal-delay-ns = <110>;
4dd61a52 742 status = "disabled";
950a3a79 743 };
4dd61a52 744
950a3a79
LP		 745 i2c5: i2c@e66e0000 {
746 #address-cells = <1>;
747 #size-cells = <0>;
748 compatible = "renesas,i2c-r8a774e1",
749 "renesas,rcar-gen3-i2c";
750 reg = <0 0xe66e0000 0 0x40>;
751 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&cpg CPG_MOD 919>;
753 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
754 resets = <&cpg 919>;
755 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
756 dma-names = "tx", "rx";
757 i2c-scl-internal-delay-ns = <110>;
758 status = "disabled";
759 };
760
761 i2c6: i2c@e66e8000 {
762 #address-cells = <1>;
763 #size-cells = <0>;
764 compatible = "renesas,i2c-r8a774e1",
765 "renesas,rcar-gen3-i2c";
766 reg = <0 0xe66e8000 0 0x40>;
767 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cpg CPG_MOD 918>;
769 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
770 resets = <&cpg 918>;
771 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
772 dma-names = "tx", "rx";
773 i2c-scl-internal-delay-ns = <6>;
774 status = "disabled";
775 };
776
8d580c0f 777 iic_pmic: i2c@e60b0000 {
950a3a79
LP		 778 #address-cells = <1>;
779 #size-cells = <0>;
780 compatible = "renesas,iic-r8a774e1",
781 "renesas,rcar-gen3-iic",
782 "renesas,rmobile-iic";
783 reg = <0 0xe60b0000 0 0x425>;
784 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&cpg CPG_MOD 926>;
786 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
787 resets = <&cpg 926>;
788 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
789 dma-names = "tx", "rx";
790 status = "disabled";
4dd61a52
MCR		 791 };
792
793 hscif0: serial@e6540000 {
b9b491a7
LP		 794 compatible = "renesas,hscif-r8a774e1",
795 "renesas,rcar-gen3-hscif",
796 "renesas,hscif";
4dd61a52 797 reg = <0 0xe6540000 0 0x60>;
b9b491a7
LP		 798 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&cpg CPG_MOD 520>,
800 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
801 <&scif_clk>;
802 clock-names = "fck", "brg_int", "scif_clk";
803 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
804 <&dmac2 0x31>, <&dmac2 0x30>;
805 dma-names = "tx", "rx", "tx", "rx";
806 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
807 resets = <&cpg 520>;
4dd61a52 808 status = "disabled";
b9b491a7 809 };
4dd61a52 810
b9b491a7
LP		 811 hscif1: serial@e6550000 {
812 compatible = "renesas,hscif-r8a774e1",
813 "renesas,rcar-gen3-hscif",
814 "renesas,hscif";
815 reg = <0 0xe6550000 0 0x60>;
816 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&cpg CPG_MOD 519>,
818 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
819 <&scif_clk>;
820 clock-names = "fck", "brg_int", "scif_clk";
821 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
822 <&dmac2 0x33>, <&dmac2 0x32>;
823 dma-names = "tx", "rx", "tx", "rx";
824 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
825 resets = <&cpg 519>;
826 status = "disabled";
827 };
828
829 hscif2: serial@e6560000 {
830 compatible = "renesas,hscif-r8a774e1",
831 "renesas,rcar-gen3-hscif",
832 "renesas,hscif";
833 reg = <0 0xe6560000 0 0x60>;
834 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&cpg CPG_MOD 518>,
836 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
837 <&scif_clk>;
838 clock-names = "fck", "brg_int", "scif_clk";
839 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
840 <&dmac2 0x35>, <&dmac2 0x34>;
841 dma-names = "tx", "rx", "tx", "rx";
842 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
843 resets = <&cpg 518>;
844 status = "disabled";
845 };
846
847 hscif3: serial@e66a0000 {
848 compatible = "renesas,hscif-r8a774e1",
849 "renesas,rcar-gen3-hscif",
850 "renesas,hscif";
851 reg = <0 0xe66a0000 0 0x60>;
852 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&cpg CPG_MOD 517>,
854 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
855 <&scif_clk>;
856 clock-names = "fck", "brg_int", "scif_clk";
857 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
858 dma-names = "tx", "rx";
859 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
860 resets = <&cpg 517>;
861 status = "disabled";
862 };
863
864 hscif4: serial@e66b0000 {
865 compatible = "renesas,hscif-r8a774e1",
866 "renesas,rcar-gen3-hscif",
867 "renesas,hscif";
868 reg = <0 0xe66b0000 0 0x60>;
869 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&cpg CPG_MOD 516>,
871 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
872 <&scif_clk>;
873 clock-names = "fck", "brg_int", "scif_clk";
874 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
875 dma-names = "tx", "rx";
876 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
877 resets = <&cpg 516>;
878 status = "disabled";
4dd61a52
MCR		 879 };
880
881 hsusb: usb@e6590000 {
896c62d4
LP		 882 compatible = "renesas,usbhs-r8a774e1",
883 "renesas,rcar-gen3-usbhs";
4dd61a52 884 reg = <0 0xe6590000 0 0x200>;
896c62d4
LP		 885 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
887 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
888 <&usb_dmac1 0>, <&usb_dmac1 1>;
889 dma-names = "ch0", "ch1", "ch2", "ch3";
890 renesas,buswait = <11>;
891 phys = <&usb2_phy0 3>;
892 phy-names = "usb";
893 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
894 resets = <&cpg 704>, <&cpg 703>;
4dd61a52 895 status = "disabled";
896c62d4 896 };
4dd61a52 897
e1076ce0
AF		 898 usb2_clksel: clock-controller@e6590630 {
899 compatible = "renesas,r8a774e1-rcar-usb2-clock-sel",
900 "renesas,rcar-gen3-usb2-clock-sel";
901 reg = <0 0xe6590630 0 0x02>;
902 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
903 <&usb_extal_clk>, <&usb3s0_clk>;
904 clock-names = "ehci_ohci", "hs-usb-if",
905 "usb_extal", "usb_xtal";
906 #clock-cells = <0>;
907 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
908 resets = <&cpg 703>, <&cpg 704>;
909 reset-names = "ehci_ohci", "hs-usb-if";
910 status = "disabled";
911 };
912
896c62d4
LP		 913 usb_dmac0: dma-controller@e65a0000 {
914 compatible = "renesas,r8a774e1-usb-dmac",
915 "renesas,usb-dmac";
916 reg = <0 0xe65a0000 0 0x100>;
917 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
919 interrupt-names = "ch0", "ch1";
920 clocks = <&cpg CPG_MOD 330>;
921 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
922 resets = <&cpg 330>;
923 #dma-cells = <1>;
924 dma-channels = <2>;
925 };
926
927 usb_dmac1: dma-controller@e65b0000 {
928 compatible = "renesas,r8a774e1-usb-dmac",
929 "renesas,usb-dmac";
930 reg = <0 0xe65b0000 0 0x100>;
931 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
933 interrupt-names = "ch0", "ch1";
934 clocks = <&cpg CPG_MOD 331>;
935 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
936 resets = <&cpg 331>;
937 #dma-cells = <1>;
938 dma-channels = <2>;
4dd61a52
MCR		 939 };
940
941 usb3_phy0: usb-phy@e65ee000 {
0faf5f95
LP		 942 compatible = "renesas,r8a774e1-usb3-phy",
943 "renesas,rcar-gen3-usb3-phy";
4dd61a52 944 reg = <0 0xe65ee000 0 0x90>;
0faf5f95
LP		 945 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
946 <&usb_extal_clk>;
947 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
948 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
949 resets = <&cpg 328>;
4dd61a52
MCR		 950 #phy-cells = <0>;
951 status = "disabled";
4dd61a52
MCR		 952 };
953
f1bf8ff8
MCR		 954 dmac0: dma-controller@e6700000 {
955 compatible = "renesas,dmac-r8a774e1",
956 "renesas,rcar-dmac";
957 reg = <0 0xe6700000 0 0x10000>;
958 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
975 interrupt-names = "error",
976 "ch0", "ch1", "ch2", "ch3",
977 "ch4", "ch5", "ch6", "ch7",
978 "ch8", "ch9", "ch10", "ch11",
979 "ch12", "ch13", "ch14", "ch15";
980 clocks = <&cpg CPG_MOD 219>;
981 clock-names = "fck";
982 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
983 resets = <&cpg 219>;
984 #dma-cells = <1>;
985 dma-channels = <16>;
986 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
987 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
988 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
989 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
990 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
991 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
992 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
993 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
994 };
995
996 dmac1: dma-controller@e7300000 {
997 compatible = "renesas,dmac-r8a774e1",
998 "renesas,rcar-dmac";
999 reg = <0 0xe7300000 0 0x10000>;
1000 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1010 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1011 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1012 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
1017 interrupt-names = "error",
1018 "ch0", "ch1", "ch2", "ch3",
1019 "ch4", "ch5", "ch6", "ch7",
1020 "ch8", "ch9", "ch10", "ch11",
1021 "ch12", "ch13", "ch14", "ch15";
1022 clocks = <&cpg CPG_MOD 218>;
1023 clock-names = "fck";
1024 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1025 resets = <&cpg 218>;
1026 #dma-cells = <1>;
1027 dma-channels = <16>;
1028 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1029 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1030 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1031 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1032 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1033 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1034 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1035 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1036 };
1037
1038 dmac2: dma-controller@e7310000 {
1039 compatible = "renesas,dmac-r8a774e1",
1040 "renesas,rcar-dmac";
1041 reg = <0 0xe7310000 0 0x10000>;
1042 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1046 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1048 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1049 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1050 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1051 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1052 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1053 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1059 interrupt-names = "error",
1060 "ch0", "ch1", "ch2", "ch3",
1061 "ch4", "ch5", "ch6", "ch7",
1062 "ch8", "ch9", "ch10", "ch11",
1063 "ch12", "ch13", "ch14", "ch15";
1064 clocks = <&cpg CPG_MOD 217>;
1065 clock-names = "fck";
1066 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1067 resets = <&cpg 217>;
1068 #dma-cells = <1>;
1069 dma-channels = <16>;
1070 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1071 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1072 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1073 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1074 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1075 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1076 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1077 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1078 };
1079
615d1a9e
MCR		 1080 ipmmu_ds0: iommu@e6740000 {
1081 compatible = "renesas,ipmmu-r8a774e1";
1082 reg = <0 0xe6740000 0 0x1000>;
1083 renesas,ipmmu-main = <&ipmmu_mm 0>;
1084 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1085 #iommu-cells = <1>;
1086 };
1087
1088 ipmmu_ds1: iommu@e7740000 {
1089 compatible = "renesas,ipmmu-r8a774e1";
1090 reg = <0 0xe7740000 0 0x1000>;
1091 renesas,ipmmu-main = <&ipmmu_mm 1>;
1092 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1093 #iommu-cells = <1>;
1094 };
1095
1096 ipmmu_hc: iommu@e6570000 {
1097 compatible = "renesas,ipmmu-r8a774e1";
1098 reg = <0 0xe6570000 0 0x1000>;
1099 renesas,ipmmu-main = <&ipmmu_mm 2>;
1100 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1101 #iommu-cells = <1>;
1102 };
1103
1104 ipmmu_mm: iommu@e67b0000 {
1105 compatible = "renesas,ipmmu-r8a774e1";
1106 reg = <0 0xe67b0000 0 0x1000>;
1107 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1109 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1110 #iommu-cells = <1>;
1111 };
1112
1113 ipmmu_mp0: iommu@ec670000 {
1114 compatible = "renesas,ipmmu-r8a774e1";
1115 reg = <0 0xec670000 0 0x1000>;
1116 renesas,ipmmu-main = <&ipmmu_mm 4>;
1117 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1118 #iommu-cells = <1>;
1119 };
1120
1121 ipmmu_pv0: iommu@fd800000 {
1122 compatible = "renesas,ipmmu-r8a774e1";
1123 reg = <0 0xfd800000 0 0x1000>;
1124 renesas,ipmmu-main = <&ipmmu_mm 6>;
1125 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1126 #iommu-cells = <1>;
1127 };
1128
1129 ipmmu_pv1: iommu@fd950000 {
1130 compatible = "renesas,ipmmu-r8a774e1";
1131 reg = <0 0xfd950000 0 0x1000>;
1132 renesas,ipmmu-main = <&ipmmu_mm 7>;
1133 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1134 #iommu-cells = <1>;
1135 };
1136
1137 ipmmu_pv2: iommu@fd960000 {
1138 compatible = "renesas,ipmmu-r8a774e1";
1139 reg = <0 0xfd960000 0 0x1000>;
1140 renesas,ipmmu-main = <&ipmmu_mm 8>;
1141 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1142 #iommu-cells = <1>;
1143 };
1144
1145 ipmmu_pv3: iommu@fd970000 {
1146 compatible = "renesas,ipmmu-r8a774e1";
1147 reg = <0 0xfd970000 0 0x1000>;
1148 renesas,ipmmu-main = <&ipmmu_mm 9>;
1149 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1150 #iommu-cells = <1>;
1151 };
1152
1153 ipmmu_vc0: iommu@fe6b0000 {
1154 compatible = "renesas,ipmmu-r8a774e1";
1155 reg = <0 0xfe6b0000 0 0x1000>;
1156 renesas,ipmmu-main = <&ipmmu_mm 12>;
1157 power-domains = <&sysc R8A774E1_PD_A3VC>;
1158 #iommu-cells = <1>;
1159 };
1160
1161 ipmmu_vc1: iommu@fe6f0000 {
1162 compatible = "renesas,ipmmu-r8a774e1";
1163 reg = <0 0xfe6f0000 0 0x1000>;
1164 renesas,ipmmu-main = <&ipmmu_mm 13>;
1165 power-domains = <&sysc R8A774E1_PD_A3VC>;
1166 #iommu-cells = <1>;
1167 };
1168
1169 ipmmu_vi0: iommu@febd0000 {
1170 compatible = "renesas,ipmmu-r8a774e1";
1171 reg = <0 0xfebd0000 0 0x1000>;
1172 renesas,ipmmu-main = <&ipmmu_mm 14>;
1173 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1174 #iommu-cells = <1>;
1175 };
1176
1177 ipmmu_vi1: iommu@febe0000 {
1178 compatible = "renesas,ipmmu-r8a774e1";
1179 reg = <0 0xfebe0000 0 0x1000>;
1180 renesas,ipmmu-main = <&ipmmu_mm 15>;
1181 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1182 #iommu-cells = <1>;
1183 };
1184
1185 ipmmu_vp0: iommu@fe990000 {
1186 compatible = "renesas,ipmmu-r8a774e1";
1187 reg = <0 0xfe990000 0 0x1000>;
1188 renesas,ipmmu-main = <&ipmmu_mm 16>;
1189 power-domains = <&sysc R8A774E1_PD_A3VP>;
1190 #iommu-cells = <1>;
1191 };
1192
1193 ipmmu_vp1: iommu@fe980000 {
1194 compatible = "renesas,ipmmu-r8a774e1";
1195 reg = <0 0xfe980000 0 0x1000>;
1196 renesas,ipmmu-main = <&ipmmu_mm 17>;
1197 power-domains = <&sysc R8A774E1_PD_A3VP>;
1198 #iommu-cells = <1>;
1199 };
1200
4dd61a52 1201 avb: ethernet@e6800000 {
8d54886c
MCR		 1202 compatible = "renesas,etheravb-r8a774e1",
1203 "renesas,etheravb-rcar-gen3";
4dd61a52 1204 reg = <0 0xe6800000 0 0x800>;
8d54886c
MCR		 1205 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1230 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1231 "ch4", "ch5", "ch6", "ch7",
1232 "ch8", "ch9", "ch10", "ch11",
1233 "ch12", "ch13", "ch14", "ch15",
1234 "ch16", "ch17", "ch18", "ch19",
1235 "ch20", "ch21", "ch22", "ch23",
1236 "ch24";
1237 clocks = <&cpg CPG_MOD 812>;
56ed0b3b 1238 clock-names = "fck";
8d54886c
MCR		 1239 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1240 resets = <&cpg 812>;
1241 phy-mode = "rgmii";
a5200e63
GU		 1242 rx-internal-delay-ps = <0>;
1243 tx-internal-delay-ps = <0>;
8d54886c 1244 iommus = <&ipmmu_ds0 16>;
4dd61a52
MCR		 1245 #address-cells = <1>;
1246 #size-cells = <0>;
1247 status = "disabled";
4dd61a52
MCR		 1248 };
1249
1250 can0: can@e6c30000 {
8e340e75
LP		 1251 compatible = "renesas,can-r8a774e1",
1252 "renesas,rcar-gen3-can";
4dd61a52 1253 reg = <0 0xe6c30000 0 0x1000>;
8e340e75
LP		 1254 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1255 clocks = <&cpg CPG_MOD 916>,
1256 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1257 <&can_clk>;
1258 clock-names = "clkp1", "clkp2", "can_clk";
1259 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1260 assigned-clock-rates = <40000000>;
1261 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1262 resets = <&cpg 916>;
4dd61a52 1263 status = "disabled";
4dd61a52
MCR		 1264 };
1265
1266 can1: can@e6c38000 {
8e340e75
LP		 1267 compatible = "renesas,can-r8a774e1",
1268 "renesas,rcar-gen3-can";
4dd61a52 1269 reg = <0 0xe6c38000 0 0x1000>;
8e340e75
LP		 1270 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&cpg CPG_MOD 915>,
1272 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1273 <&can_clk>;
1274 clock-names = "clkp1", "clkp2", "can_clk";
1275 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1276 assigned-clock-rates = <40000000>;
1277 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1278 resets = <&cpg 915>;
4dd61a52 1279 status = "disabled";
8e340e75 1280 };
4dd61a52 1281
8e340e75
LP		 1282 canfd: can@e66c0000 {
1283 compatible = "renesas,r8a774e1-canfd",
1284 "renesas,rcar-gen3-canfd";
1285 reg = <0 0xe66c0000 0 0x8000>;
1286 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6af663af 1288 interrupt-names = "ch_int", "g_int";
8e340e75
LP		 1289 clocks = <&cpg CPG_MOD 914>,
1290 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1291 <&can_clk>;
1292 clock-names = "fck", "canfd", "can_clk";
1293 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1294 assigned-clock-rates = <40000000>;
1295 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1296 resets = <&cpg 914>;
1297 status = "disabled";
1298
1299 channel0 {
1300 status = "disabled";
1301 };
1302
1303 channel1 {
1304 status = "disabled";
1305 };
4dd61a52
MCR		 1306 };
1307
1308 pwm0: pwm@e6e30000 {
557e6408 1309 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
4dd61a52 1310 reg = <0 0xe6e30000 0 0x8>;
557e6408
MCR		 1311 clocks = <&cpg CPG_MOD 523>;
1312 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1313 resets = <&cpg 523>;
1314 #pwm-cells = <2>;
1315 status = "disabled";
1316 };
1317
1318 pwm1: pwm@e6e31000 {
1319 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1320 reg = <0 0xe6e31000 0 0x8>;
1321 clocks = <&cpg CPG_MOD 523>;
1322 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1323 resets = <&cpg 523>;
1324 #pwm-cells = <2>;
1325 status = "disabled";
1326 };
1327
1328 pwm2: pwm@e6e32000 {
1329 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1330 reg = <0 0xe6e32000 0 0x8>;
1331 clocks = <&cpg CPG_MOD 523>;
1332 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1333 resets = <&cpg 523>;
1334 #pwm-cells = <2>;
1335 status = "disabled";
1336 };
1337
1338 pwm3: pwm@e6e33000 {
1339 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1340 reg = <0 0xe6e33000 0 0x8>;
1341 clocks = <&cpg CPG_MOD 523>;
1342 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1343 resets = <&cpg 523>;
1344 #pwm-cells = <2>;
1345 status = "disabled";
1346 };
1347
1348 pwm4: pwm@e6e34000 {
1349 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1350 reg = <0 0xe6e34000 0 0x8>;
1351 clocks = <&cpg CPG_MOD 523>;
1352 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1353 resets = <&cpg 523>;
4dd61a52
MCR		 1354 #pwm-cells = <2>;
1355 status = "disabled";
557e6408 1356 };
4dd61a52 1357
557e6408
MCR		 1358 pwm5: pwm@e6e35000 {
1359 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1360 reg = <0 0xe6e35000 0 0x8>;
1361 clocks = <&cpg CPG_MOD 523>;
1362 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1363 resets = <&cpg 523>;
1364 #pwm-cells = <2>;
1365 status = "disabled";
1366 };
1367
1368 pwm6: pwm@e6e36000 {
1369 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1370 reg = <0 0xe6e36000 0 0x8>;
1371 clocks = <&cpg CPG_MOD 523>;
1372 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1373 resets = <&cpg 523>;
1374 #pwm-cells = <2>;
1375 status = "disabled";
4dd61a52
MCR		 1376 };
1377
b9b491a7
LP		 1378 scif0: serial@e6e60000 {
1379 compatible = "renesas,scif-r8a774e1",
1380 "renesas,rcar-gen3-scif", "renesas,scif";
1381 reg = <0 0xe6e60000 0 0x40>;
1382 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&cpg CPG_MOD 207>,
1384 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1385 <&scif_clk>;
1386 clock-names = "fck", "brg_int", "scif_clk";
1387 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1388 <&dmac2 0x51>, <&dmac2 0x50>;
1389 dma-names = "tx", "rx", "tx", "rx";
1390 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1391 resets = <&cpg 207>;
1392 status = "disabled";
1393 };
1394
1395 scif1: serial@e6e68000 {
1396 compatible = "renesas,scif-r8a774e1",
1397 "renesas,rcar-gen3-scif", "renesas,scif";
1398 reg = <0 0xe6e68000 0 0x40>;
1399 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1400 clocks = <&cpg CPG_MOD 206>,
1401 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1402 <&scif_clk>;
1403 clock-names = "fck", "brg_int", "scif_clk";
1404 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1405 <&dmac2 0x53>, <&dmac2 0x52>;
1406 dma-names = "tx", "rx", "tx", "rx";
1407 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1408 resets = <&cpg 206>;
1409 status = "disabled";
1410 };
1411
4dd61a52
MCR		 1412 scif2: serial@e6e88000 {
1413 compatible = "renesas,scif-r8a774e1",
1414 "renesas,rcar-gen3-scif", "renesas,scif";
1415 reg = <0 0xe6e88000 0 0x40>;
1416 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1417 clocks = <&cpg CPG_MOD 310>,
1418 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1419 <&scif_clk>;
1420 clock-names = "fck", "brg_int", "scif_clk";
b9b491a7
LP		 1421 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1422 <&dmac2 0x13>, <&dmac2 0x12>;
1423 dma-names = "tx", "rx", "tx", "rx";
4dd61a52
MCR		 1424 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1425 resets = <&cpg 310>;
1426 status = "disabled";
1427 };
1428
b9b491a7
LP		 1429 scif3: serial@e6c50000 {
1430 compatible = "renesas,scif-r8a774e1",
1431 "renesas,rcar-gen3-scif", "renesas,scif";
1432 reg = <0 0xe6c50000 0 0x40>;
1433 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1434 clocks = <&cpg CPG_MOD 204>,
1435 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1436 <&scif_clk>;
1437 clock-names = "fck", "brg_int", "scif_clk";
1438 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1439 dma-names = "tx", "rx";
1440 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1441 resets = <&cpg 204>;
1442 status = "disabled";
1443 };
1444
1445 scif4: serial@e6c40000 {
1446 compatible = "renesas,scif-r8a774e1",
1447 "renesas,rcar-gen3-scif", "renesas,scif";
1448 reg = <0 0xe6c40000 0 0x40>;
1449 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1450 clocks = <&cpg CPG_MOD 203>,
1451 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1452 <&scif_clk>;
1453 clock-names = "fck", "brg_int", "scif_clk";
1454 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1455 dma-names = "tx", "rx";
1456 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1457 resets = <&cpg 203>;
1458 status = "disabled";
1459 };
1460
1461 scif5: serial@e6f30000 {
1462 compatible = "renesas,scif-r8a774e1",
1463 "renesas,rcar-gen3-scif", "renesas,scif";
1464 reg = <0 0xe6f30000 0 0x40>;
1465 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1466 clocks = <&cpg CPG_MOD 202>,
1467 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1468 <&scif_clk>;
1469 clock-names = "fck", "brg_int", "scif_clk";
1470 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1471 <&dmac2 0x5b>, <&dmac2 0x5a>;
1472 dma-names = "tx", "rx", "tx", "rx";
1473 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1474 resets = <&cpg 202>;
1475 status = "disabled";
05c79a8f
LP		 1476 };
1477
1478 msiof0: spi@e6e90000 {
1479 compatible = "renesas,msiof-r8a774e1",
1480 "renesas,rcar-gen3-msiof";
1481 reg = <0 0xe6e90000 0 0x0064>;
1482 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1483 clocks = <&cpg CPG_MOD 211>;
1484 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1485 <&dmac2 0x41>, <&dmac2 0x40>;
1486 dma-names = "tx", "rx", "tx", "rx";
1487 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1488 resets = <&cpg 211>;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1491 status = "disabled";
1492 };
1493
1494 msiof1: spi@e6ea0000 {
1495 compatible = "renesas,msiof-r8a774e1",
1496 "renesas,rcar-gen3-msiof";
1497 reg = <0 0xe6ea0000 0 0x0064>;
1498 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1499 clocks = <&cpg CPG_MOD 210>;
1500 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1501 <&dmac2 0x43>, <&dmac2 0x42>;
1502 dma-names = "tx", "rx", "tx", "rx";
1503 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1504 resets = <&cpg 210>;
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1507 status = "disabled";
1508 };
1509
1510 msiof2: spi@e6c00000 {
1511 compatible = "renesas,msiof-r8a774e1",
1512 "renesas,rcar-gen3-msiof";
1513 reg = <0 0xe6c00000 0 0x0064>;
1514 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1515 clocks = <&cpg CPG_MOD 209>;
1516 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1517 dma-names = "tx", "rx";
1518 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1519 resets = <&cpg 209>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1522 status = "disabled";
1523 };
1524
1525 msiof3: spi@e6c10000 {
1526 compatible = "renesas,msiof-r8a774e1",
1527 "renesas,rcar-gen3-msiof";
1528 reg = <0 0xe6c10000 0 0x0064>;
1529 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1530 clocks = <&cpg CPG_MOD 208>;
1531 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1532 dma-names = "tx", "rx";
1533 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1534 resets = <&cpg 208>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1537 status = "disabled";
b9b491a7
LP		 1538 };
1539
cfc7ba10
LP		 1540 vin0: video@e6ef0000 {
1541 compatible = "renesas,vin-r8a774e1";
1542 reg = <0 0xe6ef0000 0 0x1000>;
1543 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1544 clocks = <&cpg CPG_MOD 811>;
1545 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1546 resets = <&cpg 811>;
1547 renesas,id = <0>;
1548 status = "disabled";
1549
1550 ports {
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1553
1554 port@1 {
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1557
1558 reg = <1>;
1559
1560 vin0csi20: endpoint@0 {
1561 reg = <0>;
1562 remote-endpoint = <&csi20vin0>;
1563 };
1564 vin0csi40: endpoint@2 {
1565 reg = <2>;
1566 remote-endpoint = <&csi40vin0>;
1567 };
1568 };
1569 };
1570 };
1571
1572 vin1: video@e6ef1000 {
1573 compatible = "renesas,vin-r8a774e1";
1574 reg = <0 0xe6ef1000 0 0x1000>;
1575 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MOD 810>;
1577 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1578 resets = <&cpg 810>;
1579 renesas,id = <1>;
1580 status = "disabled";
1581
1582 ports {
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1585
1586 port@1 {
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1589
1590 reg = <1>;
1591
1592 vin1csi20: endpoint@0 {
1593 reg = <0>;
1594 remote-endpoint = <&csi20vin1>;
1595 };
1596 vin1csi40: endpoint@2 {
1597 reg = <2>;
1598 remote-endpoint = <&csi40vin1>;
1599 };
1600 };
1601 };
1602 };
1603
1604 vin2: video@e6ef2000 {
1605 compatible = "renesas,vin-r8a774e1";
1606 reg = <0 0xe6ef2000 0 0x1000>;
1607 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1608 clocks = <&cpg CPG_MOD 809>;
1609 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1610 resets = <&cpg 809>;
1611 renesas,id = <2>;
1612 status = "disabled";
1613
1614 ports {
1615 #address-cells = <1>;
1616 #size-cells = <0>;
1617
1618 port@1 {
1619 #address-cells = <1>;
1620 #size-cells = <0>;
1621
1622 reg = <1>;
1623
1624 vin2csi20: endpoint@0 {
1625 reg = <0>;
1626 remote-endpoint = <&csi20vin2>;
1627 };
1628 vin2csi40: endpoint@2 {
1629 reg = <2>;
1630 remote-endpoint = <&csi40vin2>;
1631 };
1632 };
1633 };
1634 };
1635
1636 vin3: video@e6ef3000 {
1637 compatible = "renesas,vin-r8a774e1";
1638 reg = <0 0xe6ef3000 0 0x1000>;
1639 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1640 clocks = <&cpg CPG_MOD 808>;
1641 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1642 resets = <&cpg 808>;
1643 renesas,id = <3>;
1644 status = "disabled";
1645
1646 ports {
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1649
1650 port@1 {
1651 #address-cells = <1>;
1652 #size-cells = <0>;
1653
1654 reg = <1>;
1655
1656 vin3csi20: endpoint@0 {
1657 reg = <0>;
1658 remote-endpoint = <&csi20vin3>;
1659 };
1660 vin3csi40: endpoint@2 {
1661 reg = <2>;
1662 remote-endpoint = <&csi40vin3>;
1663 };
1664 };
1665 };
1666 };
1667
1668 vin4: video@e6ef4000 {
1669 compatible = "renesas,vin-r8a774e1";
1670 reg = <0 0xe6ef4000 0 0x1000>;
1671 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1672 clocks = <&cpg CPG_MOD 807>;
1673 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1674 resets = <&cpg 807>;
1675 renesas,id = <4>;
1676 status = "disabled";
1677
1678 ports {
1679 #address-cells = <1>;
1680 #size-cells = <0>;
1681
1682 port@1 {
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1685
1686 reg = <1>;
1687
1688 vin4csi20: endpoint@0 {
1689 reg = <0>;
1690 remote-endpoint = <&csi20vin4>;
1691 };
1692 };
1693 };
1694 };
1695
1696 vin5: video@e6ef5000 {
1697 compatible = "renesas,vin-r8a774e1";
1698 reg = <0 0xe6ef5000 0 0x1000>;
1699 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1700 clocks = <&cpg CPG_MOD 806>;
1701 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1702 resets = <&cpg 806>;
1703 renesas,id = <5>;
1704 status = "disabled";
1705
1706 ports {
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1709
1710 port@1 {
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1713
1714 reg = <1>;
1715
1716 vin5csi20: endpoint@0 {
1717 reg = <0>;
1718 remote-endpoint = <&csi20vin5>;
1719 };
1720 };
1721 };
1722 };
1723
1724 vin6: video@e6ef6000 {
1725 compatible = "renesas,vin-r8a774e1";
1726 reg = <0 0xe6ef6000 0 0x1000>;
1727 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1728 clocks = <&cpg CPG_MOD 805>;
1729 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1730 resets = <&cpg 805>;
1731 renesas,id = <6>;
1732 status = "disabled";
1733
1734 ports {
1735 #address-cells = <1>;
1736 #size-cells = <0>;
1737
1738 port@1 {
1739 #address-cells = <1>;
1740 #size-cells = <0>;
1741
1742 reg = <1>;
1743
1744 vin6csi20: endpoint@0 {
1745 reg = <0>;
1746 remote-endpoint = <&csi20vin6>;
1747 };
1748 };
1749 };
1750 };
1751
1752 vin7: video@e6ef7000 {
1753 compatible = "renesas,vin-r8a774e1";
1754 reg = <0 0xe6ef7000 0 0x1000>;
1755 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1756 clocks = <&cpg CPG_MOD 804>;
1757 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1758 resets = <&cpg 804>;
1759 renesas,id = <7>;
1760 status = "disabled";
1761
1762 ports {
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765
1766 port@1 {
1767 #address-cells = <1>;
1768 #size-cells = <0>;
1769
1770 reg = <1>;
1771
1772 vin7csi20: endpoint@0 {
1773 reg = <0>;
1774 remote-endpoint = <&csi20vin7>;
1775 };
1776 };
1777 };
1778 };
1779
4dd61a52 1780 rcar_sound: sound@ec500000 {
8183a793 1781 /*
9e72606c 1782 * #sound-dai-cells is required if simple-card
8183a793
LP		 1783 *
1784 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1785 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1786 */
1787 /*
1788 * #clock-cells is required for audio_clkout0/1/2/3
1789 *
1790 * clkout : #clock-cells = <0>; <&rcar_sound>;
1791 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1792 */
953b392a 1793 compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
4dd61a52
MCR		 1794 reg = <0 0xec500000 0 0x1000>, /* SCU */
1795 <0 0xec5a0000 0 0x100>, /* ADG */
1796 <0 0xec540000 0 0x1000>, /* SSIU */
1797 <0 0xec541000 0 0x280>, /* SSI */
1798 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1799 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1800
8183a793
LP		 1801 clocks = <&cpg CPG_MOD 1005>,
1802 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1803 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1804 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1805 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1806 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1807 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1808 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1809 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1810 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1811 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1812 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1813 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1814 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1815 <&audio_clk_a>, <&audio_clk_b>,
1816 <&audio_clk_c>,
f2802c62 1817 <&cpg CPG_MOD 922>;
8183a793
LP		 1818 clock-names = "ssi-all",
1819 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1820 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1821 "ssi.1", "ssi.0",
1822 "src.9", "src.8", "src.7", "src.6",
1823 "src.5", "src.4", "src.3", "src.2",
1824 "src.1", "src.0",
1825 "mix.1", "mix.0",
1826 "ctu.1", "ctu.0",
1827 "dvc.0", "dvc.1",
1828 "clk_a", "clk_b", "clk_c", "clk_i";
1829 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1830 resets = <&cpg 1005>,
1831 <&cpg 1006>, <&cpg 1007>,
1832 <&cpg 1008>, <&cpg 1009>,
1833 <&cpg 1010>, <&cpg 1011>,
1834 <&cpg 1012>, <&cpg 1013>,
1835 <&cpg 1014>, <&cpg 1015>;
1836 reset-names = "ssi-all",
1837 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1838 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1839 "ssi.1", "ssi.0";
4dd61a52
MCR		 1840 status = "disabled";
1841
8183a793
LP		 1842 rcar_sound,dvc {
1843 dvc0: dvc-0 {
1844 dmas = <&audma1 0xbc>;
1845 dma-names = "tx";
1846 };
1847 dvc1: dvc-1 {
1848 dmas = <&audma1 0xbe>;
1849 dma-names = "tx";
1850 };
1851 };
1852
1853 rcar_sound,mix {
1854 mix0: mix-0 { };
1855 mix1: mix-1 { };
1856 };
1857
1858 rcar_sound,ctu {
1859 ctu00: ctu-0 { };
1860 ctu01: ctu-1 { };
1861 ctu02: ctu-2 { };
1862 ctu03: ctu-3 { };
1863 ctu10: ctu-4 { };
1864 ctu11: ctu-5 { };
1865 ctu12: ctu-6 { };
1866 ctu13: ctu-7 { };
1867 };
1868
1869 rcar_sound,src {
1870 src0: src-0 {
1871 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1872 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1873 dma-names = "rx", "tx";
1874 };
1875 src1: src-1 {
1876 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1877 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1878 dma-names = "rx", "tx";
1879 };
1880 src2: src-2 {
1881 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1882 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1883 dma-names = "rx", "tx";
1884 };
1885 src3: src-3 {
1886 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1887 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1888 dma-names = "rx", "tx";
1889 };
1890 src4: src-4 {
1891 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1892 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1893 dma-names = "rx", "tx";
1894 };
1895 src5: src-5 {
1896 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1897 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1898 dma-names = "rx", "tx";
1899 };
1900 src6: src-6 {
1901 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1902 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1903 dma-names = "rx", "tx";
1904 };
1905 src7: src-7 {
1906 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1908 dma-names = "rx", "tx";
1909 };
1910 src8: src-8 {
1911 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1912 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1913 dma-names = "rx", "tx";
1914 };
1915 src9: src-9 {
1916 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1917 dmas = <&audma0 0x97>, <&audma1 0xba>;
1918 dma-names = "rx", "tx";
1919 };
1920 };
1921
1922 rcar_sound,ssiu {
1923 ssiu00: ssiu-0 {
1924 dmas = <&audma0 0x15>, <&audma1 0x16>;
1925 dma-names = "rx", "tx";
1926 };
1927 ssiu01: ssiu-1 {
1928 dmas = <&audma0 0x35>, <&audma1 0x36>;
1929 dma-names = "rx", "tx";
1930 };
1931 ssiu02: ssiu-2 {
1932 dmas = <&audma0 0x37>, <&audma1 0x38>;
1933 dma-names = "rx", "tx";
1934 };
1935 ssiu03: ssiu-3 {
1936 dmas = <&audma0 0x47>, <&audma1 0x48>;
1937 dma-names = "rx", "tx";
1938 };
1939 ssiu04: ssiu-4 {
1940 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1941 dma-names = "rx", "tx";
1942 };
1943 ssiu05: ssiu-5 {
1944 dmas = <&audma0 0x43>, <&audma1 0x44>;
1945 dma-names = "rx", "tx";
1946 };
1947 ssiu06: ssiu-6 {
1948 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1949 dma-names = "rx", "tx";
1950 };
1951 ssiu07: ssiu-7 {
1952 dmas = <&audma0 0x53>, <&audma1 0x54>;
1953 dma-names = "rx", "tx";
1954 };
1955 ssiu10: ssiu-8 {
1956 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1957 dma-names = "rx", "tx";
1958 };
1959 ssiu11: ssiu-9 {
1960 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1961 dma-names = "rx", "tx";
1962 };
1963 ssiu12: ssiu-10 {
1964 dmas = <&audma0 0x57>, <&audma1 0x58>;
1965 dma-names = "rx", "tx";
1966 };
1967 ssiu13: ssiu-11 {
1968 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1969 dma-names = "rx", "tx";
1970 };
1971 ssiu14: ssiu-12 {
1972 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1973 dma-names = "rx", "tx";
1974 };
1975 ssiu15: ssiu-13 {
1976 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1977 dma-names = "rx", "tx";
1978 };
1979 ssiu16: ssiu-14 {
1980 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1981 dma-names = "rx", "tx";
1982 };
1983 ssiu17: ssiu-15 {
1984 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1985 dma-names = "rx", "tx";
1986 };
1987 ssiu20: ssiu-16 {
1988 dmas = <&audma0 0x63>, <&audma1 0x64>;
1989 dma-names = "rx", "tx";
1990 };
1991 ssiu21: ssiu-17 {
1992 dmas = <&audma0 0x67>, <&audma1 0x68>;
1993 dma-names = "rx", "tx";
1994 };
1995 ssiu22: ssiu-18 {
1996 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1997 dma-names = "rx", "tx";
1998 };
1999 ssiu23: ssiu-19 {
2000 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2001 dma-names = "rx", "tx";
2002 };
2003 ssiu24: ssiu-20 {
2004 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2005 dma-names = "rx", "tx";
2006 };
2007 ssiu25: ssiu-21 {
2008 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2009 dma-names = "rx", "tx";
2010 };
2011 ssiu26: ssiu-22 {
2012 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2013 dma-names = "rx", "tx";
2014 };
2015 ssiu27: ssiu-23 {
2016 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2017 dma-names = "rx", "tx";
2018 };
2019 ssiu30: ssiu-24 {
2020 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2021 dma-names = "rx", "tx";
2022 };
2023 ssiu31: ssiu-25 {
2024 dmas = <&audma0 0x21>, <&audma1 0x22>;
2025 dma-names = "rx", "tx";
2026 };
2027 ssiu32: ssiu-26 {
2028 dmas = <&audma0 0x23>, <&audma1 0x24>;
2029 dma-names = "rx", "tx";
2030 };
2031 ssiu33: ssiu-27 {
2032 dmas = <&audma0 0x25>, <&audma1 0x26>;
2033 dma-names = "rx", "tx";
2034 };
2035 ssiu34: ssiu-28 {
2036 dmas = <&audma0 0x27>, <&audma1 0x28>;
2037 dma-names = "rx", "tx";
2038 };
2039 ssiu35: ssiu-29 {
2040 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2041 dma-names = "rx", "tx";
2042 };
2043 ssiu36: ssiu-30 {
2044 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2045 dma-names = "rx", "tx";
2046 };
2047 ssiu37: ssiu-31 {
2048 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2049 dma-names = "rx", "tx";
2050 };
2051 ssiu40: ssiu-32 {
953b392a 2052 dmas = <&audma0 0x71>, <&audma1 0x72>;
8183a793
LP		 2053 dma-names = "rx", "tx";
2054 };
2055 ssiu41: ssiu-33 {
2056 dmas = <&audma0 0x17>, <&audma1 0x18>;
2057 dma-names = "rx", "tx";
2058 };
2059 ssiu42: ssiu-34 {
2060 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2061 dma-names = "rx", "tx";
2062 };
2063 ssiu43: ssiu-35 {
2064 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2065 dma-names = "rx", "tx";
2066 };
2067 ssiu44: ssiu-36 {
2068 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2069 dma-names = "rx", "tx";
2070 };
2071 ssiu45: ssiu-37 {
2072 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2073 dma-names = "rx", "tx";
2074 };
2075 ssiu46: ssiu-38 {
2076 dmas = <&audma0 0x31>, <&audma1 0x32>;
2077 dma-names = "rx", "tx";
2078 };
2079 ssiu47: ssiu-39 {
2080 dmas = <&audma0 0x33>, <&audma1 0x34>;
2081 dma-names = "rx", "tx";
2082 };
2083 ssiu50: ssiu-40 {
2084 dmas = <&audma0 0x73>, <&audma1 0x74>;
2085 dma-names = "rx", "tx";
2086 };
2087 ssiu60: ssiu-41 {
2088 dmas = <&audma0 0x75>, <&audma1 0x76>;
2089 dma-names = "rx", "tx";
2090 };
2091 ssiu70: ssiu-42 {
2092 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2093 dma-names = "rx", "tx";
2094 };
2095 ssiu80: ssiu-43 {
2096 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2097 dma-names = "rx", "tx";
2098 };
2099 ssiu90: ssiu-44 {
2100 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2101 dma-names = "rx", "tx";
2102 };
2103 ssiu91: ssiu-45 {
2104 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2105 dma-names = "rx", "tx";
2106 };
2107 ssiu92: ssiu-46 {
2108 dmas = <&audma0 0x81>, <&audma1 0x82>;
2109 dma-names = "rx", "tx";
2110 };
2111 ssiu93: ssiu-47 {
2112 dmas = <&audma0 0x83>, <&audma1 0x84>;
2113 dma-names = "rx", "tx";
2114 };
2115 ssiu94: ssiu-48 {
2116 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2117 dma-names = "rx", "tx";
2118 };
2119 ssiu95: ssiu-49 {
2120 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2121 dma-names = "rx", "tx";
2122 };
2123 ssiu96: ssiu-50 {
2124 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2125 dma-names = "rx", "tx";
2126 };
2127 ssiu97: ssiu-51 {
2128 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2129 dma-names = "rx", "tx";
2130 };
2131 };
4dd61a52
MCR		 2132
2133 rcar_sound,ssi {
8183a793
LP		 2134 ssi0: ssi-0 {
2135 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2136 dmas = <&audma0 0x01>, <&audma1 0x02>;
2137 dma-names = "rx", "tx";
2138 };
2139 ssi1: ssi-1 {
2140 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2141 dmas = <&audma0 0x03>, <&audma1 0x04>;
2142 dma-names = "rx", "tx";
2143 };
4dd61a52 2144 ssi2: ssi-2 {
8183a793
LP		 2145 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2146 dmas = <&audma0 0x05>, <&audma1 0x06>;
2147 dma-names = "rx", "tx";
2148 };
2149 ssi3: ssi-3 {
2150 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2151 dmas = <&audma0 0x07>, <&audma1 0x08>;
2152 dma-names = "rx", "tx";
2153 };
2154 ssi4: ssi-4 {
2155 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2156 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2157 dma-names = "rx", "tx";
2158 };
2159 ssi5: ssi-5 {
2160 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2161 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2162 dma-names = "rx", "tx";
2163 };
2164 ssi6: ssi-6 {
2165 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2166 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2167 dma-names = "rx", "tx";
2168 };
2169 ssi7: ssi-7 {
2170 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2171 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2172 dma-names = "rx", "tx";
2173 };
2174 ssi8: ssi-8 {
2175 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2176 dmas = <&audma0 0x11>, <&audma1 0x12>;
2177 dma-names = "rx", "tx";
2178 };
2179 ssi9: ssi-9 {
2180 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2181 dmas = <&audma0 0x13>, <&audma1 0x14>;
2182 dma-names = "rx", "tx";
4dd61a52
MCR		 2183 };
2184 };
2185 };
2186
8183a793
LP		 2187 audma0: dma-controller@ec700000 {
2188 compatible = "renesas,dmac-r8a774e1",
2189 "renesas,rcar-dmac";
2190 reg = <0 0xec700000 0 0x10000>;
2191 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2192 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2193 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2194 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2195 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2196 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2197 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2198 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2199 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2200 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2201 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2202 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2203 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2204 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2205 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2206 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2207 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2208 interrupt-names = "error",
2209 "ch0", "ch1", "ch2", "ch3",
2210 "ch4", "ch5", "ch6", "ch7",
2211 "ch8", "ch9", "ch10", "ch11",
2212 "ch12", "ch13", "ch14", "ch15";
2213 clocks = <&cpg CPG_MOD 502>;
2214 clock-names = "fck";
2215 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2216 resets = <&cpg 502>;
2217 #dma-cells = <1>;
2218 dma-channels = <16>;
2219 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2220 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
2221 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
2222 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
2223 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
2224 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
2225 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
2226 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
2227 };
2228
2229 audma1: dma-controller@ec720000 {
2230 compatible = "renesas,dmac-r8a774e1",
2231 "renesas,rcar-dmac";
2232 reg = <0 0xec720000 0 0x10000>;
2233 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2250 interrupt-names = "error",
2251 "ch0", "ch1", "ch2", "ch3",
2252 "ch4", "ch5", "ch6", "ch7",
2253 "ch8", "ch9", "ch10", "ch11",
2254 "ch12", "ch13", "ch14", "ch15";
2255 clocks = <&cpg CPG_MOD 501>;
2256 clock-names = "fck";
2257 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2258 resets = <&cpg 501>;
2259 #dma-cells = <1>;
2260 dma-channels = <16>;
2261 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
2262 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
2263 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
2264 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
2265 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
2266 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
2267 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
2268 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
2269 };
2270
4dd61a52 2271 xhci0: usb@ee000000 {
0faf5f95
LP		 2272 compatible = "renesas,xhci-r8a774e1",
2273 "renesas,rcar-gen3-xhci";
4dd61a52 2274 reg = <0 0xee000000 0 0xc00>;
0faf5f95
LP		 2275 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2276 clocks = <&cpg CPG_MOD 328>;
2277 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2278 resets = <&cpg 328>;
4dd61a52 2279 status = "disabled";
4dd61a52
MCR		 2280 };
2281
2282 usb3_peri0: usb@ee020000 {
0faf5f95
LP		 2283 compatible = "renesas,r8a774e1-usb3-peri",
2284 "renesas,rcar-gen3-usb3-peri";
4dd61a52 2285 reg = <0 0xee020000 0 0x400>;
0faf5f95
LP		 2286 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2287 clocks = <&cpg CPG_MOD 328>;
2288 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2289 resets = <&cpg 328>;
4dd61a52 2290 status = "disabled";
4dd61a52
MCR		 2291 };
2292
2293 ohci0: usb@ee080000 {
92b2c276 2294 compatible = "generic-ohci";
4dd61a52 2295 reg = <0 0xee080000 0 0x100>;
92b2c276
LP		 2296 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2297 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2298 phys = <&usb2_phy0 1>;
2299 phy-names = "usb";
2300 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2301 resets = <&cpg 703>, <&cpg 704>;
4dd61a52 2302 status = "disabled";
4dd61a52
MCR		 2303 };
2304
2305 ohci1: usb@ee0a0000 {
92b2c276 2306 compatible = "generic-ohci";
4dd61a52 2307 reg = <0 0xee0a0000 0 0x100>;
92b2c276
LP		 2308 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2309 clocks = <&cpg CPG_MOD 702>;
2310 phys = <&usb2_phy1 1>;
2311 phy-names = "usb";
2312 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2313 resets = <&cpg 702>;
4dd61a52 2314 status = "disabled";
4dd61a52
MCR		 2315 };
2316
2317 ehci0: usb@ee080100 {
92b2c276 2318 compatible = "generic-ehci";
4dd61a52 2319 reg = <0 0xee080100 0 0x100>;
92b2c276
LP		 2320 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2321 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2322 phys = <&usb2_phy0 2>;
2323 phy-names = "usb";
2324 companion = <&ohci0>;
2325 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2326 resets = <&cpg 703>, <&cpg 704>;
4dd61a52 2327 status = "disabled";
4dd61a52
MCR		 2328 };
2329
2330 ehci1: usb@ee0a0100 {
92b2c276 2331 compatible = "generic-ehci";
4dd61a52 2332 reg = <0 0xee0a0100 0 0x100>;
92b2c276
LP		 2333 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2334 clocks = <&cpg CPG_MOD 702>;
2335 phys = <&usb2_phy1 2>;
2336 phy-names = "usb";
2337 companion = <&ohci1>;
2338 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2339 resets = <&cpg 702>;
4dd61a52 2340 status = "disabled";
4dd61a52
MCR		 2341 };
2342
2343 usb2_phy0: usb-phy@ee080200 {
92b2c276
LP		 2344 compatible = "renesas,usb2-phy-r8a774e1",
2345 "renesas,rcar-gen3-usb2-phy";
4dd61a52 2346 reg = <0 0xee080200 0 0x700>;
92b2c276
LP		 2347 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2348 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2349 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2350 resets = <&cpg 703>, <&cpg 704>;
2351 #phy-cells = <1>;
4dd61a52 2352 status = "disabled";
4dd61a52
MCR		 2353 };
2354
2355 usb2_phy1: usb-phy@ee0a0200 {
92b2c276
LP		 2356 compatible = "renesas,usb2-phy-r8a774e1",
2357 "renesas,rcar-gen3-usb2-phy";
4dd61a52 2358 reg = <0 0xee0a0200 0 0x700>;
92b2c276
LP		 2359 clocks = <&cpg CPG_MOD 702>;
2360 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2361 resets = <&cpg 702>;
2362 #phy-cells = <1>;
4dd61a52 2363 status = "disabled";
4dd61a52
MCR		 2364 };
2365
2366 sdhi0: mmc@ee100000 {
31941342
LP		 2367 compatible = "renesas,sdhi-r8a774e1",
2368 "renesas,rcar-gen3-sdhi";
4dd61a52 2369 reg = <0 0xee100000 0 0x2000>;
31941342 2370 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
52e844ee
WS		 2371 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
2372 clock-names = "core", "clkh";
31941342
LP		 2373 max-frequency = <200000000>;
2374 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2375 resets = <&cpg 314>;
2376 iommus = <&ipmmu_ds1 32>;
4dd61a52 2377 status = "disabled";
31941342 2378 };
4dd61a52 2379
31941342
LP		 2380 sdhi1: mmc@ee120000 {
2381 compatible = "renesas,sdhi-r8a774e1",
2382 "renesas,rcar-gen3-sdhi";
2383 reg = <0 0xee120000 0 0x2000>;
2384 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
52e844ee
WS		 2385 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
2386 clock-names = "core", "clkh";
31941342
LP		 2387 max-frequency = <200000000>;
2388 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2389 resets = <&cpg 313>;
2390 iommus = <&ipmmu_ds1 33>;
2391 status = "disabled";
4dd61a52
MCR		 2392 };
2393
2394 sdhi2: mmc@ee140000 {
31941342
LP		 2395 compatible = "renesas,sdhi-r8a774e1",
2396 "renesas,rcar-gen3-sdhi";
4dd61a52 2397 reg = <0 0xee140000 0 0x2000>;
31941342 2398 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
52e844ee
WS		 2399 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
2400 clock-names = "core", "clkh";
31941342
LP		 2401 max-frequency = <200000000>;
2402 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2403 resets = <&cpg 312>;
2404 iommus = <&ipmmu_ds1 34>;
4dd61a52 2405 status = "disabled";
4dd61a52
MCR		 2406 };
2407
2408 sdhi3: mmc@ee160000 {
2409 compatible = "renesas,sdhi-r8a774e1",
2410 "renesas,rcar-gen3-sdhi";
2411 reg = <0 0xee160000 0 0x2000>;
2412 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
52e844ee
WS		 2413 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
2414 clock-names = "core", "clkh";
4dd61a52
MCR		 2415 max-frequency = <200000000>;
2416 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2417 resets = <&cpg 311>;
31941342 2418 iommus = <&ipmmu_ds1 35>;
4dd61a52
MCR		 2419 status = "disabled";
2420 };
2421
8811955d
AF		 2422 rpc: spi@ee200000 {
2423 compatible = "renesas,r8a774e1-rpc-if",
2424 "renesas,rcar-gen3-rpc-if";
2425 reg = <0 0xee200000 0 0x200>,
2426 <0 0x08000000 0 0x4000000>,
2427 <0 0xee208000 0 0x100>;
2428 reg-names = "regs", "dirmap", "wbuf";
2429 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2430 clocks = <&cpg CPG_MOD 917>;
8811955d
AF		 2431 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2432 resets = <&cpg 917>;
2433 #address-cells = <1>;
2434 #size-cells = <0>;
2435 status = "disabled";
2436 };
2437
2f3c7323
LP		 2438 sata: sata@ee300000 {
2439 compatible = "renesas,sata-r8a774e1",
2440 "renesas,rcar-gen3-sata";
2441 reg = <0 0xee300000 0 0x200000>;
2442 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2443 clocks = <&cpg CPG_MOD 815>;
2444 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2445 resets = <&cpg 815>;
2446 iommus = <&ipmmu_hc 2>;
2447 status = "disabled";
2448 };
2449
4dd61a52
MCR		 2450 gic: interrupt-controller@f1010000 {
2451 compatible = "arm,gic-400";
2452 #interrupt-cells = <3>;
2453 #address-cells = <0>;
2454 interrupt-controller;
2455 reg = <0x0 0xf1010000 0 0x1000>,
2456 <0x0 0xf1020000 0 0x20000>,
2457 <0x0 0xf1040000 0 0x20000>,
2458 <0x0 0xf1060000 0 0x20000>;
2459 interrupts = <GIC_PPI 9
2460 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2461 clocks = <&cpg CPG_MOD 408>;
2462 clock-names = "clk";
2463 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2464 resets = <&cpg 408>;
2465 };
2466
2467 pciec0: pcie@fe000000 {
cbb2f09a
LP		 2468 compatible = "renesas,pcie-r8a774e1",
2469 "renesas,pcie-rcar-gen3";
4dd61a52
MCR		 2470 reg = <0 0xfe000000 0 0x80000>;
2471 #address-cells = <3>;
2472 #size-cells = <2>;
cbb2f09a
LP		 2473 bus-range = <0x00 0xff>;
2474 device_type = "pci";
2475 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2476 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2477 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2478 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
86d904b6
YS		 2479 /* Map all possible DDR/IOMMU as inbound ranges */
2480 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
cbb2f09a
LP		 2481 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2482 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2483 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2484 #interrupt-cells = <1>;
2485 interrupt-map-mask = <0 0 0 0>;
2486 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2487 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2488 clock-names = "pcie", "pcie_bus";
2489 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2490 resets = <&cpg 319>;
86d904b6
YS		 2491 iommu-map = <0 &ipmmu_hc 0 1>;
2492 iommu-map-mask = <0>;
4dd61a52 2493 status = "disabled";
cbb2f09a 2494 };
4dd61a52 2495
cbb2f09a
LP		 2496 pciec1: pcie@ee800000 {
2497 compatible = "renesas,pcie-r8a774e1",
2498 "renesas,pcie-rcar-gen3";
2499 reg = <0 0xee800000 0 0x80000>;
2500 #address-cells = <3>;
2501 #size-cells = <2>;
2502 bus-range = <0x00 0xff>;
2503 device_type = "pci";
2504 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2505 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2506 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2507 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
86d904b6
YS		 2508 /* Map all possible DDR/IOMMU as inbound ranges */
2509 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
cbb2f09a
LP		 2510 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2511 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2512 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2513 #interrupt-cells = <1>;
2514 interrupt-map-mask = <0 0 0 0>;
2515 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2516 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2517 clock-names = "pcie", "pcie_bus";
2518 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2519 resets = <&cpg 318>;
86d904b6
YS		 2520 iommu-map = <0 &ipmmu_hc 1 1>;
2521 iommu-map-mask = <0>;
cbb2f09a 2522 status = "disabled";
4dd61a52
MCR		 2523 };
2524
b7ecb51b
LP		 2525 pciec0_ep: pcie-ep@fe000000 {
2526 compatible = "renesas,r8a774e1-pcie-ep",
2527 "renesas,rcar-gen3-pcie-ep";
2528 reg = <0x0 0xfe000000 0 0x80000>,
2529 <0x0 0xfe100000 0 0x100000>,
2530 <0x0 0xfe200000 0 0x200000>,
2531 <0x0 0x30000000 0 0x8000000>,
2532 <0x0 0x38000000 0 0x8000000>;
2533 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2534 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2535 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2536 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2537 clocks = <&cpg CPG_MOD 319>;
2538 clock-names = "pcie";
2539 resets = <&cpg 319>;
2540 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2541 status = "disabled";
2542 };
2543
2544 pciec1_ep: pcie-ep@ee800000 {
2545 compatible = "renesas,r8a774e1-pcie-ep",
2546 "renesas,rcar-gen3-pcie-ep";
2547 reg = <0x0 0xee800000 0 0x80000>,
2548 <0x0 0xee900000 0 0x100000>,
2549 <0x0 0xeea00000 0 0x200000>,
2550 <0x0 0xc0000000 0 0x8000000>,
2551 <0x0 0xc8000000 0 0x8000000>;
2552 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2553 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2554 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2555 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2556 clocks = <&cpg CPG_MOD 318>;
2557 clock-names = "pcie";
2558 resets = <&cpg 318>;
2559 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2560 status = "disabled";
2561 };
2562
4398ab23
MCR		 2563 vspbc: vsp@fe920000 {
2564 compatible = "renesas,vsp2";
2565 reg = <0 0xfe920000 0 0x8000>;
2566 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
2567 clocks = <&cpg CPG_MOD 624>;
2568 power-domains = <&sysc R8A774E1_PD_A3VP>;
2569 resets = <&cpg 624>;
2570
2571 renesas,fcp = <&fcpvb1>;
2572 };
2573
2574 vspbd: vsp@fe960000 {
2575 compatible = "renesas,vsp2";
2576 reg = <0 0xfe960000 0 0x8000>;
2577 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2578 clocks = <&cpg CPG_MOD 626>;
2579 power-domains = <&sysc R8A774E1_PD_A3VP>;
2580 resets = <&cpg 626>;
2581
2582 renesas,fcp = <&fcpvb0>;
2583 };
2584
2585 vspd0: vsp@fea20000 {
2586 compatible = "renesas,vsp2";
2587 reg = <0 0xfea20000 0 0x5000>;
2588 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2589 clocks = <&cpg CPG_MOD 623>;
2590 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2591 resets = <&cpg 623>;
2592
2593 renesas,fcp = <&fcpvd0>;
2594 };
2595
2596 vspd1: vsp@fea28000 {
2597 compatible = "renesas,vsp2";
2598 reg = <0 0xfea28000 0 0x5000>;
2599 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2600 clocks = <&cpg CPG_MOD 622>;
2601 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2602 resets = <&cpg 622>;
2603
2604 renesas,fcp = <&fcpvd1>;
2605 };
2606
2607 vspi0: vsp@fe9a0000 {
2608 compatible = "renesas,vsp2";
2609 reg = <0 0xfe9a0000 0 0x8000>;
2610 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2611 clocks = <&cpg CPG_MOD 631>;
2612 power-domains = <&sysc R8A774E1_PD_A3VP>;
2613 resets = <&cpg 631>;
2614
2615 renesas,fcp = <&fcpvi0>;
2616 };
2617
2618 vspi1: vsp@fe9b0000 {
2619 compatible = "renesas,vsp2";
2620 reg = <0 0xfe9b0000 0 0x8000>;
2621 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
2622 clocks = <&cpg CPG_MOD 630>;
2623 power-domains = <&sysc R8A774E1_PD_A3VP>;
2624 resets = <&cpg 630>;
2625
2626 renesas,fcp = <&fcpvi1>;
2627 };
2628
ff9e786f
MCR		 2629 fdp1@fe940000 {
2630 compatible = "renesas,fdp1";
2631 reg = <0 0xfe940000 0 0x2400>;
2632 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2633 clocks = <&cpg CPG_MOD 119>;
2634 power-domains = <&sysc R8A774E1_PD_A3VP>;
2635 resets = <&cpg 119>;
2636 renesas,fcp = <&fcpf0>;
2637 };
2638
2639 fdp1@fe944000 {
2640 compatible = "renesas,fdp1";
2641 reg = <0 0xfe944000 0 0x2400>;
2642 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2643 clocks = <&cpg CPG_MOD 118>;
2644 power-domains = <&sysc R8A774E1_PD_A3VP>;
2645 resets = <&cpg 118>;
2646 renesas,fcp = <&fcpf1>;
2647 };
2648
a3855ebc
MCR		 2649 fcpf0: fcp@fe950000 {
2650 compatible = "renesas,fcpf";
2651 reg = <0 0xfe950000 0 0x200>;
2652 clocks = <&cpg CPG_MOD 615>;
2653 power-domains = <&sysc R8A774E1_PD_A3VP>;
2654 resets = <&cpg 615>;
2655 };
2656
2657 fcpf1: fcp@fe951000 {
2658 compatible = "renesas,fcpf";
2659 reg = <0 0xfe951000 0 0x200>;
2660 clocks = <&cpg CPG_MOD 614>;
2661 power-domains = <&sysc R8A774E1_PD_A3VP>;
2662 resets = <&cpg 614>;
2663 };
2664
2665 fcpvb0: fcp@fe96f000 {
2666 compatible = "renesas,fcpv";
2667 reg = <0 0xfe96f000 0 0x200>;
2668 clocks = <&cpg CPG_MOD 607>;
2669 power-domains = <&sysc R8A774E1_PD_A3VP>;
2670 resets = <&cpg 607>;
2671 };
2672
2673 fcpvb1: fcp@fe92f000 {
2674 compatible = "renesas,fcpv";
2675 reg = <0 0xfe92f000 0 0x200>;
2676 clocks = <&cpg CPG_MOD 606>;
2677 power-domains = <&sysc R8A774E1_PD_A3VP>;
2678 resets = <&cpg 606>;
2679 };
2680
2681 fcpvi0: fcp@fe9af000 {
2682 compatible = "renesas,fcpv";
2683 reg = <0 0xfe9af000 0 0x200>;
2684 clocks = <&cpg CPG_MOD 611>;
2685 power-domains = <&sysc R8A774E1_PD_A3VP>;
2686 resets = <&cpg 611>;
2687 };
2688
2689 fcpvi1: fcp@fe9bf000 {
2690 compatible = "renesas,fcpv";
2691 reg = <0 0xfe9bf000 0 0x200>;
2692 clocks = <&cpg CPG_MOD 610>;
2693 power-domains = <&sysc R8A774E1_PD_A3VP>;
2694 resets = <&cpg 610>;
2695 };
2696
2697 fcpvd0: fcp@fea27000 {
2698 compatible = "renesas,fcpv";
2699 reg = <0 0xfea27000 0 0x200>;
2700 clocks = <&cpg CPG_MOD 603>;
2701 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2702 resets = <&cpg 603>;
2703 };
2704
2705 fcpvd1: fcp@fea2f000 {
2706 compatible = "renesas,fcpv";
2707 reg = <0 0xfea2f000 0 0x200>;
2708 clocks = <&cpg CPG_MOD 602>;
2709 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2710 resets = <&cpg 602>;
2711 };
2712
cfc7ba10
LP		 2713 csi20: csi2@fea80000 {
2714 compatible = "renesas,r8a774e1-csi2";
2715 reg = <0 0xfea80000 0 0x10000>;
2716 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2717 clocks = <&cpg CPG_MOD 714>;
2718 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2719 resets = <&cpg 714>;
2720 status = "disabled";
2721
2722 ports {
2723 #address-cells = <1>;
2724 #size-cells = <0>;
2725
0a96c059
NS		 2726 port@0 {
2727 reg = <0>;
2728 };
2729
cfc7ba10
LP		 2730 port@1 {
2731 #address-cells = <1>;
2732 #size-cells = <0>;
2733
2734 reg = <1>;
2735
2736 csi20vin0: endpoint@0 {
2737 reg = <0>;
2738 remote-endpoint = <&vin0csi20>;
2739 };
2740 csi20vin1: endpoint@1 {
2741 reg = <1>;
2742 remote-endpoint = <&vin1csi20>;
2743 };
2744 csi20vin2: endpoint@2 {
2745 reg = <2>;
2746 remote-endpoint = <&vin2csi20>;
2747 };
2748 csi20vin3: endpoint@3 {
2749 reg = <3>;
2750 remote-endpoint = <&vin3csi20>;
2751 };
2752 csi20vin4: endpoint@4 {
2753 reg = <4>;
2754 remote-endpoint = <&vin4csi20>;
2755 };
2756 csi20vin5: endpoint@5 {
2757 reg = <5>;
2758 remote-endpoint = <&vin5csi20>;
2759 };
2760 csi20vin6: endpoint@6 {
2761 reg = <6>;
2762 remote-endpoint = <&vin6csi20>;
2763 };
2764 csi20vin7: endpoint@7 {
2765 reg = <7>;
2766 remote-endpoint = <&vin7csi20>;
2767 };
2768 };
2769 };
2770 };
2771
2772 csi40: csi2@feaa0000 {
2773 compatible = "renesas,r8a774e1-csi2";
2774 reg = <0 0xfeaa0000 0 0x10000>;
2775 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2776 clocks = <&cpg CPG_MOD 716>;
2777 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2778 resets = <&cpg 716>;
2779 status = "disabled";
2780
2781 ports {
2782 #address-cells = <1>;
2783 #size-cells = <0>;
2784
0a96c059
NS		 2785 port@0 {
2786 reg = <0>;
2787 };
2788
cfc7ba10
LP		 2789 port@1 {
2790 #address-cells = <1>;
2791 #size-cells = <0>;
2792
2793 reg = <1>;
2794
2795 csi40vin0: endpoint@0 {
2796 reg = <0>;
2797 remote-endpoint = <&vin0csi40>;
2798 };
2799 csi40vin1: endpoint@1 {
2800 reg = <1>;
2801 remote-endpoint = <&vin1csi40>;
2802 };
2803 csi40vin2: endpoint@2 {
2804 reg = <2>;
2805 remote-endpoint = <&vin2csi40>;
2806 };
2807 csi40vin3: endpoint@3 {
2808 reg = <3>;
2809 remote-endpoint = <&vin3csi40>;
2810 };
2811 };
2812 };
2813 };
2814
4dd61a52 2815 hdmi0: hdmi@fead0000 {
5698b68d
MCR		 2816 compatible = "renesas,r8a774e1-hdmi",
2817 "renesas,rcar-gen3-hdmi";
4dd61a52 2818 reg = <0 0xfead0000 0 0x10000>;
5698b68d
MCR		 2819 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2820 clocks = <&cpg CPG_MOD 729>,
2821 <&cpg CPG_CORE R8A774E1_CLK_HDMI>;
2822 clock-names = "iahb", "isfr";
2823 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2824 resets = <&cpg 729>;
4dd61a52
MCR		 2825 status = "disabled";
2826
4dd61a52
MCR		 2827 ports {
2828 #address-cells = <1>;
2829 #size-cells = <0>;
2830
2831 port@0 {
2832 reg = <0>;
5698b68d
MCR		 2833 dw_hdmi0_in: endpoint {
2834 remote-endpoint = <&du_out_hdmi0>;
2835 };
4dd61a52
MCR		 2836 };
2837 port@1 {
2838 reg = <1>;
2839 };
2840 port@2 {
5698b68d 2841 /* HDMI sound */
4dd61a52
MCR		 2842 reg = <2>;
2843 };
2844 };
2845 };
2846
2847 du: display@feb00000 {
f22d0550 2848 compatible = "renesas,du-r8a774e1";
4dd61a52 2849 reg = <0 0xfeb00000 0 0x80000>;
f22d0550
MCR		 2850 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2851 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2852 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
2853 clocks = <&cpg CPG_MOD 724>,
2854 <&cpg CPG_MOD 723>,
2855 <&cpg CPG_MOD 721>;
2856 clock-names = "du.0", "du.1", "du.3";
2857 resets = <&cpg 724>, <&cpg 722>;
2858 reset-names = "du.0", "du.3";
4dd61a52
MCR		 2859 status = "disabled";
2860
f22d0550
MCR		 2861 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2862
4dd61a52
MCR		 2863 ports {
2864 #address-cells = <1>;
2865 #size-cells = <0>;
2866
2867 port@0 {
2868 reg = <0>;
2869 };
2870 port@1 {
2871 reg = <1>;
f22d0550 2872 du_out_hdmi0: endpoint {
5698b68d 2873 remote-endpoint = <&dw_hdmi0_in>;
f22d0550 2874 };
4dd61a52
MCR		 2875 };
2876 port@2 {
2877 reg = <2>;
f22d0550 2878 du_out_lvds0: endpoint {
112441c2
MCR		 2879 remote-endpoint = <&lvds0_in>;
2880 };
2881 };
2882 };
2883 };
2884
2885 lvds0: lvds@feb90000 {
2886 compatible = "renesas,r8a774e1-lvds";
2887 reg = <0 0xfeb90000 0 0x14>;
2888 clocks = <&cpg CPG_MOD 727>;
2889 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2890 resets = <&cpg 727>;
2891 status = "disabled";
2892
2893 ports {
2894 #address-cells = <1>;
2895 #size-cells = <0>;
2896
2897 port@0 {
2898 reg = <0>;
2899 lvds0_in: endpoint {
2900 remote-endpoint = <&du_out_lvds0>;
2901 };
2902 };
2903 port@1 {
2904 reg = <1>;
4dd61a52
MCR		 2905 };
2906 };
2907 };
2908
2909 prr: chipid@fff00044 {
2910 compatible = "renesas,prr";
2911 reg = <0 0xfff00044 0 4>;
2912 };
2913 };
2914
6dd73367 2915 thermal-zones {
82ce7939 2916 sensor1_thermal: sensor1-thermal {
6dd73367
MCR		 2917 polling-delay-passive = <250>;
2918 polling-delay = <1000>;
2919 thermal-sensors = <&tsc 0>;
2920 sustainable-power = <6313>;
2921
2922 trips {
2923 sensor1_crit: sensor1-crit {
2924 temperature = <120000>;
2925 hysteresis = <1000>;
2926 type = "critical";
2927 };
2928 };
2929 };
2930
82ce7939 2931 sensor2_thermal: sensor2-thermal {
6dd73367
MCR		 2932 polling-delay-passive = <250>;
2933 polling-delay = <1000>;
2934 thermal-sensors = <&tsc 1>;
2935 sustainable-power = <6313>;
2936
2937 trips {
2938 sensor2_crit: sensor2-crit {
2939 temperature = <120000>;
2940 hysteresis = <1000>;
2941 type = "critical";
2942 };
2943 };
2944 };
2945
82ce7939 2946 sensor3_thermal: sensor3-thermal {
6dd73367
MCR		 2947 polling-delay-passive = <250>;
2948 polling-delay = <1000>;
2949 thermal-sensors = <&tsc 2>;
2950 sustainable-power = <6313>;
2951
2952 trips {
2953 target: trip-point1 {
2954 temperature = <100000>;
2955 hysteresis = <1000>;
2956 type = "passive";
2957 };
2958
2959 sensor3_crit: sensor3-crit {
2960 temperature = <120000>;
2961 hysteresis = <1000>;
2962 type = "critical";
2963 };
2964 };
2965
2966 cooling-maps {
2967 map0 {
2968 trip = <&target>;
2969 cooling-device = <&a57_0 0 2>;
2970 contribution = <1024>;
2971 };
2972
2973 map1 {
2974 trip = <&target>;
2975 cooling-device = <&a53_0 0 2>;
2976 contribution = <1024>;
2977 };
2978 };
2979 };
2980 };
2981
4dd61a52
MCR		 2982 timer {
2983 compatible = "arm,armv8-timer";
2984 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2985 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2986 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2987 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2988 };
2989
2990 /* External USB clocks - can be overridden by the board */
2991 usb3s0_clk: usb3s0 {
2992 compatible = "fixed-clock";
2993 #clock-cells = <0>;
2994 clock-frequency = <0>;
2995 };
2996
2997 usb_extal_clk: usb_extal {
2998 compatible = "fixed-clock";
2999 #clock-cells = <0>;
3000 clock-frequency = <0>;
3001 };
3002};
Linux 6.x block layer and io_uring tree(s)