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deadcd50 MCR |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Device Tree Source for the HiHope RZ/G2H main board | |
4 | * | |
5 | * Copyright (C) 2020 Renesas Electronics Corp. | |
6 | */ | |
7 | ||
8 | /dts-v1/; | |
9 | #include "r8a774e1.dtsi" | |
10 | #include "hihope-rev4.dtsi" | |
11 | ||
12 | / { | |
13 | model = "HopeRun HiHope RZ/G2H main board based on r8a774e1"; | |
14 | compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; | |
15 | ||
16 | memory@48000000 { | |
17 | device_type = "memory"; | |
18 | /* first 128MB is reserved for secure area. */ | |
19 | reg = <0x0 0x48000000 0x0 0x78000000>; | |
20 | }; | |
21 | ||
22 | memory@500000000 { | |
23 | device_type = "memory"; | |
24 | reg = <0x5 0x00000000 0x0 0x80000000>; | |
25 | }; | |
26 | }; | |
2e23a1db LP |
27 | |
28 | &du { | |
29 | clocks = <&cpg CPG_MOD 724>, | |
30 | <&cpg CPG_MOD 723>, | |
31 | <&cpg CPG_MOD 721>, | |
32 | <&versaclock5 1>, | |
33 | <&x302_clk>, | |
34 | <&versaclock5 2>; | |
35 | clock-names = "du.0", "du.1", "du.3", | |
36 | "dclkin.0", "dclkin.1", "dclkin.3"; | |
37 | }; | |
7da4d2a8 BD |
38 | |
39 | &sdhi3 { | |
40 | mmc-hs400-1_8v; | |
41 | }; |