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Merge tag 'drm-intel-gt-next-2023-12-08' of git://anongit.freedesktop.org/drm/drm...
[linux-block.git] / arch / arm64 / boot / dts / renesas / r8a774a1.dtsi
CommitLineData
90493b09
BD		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
8ebb5038 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
aeee3d9c 11#include <dt-bindings/power/r8a774a1-sysc.h>
90493b09
BD		 12
13/ {
14 compatible = "renesas,r8a774a1";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 /*
19 * The external audio clocks are configured as 0 Hz fixed frequency
20 * clocks by default.
21 * Boards that provide audio clocks should override them.
22 */
23 audio_clk_a: audio_clk_a {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
27 };
28
29 audio_clk_b: audio_clk_b {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
33 };
34
35 audio_clk_c: audio_clk_c {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
39 };
40
41 /* External CAN clock - to be overridden by boards that provide it */
42 can_clk: can {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <0>;
46 };
47
7744b393 48 cluster0_opp: opp-table-0 {
800037e8
FC		 49 compatible = "operating-points-v2";
50 opp-shared;
51
52 opp-500000000 {
53 opp-hz = /bits/ 64 <500000000>;
54 opp-microvolt = <820000>;
55 clock-latency-ns = <300000>;
56 };
57 opp-1000000000 {
58 opp-hz = /bits/ 64 <1000000000>;
59 opp-microvolt = <820000>;
60 clock-latency-ns = <300000>;
61 };
62 opp-1500000000 {
63 opp-hz = /bits/ 64 <1500000000>;
64 opp-microvolt = <820000>;
65 clock-latency-ns = <300000>;
44b615ac 66 opp-suspend;
800037e8
FC		 67 };
68 };
69
7744b393 70 cluster1_opp: opp-table-1 {
800037e8
FC		 71 compatible = "operating-points-v2";
72 opp-shared;
73
74 opp-800000000 {
75 opp-hz = /bits/ 64 <800000000>;
76 opp-microvolt = <820000>;
77 clock-latency-ns = <300000>;
78 };
79 opp-1000000000 {
80 opp-hz = /bits/ 64 <1000000000>;
81 opp-microvolt = <820000>;
82 clock-latency-ns = <300000>;
83 };
84 opp-1200000000 {
85 opp-hz = /bits/ 64 <1200000000>;
86 opp-microvolt = <820000>;
87 clock-latency-ns = <300000>;
88 };
89 };
90
90493b09
BD		 91 cpus {
92 #address-cells = <1>;
93 #size-cells = <0>;
94
7b996955
BD		 95 cpu-map {
96 cluster0 {
97 core0 {
98 cpu = <&a57_0>;
99 };
100 core1 {
101 cpu = <&a57_1>;
102 };
103 };
104
105 cluster1 {
106 core0 {
107 cpu = <&a53_0>;
108 };
109 core1 {
110 cpu = <&a53_1>;
111 };
112 core2 {
113 cpu = <&a53_2>;
114 };
115 core3 {
116 cpu = <&a53_3>;
117 };
118 };
119 };
120
90493b09 121 a57_0: cpu@0 {
31af04cd 122 compatible = "arm,cortex-a57";
90493b09
BD		 123 reg = <0x0>;
124 device_type = "cpu";
aeee3d9c 125 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
90493b09
BD		 126 next-level-cache = <&L2_CA57>;
127 enable-method = "psci";
9e35f49c 128 dynamic-power-coefficient = <854>;
8ebb5038 129 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
800037e8 130 operating-points-v2 = <&cluster0_opp>;
5f524949 131 capacity-dmips-mhz = <1024>;
06a928fb 132 #cooling-cells = <2>;
90493b09
BD		 133 };
134
135 a57_1: cpu@1 {
31af04cd 136 compatible = "arm,cortex-a57";
90493b09
BD		 137 reg = <0x1>;
138 device_type = "cpu";
aeee3d9c 139 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
90493b09
BD		 140 next-level-cache = <&L2_CA57>;
141 enable-method = "psci";
8ebb5038 142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
800037e8 143 operating-points-v2 = <&cluster0_opp>;
5f524949 144 capacity-dmips-mhz = <1024>;
06a928fb 145 #cooling-cells = <2>;
90493b09
BD		 146 };
147
09f49bcf 148 a53_0: cpu@100 {
31af04cd 149 compatible = "arm,cortex-a53";
09f49bcf
BD		 150 reg = <0x100>;
151 device_type = "cpu";
aeee3d9c 152 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
09f49bcf
BD		 153 next-level-cache = <&L2_CA53>;
154 enable-method = "psci";
06a928fb 155 #cooling-cells = <2>;
9e35f49c 156 dynamic-power-coefficient = <277>;
8ebb5038 157 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
800037e8 158 operating-points-v2 = <&cluster1_opp>;
5f524949 159 capacity-dmips-mhz = <560>;
09f49bcf
BD		 160 };
161
162 a53_1: cpu@101 {
31af04cd 163 compatible = "arm,cortex-a53";
09f49bcf
BD		 164 reg = <0x101>;
165 device_type = "cpu";
aeee3d9c 166 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
09f49bcf
BD		 167 next-level-cache = <&L2_CA53>;
168 enable-method = "psci";
8ebb5038 169 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
800037e8 170 operating-points-v2 = <&cluster1_opp>;
5f524949 171 capacity-dmips-mhz = <560>;
09f49bcf
BD		 172 };
173
174 a53_2: cpu@102 {
31af04cd 175 compatible = "arm,cortex-a53";
09f49bcf
BD		 176 reg = <0x102>;
177 device_type = "cpu";
aeee3d9c 178 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
09f49bcf
BD		 179 next-level-cache = <&L2_CA53>;
180 enable-method = "psci";
8ebb5038 181 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
800037e8 182 operating-points-v2 = <&cluster1_opp>;
5f524949 183 capacity-dmips-mhz = <560>;
09f49bcf
BD		 184 };
185
186 a53_3: cpu@103 {
31af04cd 187 compatible = "arm,cortex-a53";
09f49bcf
BD		 188 reg = <0x103>;
189 device_type = "cpu";
aeee3d9c 190 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
09f49bcf
BD		 191 next-level-cache = <&L2_CA53>;
192 enable-method = "psci";
8ebb5038 193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
800037e8 194 operating-points-v2 = <&cluster1_opp>;
5f524949 195 capacity-dmips-mhz = <560>;
09f49bcf
BD		 196 };
197
90493b09
BD		 198 L2_CA57: cache-controller-0 {
199 compatible = "cache";
aeee3d9c 200 power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
90493b09
BD		 201 cache-unified;
202 cache-level = <2>;
203 };
09f49bcf
BD		 204
205 L2_CA53: cache-controller-1 {
206 compatible = "cache";
aeee3d9c 207 power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
09f49bcf
BD		 208 cache-unified;
209 cache-level = <2>;
210 };
90493b09
BD		 211 };
212
213 extal_clk: extal {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
216 /* This value must be overridden by the board */
217 clock-frequency = <0>;
218 };
219
220 extalr_clk: extalr {
221 compatible = "fixed-clock";
222 #clock-cells = <0>;
223 /* This value must be overridden by the board */
224 clock-frequency = <0>;
225 };
226
227 /* External PCIe clock - can be overridden by the board */
228 pcie_bus_clk: pcie_bus {
229 compatible = "fixed-clock";
230 #clock-cells = <0>;
231 clock-frequency = <0>;
232 };
233
09f49bcf
BD		 234 pmu_a53 {
235 compatible = "arm,cortex-a53-pmu";
236 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
237 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
238 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
239 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
240 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
241 };
242
90493b09
BD		 243 pmu_a57 {
244 compatible = "arm,cortex-a57-pmu";
245 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
246 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
247 interrupt-affinity = <&a57_0>, <&a57_1>;
248 };
249
250 psci {
251 compatible = "arm,psci-1.0", "arm,psci-0.2";
252 method = "smc";
253 };
254
255 /* External SCIF clock - to be overridden by boards that provide it */
256 scif_clk: scif {
257 compatible = "fixed-clock";
258 #clock-cells = <0>;
259 clock-frequency = <0>;
260 };
261
262 soc {
263 compatible = "simple-bus";
264 interrupt-parent = <&gic>;
265 #address-cells = <2>;
266 #size-cells = <2>;
267 ranges;
268
426f0b95
BD		 269 rwdt: watchdog@e6020000 {
270 compatible = "renesas,r8a774a1-wdt",
271 "renesas,rcar-gen3-wdt";
272 reg = <0 0xe6020000 0 0x0c>;
7ac8afba 273 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
426f0b95 274 clocks = <&cpg CPG_MOD 402>;
aeee3d9c 275 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
426f0b95
BD		 276 resets = <&cpg 402>;
277 status = "disabled";
278 };
279
53ae5809
FC		 280 gpio0: gpio@e6050000 {
281 compatible = "renesas,gpio-r8a774a1",
282 "renesas,rcar-gen3-gpio";
283 reg = <0 0xe6050000 0 0x50>;
284 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
285 #gpio-cells = <2>;
286 gpio-controller;
287 gpio-ranges = <&pfc 0 0 16>;
288 #interrupt-cells = <2>;
289 interrupt-controller;
290 clocks = <&cpg CPG_MOD 912>;
aeee3d9c 291 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
53ae5809
FC		 292 resets = <&cpg 912>;
293 };
294
295 gpio1: gpio@e6051000 {
296 compatible = "renesas,gpio-r8a774a1",
297 "renesas,rcar-gen3-gpio";
298 reg = <0 0xe6051000 0 0x50>;
299 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
300 #gpio-cells = <2>;
301 gpio-controller;
302 gpio-ranges = <&pfc 0 32 29>;
303 #interrupt-cells = <2>;
304 interrupt-controller;
305 clocks = <&cpg CPG_MOD 911>;
aeee3d9c 306 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
53ae5809
FC		 307 resets = <&cpg 911>;
308 };
309
310 gpio2: gpio@e6052000 {
311 compatible = "renesas,gpio-r8a774a1",
312 "renesas,rcar-gen3-gpio";
313 reg = <0 0xe6052000 0 0x50>;
314 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
315 #gpio-cells = <2>;
316 gpio-controller;
317 gpio-ranges = <&pfc 0 64 15>;
318 #interrupt-cells = <2>;
319 interrupt-controller;
320 clocks = <&cpg CPG_MOD 910>;
aeee3d9c 321 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
53ae5809
FC		 322 resets = <&cpg 910>;
323 };
324
325 gpio3: gpio@e6053000 {
326 compatible = "renesas,gpio-r8a774a1",
327 "renesas,rcar-gen3-gpio";
328 reg = <0 0xe6053000 0 0x50>;
329 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
330 #gpio-cells = <2>;
331 gpio-controller;
332 gpio-ranges = <&pfc 0 96 16>;
333 #interrupt-cells = <2>;
334 interrupt-controller;
335 clocks = <&cpg CPG_MOD 909>;
aeee3d9c 336 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
53ae5809
FC		 337 resets = <&cpg 909>;
338 };
339
340 gpio4: gpio@e6054000 {
341 compatible = "renesas,gpio-r8a774a1",
342 "renesas,rcar-gen3-gpio";
343 reg = <0 0xe6054000 0 0x50>;
344 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
345 #gpio-cells = <2>;
346 gpio-controller;
347 gpio-ranges = <&pfc 0 128 18>;
348 #interrupt-cells = <2>;
349 interrupt-controller;
350 clocks = <&cpg CPG_MOD 908>;
aeee3d9c 351 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
53ae5809
FC		 352 resets = <&cpg 908>;
353 };
354
355 gpio5: gpio@e6055000 {
356 compatible = "renesas,gpio-r8a774a1",
357 "renesas,rcar-gen3-gpio";
358 reg = <0 0xe6055000 0 0x50>;
359 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
360 #gpio-cells = <2>;
361 gpio-controller;
362 gpio-ranges = <&pfc 0 160 26>;
363 #interrupt-cells = <2>;
364 interrupt-controller;
365 clocks = <&cpg CPG_MOD 907>;
aeee3d9c 366 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
53ae5809
FC		 367 resets = <&cpg 907>;
368 };
369
370 gpio6: gpio@e6055400 {
371 compatible = "renesas,gpio-r8a774a1",
372 "renesas,rcar-gen3-gpio";
373 reg = <0 0xe6055400 0 0x50>;
374 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
375 #gpio-cells = <2>;
376 gpio-controller;
377 gpio-ranges = <&pfc 0 192 32>;
378 #interrupt-cells = <2>;
379 interrupt-controller;
380 clocks = <&cpg CPG_MOD 906>;
aeee3d9c 381 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
53ae5809
FC		 382 resets = <&cpg 906>;
383 };
384
385 gpio7: gpio@e6055800 {
386 compatible = "renesas,gpio-r8a774a1",
387 "renesas,rcar-gen3-gpio";
388 reg = <0 0xe6055800 0 0x50>;
389 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
390 #gpio-cells = <2>;
391 gpio-controller;
392 gpio-ranges = <&pfc 0 224 4>;
393 #interrupt-cells = <2>;
394 interrupt-controller;
395 clocks = <&cpg CPG_MOD 905>;
aeee3d9c 396 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
53ae5809
FC		 397 resets = <&cpg 905>;
398 };
399
a2053990 400 pfc: pinctrl@e6060000 {
3698dbd0
FC		 401 compatible = "renesas,pfc-r8a774a1";
402 reg = <0 0xe6060000 0 0x50c>;
403 };
404
aa85b3ca
FC		 405 cmt0: timer@e60f0000 {
406 compatible = "renesas,r8a774a1-cmt0",
407 "renesas,rcar-gen3-cmt0";
408 reg = <0 0xe60f0000 0 0x1004>;
409 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&cpg CPG_MOD 303>;
412 clock-names = "fck";
413 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
414 resets = <&cpg 303>;
415 status = "disabled";
416 };
417
418 cmt1: timer@e6130000 {
419 compatible = "renesas,r8a774a1-cmt1",
420 "renesas,rcar-gen3-cmt1";
421 reg = <0 0xe6130000 0 0x1004>;
422 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cpg CPG_MOD 302>;
431 clock-names = "fck";
432 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
433 resets = <&cpg 302>;
434 status = "disabled";
435 };
436
437 cmt2: timer@e6140000 {
438 compatible = "renesas,r8a774a1-cmt1",
439 "renesas,rcar-gen3-cmt1";
440 reg = <0 0xe6140000 0 0x1004>;
441 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&cpg CPG_MOD 301>;
450 clock-names = "fck";
451 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
452 resets = <&cpg 301>;
453 status = "disabled";
454 };
455
456 cmt3: timer@e6148000 {
457 compatible = "renesas,r8a774a1-cmt1",
458 "renesas,rcar-gen3-cmt1";
459 reg = <0 0xe6148000 0 0x1004>;
460 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cpg CPG_MOD 300>;
469 clock-names = "fck";
470 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
471 resets = <&cpg 300>;
472 status = "disabled";
473 };
474
90493b09
BD		 475 cpg: clock-controller@e6150000 {
476 compatible = "renesas,r8a774a1-cpg-mssr";
477 reg = <0 0xe6150000 0 0x0bb0>;
478 clocks = <&extal_clk>, <&extalr_clk>;
479 clock-names = "extal", "extalr";
480 #clock-cells = <2>;
481 #power-domain-cells = <0>;
482 #reset-cells = <1>;
483 };
484
485 rst: reset-controller@e6160000 {
486 compatible = "renesas,r8a774a1-rst";
487 reg = <0 0xe6160000 0 0x018c>;
488 };
489
490 sysc: system-controller@e6180000 {
491 compatible = "renesas,r8a774a1-sysc";
492 reg = <0 0xe6180000 0 0x0400>;
493 #power-domain-cells = <1>;
494 };
495
a4165904
BD		 496 tsc: thermal@e6198000 {
497 compatible = "renesas,r8a774a1-thermal";
498 reg = <0 0xe6198000 0 0x100>,
499 <0 0xe61a0000 0 0x100>,
500 <0 0xe61a8000 0 0x100>;
501 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cpg CPG_MOD 522>;
aeee3d9c 505 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
a4165904
BD		 506 resets = <&cpg 522>;
507 #thermal-sensor-cells = <1>;
a4165904
BD		 508 };
509
a21c572c
BD		 510 intc_ex: interrupt-controller@e61c0000 {
511 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
512 #interrupt-cells = <2>;
513 interrupt-controller;
514 reg = <0 0xe61c0000 0 0x200>;
0aab5b91
GU		 515 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
a21c572c 521 clocks = <&cpg CPG_MOD 407>;
aeee3d9c 522 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
a21c572c
BD		 523 resets = <&cpg 407>;
524 };
525
67e29136
FC		 526 tmu0: timer@e61e0000 {
527 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
528 reg = <0 0xe61e0000 0 0x30>;
529 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cpg CPG_MOD 125>;
533 clock-names = "fck";
534 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
535 resets = <&cpg 125>;
536 status = "disabled";
537 };
538
539 tmu1: timer@e6fc0000 {
540 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
541 reg = <0 0xe6fc0000 0 0x30>;
542 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&cpg CPG_MOD 124>;
546 clock-names = "fck";
547 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
548 resets = <&cpg 124>;
549 status = "disabled";
550 };
551
552 tmu2: timer@e6fd0000 {
553 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
554 reg = <0 0xe6fd0000 0 0x30>;
555 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cpg CPG_MOD 123>;
559 clock-names = "fck";
560 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
561 resets = <&cpg 123>;
562 status = "disabled";
563 };
564
565 tmu3: timer@e6fe0000 {
566 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
567 reg = <0 0xe6fe0000 0 0x30>;
568 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cpg CPG_MOD 122>;
572 clock-names = "fck";
573 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
574 resets = <&cpg 122>;
575 status = "disabled";
576 };
577
578 tmu4: timer@ffc00000 {
579 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
580 reg = <0 0xffc00000 0 0x30>;
581 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cpg CPG_MOD 121>;
585 clock-names = "fck";
586 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
587 resets = <&cpg 121>;
588 status = "disabled";
589 };
590
c674e8a7
BD		 591 i2c0: i2c@e6500000 {
592 #address-cells = <1>;
593 #size-cells = <0>;
594 compatible = "renesas,i2c-r8a774a1",
595 "renesas,rcar-gen3-i2c";
596 reg = <0 0xe6500000 0 0x40>;
597 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&cpg CPG_MOD 931>;
aeee3d9c 599 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c674e8a7
BD		 600 resets = <&cpg 931>;
601 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
602 <&dmac2 0x91>, <&dmac2 0x90>;
603 dma-names = "tx", "rx", "tx", "rx";
604 i2c-scl-internal-delay-ns = <110>;
605 status = "disabled";
606 };
607
608 i2c1: i2c@e6508000 {
609 #address-cells = <1>;
610 #size-cells = <0>;
611 compatible = "renesas,i2c-r8a774a1",
612 "renesas,rcar-gen3-i2c";
613 reg = <0 0xe6508000 0 0x40>;
614 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&cpg CPG_MOD 930>;
aeee3d9c 616 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c674e8a7
BD		 617 resets = <&cpg 930>;
618 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
619 <&dmac2 0x93>, <&dmac2 0x92>;
620 dma-names = "tx", "rx", "tx", "rx";
621 i2c-scl-internal-delay-ns = <6>;
622 status = "disabled";
623 };
624
625 i2c2: i2c@e6510000 {
626 #address-cells = <1>;
627 #size-cells = <0>;
628 compatible = "renesas,i2c-r8a774a1",
629 "renesas,rcar-gen3-i2c";
630 reg = <0 0xe6510000 0 0x40>;
631 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cpg CPG_MOD 929>;
aeee3d9c 633 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c674e8a7
BD		 634 resets = <&cpg 929>;
635 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
636 <&dmac2 0x95>, <&dmac2 0x94>;
637 dma-names = "tx", "rx", "tx", "rx";
638 i2c-scl-internal-delay-ns = <6>;
639 status = "disabled";
640 };
641
642 i2c3: i2c@e66d0000 {
643 #address-cells = <1>;
644 #size-cells = <0>;
645 compatible = "renesas,i2c-r8a774a1",
646 "renesas,rcar-gen3-i2c";
647 reg = <0 0xe66d0000 0 0x40>;
648 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cpg CPG_MOD 928>;
aeee3d9c 650 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c674e8a7
BD		 651 resets = <&cpg 928>;
652 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
653 dma-names = "tx", "rx";
654 i2c-scl-internal-delay-ns = <110>;
655 status = "disabled";
656 };
657
658 i2c4: i2c@e66d8000 {
659 #address-cells = <1>;
660 #size-cells = <0>;
661 compatible = "renesas,i2c-r8a774a1",
662 "renesas,rcar-gen3-i2c";
663 reg = <0 0xe66d8000 0 0x40>;
664 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&cpg CPG_MOD 927>;
aeee3d9c 666 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c674e8a7
BD		 667 resets = <&cpg 927>;
668 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
669 dma-names = "tx", "rx";
670 i2c-scl-internal-delay-ns = <110>;
671 status = "disabled";
672 };
673
674 i2c5: i2c@e66e0000 {
675 #address-cells = <1>;
676 #size-cells = <0>;
677 compatible = "renesas,i2c-r8a774a1",
678 "renesas,rcar-gen3-i2c";
679 reg = <0 0xe66e0000 0 0x40>;
680 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&cpg CPG_MOD 919>;
aeee3d9c 682 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c674e8a7
BD		 683 resets = <&cpg 919>;
684 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
685 dma-names = "tx", "rx";
686 i2c-scl-internal-delay-ns = <110>;
687 status = "disabled";
688 };
689
690 i2c6: i2c@e66e8000 {
691 #address-cells = <1>;
692 #size-cells = <0>;
693 compatible = "renesas,i2c-r8a774a1",
694 "renesas,rcar-gen3-i2c";
695 reg = <0 0xe66e8000 0 0x40>;
696 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&cpg CPG_MOD 918>;
aeee3d9c 698 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c674e8a7
BD		 699 resets = <&cpg 918>;
700 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
701 dma-names = "tx", "rx";
702 i2c-scl-internal-delay-ns = <6>;
703 status = "disabled";
704 };
705
a636d803 706 iic_pmic: i2c@e60b0000 {
c674e8a7
BD		 707 #address-cells = <1>;
708 #size-cells = <0>;
709 compatible = "renesas,iic-r8a774a1",
710 "renesas,rcar-gen3-iic",
711 "renesas,rmobile-iic";
712 reg = <0 0xe60b0000 0 0x425>;
713 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&cpg CPG_MOD 926>;
aeee3d9c 715 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c674e8a7
BD		 716 resets = <&cpg 926>;
717 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
718 dma-names = "tx", "rx";
719 status = "disabled";
720 };
721
3a3933a4
FC		 722 hscif0: serial@e6540000 {
723 compatible = "renesas,hscif-r8a774a1",
724 "renesas,rcar-gen3-hscif",
725 "renesas,hscif";
726 reg = <0 0xe6540000 0 0x60>;
727 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&cpg CPG_MOD 520>,
8ebb5038 729 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 730 <&scif_clk>;
731 clock-names = "fck", "brg_int", "scif_clk";
732 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
733 <&dmac2 0x31>, <&dmac2 0x30>;
734 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 735 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 736 resets = <&cpg 520>;
737 status = "disabled";
738 };
739
740 hscif1: serial@e6550000 {
741 compatible = "renesas,hscif-r8a774a1",
742 "renesas,rcar-gen3-hscif",
743 "renesas,hscif";
744 reg = <0 0xe6550000 0 0x60>;
745 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&cpg CPG_MOD 519>,
8ebb5038 747 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 748 <&scif_clk>;
749 clock-names = "fck", "brg_int", "scif_clk";
750 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
751 <&dmac2 0x33>, <&dmac2 0x32>;
752 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 753 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 754 resets = <&cpg 519>;
755 status = "disabled";
756 };
757
758 hscif2: serial@e6560000 {
759 compatible = "renesas,hscif-r8a774a1",
760 "renesas,rcar-gen3-hscif",
761 "renesas,hscif";
762 reg = <0 0xe6560000 0 0x60>;
763 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&cpg CPG_MOD 518>,
8ebb5038 765 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 766 <&scif_clk>;
767 clock-names = "fck", "brg_int", "scif_clk";
768 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
769 <&dmac2 0x35>, <&dmac2 0x34>;
770 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 771 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 772 resets = <&cpg 518>;
773 status = "disabled";
774 };
775
776 hscif3: serial@e66a0000 {
777 compatible = "renesas,hscif-r8a774a1",
778 "renesas,rcar-gen3-hscif",
779 "renesas,hscif";
780 reg = <0 0xe66a0000 0 0x60>;
781 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cpg CPG_MOD 517>,
8ebb5038 783 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 784 <&scif_clk>;
785 clock-names = "fck", "brg_int", "scif_clk";
786 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
787 dma-names = "tx", "rx";
aeee3d9c 788 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 789 resets = <&cpg 517>;
790 status = "disabled";
791 };
792
793 hscif4: serial@e66b0000 {
794 compatible = "renesas,hscif-r8a774a1",
795 "renesas,rcar-gen3-hscif",
796 "renesas,hscif";
797 reg = <0 0xe66b0000 0 0x60>;
798 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&cpg CPG_MOD 516>,
8ebb5038 800 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 801 <&scif_clk>;
802 clock-names = "fck", "brg_int", "scif_clk";
803 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
804 dma-names = "tx", "rx";
aeee3d9c 805 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 806 resets = <&cpg 516>;
807 status = "disabled";
808 };
809
ed898d4f
BD		 810 hsusb: usb@e6590000 {
811 compatible = "renesas,usbhs-r8a774a1",
812 "renesas,rcar-gen3-usbhs";
173c3b3c 813 reg = <0 0xe6590000 0 0x200>;
ed898d4f 814 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
a573cb67 815 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
ed898d4f
BD		 816 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
817 <&usb_dmac1 0>, <&usb_dmac1 1>;
818 dma-names = "ch0", "ch1", "ch2", "ch3";
819 renesas,buswait = <11>;
7794bd7e 820 phys = <&usb2_phy0 3>;
ed898d4f 821 phy-names = "usb";
aeee3d9c 822 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
a573cb67 823 resets = <&cpg 704>, <&cpg 703>;
ed898d4f
BD		 824 status = "disabled";
825 };
826
e1076ce0
AF		 827 usb2_clksel: clock-controller@e6590630 {
828 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel",
829 "renesas,rcar-gen3-usb2-clock-sel";
830 reg = <0 0xe6590630 0 0x02>;
831 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
832 <&usb_extal_clk>, <&usb3s0_clk>;
833 clock-names = "ehci_ohci", "hs-usb-if",
834 "usb_extal", "usb_xtal";
835 #clock-cells = <0>;
836 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
837 resets = <&cpg 703>, <&cpg 704>;
838 reset-names = "ehci_ohci", "hs-usb-if";
839 status = "disabled";
840 };
841
ed898d4f
BD		 842 usb_dmac0: dma-controller@e65a0000 {
843 compatible = "renesas,r8a774a1-usb-dmac",
844 "renesas,usb-dmac";
845 reg = <0 0xe65a0000 0 0x100>;
0aab5b91
GU		 846 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
ed898d4f
BD		 848 interrupt-names = "ch0", "ch1";
849 clocks = <&cpg CPG_MOD 330>;
aeee3d9c 850 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
ed898d4f
BD		 851 resets = <&cpg 330>;
852 #dma-cells = <1>;
853 dma-channels = <2>;
854 };
855
856 usb_dmac1: dma-controller@e65b0000 {
857 compatible = "renesas,r8a774a1-usb-dmac",
858 "renesas,usb-dmac";
859 reg = <0 0xe65b0000 0 0x100>;
0aab5b91
GU		 860 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
861 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
ed898d4f
BD		 862 interrupt-names = "ch0", "ch1";
863 clocks = <&cpg CPG_MOD 331>;
aeee3d9c 864 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
ed898d4f
BD		 865 resets = <&cpg 331>;
866 #dma-cells = <1>;
867 dma-channels = <2>;
868 };
869
453240f6
BD		 870 usb3_phy0: usb-phy@e65ee000 {
871 compatible = "renesas,r8a774a1-usb3-phy",
872 "renesas,rcar-gen3-usb3-phy";
873 reg = <0 0xe65ee000 0 0x90>;
874 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
875 <&usb_extal_clk>;
876 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
aeee3d9c 877 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
453240f6
BD		 878 resets = <&cpg 328>;
879 #phy-cells = <0>;
880 status = "disabled";
881 };
882
37a61e4d
BD		 883 dmac0: dma-controller@e6700000 {
884 compatible = "renesas,dmac-r8a774a1",
885 "renesas,rcar-dmac";
886 reg = <0 0xe6700000 0 0x10000>;
0aab5b91
GU		 887 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
37a61e4d
BD		 904 interrupt-names = "error",
905 "ch0", "ch1", "ch2", "ch3",
906 "ch4", "ch5", "ch6", "ch7",
907 "ch8", "ch9", "ch10", "ch11",
908 "ch12", "ch13", "ch14", "ch15";
909 clocks = <&cpg CPG_MOD 219>;
910 clock-names = "fck";
aeee3d9c 911 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
37a61e4d
BD		 912 resets = <&cpg 219>;
913 #dma-cells = <1>;
914 dma-channels = <16>;
c3362a74
BD		 915 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
916 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
917 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
918 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
919 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
920 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
921 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
922 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
37a61e4d
BD		 923 };
924
925 dmac1: dma-controller@e7300000 {
926 compatible = "renesas,dmac-r8a774a1",
927 "renesas,rcar-dmac";
928 reg = <0 0xe7300000 0 0x10000>;
0aab5b91
GU		 929 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
37a61e4d
BD		 946 interrupt-names = "error",
947 "ch0", "ch1", "ch2", "ch3",
948 "ch4", "ch5", "ch6", "ch7",
949 "ch8", "ch9", "ch10", "ch11",
950 "ch12", "ch13", "ch14", "ch15";
951 clocks = <&cpg CPG_MOD 218>;
952 clock-names = "fck";
aeee3d9c 953 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
37a61e4d
BD		 954 resets = <&cpg 218>;
955 #dma-cells = <1>;
956 dma-channels = <16>;
c3362a74
BD		 957 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
958 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
959 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
960 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
961 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
962 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
963 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
964 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
37a61e4d
BD		 965 };
966
967 dmac2: dma-controller@e7310000 {
968 compatible = "renesas,dmac-r8a774a1",
969 "renesas,rcar-dmac";
970 reg = <0 0xe7310000 0 0x10000>;
0aab5b91
GU		 971 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
37a61e4d
BD		 988 interrupt-names = "error",
989 "ch0", "ch1", "ch2", "ch3",
990 "ch4", "ch5", "ch6", "ch7",
991 "ch8", "ch9", "ch10", "ch11",
992 "ch12", "ch13", "ch14", "ch15";
993 clocks = <&cpg CPG_MOD 217>;
994 clock-names = "fck";
aeee3d9c 995 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
37a61e4d
BD		 996 resets = <&cpg 217>;
997 #dma-cells = <1>;
998 dma-channels = <16>;
c3362a74
BD		 999 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1000 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1001 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1002 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1003 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1004 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1005 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1006 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
37a61e4d
BD		 1007 };
1008
cf8ae446 1009 ipmmu_ds0: iommu@e6740000 {
8f507bab
FC		 1010 compatible = "renesas,ipmmu-r8a774a1";
1011 reg = <0 0xe6740000 0 0x1000>;
1012 renesas,ipmmu-main = <&ipmmu_mm 0>;
aeee3d9c 1013 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
8f507bab
FC		 1014 #iommu-cells = <1>;
1015 };
1016
cf8ae446 1017 ipmmu_ds1: iommu@e7740000 {
8f507bab
FC		 1018 compatible = "renesas,ipmmu-r8a774a1";
1019 reg = <0 0xe7740000 0 0x1000>;
1020 renesas,ipmmu-main = <&ipmmu_mm 1>;
aeee3d9c 1021 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
8f507bab
FC		 1022 #iommu-cells = <1>;
1023 };
1024
cf8ae446 1025 ipmmu_hc: iommu@e6570000 {
8f507bab
FC		 1026 compatible = "renesas,ipmmu-r8a774a1";
1027 reg = <0 0xe6570000 0 0x1000>;
1028 renesas,ipmmu-main = <&ipmmu_mm 2>;
aeee3d9c 1029 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
8f507bab
FC		 1030 #iommu-cells = <1>;
1031 };
1032
cf8ae446 1033 ipmmu_mm: iommu@e67b0000 {
8f507bab
FC		 1034 compatible = "renesas,ipmmu-r8a774a1";
1035 reg = <0 0xe67b0000 0 0x1000>;
1036 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
aeee3d9c 1038 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
8f507bab
FC		 1039 #iommu-cells = <1>;
1040 };
1041
cf8ae446 1042 ipmmu_mp: iommu@ec670000 {
8f507bab
FC		 1043 compatible = "renesas,ipmmu-r8a774a1";
1044 reg = <0 0xec670000 0 0x1000>;
1045 renesas,ipmmu-main = <&ipmmu_mm 4>;
aeee3d9c 1046 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
8f507bab
FC		 1047 #iommu-cells = <1>;
1048 };
1049
cf8ae446 1050 ipmmu_pv0: iommu@fd800000 {
8f507bab
FC		 1051 compatible = "renesas,ipmmu-r8a774a1";
1052 reg = <0 0xfd800000 0 0x1000>;
1053 renesas,ipmmu-main = <&ipmmu_mm 5>;
aeee3d9c 1054 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
8f507bab
FC		 1055 #iommu-cells = <1>;
1056 };
1057
cf8ae446 1058 ipmmu_pv1: iommu@fd950000 {
8f507bab
FC		 1059 compatible = "renesas,ipmmu-r8a774a1";
1060 reg = <0 0xfd950000 0 0x1000>;
1061 renesas,ipmmu-main = <&ipmmu_mm 6>;
aeee3d9c 1062 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
8f507bab
FC		 1063 #iommu-cells = <1>;
1064 };
1065
cf8ae446 1066 ipmmu_vc0: iommu@fe6b0000 {
8f507bab
FC		 1067 compatible = "renesas,ipmmu-r8a774a1";
1068 reg = <0 0xfe6b0000 0 0x1000>;
1069 renesas,ipmmu-main = <&ipmmu_mm 8>;
aeee3d9c 1070 power-domains = <&sysc R8A774A1_PD_A3VC>;
8f507bab
FC		 1071 #iommu-cells = <1>;
1072 };
1073
cf8ae446 1074 ipmmu_vi0: iommu@febd0000 {
8f507bab
FC		 1075 compatible = "renesas,ipmmu-r8a774a1";
1076 reg = <0 0xfebd0000 0 0x1000>;
1077 renesas,ipmmu-main = <&ipmmu_mm 9>;
aeee3d9c 1078 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
8f507bab
FC		 1079 #iommu-cells = <1>;
1080 };
1081
71bddde2
FC		 1082 avb: ethernet@e6800000 {
1083 compatible = "renesas,etheravb-r8a774a1",
1084 "renesas,etheravb-rcar-gen3";
1085 reg = <0 0xe6800000 0 0x800>;
1086 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1087 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1103 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1111 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1112 "ch4", "ch5", "ch6", "ch7",
1113 "ch8", "ch9", "ch10", "ch11",
1114 "ch12", "ch13", "ch14", "ch15",
1115 "ch16", "ch17", "ch18", "ch19",
1116 "ch20", "ch21", "ch22", "ch23",
1117 "ch24";
1118 clocks = <&cpg CPG_MOD 812>;
56ed0b3b 1119 clock-names = "fck";
aeee3d9c 1120 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
71bddde2
FC		 1121 resets = <&cpg 812>;
1122 phy-mode = "rgmii";
a5200e63
GU		 1123 rx-internal-delay-ps = <0>;
1124 tx-internal-delay-ps = <0>;
57cfa731 1125 iommus = <&ipmmu_ds0 16>;
71bddde2
FC		 1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 status = "disabled";
1129 };
1130
b823d65f
CP		 1131 can0: can@e6c30000 {
1132 compatible = "renesas,can-r8a774a1",
1133 "renesas,rcar-gen3-can";
1134 reg = <0 0xe6c30000 0 0x1000>;
1135 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
eccc4000
FC		 1136 clocks = <&cpg CPG_MOD 916>,
1137 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1138 <&can_clk>;
1139 clock-names = "clkp1", "clkp2", "can_clk";
0a930f64
FC		 1140 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1141 assigned-clock-rates = <40000000>;
aeee3d9c 1142 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
b823d65f
CP		 1143 resets = <&cpg 916>;
1144 status = "disabled";
1145 };
1146
1147 can1: can@e6c38000 {
1148 compatible = "renesas,can-r8a774a1",
1149 "renesas,rcar-gen3-can";
1150 reg = <0 0xe6c38000 0 0x1000>;
1151 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
eccc4000
FC		 1152 clocks = <&cpg CPG_MOD 915>,
1153 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1154 <&can_clk>;
1155 clock-names = "clkp1", "clkp2", "can_clk";
0a930f64
FC		 1156 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1157 assigned-clock-rates = <40000000>;
aeee3d9c 1158 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
b823d65f
CP		 1159 resets = <&cpg 915>;
1160 status = "disabled";
1161 };
1162
5b971c71
FC		 1163 canfd: can@e66c0000 {
1164 compatible = "renesas,r8a774a1-canfd",
1165 "renesas,rcar-gen3-canfd";
1166 reg = <0 0xe66c0000 0 0x8000>;
1167 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6af663af 1169 interrupt-names = "ch_int", "g_int";
5b971c71
FC		 1170 clocks = <&cpg CPG_MOD 914>,
1171 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1172 <&can_clk>;
1173 clock-names = "fck", "canfd", "can_clk";
1174 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1175 assigned-clock-rates = <40000000>;
1176 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1177 resets = <&cpg 914>;
1178 status = "disabled";
1179
1180 channel0 {
1181 status = "disabled";
1182 };
1183
1184 channel1 {
1185 status = "disabled";
1186 };
1187 };
1188
9567a856
FC		 1189 pwm0: pwm@e6e30000 {
1190 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1191 reg = <0 0xe6e30000 0 0x8>;
1192 #pwm-cells = <2>;
1193 clocks = <&cpg CPG_MOD 523>;
1194 resets = <&cpg 523>;
aeee3d9c 1195 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
9567a856
FC		 1196 status = "disabled";
1197 };
1198
1199 pwm1: pwm@e6e31000 {
1200 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1201 reg = <0 0xe6e31000 0 0x8>;
1202 #pwm-cells = <2>;
1203 clocks = <&cpg CPG_MOD 523>;
1204 resets = <&cpg 523>;
aeee3d9c 1205 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
9567a856
FC		 1206 status = "disabled";
1207 };
1208
1209 pwm2: pwm@e6e32000 {
1210 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1211 reg = <0 0xe6e32000 0 0x8>;
1212 #pwm-cells = <2>;
1213 clocks = <&cpg CPG_MOD 523>;
1214 resets = <&cpg 523>;
aeee3d9c 1215 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
9567a856
FC		 1216 status = "disabled";
1217 };
1218
1219 pwm3: pwm@e6e33000 {
1220 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1221 reg = <0 0xe6e33000 0 0x8>;
1222 #pwm-cells = <2>;
1223 clocks = <&cpg CPG_MOD 523>;
1224 resets = <&cpg 523>;
aeee3d9c 1225 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
9567a856
FC		 1226 status = "disabled";
1227 };
1228
1229 pwm4: pwm@e6e34000 {
1230 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1231 reg = <0 0xe6e34000 0 0x8>;
1232 #pwm-cells = <2>;
1233 clocks = <&cpg CPG_MOD 523>;
1234 resets = <&cpg 523>;
aeee3d9c 1235 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
9567a856
FC		 1236 status = "disabled";
1237 };
1238
1239 pwm5: pwm@e6e35000 {
1240 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1241 reg = <0 0xe6e35000 0 0x8>;
1242 #pwm-cells = <2>;
1243 clocks = <&cpg CPG_MOD 523>;
1244 resets = <&cpg 523>;
aeee3d9c 1245 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
9567a856
FC		 1246 status = "disabled";
1247 };
1248
1249 pwm6: pwm@e6e36000 {
1250 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1251 reg = <0 0xe6e36000 0 0x8>;
1252 #pwm-cells = <2>;
1253 clocks = <&cpg CPG_MOD 523>;
1254 resets = <&cpg 523>;
aeee3d9c 1255 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
9567a856
FC		 1256 status = "disabled";
1257 };
1258
3a3933a4
FC		 1259 scif0: serial@e6e60000 {
1260 compatible = "renesas,scif-r8a774a1",
1261 "renesas,rcar-gen3-scif", "renesas,scif";
1262 reg = <0 0xe6e60000 0 0x40>;
1263 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&cpg CPG_MOD 207>,
8ebb5038 1265 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 1266 <&scif_clk>;
1267 clock-names = "fck", "brg_int", "scif_clk";
1268 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1269 <&dmac2 0x51>, <&dmac2 0x50>;
1270 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 1271 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 1272 resets = <&cpg 207>;
1273 status = "disabled";
1274 };
1275
1276 scif1: serial@e6e68000 {
1277 compatible = "renesas,scif-r8a774a1",
1278 "renesas,rcar-gen3-scif", "renesas,scif";
1279 reg = <0 0xe6e68000 0 0x40>;
1280 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&cpg CPG_MOD 206>,
8ebb5038 1282 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 1283 <&scif_clk>;
1284 clock-names = "fck", "brg_int", "scif_clk";
1285 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1286 <&dmac2 0x53>, <&dmac2 0x52>;
1287 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 1288 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 1289 resets = <&cpg 206>;
1290 status = "disabled";
1291 };
1292
1293 scif2: serial@e6e88000 {
1294 compatible = "renesas,scif-r8a774a1",
1295 "renesas,rcar-gen3-scif", "renesas,scif";
1296 reg = <0 0xe6e88000 0 0x40>;
1297 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cpg CPG_MOD 310>,
8ebb5038 1299 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 1300 <&scif_clk>;
1301 clock-names = "fck", "brg_int", "scif_clk";
2bb7b675
GU		 1302 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1303 <&dmac2 0x13>, <&dmac2 0x12>;
1304 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 1305 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 1306 resets = <&cpg 310>;
1307 status = "disabled";
1308 };
1309
1310 scif3: serial@e6c50000 {
1311 compatible = "renesas,scif-r8a774a1",
1312 "renesas,rcar-gen3-scif", "renesas,scif";
1313 reg = <0 0xe6c50000 0 0x40>;
1314 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1315 clocks = <&cpg CPG_MOD 204>,
8ebb5038 1316 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 1317 <&scif_clk>;
1318 clock-names = "fck", "brg_int", "scif_clk";
1319 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1320 dma-names = "tx", "rx";
aeee3d9c 1321 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 1322 resets = <&cpg 204>;
1323 status = "disabled";
1324 };
1325
1326 scif4: serial@e6c40000 {
1327 compatible = "renesas,scif-r8a774a1",
1328 "renesas,rcar-gen3-scif", "renesas,scif";
1329 reg = <0 0xe6c40000 0 0x40>;
1330 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&cpg CPG_MOD 203>,
8ebb5038 1332 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 1333 <&scif_clk>;
1334 clock-names = "fck", "brg_int", "scif_clk";
1335 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1336 dma-names = "tx", "rx";
aeee3d9c 1337 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 1338 resets = <&cpg 203>;
1339 status = "disabled";
1340 };
1341
1342 scif5: serial@e6f30000 {
1343 compatible = "renesas,scif-r8a774a1",
1344 "renesas,rcar-gen3-scif", "renesas,scif";
1345 reg = <0 0xe6f30000 0 0x40>;
1346 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MOD 202>,
8ebb5038 1348 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
3a3933a4
FC		 1349 <&scif_clk>;
1350 clock-names = "fck", "brg_int", "scif_clk";
1351 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1352 <&dmac2 0x5b>, <&dmac2 0x5a>;
1353 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 1354 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
3a3933a4
FC		 1355 resets = <&cpg 202>;
1356 status = "disabled";
1357 };
1358
c512110d
BD		 1359 msiof0: spi@e6e90000 {
1360 compatible = "renesas,msiof-r8a774a1",
1361 "renesas,rcar-gen3-msiof";
1362 reg = <0 0xe6e90000 0 0x0064>;
1363 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MOD 211>;
1365 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1366 <&dmac2 0x41>, <&dmac2 0x40>;
1367 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 1368 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c512110d
BD		 1369 resets = <&cpg 211>;
1370 #address-cells = <1>;
1371 #size-cells = <0>;
1372 status = "disabled";
1373 };
1374
1375 msiof1: spi@e6ea0000 {
1376 compatible = "renesas,msiof-r8a774a1",
1377 "renesas,rcar-gen3-msiof";
1378 reg = <0 0xe6ea0000 0 0x0064>;
1379 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1380 clocks = <&cpg CPG_MOD 210>;
1381 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1382 <&dmac2 0x43>, <&dmac2 0x42>;
1383 dma-names = "tx", "rx", "tx", "rx";
aeee3d9c 1384 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c512110d
BD		 1385 resets = <&cpg 210>;
1386 #address-cells = <1>;
1387 #size-cells = <0>;
1388 status = "disabled";
1389 };
1390
1391 msiof2: spi@e6c00000 {
1392 compatible = "renesas,msiof-r8a774a1",
1393 "renesas,rcar-gen3-msiof";
1394 reg = <0 0xe6c00000 0 0x0064>;
1395 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1396 clocks = <&cpg CPG_MOD 209>;
1397 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1398 dma-names = "tx", "rx";
aeee3d9c 1399 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c512110d
BD		 1400 resets = <&cpg 209>;
1401 #address-cells = <1>;
1402 #size-cells = <0>;
1403 status = "disabled";
1404 };
1405
1406 msiof3: spi@e6c10000 {
1407 compatible = "renesas,msiof-r8a774a1",
1408 "renesas,rcar-gen3-msiof";
1409 reg = <0 0xe6c10000 0 0x0064>;
1410 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1411 clocks = <&cpg CPG_MOD 208>;
1412 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1413 dma-names = "tx", "rx";
aeee3d9c 1414 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
c512110d
BD		 1415 resets = <&cpg 208>;
1416 #address-cells = <1>;
1417 #size-cells = <0>;
1418 status = "disabled";
1419 };
1420
0c85e78f
BD		 1421 vin0: video@e6ef0000 {
1422 compatible = "renesas,vin-r8a774a1";
1423 reg = <0 0xe6ef0000 0 0x1000>;
1424 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&cpg CPG_MOD 811>;
aeee3d9c 1426 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 1427 resets = <&cpg 811>;
1428 renesas,id = <0>;
1429 status = "disabled";
1430
1431 ports {
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1434
1435 port@1 {
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1438
1439 reg = <1>;
1440
1441 vin0csi20: endpoint@0 {
1442 reg = <0>;
1443 remote-endpoint = <&csi20vin0>;
1444 };
1445 vin0csi40: endpoint@2 {
1446 reg = <2>;
1447 remote-endpoint = <&csi40vin0>;
1448 };
1449 };
1450 };
1451 };
1452
1453 vin1: video@e6ef1000 {
1454 compatible = "renesas,vin-r8a774a1";
1455 reg = <0 0xe6ef1000 0 0x1000>;
1456 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&cpg CPG_MOD 810>;
aeee3d9c 1458 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 1459 resets = <&cpg 810>;
1460 renesas,id = <1>;
1461 status = "disabled";
1462
1463 ports {
1464 #address-cells = <1>;
1465 #size-cells = <0>;
1466
1467 port@1 {
1468 #address-cells = <1>;
1469 #size-cells = <0>;
1470
1471 reg = <1>;
1472
1473 vin1csi20: endpoint@0 {
1474 reg = <0>;
1475 remote-endpoint = <&csi20vin1>;
1476 };
1477 vin1csi40: endpoint@2 {
1478 reg = <2>;
1479 remote-endpoint = <&csi40vin1>;
1480 };
1481 };
1482 };
1483 };
1484
1485 vin2: video@e6ef2000 {
1486 compatible = "renesas,vin-r8a774a1";
1487 reg = <0 0xe6ef2000 0 0x1000>;
1488 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1489 clocks = <&cpg CPG_MOD 809>;
aeee3d9c 1490 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 1491 resets = <&cpg 809>;
1492 renesas,id = <2>;
1493 status = "disabled";
1494
1495 ports {
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498
1499 port@1 {
1500 #address-cells = <1>;
1501 #size-cells = <0>;
1502
1503 reg = <1>;
1504
1505 vin2csi20: endpoint@0 {
1506 reg = <0>;
1507 remote-endpoint = <&csi20vin2>;
1508 };
1509 vin2csi40: endpoint@2 {
1510 reg = <2>;
1511 remote-endpoint = <&csi40vin2>;
1512 };
1513 };
1514 };
1515 };
1516
1517 vin3: video@e6ef3000 {
1518 compatible = "renesas,vin-r8a774a1";
1519 reg = <0 0xe6ef3000 0 0x1000>;
1520 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1521 clocks = <&cpg CPG_MOD 808>;
aeee3d9c 1522 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 1523 resets = <&cpg 808>;
1524 renesas,id = <3>;
1525 status = "disabled";
1526
1527 ports {
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530
1531 port@1 {
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1534
1535 reg = <1>;
1536
1537 vin3csi20: endpoint@0 {
1538 reg = <0>;
1539 remote-endpoint = <&csi20vin3>;
1540 };
1541 vin3csi40: endpoint@2 {
1542 reg = <2>;
1543 remote-endpoint = <&csi40vin3>;
1544 };
1545 };
1546 };
1547 };
1548
1549 vin4: video@e6ef4000 {
1550 compatible = "renesas,vin-r8a774a1";
1551 reg = <0 0xe6ef4000 0 0x1000>;
1552 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1553 clocks = <&cpg CPG_MOD 807>;
aeee3d9c 1554 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 1555 resets = <&cpg 807>;
1556 renesas,id = <4>;
1557 status = "disabled";
1558
1559 ports {
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1562
1563 port@1 {
1564 #address-cells = <1>;
1565 #size-cells = <0>;
1566
1567 reg = <1>;
1568
1569 vin4csi20: endpoint@0 {
1570 reg = <0>;
1571 remote-endpoint = <&csi20vin4>;
1572 };
1573 vin4csi40: endpoint@2 {
1574 reg = <2>;
1575 remote-endpoint = <&csi40vin4>;
1576 };
1577 };
1578 };
1579 };
1580
1581 vin5: video@e6ef5000 {
1582 compatible = "renesas,vin-r8a774a1";
1583 reg = <0 0xe6ef5000 0 0x1000>;
1584 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1585 clocks = <&cpg CPG_MOD 806>;
aeee3d9c 1586 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 1587 resets = <&cpg 806>;
1588 renesas,id = <5>;
1589 status = "disabled";
1590
1591 ports {
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1594
1595 port@1 {
1596 #address-cells = <1>;
1597 #size-cells = <0>;
1598
1599 reg = <1>;
1600
1601 vin5csi20: endpoint@0 {
1602 reg = <0>;
1603 remote-endpoint = <&csi20vin5>;
1604 };
1605 vin5csi40: endpoint@2 {
1606 reg = <2>;
1607 remote-endpoint = <&csi40vin5>;
1608 };
1609 };
1610 };
1611 };
1612
1613 vin6: video@e6ef6000 {
1614 compatible = "renesas,vin-r8a774a1";
1615 reg = <0 0xe6ef6000 0 0x1000>;
1616 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1617 clocks = <&cpg CPG_MOD 805>;
aeee3d9c 1618 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 1619 resets = <&cpg 805>;
1620 renesas,id = <6>;
1621 status = "disabled";
1622
1623 ports {
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1626
1627 port@1 {
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1630
1631 reg = <1>;
1632
1633 vin6csi20: endpoint@0 {
1634 reg = <0>;
1635 remote-endpoint = <&csi20vin6>;
1636 };
1637 vin6csi40: endpoint@2 {
1638 reg = <2>;
1639 remote-endpoint = <&csi40vin6>;
1640 };
1641 };
1642 };
1643 };
1644
1645 vin7: video@e6ef7000 {
1646 compatible = "renesas,vin-r8a774a1";
1647 reg = <0 0xe6ef7000 0 0x1000>;
1648 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1649 clocks = <&cpg CPG_MOD 804>;
aeee3d9c 1650 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 1651 resets = <&cpg 804>;
1652 renesas,id = <7>;
1653 status = "disabled";
1654
1655 ports {
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1658
1659 port@1 {
1660 #address-cells = <1>;
1661 #size-cells = <0>;
1662
1663 reg = <1>;
1664
1665 vin7csi20: endpoint@0 {
1666 reg = <0>;
1667 remote-endpoint = <&csi20vin7>;
1668 };
1669 vin7csi40: endpoint@2 {
1670 reg = <2>;
1671 remote-endpoint = <&csi40vin7>;
1672 };
1673 };
1674 };
1675 };
1676
e2f04248
BD		 1677 rcar_sound: sound@ec500000 {
1678 /*
9e72606c 1679 * #sound-dai-cells is required if simple-card
e2f04248
BD		 1680 *
1681 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1682 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1683 */
1684 /*
1685 * #clock-cells is required for audio_clkout0/1/2/3
1686 *
1687 * clkout : #clock-cells = <0>; <&rcar_sound>;
1688 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1689 */
953b392a
GU		 1690 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1691 reg = <0 0xec500000 0 0x1000>, /* SCU */
1692 <0 0xec5a0000 0 0x100>, /* ADG */
1693 <0 0xec540000 0 0x1000>, /* SSIU */
1694 <0 0xec541000 0 0x280>, /* SSI */
1695 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
e2f04248
BD		 1696 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1697
1698 clocks = <&cpg CPG_MOD 1005>,
1699 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1700 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1701 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1702 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1703 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1704 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1705 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1706 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1707 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1708 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1709 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1710 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1711 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1712 <&audio_clk_a>, <&audio_clk_b>,
1713 <&audio_clk_c>,
f2802c62 1714 <&cpg CPG_MOD 922>;
e2f04248
BD		 1715 clock-names = "ssi-all",
1716 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1717 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1718 "ssi.1", "ssi.0",
1719 "src.9", "src.8", "src.7", "src.6",
1720 "src.5", "src.4", "src.3", "src.2",
1721 "src.1", "src.0",
1722 "mix.1", "mix.0",
1723 "ctu.1", "ctu.0",
1724 "dvc.0", "dvc.1",
1725 "clk_a", "clk_b", "clk_c", "clk_i";
aeee3d9c 1726 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
e2f04248
BD		 1727 resets = <&cpg 1005>,
1728 <&cpg 1006>, <&cpg 1007>,
1729 <&cpg 1008>, <&cpg 1009>,
1730 <&cpg 1010>, <&cpg 1011>,
1731 <&cpg 1012>, <&cpg 1013>,
1732 <&cpg 1014>, <&cpg 1015>;
1733 reset-names = "ssi-all",
1734 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1735 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1736 "ssi.1", "ssi.0";
1737 status = "disabled";
1738
fadbdd06
YK		 1739 rcar_sound,ctu {
1740 ctu00: ctu-0 { };
1741 ctu01: ctu-1 { };
1742 ctu02: ctu-2 { };
1743 ctu03: ctu-3 { };
1744 ctu10: ctu-4 { };
1745 ctu11: ctu-5 { };
1746 ctu12: ctu-6 { };
1747 ctu13: ctu-7 { };
1748 };
1749
e2f04248
BD		 1750 rcar_sound,dvc {
1751 dvc0: dvc-0 {
1752 dmas = <&audma1 0xbc>;
1753 dma-names = "tx";
1754 };
1755 dvc1: dvc-1 {
1756 dmas = <&audma1 0xbe>;
1757 dma-names = "tx";
1758 };
1759 };
1760
1761 rcar_sound,mix {
1762 mix0: mix-0 { };
1763 mix1: mix-1 { };
1764 };
1765
e2f04248
BD		 1766 rcar_sound,src {
1767 src0: src-0 {
1768 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1769 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1770 dma-names = "rx", "tx";
1771 };
1772 src1: src-1 {
1773 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1774 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1775 dma-names = "rx", "tx";
1776 };
1777 src2: src-2 {
1778 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1779 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1780 dma-names = "rx", "tx";
1781 };
1782 src3: src-3 {
1783 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1784 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1785 dma-names = "rx", "tx";
1786 };
1787 src4: src-4 {
1788 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1789 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1790 dma-names = "rx", "tx";
1791 };
1792 src5: src-5 {
1793 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1794 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1795 dma-names = "rx", "tx";
1796 };
1797 src6: src-6 {
1798 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1799 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1800 dma-names = "rx", "tx";
1801 };
1802 src7: src-7 {
1803 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1804 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1805 dma-names = "rx", "tx";
1806 };
1807 src8: src-8 {
1808 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1809 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1810 dma-names = "rx", "tx";
1811 };
1812 src9: src-9 {
1813 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1814 dmas = <&audma0 0x97>, <&audma1 0xba>;
1815 dma-names = "rx", "tx";
1816 };
1817 };
1818
fadbdd06
YK		 1819 rcar_sound,ssi {
1820 ssi0: ssi-0 {
1821 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1822 dmas = <&audma0 0x01>, <&audma1 0x02>;
1823 dma-names = "rx", "tx";
1824 };
1825 ssi1: ssi-1 {
1826 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1827 dmas = <&audma0 0x03>, <&audma1 0x04>;
1828 dma-names = "rx", "tx";
1829 };
1830 ssi2: ssi-2 {
1831 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1832 dmas = <&audma0 0x05>, <&audma1 0x06>;
1833 dma-names = "rx", "tx";
1834 };
1835 ssi3: ssi-3 {
1836 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1837 dmas = <&audma0 0x07>, <&audma1 0x08>;
1838 dma-names = "rx", "tx";
1839 };
1840 ssi4: ssi-4 {
1841 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1842 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1843 dma-names = "rx", "tx";
1844 };
1845 ssi5: ssi-5 {
1846 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1847 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1848 dma-names = "rx", "tx";
1849 };
1850 ssi6: ssi-6 {
1851 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1852 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1853 dma-names = "rx", "tx";
1854 };
1855 ssi7: ssi-7 {
1856 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1857 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1858 dma-names = "rx", "tx";
1859 };
1860 ssi8: ssi-8 {
1861 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&audma0 0x11>, <&audma1 0x12>;
1863 dma-names = "rx", "tx";
1864 };
1865 ssi9: ssi-9 {
1866 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1867 dmas = <&audma0 0x13>, <&audma1 0x14>;
1868 dma-names = "rx", "tx";
1869 };
1870 };
1871
a44efeaa
FC		 1872 rcar_sound,ssiu {
1873 ssiu00: ssiu-0 {
1874 dmas = <&audma0 0x15>, <&audma1 0x16>;
1875 dma-names = "rx", "tx";
1876 };
1877 ssiu01: ssiu-1 {
1878 dmas = <&audma0 0x35>, <&audma1 0x36>;
1879 dma-names = "rx", "tx";
1880 };
1881 ssiu02: ssiu-2 {
1882 dmas = <&audma0 0x37>, <&audma1 0x38>;
1883 dma-names = "rx", "tx";
1884 };
1885 ssiu03: ssiu-3 {
1886 dmas = <&audma0 0x47>, <&audma1 0x48>;
1887 dma-names = "rx", "tx";
1888 };
1889 ssiu04: ssiu-4 {
1890 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1891 dma-names = "rx", "tx";
1892 };
1893 ssiu05: ssiu-5 {
1894 dmas = <&audma0 0x43>, <&audma1 0x44>;
1895 dma-names = "rx", "tx";
1896 };
1897 ssiu06: ssiu-6 {
1898 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1899 dma-names = "rx", "tx";
1900 };
1901 ssiu07: ssiu-7 {
1902 dmas = <&audma0 0x53>, <&audma1 0x54>;
1903 dma-names = "rx", "tx";
1904 };
1905 ssiu10: ssiu-8 {
1906 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1907 dma-names = "rx", "tx";
1908 };
1909 ssiu11: ssiu-9 {
1910 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1911 dma-names = "rx", "tx";
1912 };
1913 ssiu12: ssiu-10 {
1914 dmas = <&audma0 0x57>, <&audma1 0x58>;
1915 dma-names = "rx", "tx";
1916 };
1917 ssiu13: ssiu-11 {
1918 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1919 dma-names = "rx", "tx";
1920 };
1921 ssiu14: ssiu-12 {
1922 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1923 dma-names = "rx", "tx";
1924 };
1925 ssiu15: ssiu-13 {
1926 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1927 dma-names = "rx", "tx";
1928 };
1929 ssiu16: ssiu-14 {
1930 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1931 dma-names = "rx", "tx";
1932 };
1933 ssiu17: ssiu-15 {
1934 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1935 dma-names = "rx", "tx";
1936 };
1937 ssiu20: ssiu-16 {
1938 dmas = <&audma0 0x63>, <&audma1 0x64>;
1939 dma-names = "rx", "tx";
1940 };
1941 ssiu21: ssiu-17 {
1942 dmas = <&audma0 0x67>, <&audma1 0x68>;
1943 dma-names = "rx", "tx";
1944 };
1945 ssiu22: ssiu-18 {
1946 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1947 dma-names = "rx", "tx";
1948 };
1949 ssiu23: ssiu-19 {
1950 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1951 dma-names = "rx", "tx";
1952 };
1953 ssiu24: ssiu-20 {
1954 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1955 dma-names = "rx", "tx";
1956 };
1957 ssiu25: ssiu-21 {
1958 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1959 dma-names = "rx", "tx";
1960 };
1961 ssiu26: ssiu-22 {
1962 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1963 dma-names = "rx", "tx";
1964 };
1965 ssiu27: ssiu-23 {
1966 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1967 dma-names = "rx", "tx";
1968 };
1969 ssiu30: ssiu-24 {
1970 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1971 dma-names = "rx", "tx";
1972 };
1973 ssiu31: ssiu-25 {
1974 dmas = <&audma0 0x21>, <&audma1 0x22>;
1975 dma-names = "rx", "tx";
1976 };
1977 ssiu32: ssiu-26 {
1978 dmas = <&audma0 0x23>, <&audma1 0x24>;
1979 dma-names = "rx", "tx";
1980 };
1981 ssiu33: ssiu-27 {
1982 dmas = <&audma0 0x25>, <&audma1 0x26>;
1983 dma-names = "rx", "tx";
1984 };
1985 ssiu34: ssiu-28 {
1986 dmas = <&audma0 0x27>, <&audma1 0x28>;
1987 dma-names = "rx", "tx";
1988 };
1989 ssiu35: ssiu-29 {
1990 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1991 dma-names = "rx", "tx";
1992 };
1993 ssiu36: ssiu-30 {
1994 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1995 dma-names = "rx", "tx";
1996 };
1997 ssiu37: ssiu-31 {
1998 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1999 dma-names = "rx", "tx";
2000 };
2001 ssiu40: ssiu-32 {
953b392a 2002 dmas = <&audma0 0x71>, <&audma1 0x72>;
a44efeaa
FC		 2003 dma-names = "rx", "tx";
2004 };
2005 ssiu41: ssiu-33 {
2006 dmas = <&audma0 0x17>, <&audma1 0x18>;
2007 dma-names = "rx", "tx";
2008 };
2009 ssiu42: ssiu-34 {
2010 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2011 dma-names = "rx", "tx";
2012 };
2013 ssiu43: ssiu-35 {
2014 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2015 dma-names = "rx", "tx";
2016 };
2017 ssiu44: ssiu-36 {
2018 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2019 dma-names = "rx", "tx";
2020 };
2021 ssiu45: ssiu-37 {
2022 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2023 dma-names = "rx", "tx";
2024 };
2025 ssiu46: ssiu-38 {
2026 dmas = <&audma0 0x31>, <&audma1 0x32>;
2027 dma-names = "rx", "tx";
2028 };
2029 ssiu47: ssiu-39 {
2030 dmas = <&audma0 0x33>, <&audma1 0x34>;
2031 dma-names = "rx", "tx";
2032 };
2033 ssiu50: ssiu-40 {
2034 dmas = <&audma0 0x73>, <&audma1 0x74>;
2035 dma-names = "rx", "tx";
2036 };
2037 ssiu60: ssiu-41 {
2038 dmas = <&audma0 0x75>, <&audma1 0x76>;
2039 dma-names = "rx", "tx";
2040 };
2041 ssiu70: ssiu-42 {
2042 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2043 dma-names = "rx", "tx";
2044 };
2045 ssiu80: ssiu-43 {
2046 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2047 dma-names = "rx", "tx";
2048 };
2049 ssiu90: ssiu-44 {
2050 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2051 dma-names = "rx", "tx";
2052 };
2053 ssiu91: ssiu-45 {
2054 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2055 dma-names = "rx", "tx";
2056 };
2057 ssiu92: ssiu-46 {
2058 dmas = <&audma0 0x81>, <&audma1 0x82>;
2059 dma-names = "rx", "tx";
2060 };
2061 ssiu93: ssiu-47 {
2062 dmas = <&audma0 0x83>, <&audma1 0x84>;
2063 dma-names = "rx", "tx";
2064 };
2065 ssiu94: ssiu-48 {
2066 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2067 dma-names = "rx", "tx";
2068 };
2069 ssiu95: ssiu-49 {
2070 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2071 dma-names = "rx", "tx";
2072 };
2073 ssiu96: ssiu-50 {
2074 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2075 dma-names = "rx", "tx";
2076 };
2077 ssiu97: ssiu-51 {
2078 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2079 dma-names = "rx", "tx";
2080 };
2081 };
e2f04248
BD		 2082 };
2083
2084 audma0: dma-controller@ec700000 {
2085 compatible = "renesas,dmac-r8a774a1",
2086 "renesas,rcar-dmac";
2087 reg = <0 0xec700000 0 0x10000>;
0aab5b91
GU		 2088 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2094 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2095 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2099 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2100 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2101 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2102 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2103 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2104 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
e2f04248
BD		 2105 interrupt-names = "error",
2106 "ch0", "ch1", "ch2", "ch3",
2107 "ch4", "ch5", "ch6", "ch7",
2108 "ch8", "ch9", "ch10", "ch11",
2109 "ch12", "ch13", "ch14", "ch15";
2110 clocks = <&cpg CPG_MOD 502>;
2111 clock-names = "fck";
aeee3d9c 2112 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
e2f04248
BD		 2113 resets = <&cpg 502>;
2114 #dma-cells = <1>;
2115 dma-channels = <16>;
01712eaa
BD		 2116 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2117 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2118 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2119 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2120 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2121 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2122 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2123 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
e2f04248
BD		 2124 };
2125
2126 audma1: dma-controller@ec720000 {
2127 compatible = "renesas,dmac-r8a774a1",
2128 "renesas,rcar-dmac";
2129 reg = <0 0xec720000 0 0x10000>;
0aab5b91
GU		 2130 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2131 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2132 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2133 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2134 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2135 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2136 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2137 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2138 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2139 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2140 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2141 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2142 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2143 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2144 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2145 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
e2f04248
BD		 2147 interrupt-names = "error",
2148 "ch0", "ch1", "ch2", "ch3",
2149 "ch4", "ch5", "ch6", "ch7",
2150 "ch8", "ch9", "ch10", "ch11",
2151 "ch12", "ch13", "ch14", "ch15";
2152 clocks = <&cpg CPG_MOD 501>;
2153 clock-names = "fck";
aeee3d9c 2154 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
e2f04248
BD		 2155 resets = <&cpg 501>;
2156 #dma-cells = <1>;
2157 dma-channels = <16>;
01712eaa
BD		 2158 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2159 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2160 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2161 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2162 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2163 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2164 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2165 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
e2f04248
BD		 2166 };
2167
453240f6
BD		 2168 xhci0: usb@ee000000 {
2169 compatible = "renesas,xhci-r8a774a1",
2170 "renesas,rcar-gen3-xhci";
2171 reg = <0 0xee000000 0 0xc00>;
2172 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2173 clocks = <&cpg CPG_MOD 328>;
aeee3d9c 2174 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
453240f6
BD		 2175 resets = <&cpg 328>;
2176 status = "disabled";
2177 };
2178
2179 usb3_peri0: usb@ee020000 {
2180 compatible = "renesas,r8a774a1-usb3-peri",
2181 "renesas,rcar-gen3-usb3-peri";
2182 reg = <0 0xee020000 0 0x400>;
2183 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2184 clocks = <&cpg CPG_MOD 328>;
aeee3d9c 2185 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
453240f6
BD		 2186 resets = <&cpg 328>;
2187 status = "disabled";
2188 };
2189
4c2c2fb9
BD		 2190 ohci0: usb@ee080000 {
2191 compatible = "generic-ohci";
2192 reg = <0 0xee080000 0 0x100>;
2193 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
a573cb67 2194 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
7794bd7e 2195 phys = <&usb2_phy0 1>;
4c2c2fb9 2196 phy-names = "usb";
aeee3d9c 2197 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
a573cb67 2198 resets = <&cpg 703>, <&cpg 704>;
4c2c2fb9
BD		 2199 status = "disabled";
2200 };
2201
2202 ohci1: usb@ee0a0000 {
2203 compatible = "generic-ohci";
2204 reg = <0 0xee0a0000 0 0x100>;
2205 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2206 clocks = <&cpg CPG_MOD 702>;
7794bd7e 2207 phys = <&usb2_phy1 1>;
4c2c2fb9 2208 phy-names = "usb";
aeee3d9c 2209 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
4c2c2fb9
BD		 2210 resets = <&cpg 702>;
2211 status = "disabled";
2212 };
2213
2214 ehci0: usb@ee080100 {
2215 compatible = "generic-ehci";
2216 reg = <0 0xee080100 0 0x100>;
2217 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
a573cb67 2218 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
7794bd7e 2219 phys = <&usb2_phy0 2>;
4c2c2fb9 2220 phy-names = "usb";
fced3a97 2221 companion = <&ohci0>;
aeee3d9c 2222 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
a573cb67 2223 resets = <&cpg 703>, <&cpg 704>;
4c2c2fb9
BD		 2224 status = "disabled";
2225 };
2226
2227 ehci1: usb@ee0a0100 {
2228 compatible = "generic-ehci";
2229 reg = <0 0xee0a0100 0 0x100>;
2230 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2231 clocks = <&cpg CPG_MOD 702>;
7794bd7e 2232 phys = <&usb2_phy1 2>;
4c2c2fb9 2233 phy-names = "usb";
fced3a97 2234 companion = <&ohci1>;
aeee3d9c 2235 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
4c2c2fb9
BD		 2236 resets = <&cpg 702>;
2237 status = "disabled";
2238 };
2239
2240 usb2_phy0: usb-phy@ee080200 {
2241 compatible = "renesas,usb2-phy-r8a774a1",
2242 "renesas,rcar-gen3-usb2-phy";
2243 reg = <0 0xee080200 0 0x700>;
2244 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
a573cb67 2245 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
aeee3d9c 2246 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
a573cb67 2247 resets = <&cpg 703>, <&cpg 704>;
7794bd7e 2248 #phy-cells = <1>;
4c2c2fb9
BD		 2249 status = "disabled";
2250 };
2251
2252 usb2_phy1: usb-phy@ee0a0200 {
2253 compatible = "renesas,usb2-phy-r8a774a1",
2254 "renesas,rcar-gen3-usb2-phy";
2255 reg = <0 0xee0a0200 0 0x700>;
2256 clocks = <&cpg CPG_MOD 702>;
aeee3d9c 2257 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
4c2c2fb9 2258 resets = <&cpg 702>;
7794bd7e 2259 #phy-cells = <1>;
4c2c2fb9
BD		 2260 status = "disabled";
2261 };
2262
a6cb262a 2263 sdhi0: mmc@ee100000 {
663386c3
FC		 2264 compatible = "renesas,sdhi-r8a774a1",
2265 "renesas,rcar-gen3-sdhi";
2266 reg = <0 0xee100000 0 0x2000>;
2267 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
52e844ee
WS		 2268 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
2269 clock-names = "core", "clkh";
663386c3 2270 max-frequency = <200000000>;
aeee3d9c 2271 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
663386c3
FC		 2272 resets = <&cpg 314>;
2273 status = "disabled";
2274 };
2275
a6cb262a 2276 sdhi1: mmc@ee120000 {
663386c3
FC		 2277 compatible = "renesas,sdhi-r8a774a1",
2278 "renesas,rcar-gen3-sdhi";
2279 reg = <0 0xee120000 0 0x2000>;
2280 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
52e844ee
WS		 2281 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
2282 clock-names = "core", "clkh";
663386c3 2283 max-frequency = <200000000>;
aeee3d9c 2284 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
663386c3
FC		 2285 resets = <&cpg 313>;
2286 status = "disabled";
2287 };
2288
a6cb262a 2289 sdhi2: mmc@ee140000 {
663386c3
FC		 2290 compatible = "renesas,sdhi-r8a774a1",
2291 "renesas,rcar-gen3-sdhi";
2292 reg = <0 0xee140000 0 0x2000>;
2293 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
52e844ee
WS		 2294 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
2295 clock-names = "core", "clkh";
663386c3 2296 max-frequency = <200000000>;
aeee3d9c 2297 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
663386c3
FC		 2298 resets = <&cpg 312>;
2299 status = "disabled";
2300 };
2301
a6cb262a 2302 sdhi3: mmc@ee160000 {
663386c3
FC		 2303 compatible = "renesas,sdhi-r8a774a1",
2304 "renesas,rcar-gen3-sdhi";
2305 reg = <0 0xee160000 0 0x2000>;
2306 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
52e844ee
WS		 2307 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
2308 clock-names = "core", "clkh";
663386c3 2309 max-frequency = <200000000>;
aeee3d9c 2310 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
663386c3
FC		 2311 resets = <&cpg 311>;
2312 status = "disabled";
2313 };
2314
8811955d
AF		 2315 rpc: spi@ee200000 {
2316 compatible = "renesas,r8a774a1-rpc-if",
2317 "renesas,rcar-gen3-rpc-if";
2318 reg = <0 0xee200000 0 0x200>,
2319 <0 0x08000000 0 0x4000000>,
2320 <0 0xee208000 0 0x100>;
2321 reg-names = "regs", "dirmap", "wbuf";
2322 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2323 clocks = <&cpg CPG_MOD 917>;
8811955d
AF		 2324 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2325 resets = <&cpg 917>;
2326 #address-cells = <1>;
2327 #size-cells = <0>;
2328 status = "disabled";
2329 };
2330
90493b09
BD		 2331 gic: interrupt-controller@f1010000 {
2332 compatible = "arm,gic-400";
2333 #interrupt-cells = <3>;
2334 #address-cells = <0>;
2335 interrupt-controller;
2336 reg = <0x0 0xf1010000 0 0x1000>,
2337 <0x0 0xf1020000 0 0x20000>,
2338 <0x0 0xf1040000 0 0x20000>,
2339 <0x0 0xf1060000 0 0x20000>;
2340 interrupts = <GIC_PPI 9
09f49bcf 2341 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
90493b09
BD		 2342 clocks = <&cpg CPG_MOD 408>;
2343 clock-names = "clk";
aeee3d9c 2344 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
90493b09
BD		 2345 resets = <&cpg 408>;
2346 };
2347
a5a41d50
BD		 2348 pciec0: pcie@fe000000 {
2349 compatible = "renesas,pcie-r8a774a1",
2350 "renesas,pcie-rcar-gen3";
2351 reg = <0 0xfe000000 0 0x80000>;
2352 #address-cells = <3>;
2353 #size-cells = <2>;
2354 bus-range = <0x00 0xff>;
2355 device_type = "pci";
9504a9f2
GU		 2356 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2357 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2358 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2359 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
86d904b6
YS		 2360 /* Map all possible DDR/IOMMU as inbound ranges */
2361 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
a5a41d50
BD		 2362 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2363 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2364 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2365 #interrupt-cells = <1>;
2366 interrupt-map-mask = <0 0 0 0>;
2367 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2368 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2369 clock-names = "pcie", "pcie_bus";
2370 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2371 resets = <&cpg 319>;
86d904b6
YS		 2372 iommu-map = <0 &ipmmu_hc 0 1>;
2373 iommu-map-mask = <0>;
a5a41d50
BD		 2374 status = "disabled";
2375 };
2376
2377 pciec1: pcie@ee800000 {
2378 compatible = "renesas,pcie-r8a774a1",
2379 "renesas,pcie-rcar-gen3";
2380 reg = <0 0xee800000 0 0x80000>;
2381 #address-cells = <3>;
2382 #size-cells = <2>;
2383 bus-range = <0x00 0xff>;
2384 device_type = "pci";
9504a9f2
GU		 2385 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2386 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2387 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2388 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
86d904b6
YS		 2389 /* Map all possible DDR/IOMMU as inbound ranges */
2390 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
a5a41d50
BD		 2391 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2392 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2394 #interrupt-cells = <1>;
2395 interrupt-map-mask = <0 0 0 0>;
2396 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2397 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2398 clock-names = "pcie", "pcie_bus";
2399 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2400 resets = <&cpg 318>;
86d904b6
YS		 2401 iommu-map = <0 &ipmmu_hc 1 1>;
2402 iommu-map-mask = <0>;
a5a41d50
BD		 2403 status = "disabled";
2404 };
2405
57845088
LP		 2406 pciec0_ep: pcie-ep@fe000000 {
2407 compatible = "renesas,r8a774a1-pcie-ep",
2408 "renesas,rcar-gen3-pcie-ep";
2409 reg = <0x0 0xfe000000 0 0x80000>,
2410 <0x0 0xfe100000 0 0x100000>,
2411 <0x0 0xfe200000 0 0x200000>,
2412 <0x0 0x30000000 0 0x8000000>,
2413 <0x0 0x38000000 0 0x8000000>;
2414 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2415 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2416 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2417 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2418 clocks = <&cpg CPG_MOD 319>;
2419 clock-names = "pcie";
2420 resets = <&cpg 319>;
2421 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2422 status = "disabled";
2423 };
2424
2425 pciec1_ep: pcie-ep@ee800000 {
2426 compatible = "renesas,r8a774a1-pcie-ep",
2427 "renesas,rcar-gen3-pcie-ep";
2428 reg = <0x0 0xee800000 0 0x80000>,
2429 <0x0 0xee900000 0 0x100000>,
2430 <0x0 0xeea00000 0 0x200000>,
2431 <0x0 0xc0000000 0 0x8000000>,
2432 <0x0 0xc8000000 0 0x8000000>;
2433 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2434 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2435 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2437 clocks = <&cpg CPG_MOD 318>;
2438 clock-names = "pcie";
2439 resets = <&cpg 318>;
2440 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2441 status = "disabled";
2442 };
2443
466f475f
BD		 2444 fdp1@fe940000 {
2445 compatible = "renesas,fdp1";
2446 reg = <0 0xfe940000 0 0x2400>;
2447 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2448 clocks = <&cpg CPG_MOD 119>;
2449 power-domains = <&sysc R8A774A1_PD_A3VC>;
2450 resets = <&cpg 119>;
2451 renesas,fcp = <&fcpf0>;
2452 };
2453
28241952
FC		 2454 fcpf0: fcp@fe950000 {
2455 compatible = "renesas,fcpf";
2456 reg = <0 0xfe950000 0 0x200>;
2457 clocks = <&cpg CPG_MOD 615>;
aeee3d9c 2458 power-domains = <&sysc R8A774A1_PD_A3VC>;
28241952
FC		 2459 resets = <&cpg 615>;
2460 };
2461
2462 fcpvb0: fcp@fe96f000 {
2463 compatible = "renesas,fcpv";
2464 reg = <0 0xfe96f000 0 0x200>;
2465 clocks = <&cpg CPG_MOD 607>;
aeee3d9c 2466 power-domains = <&sysc R8A774A1_PD_A3VC>;
28241952
FC		 2467 resets = <&cpg 607>;
2468 };
2469
2470 fcpvd0: fcp@fea27000 {
2471 compatible = "renesas,fcpv";
2472 reg = <0 0xfea27000 0 0x200>;
2473 clocks = <&cpg CPG_MOD 603>;
aeee3d9c 2474 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
28241952
FC		 2475 resets = <&cpg 603>;
2476 iommus = <&ipmmu_vi0 8>;
2477 };
2478
2479 fcpvd1: fcp@fea2f000 {
2480 compatible = "renesas,fcpv";
2481 reg = <0 0xfea2f000 0 0x200>;
2482 clocks = <&cpg CPG_MOD 602>;
aeee3d9c 2483 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
28241952
FC		 2484 resets = <&cpg 602>;
2485 iommus = <&ipmmu_vi0 9>;
2486 };
2487
2488 fcpvd2: fcp@fea37000 {
2489 compatible = "renesas,fcpv";
2490 reg = <0 0xfea37000 0 0x200>;
2491 clocks = <&cpg CPG_MOD 601>;
aeee3d9c 2492 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
28241952
FC		 2493 resets = <&cpg 601>;
2494 iommus = <&ipmmu_vi0 10>;
2495 };
2496
2497 fcpvi0: fcp@fe9af000 {
2498 compatible = "renesas,fcpv";
2499 reg = <0 0xfe9af000 0 0x200>;
2500 clocks = <&cpg CPG_MOD 611>;
aeee3d9c 2501 power-domains = <&sysc R8A774A1_PD_A3VC>;
28241952
FC		 2502 resets = <&cpg 611>;
2503 iommus = <&ipmmu_vc0 19>;
2504 };
2505
391dca21
BD		 2506 vspb: vsp@fe960000 {
2507 compatible = "renesas,vsp2";
2508 reg = <0 0xfe960000 0 0x8000>;
2509 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2510 clocks = <&cpg CPG_MOD 626>;
2511 power-domains = <&sysc R8A774A1_PD_A3VC>;
2512 resets = <&cpg 626>;
2513
2514 renesas,fcp = <&fcpvb0>;
2515 };
2516
2517 vspd0: vsp@fea20000 {
2518 compatible = "renesas,vsp2";
2519 reg = <0 0xfea20000 0 0x5000>;
2520 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2521 clocks = <&cpg CPG_MOD 623>;
2522 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2523 resets = <&cpg 623>;
2524
2525 renesas,fcp = <&fcpvd0>;
2526 };
2527
2528 vspd1: vsp@fea28000 {
2529 compatible = "renesas,vsp2";
2530 reg = <0 0xfea28000 0 0x5000>;
2531 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2532 clocks = <&cpg CPG_MOD 622>;
2533 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2534 resets = <&cpg 622>;
2535
2536 renesas,fcp = <&fcpvd1>;
2537 };
2538
2539 vspd2: vsp@fea30000 {
2540 compatible = "renesas,vsp2";
2541 reg = <0 0xfea30000 0 0x5000>;
2542 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2543 clocks = <&cpg CPG_MOD 621>;
2544 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2545 resets = <&cpg 621>;
2546
2547 renesas,fcp = <&fcpvd2>;
2548 };
2549
2550 vspi0: vsp@fe9a0000 {
2551 compatible = "renesas,vsp2";
2552 reg = <0 0xfe9a0000 0 0x8000>;
2553 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2554 clocks = <&cpg CPG_MOD 631>;
2555 power-domains = <&sysc R8A774A1_PD_A3VC>;
2556 resets = <&cpg 631>;
2557
2558 renesas,fcp = <&fcpvi0>;
2559 };
2560
0c85e78f
BD		 2561 csi20: csi2@fea80000 {
2562 compatible = "renesas,r8a774a1-csi2";
2563 reg = <0 0xfea80000 0 0x10000>;
2564 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2565 clocks = <&cpg CPG_MOD 714>;
aeee3d9c 2566 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 2567 resets = <&cpg 714>;
2568 status = "disabled";
2569
2570 ports {
2571 #address-cells = <1>;
2572 #size-cells = <0>;
2573
0a96c059
NS		 2574 port@0 {
2575 reg = <0>;
2576 };
2577
0c85e78f
BD		 2578 port@1 {
2579 #address-cells = <1>;
2580 #size-cells = <0>;
2581
2582 reg = <1>;
2583
2584 csi20vin0: endpoint@0 {
2585 reg = <0>;
2586 remote-endpoint = <&vin0csi20>;
2587 };
2588 csi20vin1: endpoint@1 {
2589 reg = <1>;
2590 remote-endpoint = <&vin1csi20>;
2591 };
2592 csi20vin2: endpoint@2 {
2593 reg = <2>;
2594 remote-endpoint = <&vin2csi20>;
2595 };
2596 csi20vin3: endpoint@3 {
2597 reg = <3>;
2598 remote-endpoint = <&vin3csi20>;
2599 };
2600 csi20vin4: endpoint@4 {
2601 reg = <4>;
2602 remote-endpoint = <&vin4csi20>;
2603 };
2604 csi20vin5: endpoint@5 {
2605 reg = <5>;
2606 remote-endpoint = <&vin5csi20>;
2607 };
2608 csi20vin6: endpoint@6 {
2609 reg = <6>;
2610 remote-endpoint = <&vin6csi20>;
2611 };
2612 csi20vin7: endpoint@7 {
2613 reg = <7>;
2614 remote-endpoint = <&vin7csi20>;
2615 };
2616 };
2617 };
2618 };
2619
2620 csi40: csi2@feaa0000 {
2621 compatible = "renesas,r8a774a1-csi2";
2622 reg = <0 0xfeaa0000 0 0x10000>;
2623 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2624 clocks = <&cpg CPG_MOD 716>;
aeee3d9c 2625 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0c85e78f
BD		 2626 resets = <&cpg 716>;
2627 status = "disabled";
2628
2629 ports {
2630 #address-cells = <1>;
2631 #size-cells = <0>;
2632
0a96c059
NS		 2633 port@0 {
2634 reg = <0>;
2635 };
2636
0c85e78f
BD		 2637 port@1 {
2638 #address-cells = <1>;
2639 #size-cells = <0>;
2640
2641 reg = <1>;
2642
2643 csi40vin0: endpoint@0 {
2644 reg = <0>;
2645 remote-endpoint = <&vin0csi40>;
2646 };
2647 csi40vin1: endpoint@1 {
2648 reg = <1>;
2649 remote-endpoint = <&vin1csi40>;
2650 };
2651 csi40vin2: endpoint@2 {
2652 reg = <2>;
2653 remote-endpoint = <&vin2csi40>;
2654 };
2655 csi40vin3: endpoint@3 {
2656 reg = <3>;
2657 remote-endpoint = <&vin3csi40>;
2658 };
2659 csi40vin4: endpoint@4 {
2660 reg = <4>;
2661 remote-endpoint = <&vin4csi40>;
2662 };
2663 csi40vin5: endpoint@5 {
2664 reg = <5>;
2665 remote-endpoint = <&vin5csi40>;
2666 };
2667 csi40vin6: endpoint@6 {
2668 reg = <6>;
2669 remote-endpoint = <&vin6csi40>;
2670 };
2671 csi40vin7: endpoint@7 {
2672 reg = <7>;
2673 remote-endpoint = <&vin7csi40>;
2674 };
2675 };
2676
2677 };
2678 };
2679
8c965642
FC		 2680 hdmi0: hdmi@fead0000 {
2681 compatible = "renesas,r8a774a1-hdmi",
2682 "renesas,rcar-gen3-hdmi";
2683 reg = <0 0xfead0000 0 0x10000>;
2684 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2685 clocks = <&cpg CPG_MOD 729>,
2686 <&cpg CPG_CORE R8A774A1_CLK_HDMI>;
2687 clock-names = "iahb", "isfr";
2688 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2689 resets = <&cpg 729>;
2690 status = "disabled";
2691
2692 ports {
2693 #address-cells = <1>;
2694 #size-cells = <0>;
2695 port@0 {
2696 reg = <0>;
2697 dw_hdmi0_in: endpoint {
2698 remote-endpoint = <&du_out_hdmi0>;
2699 };
2700 };
2701 port@1 {
2702 reg = <1>;
2703 };
2704 port@2 {
2705 /* HDMI sound */
2706 reg = <2>;
2707 };
2708 };
2709 };
2710
c4f223b4
BD		 2711 du: display@feb00000 {
2712 compatible = "renesas,du-r8a774a1";
2713 reg = <0 0xfeb00000 0 0x70000>;
2714 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2715 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2716 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
721b7619 2717 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
c4f223b4
BD		 2718 <&cpg CPG_MOD 722>;
2719 clock-names = "du.0", "du.1", "du.2";
721b7619
GU		 2720 resets = <&cpg 724>, <&cpg 722>;
2721 reset-names = "du.0", "du.2";
c4f223b4
BD		 2722 status = "disabled";
2723
03abfdd3 2724 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
c4f223b4
BD		 2725
2726 ports {
2727 #address-cells = <1>;
2728 #size-cells = <0>;
2729
2730 port@0 {
2731 reg = <0>;
c4f223b4
BD		 2732 };
2733 port@1 {
2734 reg = <1>;
2735 du_out_hdmi0: endpoint {
8c965642 2736 remote-endpoint = <&dw_hdmi0_in>;
c4f223b4
BD		 2737 };
2738 };
2739 port@2 {
2740 reg = <2>;
2741 du_out_lvds0: endpoint {
2742 remote-endpoint = <&lvds0_in>;
2743 };
2744 };
2745 };
2746 };
2747
2748 lvds0: lvds@feb90000 {
2749 compatible = "renesas,r8a774a1-lvds";
2750 reg = <0 0xfeb90000 0 0x14>;
2751 clocks = <&cpg CPG_MOD 727>;
2752 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2753 resets = <&cpg 727>;
2754 status = "disabled";
2755
2756 ports {
2757 #address-cells = <1>;
2758 #size-cells = <0>;
2759
2760 port@0 {
2761 reg = <0>;
2762 lvds0_in: endpoint {
2763 remote-endpoint = <&du_out_lvds0>;
2764 };
2765 };
2766 port@1 {
2767 reg = <1>;
c4f223b4
BD		 2768 };
2769 };
2770 };
2771
90493b09
BD		 2772 prr: chipid@fff00044 {
2773 compatible = "renesas,prr";
2774 reg = <0 0xfff00044 0 4>;
2775 };
2776 };
2777
a4165904 2778 thermal-zones {
82ce7939 2779 sensor1_thermal: sensor1-thermal {
a4165904
BD		 2780 polling-delay-passive = <250>;
2781 polling-delay = <1000>;
2782 thermal-sensors = <&tsc 0>;
06a928fb 2783 sustainable-power = <3874>;
a4165904
BD		 2784
2785 trips {
2786 sensor1_crit: sensor1-crit {
2787 temperature = <120000>;
2788 hysteresis = <1000>;
2789 type = "critical";
2790 };
2791 };
2792 };
2793
82ce7939 2794 sensor2_thermal: sensor2-thermal {
a4165904
BD		 2795 polling-delay-passive = <250>;
2796 polling-delay = <1000>;
2797 thermal-sensors = <&tsc 1>;
06a928fb 2798 sustainable-power = <3874>;
a4165904
BD		 2799
2800 trips {
2801 sensor2_crit: sensor2-crit {
2802 temperature = <120000>;
2803 hysteresis = <1000>;
2804 type = "critical";
2805 };
2806 };
a4165904
BD		 2807 };
2808
82ce7939 2809 sensor3_thermal: sensor3-thermal {
a4165904
BD		 2810 polling-delay-passive = <250>;
2811 polling-delay = <1000>;
2812 thermal-sensors = <&tsc 2>;
06a928fb 2813 sustainable-power = <3874>;
a4165904 2814
fadbdd06
YK		 2815 cooling-maps {
2816 map0 {
2817 trip = <&target>;
2818 cooling-device = <&a57_0 0 2>;
2819 contribution = <1024>;
2820 };
2821 map1 {
2822 trip = <&target>;
2823 cooling-device = <&a53_0 0 2>;
2824 contribution = <1024>;
2825 };
2826 };
a4165904 2827 trips {
06a928fb
BD		 2828 target: trip-point1 {
2829 temperature = <100000>;
2830 hysteresis = <1000>;
2831 type = "passive";
2832 };
2833
a4165904
BD		 2834 sensor3_crit: sensor3-crit {
2835 temperature = <120000>;
2836 hysteresis = <1000>;
2837 type = "critical";
2838 };
2839 };
2840 };
2841 };
2842
90493b09
BD		 2843 timer {
2844 compatible = "arm,armv8-timer";
09f49bcf
BD		 2845 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2846 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2847 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2848 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
90493b09
BD		 2849 };
2850
2851 /* External USB clocks - can be overridden by the board */
2852 usb3s0_clk: usb3s0 {
2853 compatible = "fixed-clock";
2854 #clock-cells = <0>;
2855 clock-frequency = <0>;
2856 };
2857
2858 usb_extal_clk: usb_extal {
2859 compatible = "fixed-clock";
2860 #clock-cells = <0>;
2861 clock-frequency = <0>;
2862 };
2863};
Linux 6.x block layer and io_uring tree(s)