Commit | Line | Data |
---|---|---|
438419eb BD |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Device Tree Source for the HiHope RZ/G2[MN] main board common parts | |
4 | * | |
5 | * Copyright (C) 2019 Renesas Electronics Corp. | |
6 | */ | |
7 | ||
7433f1fb BD |
8 | #include <dt-bindings/gpio/gpio.h> |
9 | ||
438419eb BD |
10 | / { |
11 | aliases { | |
12 | serial0 = &scif2; | |
13 | }; | |
14 | ||
15 | chosen { | |
16 | bootargs = "ignore_loglevel"; | |
17 | stdout-path = "serial0:115200n8"; | |
18 | }; | |
19 | }; | |
20 | ||
21 | &extal_clk { | |
22 | clock-frequency = <16666666>; | |
23 | }; | |
24 | ||
25 | &extalr_clk { | |
26 | clock-frequency = <32768>; | |
27 | }; | |
28 | ||
61e0505b BD |
29 | &pcie_bus_clk { |
30 | clock-frequency = <100000000>; | |
31 | }; | |
32 | ||
871c13a4 BD |
33 | &pfc { |
34 | pinctrl-0 = <&scif_clk_pins>; | |
35 | pinctrl-names = "default"; | |
36 | ||
37 | scif2_pins: scif2 { | |
38 | groups = "scif2_data_a"; | |
39 | function = "scif2"; | |
40 | }; | |
41 | ||
42 | scif_clk_pins: scif_clk { | |
43 | groups = "scif_clk_a"; | |
44 | function = "scif_clk"; | |
45 | }; | |
46 | }; | |
47 | ||
736a291d BD |
48 | &rwdt { |
49 | timeout-sec = <60>; | |
50 | status = "okay"; | |
51 | }; | |
52 | ||
438419eb | 53 | &scif2 { |
871c13a4 BD |
54 | pinctrl-0 = <&scif2_pins>; |
55 | pinctrl-names = "default"; | |
56 | ||
438419eb BD |
57 | status = "okay"; |
58 | }; | |
59 | ||
60 | &scif_clk { | |
61 | clock-frequency = <14745600>; | |
62 | }; |