projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 5188049c VK |
1 | // SPDX-License-Identifier: BSD-3-Clause |
| 2 | /* | |
| 3 | * Copyright (c) 2021, Linaro Limited | |
| 4 | */ | |
| 5 | ||
| 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 7 | #include <dt-bindings/clock/qcom,gcc-sm8450.h> | |
| 8 | #include <dt-bindings/clock/qcom,rpmh.h> | |
| b9c84330 | 9 | #include <dt-bindings/dma/qcom-gpi.h> |
| 5188049c | 10 | #include <dt-bindings/gpio/gpio.h> |
| 11727295 | 11 | #include <dt-bindings/mailbox/qcom-ipcc.h> |
| 61eba74e | 12 | #include <dt-bindings/power/qcom-rpmpd.h> |
| aa2d0bf0 | 13 | #include <dt-bindings/interconnect/qcom,sm8450.h> |
| 5188049c | 14 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| fccf8e31 | 15 | #include <dt-bindings/thermal/thermal.h> |
| 5188049c VK |
16 | |
| 17 | / { | |
| 18 | interrupt-parent = <&intc>; | |
| 19 | ||
| 20 | #address-cells = <2>; | |
| 21 | #size-cells = <2>; | |
| 22 | ||
| 23 | chosen { }; | |
| 24 | ||
| 25 | clocks { | |
| 26 | xo_board: xo-board { | |
| 27 | compatible = "fixed-clock"; | |
| 28 | #clock-cells = <0>; | |
| 29 | clock-frequency = <76800000>; | |
| 30 | }; | |
| 31 | ||
| 32 | sleep_clk: sleep-clk { | |
| 33 | compatible = "fixed-clock"; | |
| 34 | #clock-cells = <0>; | |
| 35 | clock-frequency = <32000>; | |
| 36 | }; | |
| 37 | }; | |
| 38 | ||
| 39 | cpus { | |
| 40 | #address-cells = <2>; | |
| 41 | #size-cells = <0>; | |
| 42 | ||
| 43 | CPU0: cpu@0 { | |
| 44 | device_type = "cpu"; | |
| 45 | compatible = "qcom,kryo780"; | |
| 46 | reg = <0x0 0x0>; | |
| 47 | enable-method = "psci"; | |
| 48 | next-level-cache = <&L2_0>; | |
| 49 | power-domains = <&CPU_PD0>; | |
| 50 | power-domain-names = "psci"; | |
| 015a89f0 | 51 | qcom,freq-domain = <&cpufreq_hw 0>; |
| fccf8e31 | 52 | #cooling-cells = <2>; |
| 5188049c VK |
53 | L2_0: l2-cache { |
| 54 | compatible = "cache"; | |
| 55 | next-level-cache = <&L3_0>; | |
| 56 | L3_0: l3-cache { | |
| 57 | compatible = "cache"; | |
| 58 | }; | |
| 59 | }; | |
| 60 | }; | |
| 61 | ||
| 62 | CPU1: cpu@100 { | |
| 63 | device_type = "cpu"; | |
| 64 | compatible = "qcom,kryo780"; | |
| 65 | reg = <0x0 0x100>; | |
| 66 | enable-method = "psci"; | |
| 67 | next-level-cache = <&L2_100>; | |
| 68 | power-domains = <&CPU_PD1>; | |
| 69 | power-domain-names = "psci"; | |
| 015a89f0 | 70 | qcom,freq-domain = <&cpufreq_hw 0>; |
| fccf8e31 | 71 | #cooling-cells = <2>; |
| 5188049c VK |
72 | L2_100: l2-cache { |
| 73 | compatible = "cache"; | |
| 74 | next-level-cache = <&L3_0>; | |
| 75 | }; | |
| 76 | }; | |
| 77 | ||
| 78 | CPU2: cpu@200 { | |
| 79 | device_type = "cpu"; | |
| 80 | compatible = "qcom,kryo780"; | |
| 81 | reg = <0x0 0x200>; | |
| 82 | enable-method = "psci"; | |
| 83 | next-level-cache = <&L2_200>; | |
| 84 | power-domains = <&CPU_PD2>; | |
| 85 | power-domain-names = "psci"; | |
| 015a89f0 | 86 | qcom,freq-domain = <&cpufreq_hw 0>; |
| fccf8e31 | 87 | #cooling-cells = <2>; |
| 5188049c VK |
88 | L2_200: l2-cache { |
| 89 | compatible = "cache"; | |
| 90 | next-level-cache = <&L3_0>; | |
| 91 | }; | |
| 92 | }; | |
| 93 | ||
| 94 | CPU3: cpu@300 { | |
| 95 | device_type = "cpu"; | |
| 96 | compatible = "qcom,kryo780"; | |
| 97 | reg = <0x0 0x300>; | |
| 98 | enable-method = "psci"; | |
| 99 | next-level-cache = <&L2_300>; | |
| 100 | power-domains = <&CPU_PD3>; | |
| 101 | power-domain-names = "psci"; | |
| 015a89f0 | 102 | qcom,freq-domain = <&cpufreq_hw 0>; |
| fccf8e31 | 103 | #cooling-cells = <2>; |
| 5188049c VK |
104 | L2_300: l2-cache { |
| 105 | compatible = "cache"; | |
| 106 | next-level-cache = <&L3_0>; | |
| 107 | }; | |
| 108 | }; | |
| 109 | ||
| 110 | CPU4: cpu@400 { | |
| 111 | device_type = "cpu"; | |
| 112 | compatible = "qcom,kryo780"; | |
| 113 | reg = <0x0 0x400>; | |
| 114 | enable-method = "psci"; | |
| 115 | next-level-cache = <&L2_400>; | |
| 116 | power-domains = <&CPU_PD4>; | |
| 117 | power-domain-names = "psci"; | |
| 015a89f0 | 118 | qcom,freq-domain = <&cpufreq_hw 1>; |
| fccf8e31 | 119 | #cooling-cells = <2>; |
| 5188049c VK |
120 | L2_400: l2-cache { |
| 121 | compatible = "cache"; | |
| 122 | next-level-cache = <&L3_0>; | |
| 123 | }; | |
| 124 | }; | |
| 125 | ||
| 126 | CPU5: cpu@500 { | |
| 127 | device_type = "cpu"; | |
| 128 | compatible = "qcom,kryo780"; | |
| 129 | reg = <0x0 0x500>; | |
| 130 | enable-method = "psci"; | |
| 131 | next-level-cache = <&L2_500>; | |
| 132 | power-domains = <&CPU_PD5>; | |
| 133 | power-domain-names = "psci"; | |
| 015a89f0 | 134 | qcom,freq-domain = <&cpufreq_hw 1>; |
| fccf8e31 | 135 | #cooling-cells = <2>; |
| 5188049c VK |
136 | L2_500: l2-cache { |
| 137 | compatible = "cache"; | |
| 138 | next-level-cache = <&L3_0>; | |
| 139 | }; | |
| 140 | ||
| 141 | }; | |
| 142 | ||
| 143 | CPU6: cpu@600 { | |
| 144 | device_type = "cpu"; | |
| 145 | compatible = "qcom,kryo780"; | |
| 146 | reg = <0x0 0x600>; | |
| 147 | enable-method = "psci"; | |
| 148 | next-level-cache = <&L2_600>; | |
| 149 | power-domains = <&CPU_PD6>; | |
| 150 | power-domain-names = "psci"; | |
| 015a89f0 | 151 | qcom,freq-domain = <&cpufreq_hw 1>; |
| fccf8e31 | 152 | #cooling-cells = <2>; |
| 5188049c VK |
153 | L2_600: l2-cache { |
| 154 | compatible = "cache"; | |
| 155 | next-level-cache = <&L3_0>; | |
| 156 | }; | |
| 157 | }; | |
| 158 | ||
| 159 | CPU7: cpu@700 { | |
| 160 | device_type = "cpu"; | |
| 161 | compatible = "qcom,kryo780"; | |
| 162 | reg = <0x0 0x700>; | |
| 163 | enable-method = "psci"; | |
| 164 | next-level-cache = <&L2_700>; | |
| 165 | power-domains = <&CPU_PD7>; | |
| 166 | power-domain-names = "psci"; | |
| 015a89f0 | 167 | qcom,freq-domain = <&cpufreq_hw 2>; |
| fccf8e31 | 168 | #cooling-cells = <2>; |
| 5188049c VK |
169 | L2_700: l2-cache { |
| 170 | compatible = "cache"; | |
| 171 | next-level-cache = <&L3_0>; | |
| 172 | }; | |
| 173 | }; | |
| 174 | ||
| 175 | cpu-map { | |
| 176 | cluster0 { | |
| 177 | core0 { | |
| 178 | cpu = <&CPU0>; | |
| 179 | }; | |
| 180 | ||
| 181 | core1 { | |
| 182 | cpu = <&CPU1>; | |
| 183 | }; | |
| 184 | ||
| 185 | core2 { | |
| 186 | cpu = <&CPU2>; | |
| 187 | }; | |
| 188 | ||
| 189 | core3 { | |
| 190 | cpu = <&CPU3>; | |
| 191 | }; | |
| 192 | ||
| 193 | core4 { | |
| 194 | cpu = <&CPU4>; | |
| 195 | }; | |
| 196 | ||
| 197 | core5 { | |
| 198 | cpu = <&CPU5>; | |
| 199 | }; | |
| 200 | ||
| 201 | core6 { | |
| 202 | cpu = <&CPU6>; | |
| 203 | }; | |
| 204 | ||
| 205 | core7 { | |
| 206 | cpu = <&CPU7>; | |
| 207 | }; | |
| 208 | }; | |
| 209 | }; | |
| 210 | ||
| 211 | idle-states { | |
| 212 | entry-method = "psci"; | |
| 213 | ||
| 214 | LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { | |
| 215 | compatible = "arm,idle-state"; | |
| 216 | idle-state-name = "silver-rail-power-collapse"; | |
| 217 | arm,psci-suspend-param = <0x40000004>; | |
| 6574702b MS |
218 | entry-latency-us = <800>; |
| 219 | exit-latency-us = <750>; | |
| 220 | min-residency-us = <4090>; | |
| 5188049c VK |
221 | local-timer-stop; |
| 222 | }; | |
| 223 | ||
| 224 | BIG_CPU_SLEEP_0: cpu-sleep-1-0 { | |
| 225 | compatible = "arm,idle-state"; | |
| 226 | idle-state-name = "gold-rail-power-collapse"; | |
| 227 | arm,psci-suspend-param = <0x40000004>; | |
| 6574702b MS |
228 | entry-latency-us = <600>; |
| 229 | exit-latency-us = <1550>; | |
| 230 | min-residency-us = <4791>; | |
| 5188049c VK |
231 | local-timer-stop; |
| 232 | }; | |
| 233 | }; | |
| 234 | ||
| 235 | domain-idle-states { | |
| 236 | CLUSTER_SLEEP_0: cluster-sleep-0 { | |
| 237 | compatible = "domain-idle-state"; | |
| 238 | idle-state-name = "cluster-l3-off"; | |
| 6574702b MS |
239 | arm,psci-suspend-param = <0x41000044>; |
| 240 | entry-latency-us = <1050>; | |
| 241 | exit-latency-us = <2500>; | |
| 242 | min-residency-us = <5309>; | |
| 5188049c VK |
243 | local-timer-stop; |
| 244 | }; | |
| 245 | ||
| 246 | CLUSTER_SLEEP_1: cluster-sleep-1 { | |
| 247 | compatible = "domain-idle-state"; | |
| 248 | idle-state-name = "cluster-power-collapse"; | |
| 249 | arm,psci-suspend-param = <0x4100c344>; | |
| 6574702b MS |
250 | entry-latency-us = <2700>; |
| 251 | exit-latency-us = <3500>; | |
| 252 | min-residency-us = <13959>; | |
| 5188049c VK |
253 | local-timer-stop; |
| 254 | }; | |
| 255 | }; | |
| 256 | }; | |
| 257 | ||
| 258 | firmware { | |
| 259 | scm: scm { | |
| 260 | compatible = "qcom,scm-sm8450", "qcom,scm"; | |
| 261 | #reset-cells = <1>; | |
| 262 | }; | |
| 263 | }; | |
| 264 | ||
| aa2d0bf0 VK |
265 | clk_virt: interconnect@0 { |
| 266 | compatible = "qcom,sm8450-clk-virt"; | |
| 267 | #interconnect-cells = <2>; | |
| 268 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 269 | }; | |
| 270 | ||
| 271 | mc_virt: interconnect@1 { | |
| 272 | compatible = "qcom,sm8450-mc-virt"; | |
| 273 | #interconnect-cells = <2>; | |
| 274 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 275 | }; | |
| 276 | ||
| 5188049c VK |
277 | memory@a0000000 { |
| 278 | device_type = "memory"; | |
| 279 | /* We expect the bootloader to fill in the size */ | |
| 280 | reg = <0x0 0xa0000000 0x0 0x0>; | |
| 281 | }; | |
| 282 | ||
| 283 | pmu { | |
| 284 | compatible = "arm,armv8-pmuv3"; | |
| 285 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 286 | }; | |
| 287 | ||
| 288 | psci { | |
| 289 | compatible = "arm,psci-1.0"; | |
| 290 | method = "smc"; | |
| 291 | ||
| 292 | CPU_PD0: cpu0 { | |
| 293 | #power-domain-cells = <0>; | |
| 294 | power-domains = <&CLUSTER_PD>; | |
| 295 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
| 296 | }; | |
| 297 | ||
| 298 | CPU_PD1: cpu1 { | |
| 299 | #power-domain-cells = <0>; | |
| 300 | power-domains = <&CLUSTER_PD>; | |
| 301 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
| 302 | }; | |
| 303 | ||
| 304 | CPU_PD2: cpu2 { | |
| 305 | #power-domain-cells = <0>; | |
| 306 | power-domains = <&CLUSTER_PD>; | |
| 307 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
| 308 | }; | |
| 309 | ||
| 310 | CPU_PD3: cpu3 { | |
| 311 | #power-domain-cells = <0>; | |
| 312 | power-domains = <&CLUSTER_PD>; | |
| 313 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
| 314 | }; | |
| 315 | ||
| 316 | CPU_PD4: cpu4 { | |
| 317 | #power-domain-cells = <0>; | |
| 318 | power-domains = <&CLUSTER_PD>; | |
| 319 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
| 320 | }; | |
| 321 | ||
| 322 | CPU_PD5: cpu5 { | |
| 323 | #power-domain-cells = <0>; | |
| 324 | power-domains = <&CLUSTER_PD>; | |
| 325 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
| 326 | }; | |
| 327 | ||
| 328 | CPU_PD6: cpu6 { | |
| 329 | #power-domain-cells = <0>; | |
| 330 | power-domains = <&CLUSTER_PD>; | |
| 331 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
| 332 | }; | |
| 333 | ||
| 334 | CPU_PD7: cpu7 { | |
| 335 | #power-domain-cells = <0>; | |
| 336 | power-domains = <&CLUSTER_PD>; | |
| 337 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
| 338 | }; | |
| 339 | ||
| 340 | CLUSTER_PD: cpu-cluster0 { | |
| 341 | #power-domain-cells = <0>; | |
| 6574702b | 342 | domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; |
| 5188049c VK |
343 | }; |
| 344 | }; | |
| 345 | ||
| a84e88e9 VK |
346 | qup_opp_table_100mhz: qup-100mhz-opp-table { |
| 347 | compatible = "operating-points-v2"; | |
| 348 | ||
| 349 | opp-50000000 { | |
| 350 | opp-hz = /bits/ 64 <50000000>; | |
| 351 | required-opps = <&rpmhpd_opp_min_svs>; | |
| 352 | }; | |
| 353 | ||
| 354 | opp-75000000 { | |
| 355 | opp-hz = /bits/ 64 <75000000>; | |
| 356 | required-opps = <&rpmhpd_opp_low_svs>; | |
| 357 | }; | |
| 358 | ||
| 359 | opp-100000000 { | |
| 360 | opp-hz = /bits/ 64 <100000000>; | |
| 361 | required-opps = <&rpmhpd_opp_svs>; | |
| 362 | }; | |
| 363 | }; | |
| 364 | ||
| 285f97bc VK |
365 | reserved_memory: reserved-memory { |
| 366 | #address-cells = <2>; | |
| 367 | #size-cells = <2>; | |
| 368 | ranges; | |
| 369 | ||
| 370 | hyp_mem: memory@80000000 { | |
| 371 | reg = <0x0 0x80000000 0x0 0x600000>; | |
| 372 | no-map; | |
| 373 | }; | |
| 374 | ||
| 375 | xbl_dt_log_mem: memory@80600000 { | |
| 376 | reg = <0x0 0x80600000 0x0 0x40000>; | |
| 377 | no-map; | |
| 378 | }; | |
| 379 | ||
| 380 | xbl_ramdump_mem: memory@80640000 { | |
| 381 | reg = <0x0 0x80640000 0x0 0x180000>; | |
| 382 | no-map; | |
| 383 | }; | |
| 384 | ||
| 385 | xbl_sc_mem: memory@807c0000 { | |
| 386 | reg = <0x0 0x807c0000 0x0 0x40000>; | |
| 387 | no-map; | |
| 388 | }; | |
| 389 | ||
| 390 | aop_image_mem: memory@80800000 { | |
| 391 | reg = <0x0 0x80800000 0x0 0x60000>; | |
| 392 | no-map; | |
| 393 | }; | |
| 394 | ||
| 395 | aop_cmd_db_mem: memory@80860000 { | |
| 396 | compatible = "qcom,cmd-db"; | |
| 397 | reg = <0x0 0x80860000 0x0 0x20000>; | |
| 398 | no-map; | |
| 399 | }; | |
| 400 | ||
| 401 | aop_config_mem: memory@80880000 { | |
| 402 | reg = <0x0 0x80880000 0x0 0x20000>; | |
| 403 | no-map; | |
| 404 | }; | |
| 405 | ||
| 406 | tme_crash_dump_mem: memory@808a0000 { | |
| 407 | reg = <0x0 0x808a0000 0x0 0x40000>; | |
| 408 | no-map; | |
| 409 | }; | |
| 410 | ||
| 411 | tme_log_mem: memory@808e0000 { | |
| 412 | reg = <0x0 0x808e0000 0x0 0x4000>; | |
| 413 | no-map; | |
| 414 | }; | |
| 415 | ||
| 416 | uefi_log_mem: memory@808e4000 { | |
| 417 | reg = <0x0 0x808e4000 0x0 0x10000>; | |
| 418 | no-map; | |
| 419 | }; | |
| 420 | ||
| 421 | /* secdata region can be reused by apps */ | |
| 422 | smem: memory@80900000 { | |
| 423 | compatible = "qcom,smem"; | |
| 424 | reg = <0x0 0x80900000 0x0 0x200000>; | |
| 425 | hwlocks = <&tcsr_mutex 3>; | |
| 426 | no-map; | |
| 427 | }; | |
| 428 | ||
| 429 | cpucp_fw_mem: memory@80b00000 { | |
| 430 | reg = <0x0 0x80b00000 0x0 0x100000>; | |
| 431 | no-map; | |
| 432 | }; | |
| 433 | ||
| 434 | cdsp_secure_heap: memory@80c00000 { | |
| 435 | reg = <0x0 0x80c00000 0x0 0x4600000>; | |
| 436 | no-map; | |
| 437 | }; | |
| 438 | ||
| 439 | camera_mem: memory@85200000 { | |
| 440 | reg = <0x0 0x85200000 0x0 0x500000>; | |
| 441 | no-map; | |
| 442 | }; | |
| 443 | ||
| 444 | video_mem: memory@85700000 { | |
| 445 | reg = <0x0 0x85700000 0x0 0x700000>; | |
| 446 | no-map; | |
| 447 | }; | |
| 448 | ||
| 449 | adsp_mem: memory@85e00000 { | |
| 450 | reg = <0x0 0x85e00000 0x0 0x2100000>; | |
| 451 | no-map; | |
| 452 | }; | |
| 453 | ||
| 454 | slpi_mem: memory@88000000 { | |
| 455 | reg = <0x0 0x88000000 0x0 0x1900000>; | |
| 456 | no-map; | |
| 457 | }; | |
| 458 | ||
| 459 | cdsp_mem: memory@89900000 { | |
| 460 | reg = <0x0 0x89900000 0x0 0x2000000>; | |
| 461 | no-map; | |
| 462 | }; | |
| 463 | ||
| 464 | ipa_fw_mem: memory@8b900000 { | |
| 465 | reg = <0x0 0x8b900000 0x0 0x10000>; | |
| 466 | no-map; | |
| 467 | }; | |
| 468 | ||
| 469 | ipa_gsi_mem: memory@8b910000 { | |
| 470 | reg = <0x0 0x8b910000 0x0 0xa000>; | |
| 471 | no-map; | |
| 472 | }; | |
| 473 | ||
| 474 | gpu_micro_code_mem: memory@8b91a000 { | |
| 475 | reg = <0x0 0x8b91a000 0x0 0x2000>; | |
| 476 | no-map; | |
| 477 | }; | |
| 478 | ||
| 479 | spss_region_mem: memory@8ba00000 { | |
| 480 | reg = <0x0 0x8ba00000 0x0 0x180000>; | |
| 481 | no-map; | |
| 482 | }; | |
| 483 | ||
| 484 | /* First part of the "SPU secure shared memory" region */ | |
| 485 | spu_tz_shared_mem: memory@8bb80000 { | |
| 486 | reg = <0x0 0x8bb80000 0x0 0x60000>; | |
| 487 | no-map; | |
| 488 | }; | |
| 489 | ||
| 490 | /* Second part of the "SPU secure shared memory" region */ | |
| 491 | spu_modem_shared_mem: memory@8bbe0000 { | |
| 492 | reg = <0x0 0x8bbe0000 0x0 0x20000>; | |
| 493 | no-map; | |
| 494 | }; | |
| 495 | ||
| 496 | mpss_mem: memory@8bc00000 { | |
| 497 | reg = <0x0 0x8bc00000 0x0 0x13200000>; | |
| 498 | no-map; | |
| 499 | }; | |
| 500 | ||
| 501 | cvp_mem: memory@9ee00000 { | |
| 502 | reg = <0x0 0x9ee00000 0x0 0x700000>; | |
| 503 | no-map; | |
| 504 | }; | |
| 505 | ||
| 11727295 BA |
506 | rmtfs_mem: memory@9fd00000 { |
| 507 | compatible = "qcom,rmtfs-mem"; | |
| 508 | reg = <0x0 0x9fd00000 0x0 0x280000>; | |
| 509 | no-map; | |
| 510 | ||
| 511 | qcom,client-id = <1>; | |
| 512 | qcom,vmid = <15>; | |
| 513 | }; | |
| 514 | ||
| 285f97bc VK |
515 | global_sync_mem: memory@a6f00000 { |
| 516 | reg = <0x0 0xa6f00000 0x0 0x100000>; | |
| 517 | no-map; | |
| 518 | }; | |
| 519 | ||
| 520 | /* uefi region can be reused by APPS */ | |
| 521 | ||
| 522 | /* Linux kernel image is loaded at 0xa0000000 */ | |
| 523 | ||
| 524 | oem_vm_mem: memory@bb000000 { | |
| 525 | reg = <0x0 0xbb000000 0x0 0x5000000>; | |
| 526 | no-map; | |
| 527 | }; | |
| 528 | ||
| 529 | mte_mem: memory@c0000000 { | |
| 530 | reg = <0x0 0xc0000000 0x0 0x20000000>; | |
| 531 | no-map; | |
| 532 | }; | |
| 533 | ||
| 534 | qheebsp_reserved_mem: memory@e0000000 { | |
| 535 | reg = <0x0 0xe0000000 0x0 0x600000>; | |
| 536 | no-map; | |
| 537 | }; | |
| 538 | ||
| 539 | cpusys_vm_mem: memory@e0600000 { | |
| 540 | reg = <0x0 0xe0600000 0x0 0x400000>; | |
| 541 | no-map; | |
| 542 | }; | |
| 543 | ||
| 544 | hyp_reserved_mem: memory@e0a00000 { | |
| 545 | reg = <0x0 0xe0a00000 0x0 0x100000>; | |
| 546 | no-map; | |
| 547 | }; | |
| 548 | ||
| 549 | trust_ui_vm_mem: memory@e0b00000 { | |
| 550 | reg = <0x0 0xe0b00000 0x0 0x4af3000>; | |
| 551 | no-map; | |
| 552 | }; | |
| 553 | ||
| 554 | trust_ui_vm_qrtr: memory@e55f3000 { | |
| 555 | reg = <0x0 0xe55f3000 0x0 0x9000>; | |
| 556 | no-map; | |
| 557 | }; | |
| 558 | ||
| 559 | trust_ui_vm_vblk0_ring: memory@e55fc000 { | |
| 560 | reg = <0x0 0xe55fc000 0x0 0x4000>; | |
| 561 | no-map; | |
| 562 | }; | |
| 563 | ||
| 564 | trust_ui_vm_swiotlb: memory@e5600000 { | |
| 565 | reg = <0x0 0xe5600000 0x0 0x100000>; | |
| 566 | no-map; | |
| 567 | }; | |
| 568 | ||
| 569 | tz_stat_mem: memory@e8800000 { | |
| 570 | reg = <0x0 0xe8800000 0x0 0x100000>; | |
| 571 | no-map; | |
| 572 | }; | |
| 573 | ||
| 574 | tags_mem: memory@e8900000 { | |
| 575 | reg = <0x0 0xe8900000 0x0 0x1200000>; | |
| 576 | no-map; | |
| 577 | }; | |
| 578 | ||
| 579 | qtee_mem: memory@e9b00000 { | |
| 580 | reg = <0x0 0xe9b00000 0x0 0x500000>; | |
| 581 | no-map; | |
| 582 | }; | |
| 583 | ||
| 584 | trusted_apps_mem: memory@ea000000 { | |
| 585 | reg = <0x0 0xea000000 0x0 0x3900000>; | |
| 586 | no-map; | |
| 587 | }; | |
| 588 | ||
| 589 | trusted_apps_ext_mem: memory@ed900000 { | |
| 590 | reg = <0x0 0xed900000 0x0 0x3b00000>; | |
| 591 | no-map; | |
| 592 | }; | |
| 593 | }; | |
| 594 | ||
| 11727295 BA |
595 | smp2p-adsp { |
| 596 | compatible = "qcom,smp2p"; | |
| 597 | qcom,smem = <443>, <429>; | |
| 598 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
| 599 | IPCC_MPROC_SIGNAL_SMP2P | |
| 600 | IRQ_TYPE_EDGE_RISING>; | |
| 601 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
| 602 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 603 | ||
| 604 | qcom,local-pid = <0>; | |
| 605 | qcom,remote-pid = <2>; | |
| 606 | ||
| 607 | smp2p_adsp_out: master-kernel { | |
| 608 | qcom,entry-name = "master-kernel"; | |
| 609 | #qcom,smem-state-cells = <1>; | |
| 610 | }; | |
| 611 | ||
| 612 | smp2p_adsp_in: slave-kernel { | |
| 613 | qcom,entry-name = "slave-kernel"; | |
| 614 | interrupt-controller; | |
| 615 | #interrupt-cells = <2>; | |
| 616 | }; | |
| 617 | }; | |
| 618 | ||
| 619 | smp2p-cdsp { | |
| 620 | compatible = "qcom,smp2p"; | |
| 621 | qcom,smem = <94>, <432>; | |
| 622 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
| 623 | IPCC_MPROC_SIGNAL_SMP2P | |
| 624 | IRQ_TYPE_EDGE_RISING>; | |
| 625 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
| 626 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 627 | ||
| 628 | qcom,local-pid = <0>; | |
| 629 | qcom,remote-pid = <5>; | |
| 630 | ||
| 631 | smp2p_cdsp_out: master-kernel { | |
| 632 | qcom,entry-name = "master-kernel"; | |
| 633 | #qcom,smem-state-cells = <1>; | |
| 634 | }; | |
| 635 | ||
| 636 | smp2p_cdsp_in: slave-kernel { | |
| 637 | qcom,entry-name = "slave-kernel"; | |
| 638 | interrupt-controller; | |
| 639 | #interrupt-cells = <2>; | |
| 640 | }; | |
| 641 | }; | |
| 642 | ||
| 643 | smp2p-modem { | |
| 644 | compatible = "qcom,smp2p"; | |
| 645 | qcom,smem = <435>, <428>; | |
| 646 | interrupts-extended = <&ipcc IPCC_CLIENT_MPSS | |
| 647 | IPCC_MPROC_SIGNAL_SMP2P | |
| 648 | IRQ_TYPE_EDGE_RISING>; | |
| 649 | mboxes = <&ipcc IPCC_CLIENT_MPSS | |
| 650 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 651 | ||
| 652 | qcom,local-pid = <0>; | |
| 653 | qcom,remote-pid = <1>; | |
| 654 | ||
| 655 | smp2p_modem_out: master-kernel { | |
| 656 | qcom,entry-name = "master-kernel"; | |
| 657 | #qcom,smem-state-cells = <1>; | |
| 658 | }; | |
| 659 | ||
| 660 | smp2p_modem_in: slave-kernel { | |
| 661 | qcom,entry-name = "slave-kernel"; | |
| 662 | interrupt-controller; | |
| 663 | #interrupt-cells = <2>; | |
| 664 | }; | |
| 665 | ||
| 666 | ipa_smp2p_out: ipa-ap-to-modem { | |
| 667 | qcom,entry-name = "ipa"; | |
| 668 | #qcom,smem-state-cells = <1>; | |
| 669 | }; | |
| 670 | ||
| 671 | ipa_smp2p_in: ipa-modem-to-ap { | |
| 672 | qcom,entry-name = "ipa"; | |
| 673 | interrupt-controller; | |
| 674 | #interrupt-cells = <2>; | |
| 675 | }; | |
| 676 | }; | |
| 677 | ||
| 678 | smp2p-slpi { | |
| 679 | compatible = "qcom,smp2p"; | |
| 680 | qcom,smem = <481>, <430>; | |
| 681 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
| 682 | IPCC_MPROC_SIGNAL_SMP2P | |
| 683 | IRQ_TYPE_EDGE_RISING>; | |
| 684 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
| 685 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 686 | ||
| 687 | qcom,local-pid = <0>; | |
| 688 | qcom,remote-pid = <3>; | |
| 689 | ||
| 690 | smp2p_slpi_out: master-kernel { | |
| 691 | qcom,entry-name = "master-kernel"; | |
| 692 | #qcom,smem-state-cells = <1>; | |
| 693 | }; | |
| 694 | ||
| 695 | smp2p_slpi_in: slave-kernel { | |
| 696 | qcom,entry-name = "slave-kernel"; | |
| 697 | interrupt-controller; | |
| 698 | #interrupt-cells = <2>; | |
| 699 | }; | |
| 700 | }; | |
| 701 | ||
| 5188049c VK |
702 | soc: soc@0 { |
| 703 | #address-cells = <2>; | |
| 704 | #size-cells = <2>; | |
| 705 | ranges = <0 0 0 0 0x10 0>; | |
| 706 | dma-ranges = <0 0 0 0 0x10 0>; | |
| 707 | compatible = "simple-bus"; | |
| 708 | ||
| 709 | gcc: clock-controller@100000 { | |
| 710 | compatible = "qcom,gcc-sm8450"; | |
| 711 | reg = <0x0 0x00100000 0x0 0x1f4200>; | |
| 712 | #clock-cells = <1>; | |
| 713 | #reset-cells = <1>; | |
| 714 | #power-domain-cells = <1>; | |
| d41a72c2 DB |
715 | clocks = <&rpmhcc RPMH_CXO_CLK>, |
| 716 | <&pcie0_lane>, | |
| 334d91d2 | 717 | <&pcie1_lane>, |
| d41a72c2 DB |
718 | <&sleep_clk>; |
| 719 | clock-names = "bi_tcxo", | |
| 720 | "pcie_0_pipe_clk", | |
| 334d91d2 | 721 | "pcie_1_pipe_clk", |
| d41a72c2 | 722 | "sleep_clk"; |
| 5188049c VK |
723 | }; |
| 724 | ||
| b9c84330 VK |
725 | gpi_dma2: dma-controller@800000 { |
| 726 | compatible = "qcom,sm8450-gpi-dma"; | |
| 727 | #dma-cells = <3>; | |
| 728 | reg = <0 0x800000 0 0x60000>; | |
| 729 | interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, | |
| 730 | <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, | |
| 731 | <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, | |
| 732 | <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, | |
| 733 | <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, | |
| 734 | <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, | |
| 735 | <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, | |
| 736 | <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, | |
| 737 | <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, | |
| 738 | <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, | |
| 739 | <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, | |
| 740 | <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; | |
| 741 | dma-channels = <12>; | |
| 742 | dma-channel-mask = <0x7e>; | |
| 743 | iommus = <&apps_smmu 0x496 0x0>; | |
| 744 | status = "disabled"; | |
| 745 | }; | |
| 746 | ||
| ba640cd3 VK |
747 | qupv3_id_2: geniqup@8c0000 { |
| 748 | compatible = "qcom,geni-se-qup"; | |
| 749 | reg = <0x0 0x008c0000 0x0 0x2000>; | |
| 750 | clock-names = "m-ahb", "s-ahb"; | |
| 751 | clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, | |
| 752 | <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; | |
| 753 | iommus = <&apps_smmu 0x483 0x0>; | |
| 754 | #address-cells = <2>; | |
| 755 | #size-cells = <2>; | |
| 756 | ranges; | |
| 757 | status = "disabled"; | |
| 758 | ||
| 759 | i2c15: i2c@880000 { | |
| 760 | compatible = "qcom,geni-i2c"; | |
| 761 | reg = <0x0 0x00880000 0x0 0x4000>; | |
| 762 | clock-names = "se"; | |
| 763 | clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; | |
| 764 | pinctrl-names = "default"; | |
| 765 | pinctrl-0 = <&qup_i2c15_data_clk>; | |
| 766 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
| 767 | #address-cells = <1>; | |
| 768 | #size-cells = <0>; | |
| 769 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 770 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 771 | <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; | |
| 772 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 773 | dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, | |
| 774 | <&gpi_dma2 1 0 QCOM_GPI_I2C>; | |
| 775 | dma-names = "tx", "rx"; | |
| 776 | status = "disabled"; | |
| 777 | }; | |
| 778 | ||
| 779 | spi15: spi@880000 { | |
| 780 | compatible = "qcom,geni-spi"; | |
| 781 | reg = <0x0 0x00880000 0x0 0x4000>; | |
| 782 | clock-names = "se"; | |
| 783 | clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; | |
| 784 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
| 785 | pinctrl-names = "default"; | |
| 786 | pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; | |
| 787 | spi-max-frequency = <50000000>; | |
| 788 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 789 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; | |
| 790 | interconnect-names = "qup-core", "qup-config"; | |
| 791 | dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, | |
| 792 | <&gpi_dma2 1 0 QCOM_GPI_SPI>; | |
| 793 | dma-names = "tx", "rx"; | |
| 794 | #address-cells = <1>; | |
| 795 | #size-cells = <0>; | |
| 796 | status = "disabled"; | |
| 797 | }; | |
| 798 | ||
| 799 | i2c16: i2c@884000 { | |
| 800 | compatible = "qcom,geni-i2c"; | |
| 801 | reg = <0x0 0x00884000 0x0 0x4000>; | |
| 802 | clock-names = "se"; | |
| 803 | clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; | |
| 804 | pinctrl-names = "default"; | |
| 805 | pinctrl-0 = <&qup_i2c16_data_clk>; | |
| 806 | interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; | |
| 807 | #address-cells = <1>; | |
| 808 | #size-cells = <0>; | |
| 809 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 810 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 811 | <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; | |
| 812 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 813 | dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, | |
| 814 | <&gpi_dma2 1 1 QCOM_GPI_I2C>; | |
| 815 | dma-names = "tx", "rx"; | |
| 816 | status = "disabled"; | |
| 817 | }; | |
| 818 | ||
| 819 | spi16: spi@884000 { | |
| 820 | compatible = "qcom,geni-spi"; | |
| 821 | reg = <0x0 0x00884000 0x0 0x4000>; | |
| 822 | clock-names = "se"; | |
| 823 | clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; | |
| 824 | interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; | |
| 825 | pinctrl-names = "default"; | |
| 826 | pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; | |
| 827 | spi-max-frequency = <50000000>; | |
| 828 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 829 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; | |
| 830 | interconnect-names = "qup-core", "qup-config"; | |
| 831 | dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, | |
| 832 | <&gpi_dma2 1 1 QCOM_GPI_SPI>; | |
| 833 | dma-names = "tx", "rx"; | |
| 834 | #address-cells = <1>; | |
| 835 | #size-cells = <0>; | |
| 836 | status = "disabled"; | |
| 837 | }; | |
| 838 | ||
| 839 | i2c17: i2c@888000 { | |
| 840 | compatible = "qcom,geni-i2c"; | |
| 841 | reg = <0x0 0x00888000 0x0 0x4000>; | |
| 842 | clock-names = "se"; | |
| 843 | clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; | |
| 844 | pinctrl-names = "default"; | |
| 845 | pinctrl-0 = <&qup_i2c17_data_clk>; | |
| 846 | interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; | |
| 847 | #address-cells = <1>; | |
| 848 | #size-cells = <0>; | |
| 849 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 850 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 851 | <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; | |
| 852 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 853 | dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, | |
| 854 | <&gpi_dma2 1 2 QCOM_GPI_I2C>; | |
| 855 | dma-names = "tx", "rx"; | |
| 856 | status = "disabled"; | |
| 857 | }; | |
| 858 | ||
| 859 | spi17: spi@888000 { | |
| 860 | compatible = "qcom,geni-spi"; | |
| 861 | reg = <0x0 0x00888000 0x0 0x4000>; | |
| 862 | clock-names = "se"; | |
| 863 | clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; | |
| 864 | interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; | |
| 865 | pinctrl-names = "default"; | |
| 866 | pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; | |
| 867 | spi-max-frequency = <50000000>; | |
| 868 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 869 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; | |
| 870 | interconnect-names = "qup-core", "qup-config"; | |
| 871 | dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, | |
| 872 | <&gpi_dma2 1 2 QCOM_GPI_SPI>; | |
| 873 | dma-names = "tx", "rx"; | |
| 874 | #address-cells = <1>; | |
| 875 | #size-cells = <0>; | |
| 876 | status = "disabled"; | |
| 877 | }; | |
| 878 | ||
| 879 | i2c18: i2c@88c000 { | |
| 880 | compatible = "qcom,geni-i2c"; | |
| 881 | reg = <0x0 0x0088c000 0x0 0x4000>; | |
| 882 | clock-names = "se"; | |
| 883 | clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; | |
| 884 | pinctrl-names = "default"; | |
| 885 | pinctrl-0 = <&qup_i2c18_data_clk>; | |
| 886 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; | |
| 887 | #address-cells = <1>; | |
| 888 | #size-cells = <0>; | |
| 889 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 890 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 891 | <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; | |
| 892 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 893 | dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, | |
| 894 | <&gpi_dma2 1 3 QCOM_GPI_I2C>; | |
| 895 | dma-names = "tx", "rx"; | |
| 896 | status = "disabled"; | |
| 897 | }; | |
| 898 | ||
| 899 | spi18: spi@88c000 { | |
| 900 | compatible = "qcom,geni-spi"; | |
| 901 | reg = <0 0x0088c000 0 0x4000>; | |
| 902 | clock-names = "se"; | |
| 903 | clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; | |
| 904 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; | |
| 905 | pinctrl-names = "default"; | |
| 906 | pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; | |
| 907 | spi-max-frequency = <50000000>; | |
| 908 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 909 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; | |
| 910 | interconnect-names = "qup-core", "qup-config"; | |
| 911 | dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, | |
| 912 | <&gpi_dma2 1 3 QCOM_GPI_I2C>; | |
| 913 | dma-names = "tx", "rx"; | |
| 914 | #address-cells = <1>; | |
| 915 | #size-cells = <0>; | |
| 916 | status = "disabled"; | |
| 917 | }; | |
| 918 | ||
| 919 | i2c19: i2c@890000 { | |
| 920 | compatible = "qcom,geni-i2c"; | |
| 921 | reg = <0x0 0x00890000 0x0 0x4000>; | |
| 922 | clock-names = "se"; | |
| 923 | clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; | |
| 924 | pinctrl-names = "default"; | |
| 925 | pinctrl-0 = <&qup_i2c19_data_clk>; | |
| 926 | interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | |
| 927 | #address-cells = <1>; | |
| 928 | #size-cells = <0>; | |
| 929 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 930 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 931 | <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; | |
| 932 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 933 | dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, | |
| 934 | <&gpi_dma2 1 4 QCOM_GPI_I2C>; | |
| 935 | dma-names = "tx", "rx"; | |
| 936 | status = "disabled"; | |
| 937 | }; | |
| 938 | ||
| 939 | spi19: spi@890000 { | |
| 940 | compatible = "qcom,geni-spi"; | |
| 941 | reg = <0 0x00890000 0 0x4000>; | |
| 942 | clock-names = "se"; | |
| 943 | clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; | |
| 944 | interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | |
| 945 | pinctrl-names = "default"; | |
| 946 | pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; | |
| 947 | spi-max-frequency = <50000000>; | |
| 948 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 949 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; | |
| 950 | interconnect-names = "qup-core", "qup-config"; | |
| 951 | dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, | |
| 952 | <&gpi_dma2 1 4 QCOM_GPI_I2C>; | |
| 953 | dma-names = "tx", "rx"; | |
| 954 | #address-cells = <1>; | |
| 955 | #size-cells = <0>; | |
| 956 | status = "disabled"; | |
| 957 | }; | |
| 958 | ||
| 959 | i2c20: i2c@894000 { | |
| 960 | compatible = "qcom,geni-i2c"; | |
| 961 | reg = <0x0 0x00894000 0x0 0x4000>; | |
| 962 | clock-names = "se"; | |
| 963 | clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; | |
| 964 | pinctrl-names = "default"; | |
| 965 | pinctrl-0 = <&qup_i2c20_data_clk>; | |
| 966 | interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; | |
| 967 | #address-cells = <1>; | |
| 968 | #size-cells = <0>; | |
| 969 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 970 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 971 | <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; | |
| 972 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 973 | dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, | |
| 974 | <&gpi_dma2 1 5 QCOM_GPI_I2C>; | |
| 975 | dma-names = "tx", "rx"; | |
| 976 | status = "disabled"; | |
| 977 | }; | |
| 978 | ||
| 979 | spi20: spi@894000 { | |
| 980 | compatible = "qcom,geni-spi"; | |
| 981 | reg = <0 0x00894000 0 0x4000>; | |
| 982 | clock-names = "se"; | |
| 983 | clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; | |
| 984 | interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; | |
| 985 | pinctrl-names = "default"; | |
| 986 | pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; | |
| 987 | spi-max-frequency = <50000000>; | |
| 988 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 989 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; | |
| 990 | interconnect-names = "qup-core", "qup-config"; | |
| 991 | dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, | |
| 992 | <&gpi_dma2 1 5 QCOM_GPI_SPI>; | |
| 993 | dma-names = "tx", "rx"; | |
| 994 | #address-cells = <1>; | |
| 995 | #size-cells = <0>; | |
| 996 | status = "disabled"; | |
| 997 | }; | |
| 998 | ||
| 999 | i2c21: i2c@898000 { | |
| 1000 | compatible = "qcom,geni-i2c"; | |
| 1001 | reg = <0x0 0x00898000 0x0 0x4000>; | |
| 1002 | clock-names = "se"; | |
| 1003 | clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; | |
| 1004 | pinctrl-names = "default"; | |
| 1005 | pinctrl-0 = <&qup_i2c21_data_clk>; | |
| 1006 | interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; | |
| 1007 | #address-cells = <1>; | |
| 1008 | #size-cells = <0>; | |
| 1009 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 1010 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1011 | <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; | |
| 1012 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1013 | dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, | |
| 1014 | <&gpi_dma2 1 6 QCOM_GPI_I2C>; | |
| 1015 | dma-names = "tx", "rx"; | |
| 1016 | status = "disabled"; | |
| 1017 | }; | |
| 1018 | ||
| 1019 | spi21: spi@898000 { | |
| 1020 | compatible = "qcom,geni-spi"; | |
| 1021 | reg = <0 0x00898000 0 0x4000>; | |
| 1022 | clock-names = "se"; | |
| 1023 | clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; | |
| 1024 | interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; | |
| 1025 | pinctrl-names = "default"; | |
| 1026 | pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; | |
| 1027 | spi-max-frequency = <50000000>; | |
| 1028 | interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, | |
| 1029 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; | |
| 1030 | interconnect-names = "qup-core", "qup-config"; | |
| 1031 | dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, | |
| 1032 | <&gpi_dma2 1 6 QCOM_GPI_SPI>; | |
| 1033 | dma-names = "tx", "rx"; | |
| 1034 | #address-cells = <1>; | |
| 1035 | #size-cells = <0>; | |
| 1036 | status = "disabled"; | |
| 1037 | }; | |
| 1038 | }; | |
| 1039 | ||
| b9c84330 VK |
1040 | gpi_dma0: dma-controller@900000 { |
| 1041 | compatible = "qcom,sm8450-gpi-dma"; | |
| 1042 | #dma-cells = <3>; | |
| 1043 | reg = <0 0x900000 0 0x60000>; | |
| 1044 | interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, | |
| 1045 | <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
| 1046 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
| 1047 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
| 1048 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, | |
| 1049 | <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, | |
| 1050 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
| 1051 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
| 1052 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, | |
| 1053 | <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, | |
| 1054 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
| 1055 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; | |
| 1056 | dma-channels = <12>; | |
| 1057 | dma-channel-mask = <0x7e>; | |
| 1058 | iommus = <&apps_smmu 0x5b6 0x0>; | |
| 1059 | status = "disabled"; | |
| 1060 | }; | |
| 1061 | ||
| 5188049c VK |
1062 | qupv3_id_0: geniqup@9c0000 { |
| 1063 | compatible = "qcom,geni-se-qup"; | |
| 1064 | reg = <0x0 0x009c0000 0x0 0x2000>; | |
| 1065 | clock-names = "m-ahb", "s-ahb"; | |
| 1066 | clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, | |
| 1067 | <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; | |
| 488922c1 VK |
1068 | iommus = <&apps_smmu 0x5a3 0x0>; |
| 1069 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; | |
| 1070 | interconnect-names = "qup-core"; | |
| 5188049c VK |
1071 | #address-cells = <2>; |
| 1072 | #size-cells = <2>; | |
| 1073 | ranges; | |
| 1074 | status = "disabled"; | |
| 1075 | ||
| a84e88e9 VK |
1076 | i2c0: i2c@980000 { |
| 1077 | compatible = "qcom,geni-i2c"; | |
| 1078 | reg = <0x0 0x00980000 0x0 0x4000>; | |
| 1079 | clock-names = "se"; | |
| 1080 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
| 1081 | pinctrl-names = "default"; | |
| 1082 | pinctrl-0 = <&qup_i2c0_data_clk>; | |
| 1083 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
| 1084 | #address-cells = <1>; | |
| 1085 | #size-cells = <0>; | |
| 1086 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1087 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1088 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1089 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1090 | dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, | |
| 1091 | <&gpi_dma0 1 0 QCOM_GPI_I2C>; | |
| 1092 | dma-names = "tx", "rx"; | |
| 1093 | status = "disabled"; | |
| 1094 | }; | |
| 1095 | ||
| 1096 | spi0: spi@980000 { | |
| 1097 | compatible = "qcom,geni-spi"; | |
| 1098 | reg = <0x0 0x00980000 0x0 0x4000>; | |
| 1099 | clock-names = "se"; | |
| 1100 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
| 1101 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
| 1102 | pinctrl-names = "default"; | |
| 1103 | pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; | |
| 1104 | power-domains = <&rpmhpd SM8450_CX>; | |
| 1105 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
| 1106 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1107 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1108 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1109 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1110 | dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, | |
| 1111 | <&gpi_dma0 1 0 QCOM_GPI_SPI>; | |
| 1112 | dma-names = "tx", "rx"; | |
| 1113 | #address-cells = <1>; | |
| 1114 | #size-cells = <0>; | |
| 1115 | status = "disabled"; | |
| 1116 | }; | |
| 1117 | ||
| 1118 | i2c1: i2c@984000 { | |
| 1119 | compatible = "qcom,geni-i2c"; | |
| 1120 | reg = <0x0 0x00984000 0x0 0x4000>; | |
| 1121 | clock-names = "se"; | |
| 1122 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
| 1123 | pinctrl-names = "default"; | |
| 1124 | pinctrl-0 = <&qup_i2c1_data_clk>; | |
| 1125 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
| 1126 | #address-cells = <1>; | |
| 1127 | #size-cells = <0>; | |
| 1128 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1129 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1130 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1131 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1132 | dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, | |
| 1133 | <&gpi_dma0 1 1 QCOM_GPI_I2C>; | |
| 1134 | dma-names = "tx", "rx"; | |
| 1135 | status = "disabled"; | |
| 1136 | }; | |
| 1137 | ||
| 1138 | spi1: spi@984000 { | |
| 1139 | compatible = "qcom,geni-spi"; | |
| 1140 | reg = <0x0 0x00984000 0x0 0x4000>; | |
| 1141 | clock-names = "se"; | |
| 1142 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
| 1143 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
| 1144 | pinctrl-names = "default"; | |
| 1145 | pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; | |
| 1146 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1147 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1148 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1149 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1150 | dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, | |
| 1151 | <&gpi_dma0 1 1 QCOM_GPI_SPI>; | |
| 1152 | dma-names = "tx", "rx"; | |
| 1153 | #address-cells = <1>; | |
| 1154 | #size-cells = <0>; | |
| 1155 | status = "disabled"; | |
| 1156 | }; | |
| 1157 | ||
| 1158 | i2c2: i2c@988000 { | |
| 1159 | compatible = "qcom,geni-i2c"; | |
| 1160 | reg = <0x0 0x00988000 0x0 0x4000>; | |
| 1161 | clock-names = "se"; | |
| 1162 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
| 1163 | pinctrl-names = "default"; | |
| 1164 | pinctrl-0 = <&qup_i2c2_data_clk>; | |
| 1165 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
| 1166 | #address-cells = <1>; | |
| 1167 | #size-cells = <0>; | |
| 1168 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1169 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1170 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1171 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1172 | dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, | |
| 1173 | <&gpi_dma0 1 2 QCOM_GPI_I2C>; | |
| 1174 | dma-names = "tx", "rx"; | |
| 1175 | status = "disabled"; | |
| 1176 | }; | |
| 1177 | ||
| 1178 | spi2: spi@988000 { | |
| 1179 | compatible = "qcom,geni-spi"; | |
| 1180 | reg = <0x0 0x00988000 0x0 0x4000>; | |
| 1181 | clock-names = "se"; | |
| 1182 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
| 1183 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
| 1184 | pinctrl-names = "default"; | |
| 1185 | pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; | |
| 1186 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1187 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1188 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1189 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1190 | dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, | |
| 1191 | <&gpi_dma0 1 2 QCOM_GPI_SPI>; | |
| 1192 | dma-names = "tx", "rx"; | |
| 1193 | #address-cells = <1>; | |
| 1194 | #size-cells = <0>; | |
| 1195 | status = "disabled"; | |
| 1196 | }; | |
| 1197 | ||
| 1198 | ||
| 1199 | i2c3: i2c@98c000 { | |
| 1200 | compatible = "qcom,geni-i2c"; | |
| 1201 | reg = <0x0 0x0098c000 0x0 0x4000>; | |
| 1202 | clock-names = "se"; | |
| 1203 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; | |
| 1204 | pinctrl-names = "default"; | |
| 1205 | pinctrl-0 = <&qup_i2c3_data_clk>; | |
| 1206 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
| 1207 | #address-cells = <1>; | |
| 1208 | #size-cells = <0>; | |
| 1209 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1210 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1211 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1212 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1213 | dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, | |
| 1214 | <&gpi_dma0 1 3 QCOM_GPI_I2C>; | |
| 1215 | dma-names = "tx", "rx"; | |
| 1216 | status = "disabled"; | |
| 1217 | }; | |
| 1218 | ||
| 1219 | spi3: spi@98c000 { | |
| 1220 | compatible = "qcom,geni-spi"; | |
| 1221 | reg = <0x0 0x0098c000 0x0 0x4000>; | |
| 1222 | clock-names = "se"; | |
| 1223 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; | |
| 1224 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
| 1225 | pinctrl-names = "default"; | |
| 1226 | pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; | |
| 1227 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1228 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1229 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1230 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1231 | dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, | |
| 1232 | <&gpi_dma0 1 3 QCOM_GPI_SPI>; | |
| 1233 | dma-names = "tx", "rx"; | |
| 1234 | #address-cells = <1>; | |
| 1235 | #size-cells = <0>; | |
| 1236 | status = "disabled"; | |
| 1237 | }; | |
| 1238 | ||
| 1239 | i2c4: i2c@990000 { | |
| 1240 | compatible = "qcom,geni-i2c"; | |
| 1241 | reg = <0x0 0x00990000 0x0 0x4000>; | |
| 1242 | clock-names = "se"; | |
| 1243 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
| 1244 | pinctrl-names = "default"; | |
| 1245 | pinctrl-0 = <&qup_i2c4_data_clk>; | |
| 1246 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
| 1247 | #address-cells = <1>; | |
| 1248 | #size-cells = <0>; | |
| 1249 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1250 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1251 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1252 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1253 | dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, | |
| 1254 | <&gpi_dma0 1 4 QCOM_GPI_I2C>; | |
| 1255 | dma-names = "tx", "rx"; | |
| 1256 | status = "disabled"; | |
| 1257 | }; | |
| 1258 | ||
| 1259 | spi4: spi@990000 { | |
| 1260 | compatible = "qcom,geni-spi"; | |
| 1261 | reg = <0x0 0x00990000 0x0 0x4000>; | |
| 1262 | clock-names = "se"; | |
| 1263 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
| 1264 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
| 1265 | pinctrl-names = "default"; | |
| 1266 | pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; | |
| 1267 | power-domains = <&rpmhpd SM8450_CX>; | |
| 1268 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
| 1269 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1270 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1271 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1272 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1273 | dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, | |
| 1274 | <&gpi_dma0 1 4 QCOM_GPI_SPI>; | |
| 1275 | dma-names = "tx", "rx"; | |
| 1276 | #address-cells = <1>; | |
| 1277 | #size-cells = <0>; | |
| 1278 | status = "disabled"; | |
| 1279 | }; | |
| 1280 | ||
| 1281 | i2c5: i2c@994000 { | |
| 1282 | compatible = "qcom,geni-i2c"; | |
| 1283 | reg = <0x0 0x00994000 0x0 0x4000>; | |
| 1284 | clock-names = "se"; | |
| 1285 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
| 1286 | pinctrl-names = "default"; | |
| 1287 | pinctrl-0 = <&qup_i2c5_data_clk>; | |
| 1288 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
| 1289 | #address-cells = <1>; | |
| 1290 | #size-cells = <0>; | |
| 1291 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1292 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1293 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1294 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1295 | dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, | |
| 1296 | <&gpi_dma0 1 5 QCOM_GPI_I2C>; | |
| 1297 | dma-names = "tx", "rx"; | |
| 1298 | status = "disabled"; | |
| 1299 | }; | |
| 1300 | ||
| 1301 | spi5: spi@994000 { | |
| 1302 | compatible = "qcom,geni-spi"; | |
| 1303 | reg = <0x0 0x00994000 0x0 0x4000>; | |
| 1304 | clock-names = "se"; | |
| 1305 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
| 1306 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
| 1307 | pinctrl-names = "default"; | |
| 1308 | pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; | |
| 1309 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1310 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1311 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1312 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1313 | dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, | |
| 1314 | <&gpi_dma0 1 5 QCOM_GPI_SPI>; | |
| 1315 | dma-names = "tx", "rx"; | |
| 1316 | #address-cells = <1>; | |
| 1317 | #size-cells = <0>; | |
| 1318 | status = "disabled"; | |
| 1319 | }; | |
| 1320 | ||
| 1321 | ||
| 1322 | i2c6: i2c@998000 { | |
| 1323 | compatible = "qcom,geni-i2c"; | |
| 1324 | reg = <0x0 0x998000 0x0 0x4000>; | |
| 1325 | clock-names = "se"; | |
| 1326 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
| 1327 | pinctrl-names = "default"; | |
| 1328 | pinctrl-0 = <&qup_i2c6_data_clk>; | |
| 1329 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
| 1330 | #address-cells = <1>; | |
| 1331 | #size-cells = <0>; | |
| 1332 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1333 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1334 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1335 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1336 | dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, | |
| 1337 | <&gpi_dma0 1 6 QCOM_GPI_I2C>; | |
| 1338 | dma-names = "tx", "rx"; | |
| 1339 | status = "disabled"; | |
| 1340 | }; | |
| 1341 | ||
| 1342 | spi6: spi@998000 { | |
| 1343 | compatible = "qcom,geni-spi"; | |
| 1344 | reg = <0x0 0x998000 0x0 0x4000>; | |
| 1345 | clock-names = "se"; | |
| 1346 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
| 1347 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
| 1348 | pinctrl-names = "default"; | |
| 1349 | pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; | |
| 1350 | interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, | |
| 1351 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1352 | <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; | |
| 1353 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1354 | dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, | |
| 1355 | <&gpi_dma0 1 6 QCOM_GPI_SPI>; | |
| 1356 | dma-names = "tx", "rx"; | |
| 1357 | #address-cells = <1>; | |
| 1358 | #size-cells = <0>; | |
| 1359 | status = "disabled"; | |
| 1360 | }; | |
| 1361 | ||
| 5188049c VK |
1362 | uart7: serial@99c000 { |
| 1363 | compatible = "qcom,geni-debug-uart"; | |
| 1364 | reg = <0 0x0099c000 0 0x4000>; | |
| 1365 | clock-names = "se"; | |
| 1366 | clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; | |
| ec950d55 VK |
1367 | pinctrl-names = "default"; |
| 1368 | pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; | |
| 5188049c VK |
1369 | interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| 1370 | #address-cells = <1>; | |
| 1371 | #size-cells = <0>; | |
| 1372 | status = "disabled"; | |
| 1373 | }; | |
| 1374 | }; | |
| 1375 | ||
| b9c84330 VK |
1376 | gpi_dma1: dma-controller@a00000 { |
| 1377 | compatible = "qcom,sm8450-gpi-dma"; | |
| 1378 | #dma-cells = <3>; | |
| 1379 | reg = <0 0xa00000 0 0x60000>; | |
| 1380 | interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
| 1381 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, | |
| 1382 | <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, | |
| 1383 | <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, | |
| 1384 | <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, | |
| 1385 | <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, | |
| 1386 | <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, | |
| 1387 | <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, | |
| 1388 | <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, | |
| 1389 | <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, | |
| 1390 | <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, | |
| 1391 | <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; | |
| 1392 | dma-channels = <12>; | |
| 1393 | dma-channel-mask = <0x7e>; | |
| 1394 | iommus = <&apps_smmu 0x56 0x0>; | |
| 1395 | status = "disabled"; | |
| 1396 | }; | |
| 1397 | ||
| bf0a257a DB |
1398 | qupv3_id_1: geniqup@ac0000 { |
| 1399 | compatible = "qcom,geni-se-qup"; | |
| 1400 | reg = <0x0 0x00ac0000 0x0 0x6000>; | |
| 1401 | clock-names = "m-ahb", "s-ahb"; | |
| 1402 | clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, | |
| 1403 | <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; | |
| 67ebdc6d VK |
1404 | iommus = <&apps_smmu 0x43 0x0>; |
| 1405 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; | |
| 1406 | interconnect-names = "qup-core"; | |
| bf0a257a DB |
1407 | #address-cells = <2>; |
| 1408 | #size-cells = <2>; | |
| 1409 | ranges; | |
| 1410 | status = "disabled"; | |
| 1411 | ||
| 1a380216 VK |
1412 | i2c8: i2c@a80000 { |
| 1413 | compatible = "qcom,geni-i2c"; | |
| 1414 | reg = <0x0 0x00a80000 0x0 0x4000>; | |
| 1415 | clock-names = "se"; | |
| 1416 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
| 1417 | pinctrl-names = "default"; | |
| 1418 | pinctrl-0 = <&qup_i2c8_data_clk>; | |
| 1419 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
| 1420 | #address-cells = <1>; | |
| 1421 | #size-cells = <0>; | |
| 1422 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1423 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1424 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1425 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1426 | dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, | |
| 1427 | <&gpi_dma1 1 0 QCOM_GPI_I2C>; | |
| 1428 | dma-names = "tx", "rx"; | |
| 1429 | status = "disabled"; | |
| 1430 | }; | |
| 1431 | ||
| 1432 | spi8: spi@a80000 { | |
| 1433 | compatible = "qcom,geni-spi"; | |
| 1434 | reg = <0x0 0x00a80000 0x0 0x4000>; | |
| 1435 | clock-names = "se"; | |
| 1436 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
| 1437 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
| 1438 | pinctrl-names = "default"; | |
| 1439 | pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; | |
| 1440 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1441 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1442 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1443 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1444 | dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, | |
| 1445 | <&gpi_dma1 1 0 QCOM_GPI_SPI>; | |
| 1446 | dma-names = "tx", "rx"; | |
| 1447 | #address-cells = <1>; | |
| 1448 | #size-cells = <0>; | |
| 1449 | status = "disabled"; | |
| 1450 | }; | |
| 1451 | ||
| 1452 | i2c9: i2c@a84000 { | |
| 1453 | compatible = "qcom,geni-i2c"; | |
| 1454 | reg = <0x0 0x00a84000 0x0 0x4000>; | |
| 1455 | clock-names = "se"; | |
| 1456 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
| 1457 | pinctrl-names = "default"; | |
| 1458 | pinctrl-0 = <&qup_i2c9_data_clk>; | |
| 1459 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
| 1460 | #address-cells = <1>; | |
| 1461 | #size-cells = <0>; | |
| 1462 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1463 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1464 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1465 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1466 | dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, | |
| 1467 | <&gpi_dma1 1 1 QCOM_GPI_I2C>; | |
| 1468 | dma-names = "tx", "rx"; | |
| 1469 | status = "disabled"; | |
| 1470 | }; | |
| 1471 | ||
| 1472 | spi9: spi@a84000 { | |
| 1473 | compatible = "qcom,geni-spi"; | |
| 1474 | reg = <0x0 0x00a84000 0x0 0x4000>; | |
| 1475 | clock-names = "se"; | |
| 1476 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
| 1477 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
| 1478 | pinctrl-names = "default"; | |
| 1479 | pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; | |
| 1480 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1481 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1482 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1483 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1484 | dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, | |
| 1485 | <&gpi_dma1 1 1 QCOM_GPI_SPI>; | |
| 1486 | dma-names = "tx", "rx"; | |
| 1487 | #address-cells = <1>; | |
| 1488 | #size-cells = <0>; | |
| 1489 | status = "disabled"; | |
| 1490 | }; | |
| 1491 | ||
| 1492 | i2c10: i2c@a88000 { | |
| 1493 | compatible = "qcom,geni-i2c"; | |
| 1494 | reg = <0x0 0x00a88000 0x0 0x4000>; | |
| 1495 | clock-names = "se"; | |
| 1496 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
| 1497 | pinctrl-names = "default"; | |
| 1498 | pinctrl-0 = <&qup_i2c10_data_clk>; | |
| 1499 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
| 1500 | #address-cells = <1>; | |
| 1501 | #size-cells = <0>; | |
| 1502 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1503 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1504 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1505 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1506 | dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, | |
| 1507 | <&gpi_dma1 1 2 QCOM_GPI_I2C>; | |
| 1508 | dma-names = "tx", "rx"; | |
| 1509 | status = "disabled"; | |
| 1510 | }; | |
| 1511 | ||
| 1512 | spi10: spi@a88000 { | |
| 1513 | compatible = "qcom,geni-spi"; | |
| 1514 | reg = <0x0 0x00a88000 0x0 0x4000>; | |
| 1515 | clock-names = "se"; | |
| 1516 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
| 1517 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
| 1518 | pinctrl-names = "default"; | |
| 1519 | pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; | |
| 1520 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1521 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1522 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1523 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1524 | dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, | |
| 1525 | <&gpi_dma1 1 2 QCOM_GPI_SPI>; | |
| 1526 | dma-names = "tx", "rx"; | |
| 1527 | #address-cells = <1>; | |
| 1528 | #size-cells = <0>; | |
| 1529 | status = "disabled"; | |
| 1530 | }; | |
| 1531 | ||
| 1532 | i2c11: i2c@a8c000 { | |
| 1533 | compatible = "qcom,geni-i2c"; | |
| 1534 | reg = <0x0 0x00a8c000 0x0 0x4000>; | |
| 1535 | clock-names = "se"; | |
| 1536 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
| 1537 | pinctrl-names = "default"; | |
| 1538 | pinctrl-0 = <&qup_i2c11_data_clk>; | |
| 1539 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
| 1540 | #address-cells = <1>; | |
| 1541 | #size-cells = <0>; | |
| 1542 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1543 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1544 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1545 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1546 | dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, | |
| 1547 | <&gpi_dma1 1 3 QCOM_GPI_I2C>; | |
| 1548 | dma-names = "tx", "rx"; | |
| 1549 | status = "disabled"; | |
| 1550 | }; | |
| 1551 | ||
| 1552 | spi11: spi@a8c000 { | |
| 1553 | compatible = "qcom,geni-spi"; | |
| 1554 | reg = <0x0 0x00a8c000 0x0 0x4000>; | |
| 1555 | clock-names = "se"; | |
| 1556 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
| 1557 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
| 1558 | pinctrl-names = "default"; | |
| 1559 | pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; | |
| 1560 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1561 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1562 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1563 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1564 | dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, | |
| 1565 | <&gpi_dma1 1 3 QCOM_GPI_SPI>; | |
| 1566 | dma-names = "tx", "rx"; | |
| 1567 | #address-cells = <1>; | |
| 1568 | #size-cells = <0>; | |
| 1569 | status = "disabled"; | |
| 1570 | }; | |
| 1571 | ||
| 1572 | i2c12: i2c@a90000 { | |
| 1573 | compatible = "qcom,geni-i2c"; | |
| 1574 | reg = <0x0 0x00a90000 0x0 0x4000>; | |
| 1575 | clock-names = "se"; | |
| 1576 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
| 1577 | pinctrl-names = "default"; | |
| 1578 | pinctrl-0 = <&qup_i2c12_data_clk>; | |
| 1579 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
| 1580 | #address-cells = <1>; | |
| 1581 | #size-cells = <0>; | |
| 1582 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1583 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1584 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1585 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1586 | dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, | |
| 1587 | <&gpi_dma1 1 4 QCOM_GPI_I2C>; | |
| 1588 | dma-names = "tx", "rx"; | |
| 1589 | status = "disabled"; | |
| 1590 | }; | |
| 1591 | ||
| 1592 | spi12: spi@a90000 { | |
| 1593 | compatible = "qcom,geni-spi"; | |
| 1594 | reg = <0x0 0x00a90000 0x0 0x4000>; | |
| 1595 | clock-names = "se"; | |
| 1596 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
| 1597 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
| 1598 | pinctrl-names = "default"; | |
| 1599 | pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; | |
| 1600 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1601 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1602 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1603 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1604 | dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, | |
| 1605 | <&gpi_dma1 1 4 QCOM_GPI_SPI>; | |
| 1606 | dma-names = "tx", "rx"; | |
| 1607 | #address-cells = <1>; | |
| 1608 | #size-cells = <0>; | |
| 1609 | status = "disabled"; | |
| 1610 | }; | |
| 1611 | ||
| bf0a257a DB |
1612 | i2c13: i2c@a94000 { |
| 1613 | compatible = "qcom,geni-i2c"; | |
| 1614 | reg = <0 0x00a94000 0 0x4000>; | |
| 1615 | clock-names = "se"; | |
| 1616 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
| 1617 | pinctrl-names = "default"; | |
| 1618 | pinctrl-0 = <&qup_i2c13_data_clk>; | |
| 1619 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
| 1a380216 VK |
1620 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| 1621 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1622 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1623 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1624 | dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, | |
| 1625 | <&gpi_dma1 1 5 QCOM_GPI_I2C>; | |
| 1626 | dma-names = "tx", "rx"; | |
| 1627 | #address-cells = <1>; | |
| 1628 | #size-cells = <0>; | |
| 1629 | status = "disabled"; | |
| 1630 | }; | |
| 1631 | ||
| 1632 | spi13: spi@a94000 { | |
| 1633 | compatible = "qcom,geni-spi"; | |
| 1634 | reg = <0x0 0x00a94000 0x0 0x4000>; | |
| 1635 | clock-names = "se"; | |
| 1636 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
| 1637 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
| 1638 | pinctrl-names = "default"; | |
| 1639 | pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; | |
| 1640 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1641 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1642 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1643 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1644 | dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, | |
| 1645 | <&gpi_dma1 1 5 QCOM_GPI_SPI>; | |
| 1646 | dma-names = "tx", "rx"; | |
| bf0a257a DB |
1647 | #address-cells = <1>; |
| 1648 | #size-cells = <0>; | |
| 1649 | status = "disabled"; | |
| 1650 | }; | |
| 1651 | ||
| 1652 | i2c14: i2c@a98000 { | |
| 1653 | compatible = "qcom,geni-i2c"; | |
| 1654 | reg = <0 0x00a98000 0 0x4000>; | |
| 1655 | clock-names = "se"; | |
| 1656 | clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; | |
| 1657 | pinctrl-names = "default"; | |
| 1658 | pinctrl-0 = <&qup_i2c14_data_clk>; | |
| 1659 | interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; | |
| 1a380216 VK |
1660 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| 1661 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1662 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1663 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1664 | dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, | |
| 1665 | <&gpi_dma1 1 6 QCOM_GPI_I2C>; | |
| 1666 | dma-names = "tx", "rx"; | |
| 1667 | #address-cells = <1>; | |
| 1668 | #size-cells = <0>; | |
| 1669 | status = "disabled"; | |
| 1670 | }; | |
| 1671 | ||
| 1672 | spi14: spi@a98000 { | |
| 1673 | compatible = "qcom,geni-spi"; | |
| 1674 | reg = <0x0 0x00a98000 0x0 0x4000>; | |
| 1675 | clock-names = "se"; | |
| 1676 | clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; | |
| 1677 | interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; | |
| 1678 | pinctrl-names = "default"; | |
| 1679 | pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; | |
| 1680 | interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, | |
| 1681 | <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, | |
| 1682 | <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; | |
| 1683 | interconnect-names = "qup-core", "qup-config", "qup-memory"; | |
| 1684 | dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, | |
| 1685 | <&gpi_dma1 1 6 QCOM_GPI_SPI>; | |
| 1686 | dma-names = "tx", "rx"; | |
| bf0a257a DB |
1687 | #address-cells = <1>; |
| 1688 | #size-cells = <0>; | |
| 1689 | status = "disabled"; | |
| d41a72c2 DB |
1690 | }; |
| 1691 | }; | |
| 1692 | ||
| 7b09b1b4 DB |
1693 | pcie0: pci@1c00000 { |
| 1694 | compatible = "qcom,pcie-sm8450-pcie0"; | |
| 1695 | reg = <0 0x01c00000 0 0x3000>, | |
| 1696 | <0 0x60000000 0 0xf1d>, | |
| 1697 | <0 0x60000f20 0 0xa8>, | |
| 1698 | <0 0x60001000 0 0x1000>, | |
| 1699 | <0 0x60100000 0 0x100000>; | |
| 1700 | reg-names = "parf", "dbi", "elbi", "atu", "config"; | |
| 1701 | device_type = "pci"; | |
| 1702 | linux,pci-domain = <0>; | |
| 1703 | bus-range = <0x00 0xff>; | |
| 1704 | num-lanes = <1>; | |
| 1705 | ||
| 1706 | #address-cells = <3>; | |
| 1707 | #size-cells = <2>; | |
| 1708 | ||
| 1709 | ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, | |
| 1710 | <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; | |
| 1711 | ||
| 1712 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; | |
| 1713 | interrupt-names = "msi"; | |
| 1714 | #interrupt-cells = <1>; | |
| 1715 | interrupt-map-mask = <0 0 0 0x7>; | |
| 1716 | interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
| 1717 | <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
| 1718 | <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
| 1719 | <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
| 1720 | ||
| 1721 | clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, | |
| 1722 | <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, | |
| 1723 | <&pcie0_lane>, | |
| 1724 | <&rpmhcc RPMH_CXO_CLK>, | |
| 1725 | <&gcc GCC_PCIE_0_AUX_CLK>, | |
| 1726 | <&gcc GCC_PCIE_0_CFG_AHB_CLK>, | |
| 1727 | <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, | |
| 1728 | <&gcc GCC_PCIE_0_SLV_AXI_CLK>, | |
| 1729 | <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, | |
| 1730 | <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, | |
| 1731 | <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, | |
| 1732 | <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; | |
| 1733 | clock-names = "pipe", | |
| 1734 | "pipe_mux", | |
| 1735 | "phy_pipe", | |
| 1736 | "ref", | |
| 1737 | "aux", | |
| 1738 | "cfg", | |
| 1739 | "bus_master", | |
| 1740 | "bus_slave", | |
| 1741 | "slave_q2a", | |
| 1742 | "ddrss_sf_tbu", | |
| 1743 | "aggre0", | |
| 1744 | "aggre1"; | |
| 1745 | ||
| 1746 | iommus = <&apps_smmu 0x1c00 0x7f>; | |
| 1747 | iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, | |
| 1748 | <0x100 &apps_smmu 0x1c01 0x1>; | |
| 1749 | ||
| 1750 | resets = <&gcc GCC_PCIE_0_BCR>; | |
| 1751 | reset-names = "pci"; | |
| 1752 | ||
| 1753 | power-domains = <&gcc PCIE_0_GDSC>; | |
| 1754 | power-domain-names = "gdsc"; | |
| 1755 | ||
| 1756 | phys = <&pcie0_lane>; | |
| 1757 | phy-names = "pciephy"; | |
| 1758 | ||
| 1759 | perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; | |
| 1760 | wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; | |
| 1761 | ||
| 1762 | pinctrl-names = "default"; | |
| 1763 | pinctrl-0 = <&pcie0_default_state>; | |
| 1764 | ||
| 1765 | status = "disabled"; | |
| 1766 | }; | |
| 1767 | ||
| d41a72c2 DB |
1768 | pcie0_phy: phy@1c06000 { |
| 1769 | compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; | |
| 1770 | reg = <0 0x01c06000 0 0x200>; | |
| 1771 | #address-cells = <2>; | |
| 1772 | #size-cells = <2>; | |
| 1773 | ranges; | |
| 1774 | clocks = <&gcc GCC_PCIE_0_AUX_CLK>, | |
| 1775 | <&gcc GCC_PCIE_0_CFG_AHB_CLK>, | |
| 1776 | <&gcc GCC_PCIE_0_CLKREF_EN>, | |
| 1777 | <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; | |
| 1778 | clock-names = "aux", "cfg_ahb", "ref", "refgen"; | |
| 1779 | ||
| 1780 | resets = <&gcc GCC_PCIE_0_PHY_BCR>; | |
| 1781 | reset-names = "phy"; | |
| 1782 | ||
| 1783 | assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; | |
| 1784 | assigned-clock-rates = <100000000>; | |
| 1785 | ||
| 1786 | status = "disabled"; | |
| 1787 | ||
| 2a31f958 | 1788 | pcie0_lane: phy@1c06200 { |
| d41a72c2 DB |
1789 | reg = <0 0x1c06e00 0 0x200>, /* tx */ |
| 1790 | <0 0x1c07000 0 0x200>, /* rx */ | |
| 1791 | <0 0x1c06200 0 0x200>, /* pcs */ | |
| 1792 | <0 0x1c06600 0 0x200>; /* pcs_pcie */ | |
| 1793 | clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; | |
| 1794 | clock-names = "pipe0"; | |
| 1795 | ||
| 1796 | #clock-cells = <0>; | |
| 1797 | #phy-cells = <0>; | |
| 1798 | clock-output-names = "pcie_0_pipe_clk"; | |
| bf0a257a DB |
1799 | }; |
| 1800 | }; | |
| 1801 | ||
| bc6588bc DB |
1802 | pcie1: pci@1c08000 { |
| 1803 | compatible = "qcom,pcie-sm8450-pcie1"; | |
| 1804 | reg = <0 0x01c08000 0 0x3000>, | |
| 1805 | <0 0x40000000 0 0xf1d>, | |
| 1806 | <0 0x40000f20 0 0xa8>, | |
| 1807 | <0 0x40001000 0 0x1000>, | |
| 1808 | <0 0x40100000 0 0x100000>; | |
| 1809 | reg-names = "parf", "dbi", "elbi", "atu", "config"; | |
| 1810 | device_type = "pci"; | |
| 1811 | linux,pci-domain = <1>; | |
| 1812 | bus-range = <0x00 0xff>; | |
| 1813 | num-lanes = <2>; | |
| 1814 | ||
| 1815 | #address-cells = <3>; | |
| 1816 | #size-cells = <2>; | |
| 1817 | ||
| 1818 | ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, | |
| 1819 | <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; | |
| 1820 | ||
| 1821 | interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; | |
| 1822 | interrupt-names = "msi"; | |
| 1823 | #interrupt-cells = <1>; | |
| 1824 | interrupt-map-mask = <0 0 0 0x7>; | |
| 1825 | interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
| 1826 | <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
| 1827 | <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
| 1828 | <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
| 1829 | ||
| 1830 | clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, | |
| 1831 | <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, | |
| 1832 | <&pcie1_lane>, | |
| 1833 | <&rpmhcc RPMH_CXO_CLK>, | |
| 1834 | <&gcc GCC_PCIE_1_AUX_CLK>, | |
| 1835 | <&gcc GCC_PCIE_1_CFG_AHB_CLK>, | |
| 1836 | <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, | |
| 1837 | <&gcc GCC_PCIE_1_SLV_AXI_CLK>, | |
| 1838 | <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, | |
| 1839 | <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, | |
| 1840 | <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; | |
| 1841 | clock-names = "pipe", | |
| 1842 | "pipe_mux", | |
| 1843 | "phy_pipe", | |
| 1844 | "ref", | |
| 1845 | "aux", | |
| 1846 | "cfg", | |
| 1847 | "bus_master", | |
| 1848 | "bus_slave", | |
| 1849 | "slave_q2a", | |
| 1850 | "ddrss_sf_tbu", | |
| 1851 | "aggre1"; | |
| 1852 | ||
| 1853 | iommus = <&apps_smmu 0x1c80 0x7f>; | |
| 1854 | iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, | |
| 1855 | <0x100 &apps_smmu 0x1c81 0x1>; | |
| 1856 | ||
| 1857 | resets = <&gcc GCC_PCIE_1_BCR>; | |
| 1858 | reset-names = "pci"; | |
| 1859 | ||
| 1860 | power-domains = <&gcc PCIE_1_GDSC>; | |
| 1861 | power-domain-names = "gdsc"; | |
| 1862 | ||
| 1863 | phys = <&pcie1_lane>; | |
| 1864 | phy-names = "pciephy"; | |
| 1865 | ||
| 1866 | perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; | |
| 1867 | enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; | |
| 1868 | ||
| 1869 | pinctrl-names = "default"; | |
| 1870 | pinctrl-0 = <&pcie1_default_state>; | |
| 1871 | ||
| 1872 | status = "disabled"; | |
| 1873 | }; | |
| 1874 | ||
| 334d91d2 DB |
1875 | pcie1_phy: phy@1c0f000 { |
| 1876 | compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; | |
| 1877 | reg = <0 0x01c0f000 0 0x200>; | |
| 1878 | #address-cells = <2>; | |
| 1879 | #size-cells = <2>; | |
| 1880 | ranges; | |
| 1881 | clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, | |
| 1882 | <&gcc GCC_PCIE_1_CFG_AHB_CLK>, | |
| 1883 | <&gcc GCC_PCIE_1_CLKREF_EN>, | |
| 1884 | <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; | |
| 1885 | clock-names = "aux", "cfg_ahb", "ref", "refgen"; | |
| 1886 | ||
| 1887 | resets = <&gcc GCC_PCIE_1_PHY_BCR>; | |
| 1888 | reset-names = "phy"; | |
| 1889 | ||
| 1890 | assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; | |
| 1891 | assigned-clock-rates = <100000000>; | |
| 1892 | ||
| 1893 | status = "disabled"; | |
| 1894 | ||
| 2a31f958 | 1895 | pcie1_lane: phy@1c0e000 { |
| 334d91d2 DB |
1896 | reg = <0 0x1c0e000 0 0x200>, /* tx */ |
| 1897 | <0 0x1c0e200 0 0x300>, /* rx */ | |
| 1898 | <0 0x1c0f200 0 0x200>, /* pcs */ | |
| 1899 | <0 0x1c0e800 0 0x200>, /* tx */ | |
| 1900 | <0 0x1c0ea00 0 0x300>, /* rx */ | |
| 1901 | <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ | |
| 1902 | clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; | |
| 1903 | clock-names = "pipe0"; | |
| 1904 | ||
| 1905 | #clock-cells = <0>; | |
| 1906 | #phy-cells = <0>; | |
| 1907 | clock-output-names = "pcie_1_pipe_clk"; | |
| 1908 | }; | |
| 1909 | }; | |
| 1910 | ||
| aa2d0bf0 VK |
1911 | config_noc: interconnect@1500000 { |
| 1912 | compatible = "qcom,sm8450-config-noc"; | |
| 1913 | reg = <0 0x01500000 0 0x1c000>; | |
| 1914 | #interconnect-cells = <2>; | |
| 1915 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1916 | }; | |
| 1917 | ||
| 1918 | system_noc: interconnect@1680000 { | |
| 1919 | compatible = "qcom,sm8450-system-noc"; | |
| 1920 | reg = <0 0x01680000 0 0x1e200>; | |
| 1921 | #interconnect-cells = <2>; | |
| 1922 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1923 | }; | |
| 1924 | ||
| 1925 | pcie_noc: interconnect@16c0000 { | |
| 1926 | compatible = "qcom,sm8450-pcie-anoc"; | |
| 1927 | reg = <0 0x016c0000 0 0xe280>; | |
| 1928 | #interconnect-cells = <2>; | |
| 1929 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1930 | }; | |
| 1931 | ||
| 1932 | aggre1_noc: interconnect@16e0000 { | |
| 1933 | compatible = "qcom,sm8450-aggre1-noc"; | |
| 1934 | reg = <0 0x016e0000 0 0x1c080>; | |
| 1935 | #interconnect-cells = <2>; | |
| 1936 | clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
| 1937 | <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; | |
| 1938 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1939 | }; | |
| 1940 | ||
| 1941 | aggre2_noc: interconnect@1700000 { | |
| 1942 | compatible = "qcom,sm8450-aggre2-noc"; | |
| 1943 | reg = <0 0x01700000 0 0x31080>; | |
| 1944 | #interconnect-cells = <2>; | |
| 1945 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1946 | clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, | |
| 1947 | <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, | |
| 1948 | <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
| 1949 | <&rpmhcc RPMH_IPA_CLK>; | |
| 1950 | }; | |
| 1951 | ||
| 1952 | mmss_noc: interconnect@1740000 { | |
| 1953 | compatible = "qcom,sm8450-mmss-noc"; | |
| 1954 | reg = <0 0x01740000 0 0x1f080>; | |
| 1955 | #interconnect-cells = <2>; | |
| 1956 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1957 | }; | |
| 1958 | ||
| 5188049c VK |
1959 | tcsr_mutex: hwlock@1f40000 { |
| 1960 | compatible = "qcom,tcsr-mutex"; | |
| 1961 | reg = <0x0 0x01f40000 0x0 0x40000>; | |
| 1962 | #hwlock-cells = <1>; | |
| 1963 | }; | |
| 1964 | ||
| 19fd04fb VK |
1965 | usb_1_hsphy: phy@88e3000 { |
| 1966 | compatible = "qcom,sm8450-usb-hs-phy", | |
| 1967 | "qcom,usb-snps-hs-7nm-phy"; | |
| 1968 | reg = <0 0x088e3000 0 0x400>; | |
| 1969 | status = "disabled"; | |
| 1970 | #phy-cells = <0>; | |
| 1971 | ||
| 1972 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 1973 | clock-names = "ref"; | |
| 1974 | ||
| 1975 | resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; | |
| 1976 | }; | |
| 1977 | ||
| 1978 | usb_1_qmpphy: phy-wrapper@88e9000 { | |
| 1979 | compatible = "qcom,sm8450-qmp-usb3-phy"; | |
| 1980 | reg = <0 0x088e9000 0 0x200>, | |
| 1981 | <0 0x088e8000 0 0x20>; | |
| 1982 | status = "disabled"; | |
| 1983 | #address-cells = <2>; | |
| 1984 | #size-cells = <2>; | |
| 1985 | ranges; | |
| 1986 | ||
| 1987 | clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, | |
| 1988 | <&rpmhcc RPMH_CXO_CLK>, | |
| 1989 | <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; | |
| 1990 | clock-names = "aux", "ref_clk_src", "com_aux"; | |
| 1991 | ||
| 1992 | resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, | |
| 1993 | <&gcc GCC_USB3_PHY_PRIM_BCR>; | |
| 1994 | reset-names = "phy", "common"; | |
| 1995 | ||
| 1996 | usb_1_ssphy: phy@88e9200 { | |
| 1997 | reg = <0 0x088e9200 0 0x200>, | |
| 1998 | <0 0x088e9400 0 0x200>, | |
| 1999 | <0 0x088e9c00 0 0x400>, | |
| 2000 | <0 0x088e9600 0 0x200>, | |
| 2001 | <0 0x088e9800 0 0x200>, | |
| 2002 | <0 0x088e9a00 0 0x100>; | |
| 2003 | #phy-cells = <0>; | |
| 2004 | #clock-cells = <1>; | |
| 2005 | clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; | |
| 2006 | clock-names = "pipe0"; | |
| 2007 | clock-output-names = "usb3_phy_pipe_clk_src"; | |
| 2008 | }; | |
| 2009 | }; | |
| 2010 | ||
| 11727295 BA |
2011 | remoteproc_slpi: remoteproc@2400000 { |
| 2012 | compatible = "qcom,sm8450-slpi-pas"; | |
| 2013 | reg = <0 0x02400000 0 0x4000>; | |
| 2014 | ||
| 2015 | interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, | |
| 2016 | <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 2017 | <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 2018 | <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 2019 | <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 2020 | interrupt-names = "wdog", "fatal", "ready", | |
| 2021 | "handover", "stop-ack"; | |
| 2022 | ||
| 2023 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 2024 | clock-names = "xo"; | |
| 2025 | ||
| 2026 | power-domains = <&rpmhpd SM8450_LCX>, | |
| 2027 | <&rpmhpd SM8450_LMX>; | |
| 2028 | power-domain-names = "lcx", "lmx"; | |
| 2029 | ||
| 2030 | memory-region = <&slpi_mem>; | |
| 2031 | ||
| 2032 | qcom,qmp = <&aoss_qmp>; | |
| 2033 | ||
| 2034 | qcom,smem-states = <&smp2p_slpi_out 0>; | |
| 2035 | qcom,smem-state-names = "stop"; | |
| 2036 | ||
| 2037 | status = "disabled"; | |
| 2038 | ||
| 2039 | glink-edge { | |
| 2040 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
| 2041 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 2042 | IRQ_TYPE_EDGE_RISING>; | |
| 2043 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
| 2044 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 2045 | ||
| 2046 | label = "slpi"; | |
| 2047 | qcom,remote-pid = <3>; | |
| 91d70eb7 DB |
2048 | |
| 2049 | fastrpc { | |
| 2050 | compatible = "qcom,fastrpc"; | |
| 2051 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| 2052 | label = "sdsp"; | |
| 2053 | #address-cells = <1>; | |
| 2054 | #size-cells = <0>; | |
| 2055 | ||
| 2056 | compute-cb@1 { | |
| 2057 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2058 | reg = <1>; | |
| 2059 | iommus = <&apps_smmu 0x0541 0x0>; | |
| 2060 | }; | |
| 2061 | ||
| 2062 | compute-cb@2 { | |
| 2063 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2064 | reg = <2>; | |
| 2065 | iommus = <&apps_smmu 0x0542 0x0>; | |
| 2066 | }; | |
| 2067 | ||
| 2068 | compute-cb@3 { | |
| 2069 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2070 | reg = <3>; | |
| 2071 | iommus = <&apps_smmu 0x0543 0x0>; | |
| 2072 | /* note: shared-cb = <4> in downstream */ | |
| 2073 | }; | |
| 2074 | }; | |
| 11727295 BA |
2075 | }; |
| 2076 | }; | |
| 2077 | ||
| 2078 | remoteproc_adsp: remoteproc@30000000 { | |
| 2079 | compatible = "qcom,sm8450-adsp-pas"; | |
| 2080 | reg = <0 0x030000000 0 0x100>; | |
| 2081 | ||
| 2082 | interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, | |
| 2083 | <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 2084 | <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 2085 | <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 2086 | <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 2087 | interrupt-names = "wdog", "fatal", "ready", | |
| 2088 | "handover", "stop-ack"; | |
| 2089 | ||
| 2090 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 2091 | clock-names = "xo"; | |
| 2092 | ||
| 2093 | power-domains = <&rpmhpd SM8450_LCX>, | |
| 2094 | <&rpmhpd SM8450_LMX>; | |
| 2095 | power-domain-names = "lcx", "lmx"; | |
| 2096 | ||
| 2097 | memory-region = <&adsp_mem>; | |
| 2098 | ||
| 2099 | qcom,qmp = <&aoss_qmp>; | |
| 2100 | ||
| 2101 | qcom,smem-states = <&smp2p_adsp_out 0>; | |
| 2102 | qcom,smem-state-names = "stop"; | |
| 2103 | ||
| 2104 | status = "disabled"; | |
| 2105 | ||
| 2106 | remoteproc_adsp_glink: glink-edge { | |
| 2107 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
| 2108 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 2109 | IRQ_TYPE_EDGE_RISING>; | |
| 2110 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
| 2111 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 2112 | ||
| 2113 | label = "lpass"; | |
| 2114 | qcom,remote-pid = <2>; | |
| 91d70eb7 DB |
2115 | |
| 2116 | fastrpc { | |
| 2117 | compatible = "qcom,fastrpc"; | |
| 2118 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| 2119 | label = "adsp"; | |
| 2120 | #address-cells = <1>; | |
| 2121 | #size-cells = <0>; | |
| 2122 | ||
| 2123 | compute-cb@3 { | |
| 2124 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2125 | reg = <3>; | |
| 2126 | iommus = <&apps_smmu 0x1803 0x0>; | |
| 2127 | }; | |
| 2128 | ||
| 2129 | compute-cb@4 { | |
| 2130 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2131 | reg = <4>; | |
| 2132 | iommus = <&apps_smmu 0x1804 0x0>; | |
| 2133 | }; | |
| 2134 | ||
| 2135 | compute-cb@5 { | |
| 2136 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2137 | reg = <5>; | |
| 2138 | iommus = <&apps_smmu 0x1805 0x0>; | |
| 2139 | }; | |
| 2140 | }; | |
| 11727295 BA |
2141 | }; |
| 2142 | }; | |
| 2143 | ||
| 2144 | remoteproc_cdsp: remoteproc@32300000 { | |
| 2145 | compatible = "qcom,sm8450-cdsp-pas"; | |
| 2146 | reg = <0 0x032300000 0 0x1400000>; | |
| 2147 | ||
| 2148 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, | |
| 2149 | <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 2150 | <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 2151 | <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 2152 | <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 2153 | interrupt-names = "wdog", "fatal", "ready", | |
| 2154 | "handover", "stop-ack"; | |
| 2155 | ||
| 2156 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 2157 | clock-names = "xo"; | |
| 2158 | ||
| 2159 | power-domains = <&rpmhpd SM8450_CX>, | |
| 2160 | <&rpmhpd SM8450_MXC>; | |
| 2161 | power-domain-names = "cx", "mxc"; | |
| 2162 | ||
| 2163 | memory-region = <&cdsp_mem>; | |
| 2164 | ||
| 2165 | qcom,qmp = <&aoss_qmp>; | |
| 2166 | ||
| 2167 | qcom,smem-states = <&smp2p_cdsp_out 0>; | |
| 2168 | qcom,smem-state-names = "stop"; | |
| 2169 | ||
| 2170 | status = "disabled"; | |
| 2171 | ||
| 2172 | glink-edge { | |
| 2173 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
| 2174 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 2175 | IRQ_TYPE_EDGE_RISING>; | |
| 2176 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
| 2177 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 2178 | ||
| 2179 | label = "cdsp"; | |
| 2180 | qcom,remote-pid = <5>; | |
| 91d70eb7 DB |
2181 | |
| 2182 | fastrpc { | |
| 2183 | compatible = "qcom,fastrpc"; | |
| 2184 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
| 2185 | label = "cdsp"; | |
| 2186 | #address-cells = <1>; | |
| 2187 | #size-cells = <0>; | |
| 2188 | ||
| 2189 | compute-cb@1 { | |
| 2190 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2191 | reg = <1>; | |
| 2192 | iommus = <&apps_smmu 0x2161 0x0400>, | |
| 2193 | <&apps_smmu 0x1021 0x1420>; | |
| 2194 | }; | |
| 2195 | ||
| 2196 | compute-cb@2 { | |
| 2197 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2198 | reg = <2>; | |
| 2199 | iommus = <&apps_smmu 0x2162 0x0400>, | |
| 2200 | <&apps_smmu 0x1022 0x1420>; | |
| 2201 | }; | |
| 2202 | ||
| 2203 | compute-cb@3 { | |
| 2204 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2205 | reg = <3>; | |
| 2206 | iommus = <&apps_smmu 0x2163 0x0400>, | |
| 2207 | <&apps_smmu 0x1023 0x1420>; | |
| 2208 | }; | |
| 2209 | ||
| 2210 | compute-cb@4 { | |
| 2211 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2212 | reg = <4>; | |
| 2213 | iommus = <&apps_smmu 0x2164 0x0400>, | |
| 2214 | <&apps_smmu 0x1024 0x1420>; | |
| 2215 | }; | |
| 2216 | ||
| 2217 | compute-cb@5 { | |
| 2218 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2219 | reg = <5>; | |
| 2220 | iommus = <&apps_smmu 0x2165 0x0400>, | |
| 2221 | <&apps_smmu 0x1025 0x1420>; | |
| 2222 | }; | |
| 2223 | ||
| 2224 | compute-cb@6 { | |
| 2225 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2226 | reg = <6>; | |
| 2227 | iommus = <&apps_smmu 0x2166 0x0400>, | |
| 2228 | <&apps_smmu 0x1026 0x1420>; | |
| 2229 | }; | |
| 2230 | ||
| 2231 | compute-cb@7 { | |
| 2232 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2233 | reg = <7>; | |
| 2234 | iommus = <&apps_smmu 0x2167 0x0400>, | |
| 2235 | <&apps_smmu 0x1027 0x1420>; | |
| 2236 | }; | |
| 2237 | ||
| 2238 | compute-cb@8 { | |
| 2239 | compatible = "qcom,fastrpc-compute-cb"; | |
| 2240 | reg = <8>; | |
| 2241 | iommus = <&apps_smmu 0x2168 0x0400>, | |
| 2242 | <&apps_smmu 0x1028 0x1420>; | |
| 2243 | }; | |
| 2244 | ||
| 2245 | /* note: secure cb9 in downstream */ | |
| 2246 | }; | |
| 11727295 BA |
2247 | }; |
| 2248 | }; | |
| 2249 | ||
| 2250 | remoteproc_mpss: remoteproc@4080000 { | |
| 2251 | compatible = "qcom,sm8450-mpss-pas"; | |
| 2252 | reg = <0x0 0x04080000 0x0 0x4040>; | |
| 2253 | ||
| 2254 | interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, | |
| 2255 | <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 2256 | <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 2257 | <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 2258 | <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, | |
| 2259 | <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; | |
| 2260 | interrupt-names = "wdog", "fatal", "ready", "handover", | |
| 2261 | "stop-ack", "shutdown-ack"; | |
| 2262 | ||
| 2263 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 2264 | clock-names = "xo"; | |
| 2265 | ||
| 2266 | power-domains = <&rpmhpd 0>, | |
| 2267 | <&rpmhpd 12>; | |
| 2268 | power-domain-names = "cx", "mss"; | |
| 2269 | ||
| 2270 | memory-region = <&mpss_mem>; | |
| 2271 | ||
| 2272 | qcom,qmp = <&aoss_qmp>; | |
| 2273 | ||
| 2274 | qcom,smem-states = <&smp2p_modem_out 0>; | |
| 2275 | qcom,smem-state-names = "stop"; | |
| 2276 | ||
| 2277 | status = "disabled"; | |
| 2278 | ||
| 2279 | glink-edge { | |
| 2280 | interrupts-extended = <&ipcc IPCC_CLIENT_MPSS | |
| 2281 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 2282 | IRQ_TYPE_EDGE_RISING>; | |
| 2283 | mboxes = <&ipcc IPCC_CLIENT_MPSS | |
| 2284 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 2285 | interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; | |
| 2286 | label = "modem"; | |
| 2287 | qcom,remote-pid = <1>; | |
| 2288 | }; | |
| 2289 | }; | |
| 2290 | ||
| 5188049c VK |
2291 | pdc: interrupt-controller@b220000 { |
| 2292 | compatible = "qcom,sm8450-pdc", "qcom,pdc"; | |
| 2293 | reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; | |
| 2294 | qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, | |
| 2295 | <94 609 31>, <125 63 1>, <126 716 12>; | |
| 2296 | #interrupt-cells = <2>; | |
| 2297 | interrupt-parent = <&intc>; | |
| 2298 | interrupt-controller; | |
| 2299 | }; | |
| 2300 | ||
| 48995e86 VZ |
2301 | tsens0: thermal-sensor@c263000 { |
| 2302 | compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; | |
| 2303 | reg = <0 0x0c263000 0 0x1000>, /* TM */ | |
| 2304 | <0 0x0c222000 0 0x1000>; /* SROT */ | |
| 2305 | #qcom,sensors = <16>; | |
| 2306 | interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, | |
| 2307 | <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; | |
| 2308 | interrupt-names = "uplow", "critical"; | |
| 2309 | #thermal-sensor-cells = <1>; | |
| 2310 | }; | |
| 2311 | ||
| 2312 | tsens1: thermal-sensor@c265000 { | |
| 2313 | compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; | |
| 2314 | reg = <0 0x0c265000 0 0x1000>, /* TM */ | |
| 2315 | <0 0x0c223000 0 0x1000>; /* SROT */ | |
| 2316 | #qcom,sensors = <16>; | |
| 2317 | interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, | |
| 2318 | <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; | |
| 2319 | interrupt-names = "uplow", "critical"; | |
| 2320 | #thermal-sensor-cells = <1>; | |
| 2321 | }; | |
| 2322 | ||
| 11727295 BA |
2323 | aoss_qmp: power-controller@c300000 { |
| 2324 | compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; | |
| 2325 | reg = <0 0x0c300000 0 0x400>; | |
| 2326 | interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 2327 | IRQ_TYPE_EDGE_RISING>; | |
| 2328 | mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 2329 | ||
| 2330 | #clock-cells = <0>; | |
| 2331 | }; | |
| 2332 | ||
| 2333 | ipcc: mailbox@ed18000 { | |
| 2334 | compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; | |
| 2335 | reg = <0 0x0ed18000 0 0x1000>; | |
| 2336 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; | |
| 2337 | interrupt-controller; | |
| 2338 | #interrupt-cells = <3>; | |
| 2339 | #mbox-cells = <2>; | |
| 2340 | }; | |
| 2341 | ||
| ec950d55 VK |
2342 | tlmm: pinctrl@f100000 { |
| 2343 | compatible = "qcom,sm8450-tlmm"; | |
| 2344 | reg = <0 0x0f100000 0 0x300000>; | |
| 2345 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
| 2346 | gpio-controller; | |
| 2347 | #gpio-cells = <2>; | |
| 2348 | interrupt-controller; | |
| 2349 | #interrupt-cells = <2>; | |
| 2350 | gpio-ranges = <&tlmm 0 0 211>; | |
| 2351 | wakeup-parent = <&pdc>; | |
| 2352 | ||
| 7b09b1b4 DB |
2353 | pcie0_default_state: pcie0-default-state { |
| 2354 | perst { | |
| 2355 | pins = "gpio94"; | |
| 2356 | function = "gpio"; | |
| 2357 | drive-strength = <2>; | |
| 2358 | bias-pull-down; | |
| 2359 | }; | |
| 2360 | ||
| 2361 | clkreq { | |
| 2362 | pins = "gpio95"; | |
| 2363 | function = "pcie0_clkreqn"; | |
| 2364 | drive-strength = <2>; | |
| 2365 | bias-pull-up; | |
| 2366 | }; | |
| 2367 | ||
| 2368 | wake { | |
| 2369 | pins = "gpio96"; | |
| 2370 | function = "gpio"; | |
| 2371 | drive-strength = <2>; | |
| 2372 | bias-pull-up; | |
| 2373 | }; | |
| 2374 | }; | |
| 2375 | ||
| bc6588bc DB |
2376 | pcie1_default_state: pcie1-default-state { |
| 2377 | perst { | |
| 2378 | pins = "gpio97"; | |
| 2379 | function = "gpio"; | |
| 2380 | drive-strength = <2>; | |
| 2381 | bias-pull-down; | |
| 2382 | }; | |
| 2383 | ||
| 2384 | clkreq { | |
| 2385 | pins = "gpio98"; | |
| 2386 | function = "pcie1_clkreqn"; | |
| 2387 | drive-strength = <2>; | |
| 2388 | bias-pull-up; | |
| 2389 | }; | |
| 2390 | ||
| 2391 | wake { | |
| 2392 | pins = "gpio99"; | |
| 2393 | function = "gpio"; | |
| 2394 | drive-strength = <2>; | |
| 2395 | bias-pull-up; | |
| 2396 | }; | |
| 2397 | }; | |
| 2398 | ||
| a84e88e9 VK |
2399 | qup_i2c0_data_clk: qup-i2c0-data-clk { |
| 2400 | pins = "gpio0", "gpio1"; | |
| 2401 | function = "qup0"; | |
| 2402 | }; | |
| 2403 | ||
| 2404 | qup_i2c1_data_clk: qup-i2c1-data-clk { | |
| 2405 | pins = "gpio4", "gpio5"; | |
| 2406 | function = "qup1"; | |
| 2407 | }; | |
| 2408 | ||
| 2409 | qup_i2c2_data_clk: qup-i2c2-data-clk { | |
| 2410 | pins = "gpio8", "gpio9"; | |
| 2411 | function = "qup2"; | |
| 2412 | }; | |
| 2413 | ||
| 2414 | qup_i2c3_data_clk: qup-i2c3-data-clk { | |
| 2415 | pins = "gpio12", "gpio13"; | |
| 2416 | function = "qup3"; | |
| 2417 | }; | |
| 2418 | ||
| 2419 | qup_i2c4_data_clk: qup-i2c4-data-clk { | |
| 2420 | pins = "gpio16", "gpio17"; | |
| 2421 | function = "qup4"; | |
| 2422 | }; | |
| 2423 | ||
| 2424 | qup_i2c5_data_clk: qup-i2c5-data-clk { | |
| 2425 | pins = "gpio206", "gpio207"; | |
| 2426 | function = "qup5"; | |
| 2427 | }; | |
| 2428 | ||
| 2429 | qup_i2c6_data_clk: qup-i2c6-data-clk { | |
| 2430 | pins = "gpio20", "gpio21"; | |
| 2431 | function = "qup6"; | |
| 2432 | }; | |
| 2433 | ||
| 1a380216 VK |
2434 | qup_i2c8_data_clk: qup-i2c8-data-clk { |
| 2435 | pins = "gpio28", "gpio29"; | |
| 2436 | function = "qup8"; | |
| 2437 | }; | |
| 2438 | ||
| 2439 | qup_i2c9_data_clk: qup-i2c9-data-clk { | |
| 2440 | pins = "gpio32", "gpio33"; | |
| 2441 | function = "qup9"; | |
| 2442 | }; | |
| 2443 | ||
| 2444 | qup_i2c10_data_clk: qup-i2c10-data-clk { | |
| 2445 | pins = "gpio36", "gpio37"; | |
| 2446 | function = "qup10"; | |
| 2447 | }; | |
| 2448 | ||
| 2449 | qup_i2c11_data_clk: qup-i2c11-data-clk { | |
| 2450 | pins = "gpio40", "gpio41"; | |
| 2451 | function = "qup11"; | |
| 2452 | }; | |
| 2453 | ||
| 2454 | qup_i2c12_data_clk: qup-i2c12-data-clk { | |
| 2455 | pins = "gpio44", "gpio45"; | |
| 2456 | function = "qup12"; | |
| 2457 | }; | |
| 2458 | ||
| bf0a257a DB |
2459 | qup_i2c13_data_clk: qup-i2c13-data-clk { |
| 2460 | pins = "gpio48", "gpio49"; | |
| 2461 | function = "qup13"; | |
| 2462 | drive-strength = <2>; | |
| 2463 | bias-pull-up; | |
| 2464 | }; | |
| 2465 | ||
| 2466 | qup_i2c14_data_clk: qup-i2c14-data-clk { | |
| 2467 | pins = "gpio52", "gpio53"; | |
| 2468 | function = "qup14"; | |
| 2469 | drive-strength = <2>; | |
| 2470 | bias-pull-up; | |
| 2471 | }; | |
| 2472 | ||
| ba640cd3 VK |
2473 | qup_i2c15_data_clk: qup-i2c15-data-clk { |
| 2474 | pins = "gpio56", "gpio57"; | |
| 2475 | function = "qup15"; | |
| 2476 | }; | |
| 2477 | ||
| 2478 | qup_i2c16_data_clk: qup-i2c16-data-clk { | |
| 2479 | pins = "gpio60", "gpio61"; | |
| 2480 | function = "qup16"; | |
| 2481 | }; | |
| 2482 | ||
| 2483 | qup_i2c17_data_clk: qup-i2c17-data-clk { | |
| 2484 | pins = "gpio64", "gpio65"; | |
| 2485 | function = "qup17"; | |
| 2486 | }; | |
| 2487 | ||
| 2488 | qup_i2c18_data_clk: qup-i2c18-data-clk { | |
| 2489 | pins = "gpio68", "gpio69"; | |
| 2490 | function = "qup18"; | |
| 2491 | }; | |
| 2492 | ||
| 2493 | qup_i2c19_data_clk: qup-i2c19-data-clk { | |
| 2494 | pins = "gpio72", "gpio73"; | |
| 2495 | function = "qup19"; | |
| 2496 | }; | |
| 2497 | ||
| 2498 | qup_i2c20_data_clk: qup-i2c20-data-clk { | |
| 2499 | pins = "gpio76", "gpio77"; | |
| 2500 | function = "qup20"; | |
| 2501 | }; | |
| 2502 | ||
| 2503 | qup_i2c21_data_clk: qup-i2c21-data-clk { | |
| 2504 | pins = "gpio80", "gpio81"; | |
| 2505 | function = "qup21"; | |
| 2506 | }; | |
| 2507 | ||
| a84e88e9 VK |
2508 | qup_spi0_cs: qup-spi0-cs { |
| 2509 | pins = "gpio3"; | |
| 2510 | function = "qup0"; | |
| 2511 | }; | |
| 2512 | ||
| 2513 | qup_spi0_data_clk: qup-spi0-data-clk { | |
| 2514 | pins = "gpio0", "gpio1", "gpio2"; | |
| 2515 | function = "qup0"; | |
| 2516 | }; | |
| 2517 | ||
| 2518 | qup_spi1_cs: qup-spi1-cs { | |
| 2519 | pins = "gpio7"; | |
| 2520 | function = "qup1"; | |
| 2521 | }; | |
| 2522 | ||
| 2523 | qup_spi1_data_clk: qup-spi1-data-clk { | |
| 2524 | pins = "gpio4", "gpio5", "gpio6"; | |
| 2525 | function = "qup1"; | |
| 2526 | }; | |
| 2527 | ||
| 2528 | qup_spi2_cs: qup-spi2-cs { | |
| 2529 | pins = "gpio11"; | |
| 2530 | function = "qup2"; | |
| 2531 | }; | |
| 2532 | ||
| 2533 | qup_spi2_data_clk: qup-spi2-data-clk { | |
| 2534 | pins = "gpio8", "gpio9", "gpio10"; | |
| 2535 | function = "qup2"; | |
| 2536 | }; | |
| 2537 | ||
| 2538 | qup_spi3_cs: qup-spi3-cs { | |
| 2539 | pins = "gpio15"; | |
| 2540 | function = "qup3"; | |
| 2541 | }; | |
| 2542 | ||
| 2543 | qup_spi3_data_clk: qup-spi3-data-clk { | |
| 2544 | pins = "gpio12", "gpio13", "gpio14"; | |
| 2545 | function = "qup3"; | |
| 2546 | }; | |
| 2547 | ||
| 2548 | qup_spi4_cs: qup-spi4-cs { | |
| 2549 | pins = "gpio19"; | |
| 2550 | function = "qup4"; | |
| 2551 | drive-strength = <6>; | |
| 2552 | bias-disable; | |
| 2553 | }; | |
| 2554 | ||
| 2555 | qup_spi4_data_clk: qup-spi4-data-clk { | |
| 2556 | pins = "gpio16", "gpio17", "gpio18"; | |
| 2557 | function = "qup4"; | |
| 2558 | }; | |
| 2559 | ||
| 2560 | qup_spi5_cs: qup-spi5-cs { | |
| 2561 | pins = "gpio85"; | |
| 2562 | function = "qup5"; | |
| 2563 | }; | |
| 2564 | ||
| 2565 | qup_spi5_data_clk: qup-spi5-data-clk { | |
| 2566 | pins = "gpio206", "gpio207", "gpio84"; | |
| 2567 | function = "qup5"; | |
| 2568 | }; | |
| 2569 | ||
| 2570 | qup_spi6_cs: qup-spi6-cs { | |
| 2571 | pins = "gpio23"; | |
| 2572 | function = "qup6"; | |
| 2573 | }; | |
| 2574 | ||
| 2575 | qup_spi6_data_clk: qup-spi6-data-clk { | |
| 2576 | pins = "gpio20", "gpio21", "gpio22"; | |
| 2577 | function = "qup6"; | |
| 2578 | }; | |
| 2579 | ||
| 1a380216 VK |
2580 | qup_spi8_cs: qup-spi8-cs { |
| 2581 | pins = "gpio31"; | |
| 2582 | function = "qup8"; | |
| 2583 | }; | |
| 2584 | ||
| 2585 | qup_spi8_data_clk: qup-spi8-data-clk { | |
| 2586 | pins = "gpio28", "gpio29", "gpio30"; | |
| 2587 | function = "qup8"; | |
| 2588 | }; | |
| 2589 | ||
| 2590 | qup_spi9_cs: qup-spi9-cs { | |
| 2591 | pins = "gpio35"; | |
| 2592 | function = "qup9"; | |
| 2593 | }; | |
| 2594 | ||
| 2595 | qup_spi9_data_clk: qup-spi9-data-clk { | |
| 2596 | pins = "gpio32", "gpio33", "gpio34"; | |
| 2597 | function = "qup9"; | |
| 2598 | }; | |
| 2599 | ||
| 2600 | qup_spi10_cs: qup-spi10-cs { | |
| 2601 | pins = "gpio39"; | |
| 2602 | function = "qup10"; | |
| 2603 | }; | |
| 2604 | ||
| 2605 | qup_spi10_data_clk: qup-spi10-data-clk { | |
| 2606 | pins = "gpio36", "gpio37", "gpio38"; | |
| 2607 | function = "qup10"; | |
| 2608 | }; | |
| 2609 | ||
| 2610 | qup_spi11_cs: qup-spi11-cs { | |
| 2611 | pins = "gpio43"; | |
| 2612 | function = "qup11"; | |
| 2613 | }; | |
| 2614 | ||
| 2615 | qup_spi11_data_clk: qup-spi11-data-clk { | |
| 2616 | pins = "gpio40", "gpio41", "gpio42"; | |
| 2617 | function = "qup11"; | |
| 2618 | }; | |
| 2619 | ||
| 2620 | qup_spi12_cs: qup-spi12-cs { | |
| 2621 | pins = "gpio47"; | |
| 2622 | function = "qup12"; | |
| 2623 | }; | |
| 2624 | ||
| 2625 | qup_spi12_data_clk: qup-spi12-data-clk { | |
| 2626 | pins = "gpio44", "gpio45", "gpio46"; | |
| 2627 | function = "qup12"; | |
| 2628 | }; | |
| 2629 | ||
| 2630 | qup_spi13_cs: qup-spi13-cs { | |
| 2631 | pins = "gpio51"; | |
| 2632 | function = "qup13"; | |
| 2633 | }; | |
| 2634 | ||
| 2635 | qup_spi13_data_clk: qup-spi13-data-clk { | |
| 2636 | pins = "gpio48", "gpio49", "gpio50"; | |
| 2637 | function = "qup13"; | |
| 2638 | }; | |
| 2639 | ||
| 2640 | qup_spi14_cs: qup-spi14-cs { | |
| 2641 | pins = "gpio55"; | |
| 2642 | function = "qup14"; | |
| 2643 | }; | |
| 2644 | ||
| 2645 | qup_spi14_data_clk: qup-spi14-data-clk { | |
| 2646 | pins = "gpio52", "gpio53", "gpio54"; | |
| 2647 | function = "qup14"; | |
| 2648 | }; | |
| 2649 | ||
| 2650 | qup_spi15_cs: qup-spi15-cs { | |
| 2651 | pins = "gpio59"; | |
| 2652 | function = "qup15"; | |
| 2653 | }; | |
| 2654 | ||
| 2655 | qup_spi15_data_clk: qup-spi15-data-clk { | |
| 2656 | pins = "gpio56", "gpio57", "gpio58"; | |
| 2657 | function = "qup15"; | |
| 2658 | }; | |
| 2659 | ||
| ba640cd3 VK |
2660 | qup_spi16_cs: qup-spi16-cs { |
| 2661 | pins = "gpio63"; | |
| 2662 | function = "qup16"; | |
| 2663 | }; | |
| 2664 | ||
| 2665 | qup_spi16_data_clk: qup-spi16-data-clk { | |
| 2666 | pins = "gpio60", "gpio61", "gpio62"; | |
| 2667 | function = "qup16"; | |
| 2668 | }; | |
| 2669 | ||
| 2670 | qup_spi17_cs: qup-spi17-cs { | |
| 2671 | pins = "gpio67"; | |
| 2672 | function = "qup17"; | |
| 2673 | }; | |
| 2674 | ||
| 2675 | qup_spi17_data_clk: qup-spi17-data-clk { | |
| 2676 | pins = "gpio64", "gpio65", "gpio66"; | |
| 2677 | function = "qup17"; | |
| 2678 | }; | |
| 2679 | ||
| 2680 | qup_spi18_cs: qup-spi18-cs { | |
| 2681 | pins = "gpio71"; | |
| 2682 | function = "qup18"; | |
| 2683 | drive-strength = <6>; | |
| 2684 | bias-disable; | |
| 2685 | }; | |
| 2686 | ||
| 2687 | qup_spi18_data_clk: qup-spi18-data-clk { | |
| 2688 | pins = "gpio68", "gpio69", "gpio70"; | |
| 2689 | function = "qup18"; | |
| 2690 | drive-strength = <6>; | |
| 2691 | bias-disable; | |
| 2692 | }; | |
| 2693 | ||
| 2694 | qup_spi19_cs: qup-spi19-cs { | |
| 2695 | pins = "gpio75"; | |
| 2696 | function = "qup19"; | |
| 2697 | drive-strength = <6>; | |
| 2698 | bias-disable; | |
| 2699 | }; | |
| 2700 | ||
| 2701 | qup_spi19_data_clk: qup-spi19-data-clk { | |
| 2702 | pins = "gpio72", "gpio73", "gpio74"; | |
| 2703 | function = "qup19"; | |
| 2704 | drive-strength = <6>; | |
| 2705 | bias-disable; | |
| 2706 | }; | |
| 2707 | ||
| 2708 | qup_spi20_cs: qup-spi20-cs { | |
| 2709 | pins = "gpio79"; | |
| 2710 | function = "qup20"; | |
| 2711 | }; | |
| 2712 | ||
| 2713 | qup_spi20_data_clk: qup-spi20-data-clk { | |
| 2714 | pins = "gpio76", "gpio77", "gpio78"; | |
| 2715 | function = "qup20"; | |
| 2716 | }; | |
| 2717 | ||
| 2718 | qup_spi21_cs: qup-spi21-cs { | |
| 2719 | pins = "gpio83"; | |
| 2720 | function = "qup21"; | |
| 2721 | }; | |
| 2722 | ||
| 2723 | qup_spi21_data_clk: qup-spi21-data-clk { | |
| 2724 | pins = "gpio80", "gpio81", "gpio82"; | |
| 2725 | function = "qup21"; | |
| 2726 | }; | |
| 2727 | ||
| ec950d55 VK |
2728 | qup_uart7_rx: qup-uart7-rx { |
| 2729 | pins = "gpio26"; | |
| 2730 | function = "qup7"; | |
| 2731 | drive-strength = <2>; | |
| 2732 | bias-disable; | |
| 2733 | }; | |
| 2734 | ||
| 2735 | qup_uart7_tx: qup-uart7-tx { | |
| 2736 | pins = "gpio27"; | |
| 2737 | function = "qup7"; | |
| 2738 | drive-strength = <2>; | |
| 2739 | bias-disable; | |
| 2740 | }; | |
| 2741 | }; | |
| 2742 | ||
| 892d5395 VK |
2743 | apps_smmu: iommu@15000000 { |
| 2744 | compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; | |
| 2745 | reg = <0 0x15000000 0 0x100000>; | |
| 2746 | #iommu-cells = <2>; | |
| 7baa00be | 2747 | #global-interrupts = <1>; |
| 892d5395 VK |
2748 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
| 2749 | <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, | |
| 2750 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, | |
| 2751 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, | |
| 2752 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
| 2753 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, | |
| 2754 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
| 2755 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, | |
| 2756 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
| 2757 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
| 2758 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
| 2759 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| 2760 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
| 2761 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| 2762 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| 2763 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
| 2764 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
| 2765 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
| 2766 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
| 2767 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
| 2768 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 2769 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 2770 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 2771 | <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, | |
| 2772 | <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, | |
| 2773 | <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, | |
| 2774 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, | |
| 2775 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, | |
| 2776 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, | |
| 2777 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, | |
| 2778 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, | |
| 2779 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, | |
| 2780 | <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, | |
| 2781 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, | |
| 2782 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, | |
| 2783 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, | |
| 2784 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, | |
| 2785 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, | |
| 2786 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, | |
| 2787 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, | |
| 2788 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
| 2789 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, | |
| 2790 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, | |
| 2791 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, | |
| 2792 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, | |
| 2793 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, | |
| 2794 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
| 2795 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, | |
| 2796 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, | |
| 2797 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
| 2798 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, | |
| 2799 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, | |
| 2800 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, | |
| 2801 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, | |
| 2802 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
| 2803 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
| 2804 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
| 2805 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
| 2806 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
| 2807 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
| 2808 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
| 2809 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, | |
| 2810 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, | |
| 2811 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, | |
| 2812 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
| 2813 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
| 2814 | <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, | |
| 2815 | <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, | |
| 2816 | <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, | |
| 2817 | <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
| 2818 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
| 2819 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
| 2820 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
| 2821 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
| 2822 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, | |
| 2823 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
| 2824 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, | |
| 2825 | <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, | |
| 2826 | <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, | |
| 2827 | <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, | |
| 2828 | <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, | |
| 2829 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
| 2830 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
| 2831 | <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, | |
| 2832 | <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, | |
| 2833 | <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, | |
| 7baa00be | 2834 | <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, |
| 892d5395 VK |
2835 | <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, |
| 2836 | <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, | |
| 2837 | <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, | |
| 2838 | <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, | |
| 2839 | <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, | |
| 2840 | <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, | |
| 2841 | <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, | |
| 2842 | <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, | |
| 2843 | <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, | |
| 2844 | <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; | |
| 2845 | }; | |
| 2846 | ||
| 5188049c VK |
2847 | intc: interrupt-controller@17100000 { |
| 2848 | compatible = "arm,gic-v3"; | |
| 2849 | #interrupt-cells = <3>; | |
| 2850 | interrupt-controller; | |
| 2851 | #redistributor-regions = <1>; | |
| 2852 | redistributor-stride = <0x0 0x40000>; | |
| 2853 | reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ | |
| 2854 | <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ | |
| 2855 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 2856 | }; | |
| 2857 | ||
| 2858 | timer@17420000 { | |
| 2859 | compatible = "arm,armv7-timer-mem"; | |
| 2860 | #address-cells = <2>; | |
| 2861 | #size-cells = <2>; | |
| 2862 | ranges; | |
| 2863 | reg = <0x0 0x17420000 0x0 0x1000>; | |
| 2864 | clock-frequency = <19200000>; | |
| 2865 | ||
| 2866 | frame@17421000 { | |
| 2867 | frame-number = <0>; | |
| 2868 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
| 2869 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 2870 | reg = <0x0 0x17421000 0x0 0x1000>, | |
| 2871 | <0x0 0x17422000 0x0 0x1000>; | |
| 2872 | }; | |
| 2873 | ||
| 2874 | frame@17423000 { | |
| 2875 | frame-number = <1>; | |
| 2876 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 2877 | reg = <0x0 0x17423000 0x0 0x1000>; | |
| 2878 | status = "disabled"; | |
| 2879 | }; | |
| 2880 | ||
| 2881 | frame@17425000 { | |
| 2882 | frame-number = <2>; | |
| 2883 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 2884 | reg = <0x0 0x17425000 0x0 0x1000>; | |
| 2885 | status = "disabled"; | |
| 2886 | }; | |
| 2887 | ||
| 2888 | frame@17427000 { | |
| 2889 | frame-number = <3>; | |
| 2890 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 2891 | reg = <0x0 0x17427000 0x0 0x1000>; | |
| 2892 | status = "disabled"; | |
| 2893 | }; | |
| 2894 | ||
| 2895 | frame@17429000 { | |
| 2896 | frame-number = <4>; | |
| 2897 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 2898 | reg = <0x0 0x17429000 0x0 0x1000>; | |
| 2899 | status = "disabled"; | |
| 2900 | }; | |
| 2901 | ||
| 2902 | frame@1742b000 { | |
| 2903 | frame-number = <5>; | |
| 2904 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| 2905 | reg = <0x0 0x1742b000 0x0 0x1000>; | |
| 2906 | status = "disabled"; | |
| 2907 | }; | |
| 2908 | ||
| 2909 | frame@1742d000 { | |
| 2910 | frame-number = <6>; | |
| 2911 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 2912 | reg = <0x0 0x1742d000 0x0 0x1000>; | |
| 2913 | status = "disabled"; | |
| 2914 | }; | |
| 2915 | }; | |
| 2916 | ||
| 2917 | apps_rsc: rsc@17a00000 { | |
| 2918 | label = "apps_rsc"; | |
| 2919 | compatible = "qcom,rpmh-rsc"; | |
| 2920 | reg = <0x0 0x17a00000 0x0 0x10000>, | |
| 2921 | <0x0 0x17a10000 0x0 0x10000>, | |
| 2922 | <0x0 0x17a20000 0x0 0x10000>, | |
| 2923 | <0x0 0x17a30000 0x0 0x10000>; | |
| 2924 | reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; | |
| 2925 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
| 2926 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
| 2927 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 2928 | qcom,tcs-offset = <0xd00>; | |
| 2929 | qcom,drv-id = <2>; | |
| 2930 | qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, | |
| 2931 | <WAKE_TCS 2>, <CONTROL_TCS 0>; | |
| 2932 | ||
| 2933 | apps_bcm_voter: bcm-voter { | |
| 2934 | compatible = "qcom,bcm-voter"; | |
| 2935 | }; | |
| 2936 | ||
| 2937 | rpmhcc: clock-controller { | |
| 2938 | compatible = "qcom,sm8450-rpmh-clk"; | |
| 2939 | #clock-cells = <1>; | |
| 2940 | clock-names = "xo"; | |
| 2941 | clocks = <&xo_board>; | |
| 2942 | }; | |
| 61eba74e DB |
2943 | |
| 2944 | rpmhpd: power-controller { | |
| 2945 | compatible = "qcom,sm8450-rpmhpd"; | |
| 2946 | #power-domain-cells = <1>; | |
| 2947 | operating-points-v2 = <&rpmhpd_opp_table>; | |
| 2948 | ||
| 2949 | rpmhpd_opp_table: opp-table { | |
| 2950 | compatible = "operating-points-v2"; | |
| 2951 | ||
| 2952 | rpmhpd_opp_ret: opp1 { | |
| 2953 | opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; | |
| 2954 | }; | |
| 2955 | ||
| 2956 | rpmhpd_opp_min_svs: opp2 { | |
| 2957 | opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; | |
| 2958 | }; | |
| 2959 | ||
| 2960 | rpmhpd_opp_low_svs: opp3 { | |
| 2961 | opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; | |
| 2962 | }; | |
| 2963 | ||
| 2964 | rpmhpd_opp_svs: opp4 { | |
| 2965 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; | |
| 2966 | }; | |
| 2967 | ||
| 2968 | rpmhpd_opp_svs_l1: opp5 { | |
| 2969 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; | |
| 2970 | }; | |
| 2971 | ||
| 2972 | rpmhpd_opp_nom: opp6 { | |
| 2973 | opp-level = <RPMH_REGULATOR_LEVEL_NOM>; | |
| 2974 | }; | |
| 2975 | ||
| 2976 | rpmhpd_opp_nom_l1: opp7 { | |
| 2977 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; | |
| 2978 | }; | |
| 2979 | ||
| 2980 | rpmhpd_opp_nom_l2: opp8 { | |
| 2981 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; | |
| 2982 | }; | |
| 2983 | ||
| 2984 | rpmhpd_opp_turbo: opp9 { | |
| 2985 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; | |
| 2986 | }; | |
| 2987 | ||
| 2988 | rpmhpd_opp_turbo_l1: opp10 { | |
| 2989 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; | |
| 2990 | }; | |
| 2991 | }; | |
| 2992 | }; | |
| 5188049c | 2993 | }; |
| 07fa917a | 2994 | |
| 015a89f0 VZ |
2995 | cpufreq_hw: cpufreq@17d91000 { |
| 2996 | compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; | |
| 2997 | reg = <0 0x17d91000 0 0x1000>, | |
| 2998 | <0 0x17d92000 0 0x1000>, | |
| 2999 | <0 0x17d93000 0 0x1000>; | |
| 3000 | reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; | |
| 3001 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; | |
| 3002 | clock-names = "xo", "alternate"; | |
| 3003 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, | |
| 3004 | <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, | |
| 3005 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
| 3006 | interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; | |
| 3007 | #freq-domain-cells = <1>; | |
| 3008 | }; | |
| 3009 | ||
| aa2d0bf0 VK |
3010 | gem_noc: interconnect@19100000 { |
| 3011 | compatible = "qcom,sm8450-gem-noc"; | |
| 3012 | reg = <0 0x19100000 0 0xbb800>; | |
| 3013 | #interconnect-cells = <2>; | |
| 3014 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 3015 | }; | |
| 3016 | ||
| 1dc3e50e SPR |
3017 | system-cache-controller@19200000 { |
| 3018 | compatible = "qcom,sm8450-llcc"; | |
| 3019 | reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; | |
| 3020 | reg-names = "llcc_base", "llcc_broadcast_base"; | |
| 3021 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; | |
| 3022 | }; | |
| 3023 | ||
| 07fa917a VK |
3024 | ufs_mem_hc: ufshc@1d84000 { |
| 3025 | compatible = "qcom,sm8450-ufshc", "qcom,ufshc", | |
| 3026 | "jedec,ufs-2.0"; | |
| 3027 | reg = <0 0x01d84000 0 0x3000>; | |
| 3028 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; | |
| 3029 | phys = <&ufs_mem_phy_lanes>; | |
| 3030 | phy-names = "ufsphy"; | |
| 3031 | lanes-per-direction = <2>; | |
| 3032 | #reset-cells = <1>; | |
| 3033 | resets = <&gcc GCC_UFS_PHY_BCR>; | |
| 3034 | reset-names = "rst"; | |
| 3035 | ||
| 3036 | power-domains = <&gcc UFS_PHY_GDSC>; | |
| 3037 | ||
| 3038 | iommus = <&apps_smmu 0xe0 0x0>; | |
| 3039 | ||
| aa2d0bf0 VK |
3040 | interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, |
| 3041 | <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; | |
| 3042 | interconnect-names = "ufs-ddr", "cpu-ufs"; | |
| 07fa917a VK |
3043 | clock-names = |
| 3044 | "core_clk", | |
| 3045 | "bus_aggr_clk", | |
| 3046 | "iface_clk", | |
| 3047 | "core_clk_unipro", | |
| 3048 | "ref_clk", | |
| 3049 | "tx_lane0_sync_clk", | |
| 3050 | "rx_lane0_sync_clk", | |
| 3051 | "rx_lane1_sync_clk"; | |
| 3052 | clocks = | |
| 3053 | <&gcc GCC_UFS_PHY_AXI_CLK>, | |
| 3054 | <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
| 3055 | <&gcc GCC_UFS_PHY_AHB_CLK>, | |
| 3056 | <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, | |
| 3057 | <&rpmhcc RPMH_CXO_CLK>, | |
| 3058 | <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, | |
| 3059 | <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, | |
| 3060 | <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; | |
| 3061 | freq-table-hz = | |
| 3062 | <75000000 300000000>, | |
| 3063 | <0 0>, | |
| 3064 | <0 0>, | |
| 3065 | <75000000 300000000>, | |
| 3066 | <75000000 300000000>, | |
| 3067 | <0 0>, | |
| 3068 | <0 0>, | |
| 3069 | <0 0>; | |
| 3070 | status = "disabled"; | |
| 3071 | }; | |
| 3072 | ||
| 3073 | ufs_mem_phy: phy@1d87000 { | |
| 3074 | compatible = "qcom,sm8450-qmp-ufs-phy"; | |
| 3075 | reg = <0 0x01d87000 0 0xe10>; | |
| 3076 | #address-cells = <2>; | |
| 3077 | #size-cells = <2>; | |
| 3078 | ranges; | |
| 3079 | clock-names = "ref", "ref_aux", "qref"; | |
| 3080 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
| 3081 | <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, | |
| 3082 | <&gcc GCC_UFS_0_CLKREF_EN>; | |
| 3083 | ||
| 3084 | resets = <&ufs_mem_hc 0>; | |
| 3085 | reset-names = "ufsphy"; | |
| 3086 | status = "disabled"; | |
| 3087 | ||
| c769a352 | 3088 | ufs_mem_phy_lanes: phy@1d87400 { |
| 07fa917a VK |
3089 | reg = <0 0x01d87400 0 0x108>, |
| 3090 | <0 0x01d87600 0 0x1e0>, | |
| 3091 | <0 0x01d87c00 0 0x1dc>, | |
| 3092 | <0 0x01d87800 0 0x108>, | |
| 3093 | <0 0x01d87a00 0 0x1e0>; | |
| 3094 | #phy-cells = <0>; | |
| 3095 | #clock-cells = <0>; | |
| 3096 | }; | |
| 3097 | }; | |
| 19fd04fb VK |
3098 | |
| 3099 | usb_1: usb@a6f8800 { | |
| 3100 | compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; | |
| 3101 | reg = <0 0x0a6f8800 0 0x400>; | |
| 3102 | status = "disabled"; | |
| 3103 | #address-cells = <2>; | |
| 3104 | #size-cells = <2>; | |
| 3105 | ranges; | |
| 3106 | ||
| 3107 | clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, | |
| 3108 | <&gcc GCC_USB30_PRIM_MASTER_CLK>, | |
| 3109 | <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, | |
| 197769fe | 3110 | <&gcc GCC_USB30_PRIM_SLEEP_CLK>, |
| 54c2cc79 | 3111 | <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| 197769fe | 3112 | <&gcc GCC_USB3_0_CLKREF_EN>; |
| 54c2cc79 LT |
3113 | clock-names = "cfg_noc", |
| 3114 | "core", | |
| 3115 | "iface", | |
| 3116 | "sleep", | |
| 3117 | "mock_utmi", | |
| 3118 | "xo"; | |
| 19fd04fb VK |
3119 | |
| 3120 | assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, | |
| 3121 | <&gcc GCC_USB30_PRIM_MASTER_CLK>; | |
| 3122 | assigned-clock-rates = <19200000>, <200000000>; | |
| 3123 | ||
| 3124 | interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
| 54c2cc79 | 3125 | <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, |
| 19fd04fb | 3126 | <&pdc 15 IRQ_TYPE_EDGE_BOTH>, |
| 54c2cc79 LT |
3127 | <&pdc 14 IRQ_TYPE_EDGE_BOTH>; |
| 3128 | interrupt-names = "hs_phy_irq", | |
| 3129 | "ss_phy_irq", | |
| 3130 | "dm_hs_phy_irq", | |
| 3131 | "dp_hs_phy_irq"; | |
| 19fd04fb VK |
3132 | |
| 3133 | power-domains = <&gcc USB30_PRIM_GDSC>; | |
| 3134 | ||
| 3135 | resets = <&gcc GCC_USB30_PRIM_BCR>; | |
| 3136 | ||
| 3137 | usb_1_dwc3: usb@a600000 { | |
| 3138 | compatible = "snps,dwc3"; | |
| 3139 | reg = <0 0x0a600000 0 0xcd00>; | |
| 3140 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
| 3141 | iommus = <&apps_smmu 0x0 0x0>; | |
| 3142 | snps,dis_u2_susphy_quirk; | |
| 3143 | snps,dis_enblslpm_quirk; | |
| 3144 | phys = <&usb_1_hsphy>, <&usb_1_ssphy>; | |
| 3145 | phy-names = "usb2-phy", "usb3-phy"; | |
| 3146 | }; | |
| 3147 | }; | |
| aa2d0bf0 VK |
3148 | |
| 3149 | nsp_noc: interconnect@320c0000 { | |
| 3150 | compatible = "qcom,sm8450-nsp-noc"; | |
| 3151 | reg = <0 0x320c0000 0 0x10000>; | |
| 3152 | #interconnect-cells = <2>; | |
| 3153 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 3154 | }; | |
| 3155 | ||
| 3156 | lpass_ag_noc: interconnect@3c40000 { | |
| 3157 | compatible = "qcom,sm8450-lpass-ag-noc"; | |
| 3158 | reg = <0 0x3c40000 0 0x17200>; | |
| 3159 | #interconnect-cells = <2>; | |
| 3160 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 3161 | }; | |
| 5188049c VK |
3162 | }; |
| 3163 | ||
| fccf8e31 VZ |
3164 | thermal-zones { |
| 3165 | aoss0-thermal { | |
| 3166 | polling-delay-passive = <0>; | |
| 3167 | polling-delay = <0>; | |
| 3168 | thermal-sensors = <&tsens0 0>; | |
| 3169 | ||
| 3170 | trips { | |
| 3171 | thermal-engine-config { | |
| 3172 | temperature = <125000>; | |
| 3173 | hysteresis = <1000>; | |
| 3174 | type = "passive"; | |
| 3175 | }; | |
| 3176 | ||
| 3177 | reset-mon-cfg { | |
| 3178 | temperature = <115000>; | |
| 3179 | hysteresis = <5000>; | |
| 3180 | type = "passive"; | |
| 3181 | }; | |
| 3182 | }; | |
| 3183 | }; | |
| 3184 | ||
| 3185 | cpuss0-thermal { | |
| 3186 | polling-delay-passive = <0>; | |
| 3187 | polling-delay = <0>; | |
| 3188 | thermal-sensors = <&tsens0 1>; | |
| 3189 | ||
| 3190 | trips { | |
| 3191 | thermal-engine-config { | |
| 3192 | temperature = <125000>; | |
| 3193 | hysteresis = <1000>; | |
| 3194 | type = "passive"; | |
| 3195 | }; | |
| 3196 | ||
| 3197 | reset-mon-cfg { | |
| 3198 | temperature = <115000>; | |
| 3199 | hysteresis = <5000>; | |
| 3200 | type = "passive"; | |
| 3201 | }; | |
| 3202 | }; | |
| 3203 | }; | |
| 3204 | ||
| 3205 | cpuss1-thermal { | |
| 3206 | polling-delay-passive = <0>; | |
| 3207 | polling-delay = <0>; | |
| 3208 | thermal-sensors = <&tsens0 2>; | |
| 3209 | ||
| 3210 | trips { | |
| 3211 | thermal-engine-config { | |
| 3212 | temperature = <125000>; | |
| 3213 | hysteresis = <1000>; | |
| 3214 | type = "passive"; | |
| 3215 | }; | |
| 3216 | ||
| 3217 | reset-mon-cfg { | |
| 3218 | temperature = <115000>; | |
| 3219 | hysteresis = <5000>; | |
| 3220 | type = "passive"; | |
| 3221 | }; | |
| 3222 | }; | |
| 3223 | }; | |
| 3224 | ||
| 3225 | cpuss3-thermal { | |
| 3226 | polling-delay-passive = <0>; | |
| 3227 | polling-delay = <0>; | |
| 3228 | thermal-sensors = <&tsens0 3>; | |
| 3229 | ||
| 3230 | trips { | |
| 3231 | thermal-engine-config { | |
| 3232 | temperature = <125000>; | |
| 3233 | hysteresis = <1000>; | |
| 3234 | type = "passive"; | |
| 3235 | }; | |
| 3236 | ||
| 3237 | reset-mon-cfg { | |
| 3238 | temperature = <115000>; | |
| 3239 | hysteresis = <5000>; | |
| 3240 | type = "passive"; | |
| 3241 | }; | |
| 3242 | }; | |
| 3243 | }; | |
| 3244 | ||
| 3245 | cpuss4-thermal { | |
| 3246 | polling-delay-passive = <0>; | |
| 3247 | polling-delay = <0>; | |
| 3248 | thermal-sensors = <&tsens0 4>; | |
| 3249 | ||
| 3250 | trips { | |
| 3251 | thermal-engine-config { | |
| 3252 | temperature = <125000>; | |
| 3253 | hysteresis = <1000>; | |
| 3254 | type = "passive"; | |
| 3255 | }; | |
| 3256 | ||
| 3257 | reset-mon-cfg { | |
| 3258 | temperature = <115000>; | |
| 3259 | hysteresis = <5000>; | |
| 3260 | type = "passive"; | |
| 3261 | }; | |
| 3262 | }; | |
| 3263 | }; | |
| 3264 | ||
| 3265 | cpu4-top-thermal { | |
| 3266 | polling-delay-passive = <0>; | |
| 3267 | polling-delay = <0>; | |
| 3268 | thermal-sensors = <&tsens0 5>; | |
| 3269 | ||
| 3270 | trips { | |
| 3271 | cpu4_top_alert0: trip-point0 { | |
| 3272 | temperature = <90000>; | |
| 3273 | hysteresis = <2000>; | |
| 3274 | type = "passive"; | |
| 3275 | }; | |
| 3276 | ||
| 3277 | cpu4_top_alert1: trip-point1 { | |
| 3278 | temperature = <95000>; | |
| 3279 | hysteresis = <2000>; | |
| 3280 | type = "passive"; | |
| 3281 | }; | |
| 3282 | ||
| 3283 | cpu4_top_crit: cpu_crit { | |
| 3284 | temperature = <110000>; | |
| 3285 | hysteresis = <1000>; | |
| 3286 | type = "critical"; | |
| 3287 | }; | |
| 3288 | }; | |
| 3289 | }; | |
| 3290 | ||
| 3291 | cpu4-bottom-thermal { | |
| 3292 | polling-delay-passive = <0>; | |
| 3293 | polling-delay = <0>; | |
| 3294 | thermal-sensors = <&tsens0 6>; | |
| 3295 | ||
| 3296 | trips { | |
| 3297 | cpu4_bottom_alert0: trip-point0 { | |
| 3298 | temperature = <90000>; | |
| 3299 | hysteresis = <2000>; | |
| 3300 | type = "passive"; | |
| 3301 | }; | |
| 3302 | ||
| 3303 | cpu4_bottom_alert1: trip-point1 { | |
| 3304 | temperature = <95000>; | |
| 3305 | hysteresis = <2000>; | |
| 3306 | type = "passive"; | |
| 3307 | }; | |
| 3308 | ||
| 3309 | cpu4_bottom_crit: cpu_crit { | |
| 3310 | temperature = <110000>; | |
| 3311 | hysteresis = <1000>; | |
| 3312 | type = "critical"; | |
| 3313 | }; | |
| 3314 | }; | |
| 3315 | }; | |
| 3316 | ||
| 3317 | cpu5-top-thermal { | |
| 3318 | polling-delay-passive = <0>; | |
| 3319 | polling-delay = <0>; | |
| 3320 | thermal-sensors = <&tsens0 7>; | |
| 3321 | ||
| 3322 | trips { | |
| 3323 | cpu5_top_alert0: trip-point0 { | |
| 3324 | temperature = <90000>; | |
| 3325 | hysteresis = <2000>; | |
| 3326 | type = "passive"; | |
| 3327 | }; | |
| 3328 | ||
| 3329 | cpu5_top_alert1: trip-point1 { | |
| 3330 | temperature = <95000>; | |
| 3331 | hysteresis = <2000>; | |
| 3332 | type = "passive"; | |
| 3333 | }; | |
| 3334 | ||
| 3335 | cpu5_top_crit: cpu_crit { | |
| 3336 | temperature = <110000>; | |
| 3337 | hysteresis = <1000>; | |
| 3338 | type = "critical"; | |
| 3339 | }; | |
| 3340 | }; | |
| 3341 | }; | |
| 3342 | ||
| 3343 | cpu5-bottom-thermal { | |
| 3344 | polling-delay-passive = <0>; | |
| 3345 | polling-delay = <0>; | |
| 3346 | thermal-sensors = <&tsens0 8>; | |
| 3347 | ||
| 3348 | trips { | |
| 3349 | cpu5_bottom_alert0: trip-point0 { | |
| 3350 | temperature = <90000>; | |
| 3351 | hysteresis = <2000>; | |
| 3352 | type = "passive"; | |
| 3353 | }; | |
| 3354 | ||
| 3355 | cpu5_bottom_alert1: trip-point1 { | |
| 3356 | temperature = <95000>; | |
| 3357 | hysteresis = <2000>; | |
| 3358 | type = "passive"; | |
| 3359 | }; | |
| 3360 | ||
| 3361 | cpu5_bottom_crit: cpu_crit { | |
| 3362 | temperature = <110000>; | |
| 3363 | hysteresis = <1000>; | |
| 3364 | type = "critical"; | |
| 3365 | }; | |
| 3366 | }; | |
| 3367 | }; | |
| 3368 | ||
| 3369 | cpu6-top-thermal { | |
| 3370 | polling-delay-passive = <0>; | |
| 3371 | polling-delay = <0>; | |
| 3372 | thermal-sensors = <&tsens0 9>; | |
| 3373 | ||
| 3374 | trips { | |
| 3375 | cpu6_top_alert0: trip-point0 { | |
| 3376 | temperature = <90000>; | |
| 3377 | hysteresis = <2000>; | |
| 3378 | type = "passive"; | |
| 3379 | }; | |
| 3380 | ||
| 3381 | cpu6_top_alert1: trip-point1 { | |
| 3382 | temperature = <95000>; | |
| 3383 | hysteresis = <2000>; | |
| 3384 | type = "passive"; | |
| 3385 | }; | |
| 3386 | ||
| 3387 | cpu6_top_crit: cpu_crit { | |
| 3388 | temperature = <110000>; | |
| 3389 | hysteresis = <1000>; | |
| 3390 | type = "critical"; | |
| 3391 | }; | |
| 3392 | }; | |
| 3393 | }; | |
| 3394 | ||
| 3395 | cpu6-bottom-thermal { | |
| 3396 | polling-delay-passive = <0>; | |
| 3397 | polling-delay = <0>; | |
| 3398 | thermal-sensors = <&tsens0 10>; | |
| 3399 | ||
| 3400 | trips { | |
| 3401 | cpu6_bottom_alert0: trip-point0 { | |
| 3402 | temperature = <90000>; | |
| 3403 | hysteresis = <2000>; | |
| 3404 | type = "passive"; | |
| 3405 | }; | |
| 3406 | ||
| 3407 | cpu6_bottom_alert1: trip-point1 { | |
| 3408 | temperature = <95000>; | |
| 3409 | hysteresis = <2000>; | |
| 3410 | type = "passive"; | |
| 3411 | }; | |
| 3412 | ||
| 3413 | cpu6_bottom_crit: cpu_crit { | |
| 3414 | temperature = <110000>; | |
| 3415 | hysteresis = <1000>; | |
| 3416 | type = "critical"; | |
| 3417 | }; | |
| 3418 | }; | |
| 3419 | }; | |
| 3420 | ||
| 3421 | cpu7-top-thermal { | |
| 3422 | polling-delay-passive = <0>; | |
| 3423 | polling-delay = <0>; | |
| 3424 | thermal-sensors = <&tsens0 11>; | |
| 3425 | ||
| 3426 | trips { | |
| 3427 | cpu7_top_alert0: trip-point0 { | |
| 3428 | temperature = <90000>; | |
| 3429 | hysteresis = <2000>; | |
| 3430 | type = "passive"; | |
| 3431 | }; | |
| 3432 | ||
| 3433 | cpu7_top_alert1: trip-point1 { | |
| 3434 | temperature = <95000>; | |
| 3435 | hysteresis = <2000>; | |
| 3436 | type = "passive"; | |
| 3437 | }; | |
| 3438 | ||
| 3439 | cpu7_top_crit: cpu_crit { | |
| 3440 | temperature = <110000>; | |
| 3441 | hysteresis = <1000>; | |
| 3442 | type = "critical"; | |
| 3443 | }; | |
| 3444 | }; | |
| 3445 | }; | |
| 3446 | ||
| 3447 | cpu7-middle-thermal { | |
| 3448 | polling-delay-passive = <0>; | |
| 3449 | polling-delay = <0>; | |
| 3450 | thermal-sensors = <&tsens0 12>; | |
| 3451 | ||
| 3452 | trips { | |
| 3453 | cpu7_middle_alert0: trip-point0 { | |
| 3454 | temperature = <90000>; | |
| 3455 | hysteresis = <2000>; | |
| 3456 | type = "passive"; | |
| 3457 | }; | |
| 3458 | ||
| 3459 | cpu7_middle_alert1: trip-point1 { | |
| 3460 | temperature = <95000>; | |
| 3461 | hysteresis = <2000>; | |
| 3462 | type = "passive"; | |
| 3463 | }; | |
| 3464 | ||
| 3465 | cpu7_middle_crit: cpu_crit { | |
| 3466 | temperature = <110000>; | |
| 3467 | hysteresis = <1000>; | |
| 3468 | type = "critical"; | |
| 3469 | }; | |
| 3470 | }; | |
| 3471 | }; | |
| 3472 | ||
| 3473 | cpu7-bottom-thermal { | |
| 3474 | polling-delay-passive = <0>; | |
| 3475 | polling-delay = <0>; | |
| 3476 | thermal-sensors = <&tsens0 13>; | |
| 3477 | ||
| 3478 | trips { | |
| 3479 | cpu7_bottom_alert0: trip-point0 { | |
| 3480 | temperature = <90000>; | |
| 3481 | hysteresis = <2000>; | |
| 3482 | type = "passive"; | |
| 3483 | }; | |
| 3484 | ||
| 3485 | cpu7_bottom_alert1: trip-point1 { | |
| 3486 | temperature = <95000>; | |
| 3487 | hysteresis = <2000>; | |
| 3488 | type = "passive"; | |
| 3489 | }; | |
| 3490 | ||
| 3491 | cpu7_bottom_crit: cpu_crit { | |
| 3492 | temperature = <110000>; | |
| 3493 | hysteresis = <1000>; | |
| 3494 | type = "critical"; | |
| 3495 | }; | |
| 3496 | }; | |
| 3497 | }; | |
| 3498 | ||
| 3499 | gpu-top-thermal { | |
| 3500 | polling-delay-passive = <10>; | |
| 3501 | polling-delay = <0>; | |
| 3502 | thermal-sensors = <&tsens0 14>; | |
| 3503 | ||
| 3504 | trips { | |
| 3505 | thermal-engine-config { | |
| 3506 | temperature = <125000>; | |
| 3507 | hysteresis = <1000>; | |
| 3508 | type = "passive"; | |
| 3509 | }; | |
| 3510 | ||
| 3511 | thermal-hal-config { | |
| 3512 | temperature = <125000>; | |
| 3513 | hysteresis = <1000>; | |
| 3514 | type = "passive"; | |
| 3515 | }; | |
| 3516 | ||
| 3517 | reset-mon-cfg { | |
| 3518 | temperature = <115000>; | |
| 3519 | hysteresis = <5000>; | |
| 3520 | type = "passive"; | |
| 3521 | }; | |
| 3522 | ||
| 3523 | gpu0_tj_cfg: tj_cfg { | |
| 3524 | temperature = <95000>; | |
| 3525 | hysteresis = <5000>; | |
| 3526 | type = "passive"; | |
| 3527 | }; | |
| 3528 | }; | |
| 3529 | }; | |
| 3530 | ||
| 3531 | gpu-bottom-thermal { | |
| 3532 | polling-delay-passive = <10>; | |
| 3533 | polling-delay = <0>; | |
| 3534 | thermal-sensors = <&tsens0 15>; | |
| 3535 | ||
| 3536 | trips { | |
| 3537 | thermal-engine-config { | |
| 3538 | temperature = <125000>; | |
| 3539 | hysteresis = <1000>; | |
| 3540 | type = "passive"; | |
| 3541 | }; | |
| 3542 | ||
| 3543 | thermal-hal-config { | |
| 3544 | temperature = <125000>; | |
| 3545 | hysteresis = <1000>; | |
| 3546 | type = "passive"; | |
| 3547 | }; | |
| 3548 | ||
| 3549 | reset-mon-cfg { | |
| 3550 | temperature = <115000>; | |
| 3551 | hysteresis = <5000>; | |
| 3552 | type = "passive"; | |
| 3553 | }; | |
| 3554 | ||
| 3555 | gpu1_tj_cfg: tj_cfg { | |
| 3556 | temperature = <95000>; | |
| 3557 | hysteresis = <5000>; | |
| 3558 | type = "passive"; | |
| 3559 | }; | |
| 3560 | }; | |
| 3561 | }; | |
| 3562 | ||
| 3563 | aoss1-thermal { | |
| 3564 | polling-delay-passive = <0>; | |
| 3565 | polling-delay = <0>; | |
| 3566 | thermal-sensors = <&tsens1 0>; | |
| 3567 | ||
| 3568 | trips { | |
| 3569 | thermal-engine-config { | |
| 3570 | temperature = <125000>; | |
| 3571 | hysteresis = <1000>; | |
| 3572 | type = "passive"; | |
| 3573 | }; | |
| 3574 | ||
| 3575 | reset-mon-cfg { | |
| 3576 | temperature = <115000>; | |
| 3577 | hysteresis = <5000>; | |
| 3578 | type = "passive"; | |
| 3579 | }; | |
| 3580 | }; | |
| 3581 | }; | |
| 3582 | ||
| 3583 | cpu0-thermal { | |
| 3584 | polling-delay-passive = <0>; | |
| 3585 | polling-delay = <0>; | |
| 3586 | thermal-sensors = <&tsens1 1>; | |
| 3587 | ||
| 3588 | trips { | |
| 3589 | cpu0_alert0: trip-point0 { | |
| 3590 | temperature = <90000>; | |
| 3591 | hysteresis = <2000>; | |
| 3592 | type = "passive"; | |
| 3593 | }; | |
| 3594 | ||
| 3595 | cpu0_alert1: trip-point1 { | |
| 3596 | temperature = <95000>; | |
| 3597 | hysteresis = <2000>; | |
| 3598 | type = "passive"; | |
| 3599 | }; | |
| 3600 | ||
| 3601 | cpu0_crit: cpu_crit { | |
| 3602 | temperature = <110000>; | |
| 3603 | hysteresis = <1000>; | |
| 3604 | type = "critical"; | |
| 3605 | }; | |
| 3606 | }; | |
| 3607 | }; | |
| 3608 | ||
| 3609 | cpu1-thermal { | |
| 3610 | polling-delay-passive = <0>; | |
| 3611 | polling-delay = <0>; | |
| 3612 | thermal-sensors = <&tsens1 2>; | |
| 3613 | ||
| 3614 | trips { | |
| 3615 | cpu1_alert0: trip-point0 { | |
| 3616 | temperature = <90000>; | |
| 3617 | hysteresis = <2000>; | |
| 3618 | type = "passive"; | |
| 3619 | }; | |
| 3620 | ||
| 3621 | cpu1_alert1: trip-point1 { | |
| 3622 | temperature = <95000>; | |
| 3623 | hysteresis = <2000>; | |
| 3624 | type = "passive"; | |
| 3625 | }; | |
| 3626 | ||
| 3627 | cpu1_crit: cpu_crit { | |
| 3628 | temperature = <110000>; | |
| 3629 | hysteresis = <1000>; | |
| 3630 | type = "critical"; | |
| 3631 | }; | |
| 3632 | }; | |
| 3633 | }; | |
| 3634 | ||
| 3635 | cpu2-thermal { | |
| 3636 | polling-delay-passive = <0>; | |
| 3637 | polling-delay = <0>; | |
| 3638 | thermal-sensors = <&tsens1 3>; | |
| 3639 | ||
| 3640 | trips { | |
| 3641 | cpu2_alert0: trip-point0 { | |
| 3642 | temperature = <90000>; | |
| 3643 | hysteresis = <2000>; | |
| 3644 | type = "passive"; | |
| 3645 | }; | |
| 3646 | ||
| 3647 | cpu2_alert1: trip-point1 { | |
| 3648 | temperature = <95000>; | |
| 3649 | hysteresis = <2000>; | |
| 3650 | type = "passive"; | |
| 3651 | }; | |
| 3652 | ||
| 3653 | cpu2_crit: cpu_crit { | |
| 3654 | temperature = <110000>; | |
| 3655 | hysteresis = <1000>; | |
| 3656 | type = "critical"; | |
| 3657 | }; | |
| 3658 | }; | |
| 3659 | }; | |
| 3660 | ||
| 3661 | cpu3-thermal { | |
| 3662 | polling-delay-passive = <0>; | |
| 3663 | polling-delay = <0>; | |
| 3664 | thermal-sensors = <&tsens1 4>; | |
| 3665 | ||
| 3666 | trips { | |
| 3667 | cpu3_alert0: trip-point0 { | |
| 3668 | temperature = <90000>; | |
| 3669 | hysteresis = <2000>; | |
| 3670 | type = "passive"; | |
| 3671 | }; | |
| 3672 | ||
| 3673 | cpu3_alert1: trip-point1 { | |
| 3674 | temperature = <95000>; | |
| 3675 | hysteresis = <2000>; | |
| 3676 | type = "passive"; | |
| 3677 | }; | |
| 3678 | ||
| 3679 | cpu3_crit: cpu_crit { | |
| 3680 | temperature = <110000>; | |
| 3681 | hysteresis = <1000>; | |
| 3682 | type = "critical"; | |
| 3683 | }; | |
| 3684 | }; | |
| 3685 | }; | |
| 3686 | ||
| 3687 | cdsp0-thermal { | |
| 3688 | polling-delay-passive = <10>; | |
| 3689 | polling-delay = <0>; | |
| 3690 | thermal-sensors = <&tsens1 5>; | |
| 3691 | ||
| 3692 | trips { | |
| 3693 | thermal-engine-config { | |
| 3694 | temperature = <125000>; | |
| 3695 | hysteresis = <1000>; | |
| 3696 | type = "passive"; | |
| 3697 | }; | |
| 3698 | ||
| 3699 | thermal-hal-config { | |
| 3700 | temperature = <125000>; | |
| 3701 | hysteresis = <1000>; | |
| 3702 | type = "passive"; | |
| 3703 | }; | |
| 3704 | ||
| 3705 | reset-mon-cfg { | |
| 3706 | temperature = <115000>; | |
| 3707 | hysteresis = <5000>; | |
| 3708 | type = "passive"; | |
| 3709 | }; | |
| 3710 | ||
| 3711 | cdsp_0_config: junction-config { | |
| 3712 | temperature = <95000>; | |
| 3713 | hysteresis = <5000>; | |
| 3714 | type = "passive"; | |
| 3715 | }; | |
| 3716 | }; | |
| 3717 | }; | |
| 3718 | ||
| 3719 | cdsp1-thermal { | |
| 3720 | polling-delay-passive = <10>; | |
| 3721 | polling-delay = <0>; | |
| 3722 | thermal-sensors = <&tsens1 6>; | |
| 3723 | ||
| 3724 | trips { | |
| 3725 | thermal-engine-config { | |
| 3726 | temperature = <125000>; | |
| 3727 | hysteresis = <1000>; | |
| 3728 | type = "passive"; | |
| 3729 | }; | |
| 3730 | ||
| 3731 | thermal-hal-config { | |
| 3732 | temperature = <125000>; | |
| 3733 | hysteresis = <1000>; | |
| 3734 | type = "passive"; | |
| 3735 | }; | |
| 3736 | ||
| 3737 | reset-mon-cfg { | |
| 3738 | temperature = <115000>; | |
| 3739 | hysteresis = <5000>; | |
| 3740 | type = "passive"; | |
| 3741 | }; | |
| 3742 | ||
| 3743 | cdsp_1_config: junction-config { | |
| 3744 | temperature = <95000>; | |
| 3745 | hysteresis = <5000>; | |
| 3746 | type = "passive"; | |
| 3747 | }; | |
| 3748 | }; | |
| 3749 | }; | |
| 3750 | ||
| 3751 | cdsp2-thermal { | |
| 3752 | polling-delay-passive = <10>; | |
| 3753 | polling-delay = <0>; | |
| 3754 | thermal-sensors = <&tsens1 7>; | |
| 3755 | ||
| 3756 | trips { | |
| 3757 | thermal-engine-config { | |
| 3758 | temperature = <125000>; | |
| 3759 | hysteresis = <1000>; | |
| 3760 | type = "passive"; | |
| 3761 | }; | |
| 3762 | ||
| 3763 | thermal-hal-config { | |
| 3764 | temperature = <125000>; | |
| 3765 | hysteresis = <1000>; | |
| 3766 | type = "passive"; | |
| 3767 | }; | |
| 3768 | ||
| 3769 | reset-mon-cfg { | |
| 3770 | temperature = <115000>; | |
| 3771 | hysteresis = <5000>; | |
| 3772 | type = "passive"; | |
| 3773 | }; | |
| 3774 | ||
| 3775 | cdsp_2_config: junction-config { | |
| 3776 | temperature = <95000>; | |
| 3777 | hysteresis = <5000>; | |
| 3778 | type = "passive"; | |
| 3779 | }; | |
| 3780 | }; | |
| 3781 | }; | |
| 3782 | ||
| 3783 | video-thermal { | |
| 3784 | polling-delay-passive = <0>; | |
| 3785 | polling-delay = <0>; | |
| 3786 | thermal-sensors = <&tsens1 8>; | |
| 3787 | ||
| 3788 | trips { | |
| 3789 | thermal-engine-config { | |
| 3790 | temperature = <125000>; | |
| 3791 | hysteresis = <1000>; | |
| 3792 | type = "passive"; | |
| 3793 | }; | |
| 3794 | ||
| 3795 | reset-mon-cfg { | |
| 3796 | temperature = <115000>; | |
| 3797 | hysteresis = <5000>; | |
| 3798 | type = "passive"; | |
| 3799 | }; | |
| 3800 | }; | |
| 3801 | }; | |
| 3802 | ||
| 3803 | mem-thermal { | |
| 3804 | polling-delay-passive = <10>; | |
| 3805 | polling-delay = <0>; | |
| 3806 | thermal-sensors = <&tsens1 9>; | |
| 3807 | ||
| 3808 | trips { | |
| 3809 | thermal-engine-config { | |
| 3810 | temperature = <125000>; | |
| 3811 | hysteresis = <1000>; | |
| 3812 | type = "passive"; | |
| 3813 | }; | |
| 3814 | ||
| 3815 | ddr_config0: ddr0-config { | |
| 3816 | temperature = <90000>; | |
| 3817 | hysteresis = <5000>; | |
| 3818 | type = "passive"; | |
| 3819 | }; | |
| 3820 | ||
| 3821 | reset-mon-cfg { | |
| 3822 | temperature = <115000>; | |
| 3823 | hysteresis = <5000>; | |
| 3824 | type = "passive"; | |
| 3825 | }; | |
| 3826 | }; | |
| 3827 | }; | |
| 3828 | ||
| 3829 | modem0-thermal { | |
| 3830 | polling-delay-passive = <0>; | |
| 3831 | polling-delay = <0>; | |
| 3832 | thermal-sensors = <&tsens1 10>; | |
| 3833 | ||
| 3834 | trips { | |
| 3835 | thermal-engine-config { | |
| 3836 | temperature = <125000>; | |
| 3837 | hysteresis = <1000>; | |
| 3838 | type = "passive"; | |
| 3839 | }; | |
| 3840 | ||
| 3841 | mdmss0_config0: mdmss0-config0 { | |
| 3842 | temperature = <102000>; | |
| 3843 | hysteresis = <3000>; | |
| 3844 | type = "passive"; | |
| 3845 | }; | |
| 3846 | ||
| 3847 | mdmss0_config1: mdmss0-config1 { | |
| 3848 | temperature = <105000>; | |
| 3849 | hysteresis = <3000>; | |
| 3850 | type = "passive"; | |
| 3851 | }; | |
| 3852 | ||
| 3853 | reset-mon-cfg { | |
| 3854 | temperature = <115000>; | |
| 3855 | hysteresis = <5000>; | |
| 3856 | type = "passive"; | |
| 3857 | }; | |
| 3858 | }; | |
| 3859 | }; | |
| 3860 | ||
| 3861 | modem1-thermal { | |
| 3862 | polling-delay-passive = <0>; | |
| 3863 | polling-delay = <0>; | |
| 3864 | thermal-sensors = <&tsens1 11>; | |
| 3865 | ||
| 3866 | trips { | |
| 3867 | thermal-engine-config { | |
| 3868 | temperature = <125000>; | |
| 3869 | hysteresis = <1000>; | |
| 3870 | type = "passive"; | |
| 3871 | }; | |
| 3872 | ||
| 3873 | mdmss1_config0: mdmss1-config0 { | |
| 3874 | temperature = <102000>; | |
| 3875 | hysteresis = <3000>; | |
| 3876 | type = "passive"; | |
| 3877 | }; | |
| 3878 | ||
| 3879 | mdmss1_config1: mdmss1-config1 { | |
| 3880 | temperature = <105000>; | |
| 3881 | hysteresis = <3000>; | |
| 3882 | type = "passive"; | |
| 3883 | }; | |
| 3884 | ||
| 3885 | reset-mon-cfg { | |
| 3886 | temperature = <115000>; | |
| 3887 | hysteresis = <5000>; | |
| 3888 | type = "passive"; | |
| 3889 | }; | |
| 3890 | }; | |
| 3891 | }; | |
| 3892 | ||
| 3893 | modem2-thermal { | |
| 3894 | polling-delay-passive = <0>; | |
| 3895 | polling-delay = <0>; | |
| 3896 | thermal-sensors = <&tsens1 12>; | |
| 3897 | ||
| 3898 | trips { | |
| 3899 | thermal-engine-config { | |
| 3900 | temperature = <125000>; | |
| 3901 | hysteresis = <1000>; | |
| 3902 | type = "passive"; | |
| 3903 | }; | |
| 3904 | ||
| 3905 | mdmss2_config0: mdmss2-config0 { | |
| 3906 | temperature = <102000>; | |
| 3907 | hysteresis = <3000>; | |
| 3908 | type = "passive"; | |
| 3909 | }; | |
| 3910 | ||
| 3911 | mdmss2_config1: mdmss2-config1 { | |
| 3912 | temperature = <105000>; | |
| 3913 | hysteresis = <3000>; | |
| 3914 | type = "passive"; | |
| 3915 | }; | |
| 3916 | ||
| 3917 | reset-mon-cfg { | |
| 3918 | temperature = <115000>; | |
| 3919 | hysteresis = <5000>; | |
| 3920 | type = "passive"; | |
| 3921 | }; | |
| 3922 | }; | |
| 3923 | }; | |
| 3924 | ||
| 3925 | modem3-thermal { | |
| 3926 | polling-delay-passive = <0>; | |
| 3927 | polling-delay = <0>; | |
| 3928 | thermal-sensors = <&tsens1 13>; | |
| 3929 | ||
| 3930 | trips { | |
| 3931 | thermal-engine-config { | |
| 3932 | temperature = <125000>; | |
| 3933 | hysteresis = <1000>; | |
| 3934 | type = "passive"; | |
| 3935 | }; | |
| 3936 | ||
| 3937 | mdmss3_config0: mdmss3-config0 { | |
| 3938 | temperature = <102000>; | |
| 3939 | hysteresis = <3000>; | |
| 3940 | type = "passive"; | |
| 3941 | }; | |
| 3942 | ||
| 3943 | mdmss3_config1: mdmss3-config1 { | |
| 3944 | temperature = <105000>; | |
| 3945 | hysteresis = <3000>; | |
| 3946 | type = "passive"; | |
| 3947 | }; | |
| 3948 | ||
| 3949 | reset-mon-cfg { | |
| 3950 | temperature = <115000>; | |
| 3951 | hysteresis = <5000>; | |
| 3952 | type = "passive"; | |
| 3953 | }; | |
| 3954 | }; | |
| 3955 | }; | |
| 3956 | ||
| 3957 | camera0-thermal { | |
| 3958 | polling-delay-passive = <0>; | |
| 3959 | polling-delay = <0>; | |
| 3960 | thermal-sensors = <&tsens1 14>; | |
| 3961 | ||
| 3962 | trips { | |
| 3963 | thermal-engine-config { | |
| 3964 | temperature = <125000>; | |
| 3965 | hysteresis = <1000>; | |
| 3966 | type = "passive"; | |
| 3967 | }; | |
| 3968 | ||
| 3969 | reset-mon-cfg { | |
| 3970 | temperature = <115000>; | |
| 3971 | hysteresis = <5000>; | |
| 3972 | type = "passive"; | |
| 3973 | }; | |
| 3974 | }; | |
| 3975 | }; | |
| 3976 | ||
| 3977 | camera1-thermal { | |
| 3978 | polling-delay-passive = <0>; | |
| 3979 | polling-delay = <0>; | |
| 3980 | thermal-sensors = <&tsens1 15>; | |
| 3981 | ||
| 3982 | trips { | |
| 3983 | thermal-engine-config { | |
| 3984 | temperature = <125000>; | |
| 3985 | hysteresis = <1000>; | |
| 3986 | type = "passive"; | |
| 3987 | }; | |
| 3988 | ||
| 3989 | reset-mon-cfg { | |
| 3990 | temperature = <115000>; | |
| 3991 | hysteresis = <5000>; | |
| 3992 | type = "passive"; | |
| 3993 | }; | |
| 3994 | }; | |
| 3995 | }; | |
| 3996 | }; | |
| 3997 | ||
| 5188049c VK |
3998 | timer { |
| 3999 | compatible = "arm,armv8-timer"; | |
| 4000 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 4001 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 4002 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 4003 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; | |
| 4004 | clock-frequency = <19200000>; | |
| 4005 | }; | |
| 4006 | }; |