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arm64: dts: qcom: sm8450: Fix the PCI I/O port range
[linux-block.git] / arch / arm64 / boot / dts / qcom / sm8350.dtsi
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b7e8f433
VK		 1// SPDX-License-Identifier: BSD-3-Clause
2/*
4f23d2a5 3 * Copyright (c) 2020, Linaro Limited
b7e8f433
VK		 4 */
5
d4a44105 6#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433 7#include <dt-bindings/interrupt-controller/arm-gic.h>
9fd4887c 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
6d91e201 9#include <dt-bindings/clock/qcom,gcc-sm8350.h>
54af0ceb 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
b7e8f433 11#include <dt-bindings/clock/qcom,rpmh.h>
bc08fbf4 12#include <dt-bindings/dma/qcom-gpi.h>
f0360a7c 13#include <dt-bindings/gpio/gpio.h>
84c856d0 14#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433 15#include <dt-bindings/mailbox/qcom-ipcc.h>
b7e8f433
VK		 16#include <dt-bindings/power/qcom-rpmpd.h>
17#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20f9d94e 18#include <dt-bindings/thermal/thermal.h>
f11d3e7d 19#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433
VK		 20
21/ {
22 interrupt-parent = <&intc>;
23
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 chosen { };
28
29 clocks {
30 xo_board: xo-board {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <38400000>;
34 clock-output-names = "xo_board";
35 };
36
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 clock-frequency = <32000>;
40 #clock-cells = <0>;
41 };
42 };
43
44 cpus {
45 #address-cells = <2>;
46 #size-cells = <0>;
47
48 CPU0: cpu@0 {
49 device_type = "cpu";
50 compatible = "qcom,kryo685";
51 reg = <0x0 0x0>;
c2a18730 52 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
ccbb3abb 55 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 56 power-domains = <&CPU_PD0>;
57 power-domain-names = "psci";
20f9d94e 58 #cooling-cells = <2>;
b7e8f433
VK		 59 L2_0: l2-cache {
60 compatible = "cache";
9435294c 61 cache-level = <2>;
b7e8f433
VK		 62 next-level-cache = <&L3_0>;
63 L3_0: l3-cache {
64 compatible = "cache";
9435294c 65 cache-level = <3>;
b7e8f433
VK		 66 };
67 };
68 };
69
70 CPU1: cpu@100 {
71 device_type = "cpu";
72 compatible = "qcom,kryo685";
73 reg = <0x0 0x100>;
c2a18730 74 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 75 enable-method = "psci";
76 next-level-cache = <&L2_100>;
ccbb3abb 77 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 78 power-domains = <&CPU_PD1>;
79 power-domain-names = "psci";
20f9d94e 80 #cooling-cells = <2>;
b7e8f433
VK		 81 L2_100: l2-cache {
82 compatible = "cache";
9435294c 83 cache-level = <2>;
b7e8f433
VK		 84 next-level-cache = <&L3_0>;
85 };
86 };
87
88 CPU2: cpu@200 {
89 device_type = "cpu";
90 compatible = "qcom,kryo685";
91 reg = <0x0 0x200>;
c2a18730 92 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 93 enable-method = "psci";
94 next-level-cache = <&L2_200>;
ccbb3abb 95 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 96 power-domains = <&CPU_PD2>;
97 power-domain-names = "psci";
20f9d94e 98 #cooling-cells = <2>;
b7e8f433
VK		 99 L2_200: l2-cache {
100 compatible = "cache";
9435294c 101 cache-level = <2>;
b7e8f433
VK		 102 next-level-cache = <&L3_0>;
103 };
104 };
105
106 CPU3: cpu@300 {
107 device_type = "cpu";
108 compatible = "qcom,kryo685";
109 reg = <0x0 0x300>;
c2a18730 110 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 111 enable-method = "psci";
112 next-level-cache = <&L2_300>;
ccbb3abb 113 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 114 power-domains = <&CPU_PD3>;
115 power-domain-names = "psci";
20f9d94e 116 #cooling-cells = <2>;
b7e8f433
VK		 117 L2_300: l2-cache {
118 compatible = "cache";
9435294c 119 cache-level = <2>;
b7e8f433
VK		 120 next-level-cache = <&L3_0>;
121 };
122 };
123
124 CPU4: cpu@400 {
125 device_type = "cpu";
126 compatible = "qcom,kryo685";
127 reg = <0x0 0x400>;
c2a18730 128 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 129 enable-method = "psci";
130 next-level-cache = <&L2_400>;
ccbb3abb 131 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 132 power-domains = <&CPU_PD4>;
133 power-domain-names = "psci";
20f9d94e 134 #cooling-cells = <2>;
b7e8f433
VK		 135 L2_400: l2-cache {
136 compatible = "cache";
9435294c 137 cache-level = <2>;
b7e8f433
VK		 138 next-level-cache = <&L3_0>;
139 };
140 };
141
142 CPU5: cpu@500 {
143 device_type = "cpu";
144 compatible = "qcom,kryo685";
145 reg = <0x0 0x500>;
c2a18730 146 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 147 enable-method = "psci";
148 next-level-cache = <&L2_500>;
ccbb3abb 149 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 150 power-domains = <&CPU_PD5>;
151 power-domain-names = "psci";
20f9d94e 152 #cooling-cells = <2>;
b7e8f433
VK		 153 L2_500: l2-cache {
154 compatible = "cache";
9435294c 155 cache-level = <2>;
b7e8f433
VK		 156 next-level-cache = <&L3_0>;
157 };
158
159 };
160
161 CPU6: cpu@600 {
162 device_type = "cpu";
163 compatible = "qcom,kryo685";
164 reg = <0x0 0x600>;
c2a18730 165 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 166 enable-method = "psci";
167 next-level-cache = <&L2_600>;
ccbb3abb 168 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 169 power-domains = <&CPU_PD6>;
170 power-domain-names = "psci";
20f9d94e 171 #cooling-cells = <2>;
b7e8f433
VK		 172 L2_600: l2-cache {
173 compatible = "cache";
9435294c 174 cache-level = <2>;
b7e8f433
VK		 175 next-level-cache = <&L3_0>;
176 };
177 };
178
179 CPU7: cpu@700 {
180 device_type = "cpu";
181 compatible = "qcom,kryo685";
182 reg = <0x0 0x700>;
c2a18730 183 clocks = <&cpufreq_hw 2>;
b7e8f433
VK		 184 enable-method = "psci";
185 next-level-cache = <&L2_700>;
ccbb3abb 186 qcom,freq-domain = <&cpufreq_hw 2>;
07ddb302
BA		 187 power-domains = <&CPU_PD7>;
188 power-domain-names = "psci";
20f9d94e 189 #cooling-cells = <2>;
b7e8f433
VK		 190 L2_700: l2-cache {
191 compatible = "cache";
9435294c 192 cache-level = <2>;
b7e8f433
VK		 193 next-level-cache = <&L3_0>;
194 };
195 };
07ddb302
BA		 196
197 cpu-map {
198 cluster0 {
199 core0 {
200 cpu = <&CPU0>;
201 };
202
203 core1 {
204 cpu = <&CPU1>;
205 };
206
207 core2 {
208 cpu = <&CPU2>;
209 };
210
211 core3 {
212 cpu = <&CPU3>;
213 };
214
215 core4 {
216 cpu = <&CPU4>;
217 };
218
219 core5 {
220 cpu = <&CPU5>;
221 };
222
223 core6 {
224 cpu = <&CPU6>;
225 };
226
227 core7 {
228 cpu = <&CPU7>;
229 };
230 };
231 };
232
233 idle-states {
234 entry-method = "psci";
235
236 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
237 compatible = "arm,idle-state";
238 idle-state-name = "silver-rail-power-collapse";
239 arm,psci-suspend-param = <0x40000004>;
240 entry-latency-us = <355>;
241 exit-latency-us = <909>;
242 min-residency-us = <3934>;
243 local-timer-stop;
244 };
245
246 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
247 compatible = "arm,idle-state";
248 idle-state-name = "gold-rail-power-collapse";
249 arm,psci-suspend-param = <0x40000004>;
250 entry-latency-us = <241>;
251 exit-latency-us = <1461>;
252 min-residency-us = <4488>;
253 local-timer-stop;
254 };
255 };
256
257 domain-idle-states {
258 CLUSTER_SLEEP_0: cluster-sleep-0 {
259 compatible = "domain-idle-state";
260 idle-state-name = "cluster-power-collapse";
261 arm,psci-suspend-param = <0x4100c344>;
262 entry-latency-us = <3263>;
263 exit-latency-us = <6562>;
264 min-residency-us = <9987>;
265 local-timer-stop;
266 };
267 };
b7e8f433
VK		 268 };
269
270 firmware {
271 scm: scm {
272 compatible = "qcom,scm-sm8350", "qcom,scm";
273 #reset-cells = <1>;
274 };
275 };
276
277 memory@80000000 {
278 device_type = "memory";
279 /* We expect the bootloader to fill in the size */
280 reg = <0x0 0x80000000 0x0 0x0>;
281 };
282
283 pmu {
284 compatible = "arm,armv8-pmuv3";
794d3e30 285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
b7e8f433
VK		 286 };
287
288 psci {
289 compatible = "arm,psci-1.0";
290 method = "smc";
07ddb302 291
a9371962 292 CPU_PD0: power-domain-cpu0 {
07ddb302
BA		 293 #power-domain-cells = <0>;
294 power-domains = <&CLUSTER_PD>;
295 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
296 };
297
a9371962 298 CPU_PD1: power-domain-cpu1 {
07ddb302
BA		 299 #power-domain-cells = <0>;
300 power-domains = <&CLUSTER_PD>;
301 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
302 };
303
a9371962 304 CPU_PD2: power-domain-cpu2 {
07ddb302
BA		 305 #power-domain-cells = <0>;
306 power-domains = <&CLUSTER_PD>;
307 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
308 };
309
a9371962 310 CPU_PD3: power-domain-cpu3 {
07ddb302
BA		 311 #power-domain-cells = <0>;
312 power-domains = <&CLUSTER_PD>;
313 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
314 };
315
a9371962 316 CPU_PD4: power-domain-cpu4 {
07ddb302
BA		 317 #power-domain-cells = <0>;
318 power-domains = <&CLUSTER_PD>;
319 domain-idle-states = <&BIG_CPU_SLEEP_0>;
320 };
321
a9371962 322 CPU_PD5: power-domain-cpu5 {
07ddb302
BA		 323 #power-domain-cells = <0>;
324 power-domains = <&CLUSTER_PD>;
325 domain-idle-states = <&BIG_CPU_SLEEP_0>;
326 };
327
a9371962 328 CPU_PD6: power-domain-cpu6 {
07ddb302
BA		 329 #power-domain-cells = <0>;
330 power-domains = <&CLUSTER_PD>;
331 domain-idle-states = <&BIG_CPU_SLEEP_0>;
332 };
333
a9371962 334 CPU_PD7: power-domain-cpu7 {
07ddb302
BA		 335 #power-domain-cells = <0>;
336 power-domains = <&CLUSTER_PD>;
337 domain-idle-states = <&BIG_CPU_SLEEP_0>;
338 };
339
a9371962 340 CLUSTER_PD: power-domain-cpu-cluster0 {
07ddb302
BA		 341 #power-domain-cells = <0>;
342 domain-idle-states = <&CLUSTER_SLEEP_0>;
343 };
b7e8f433
VK		 344 };
345
e2eedde4
VK		 346 qup_opp_table_100mhz: opp-table-qup100mhz {
347 compatible = "operating-points-v2";
348
349 opp-50000000 {
350 opp-hz = /bits/ 64 <50000000>;
351 required-opps = <&rpmhpd_opp_min_svs>;
352 };
353
354 opp-75000000 {
355 opp-hz = /bits/ 64 <75000000>;
356 required-opps = <&rpmhpd_opp_low_svs>;
357 };
358
359 opp-100000000 {
360 opp-hz = /bits/ 64 <100000000>;
361 required-opps = <&rpmhpd_opp_svs>;
362 };
363 };
364
365 qup_opp_table_120mhz: opp-table-qup120mhz {
366 compatible = "operating-points-v2";
367
368 opp-50000000 {
369 opp-hz = /bits/ 64 <50000000>;
370 required-opps = <&rpmhpd_opp_min_svs>;
371 };
372
373 opp-75000000 {
374 opp-hz = /bits/ 64 <75000000>;
375 required-opps = <&rpmhpd_opp_low_svs>;
376 };
377
378 opp-120000000 {
379 opp-hz = /bits/ 64 <120000000>;
380 required-opps = <&rpmhpd_opp_svs>;
381 };
382 };
383
b7e8f433
VK		 384 reserved_memory: reserved-memory {
385 #address-cells = <2>;
386 #size-cells = <2>;
387 ranges;
388
389 hyp_mem: memory@80000000 {
390 reg = <0x0 0x80000000 0x0 0x600000>;
391 no-map;
392 };
393
394 xbl_aop_mem: memory@80700000 {
395 no-map;
396 reg = <0x0 0x80700000 0x0 0x160000>;
397 };
398
399 cmd_db: memory@80860000 {
400 compatible = "qcom,cmd-db";
401 reg = <0x0 0x80860000 0x0 0x20000>;
402 no-map;
403 };
404
405 reserved_xbl_uefi_log: memory@80880000 {
406 reg = <0x0 0x80880000 0x0 0x14000>;
407 no-map;
408 };
409
8503babc
KD		 410 smem@80900000 {
411 compatible = "qcom,smem";
b7e8f433 412 reg = <0x0 0x80900000 0x0 0x200000>;
8503babc 413 hwlocks = <&tcsr_mutex 3>;
b7e8f433
VK		 414 no-map;
415 };
416
417 cpucp_fw_mem: memory@80b00000 {
418 reg = <0x0 0x80b00000 0x0 0x100000>;
419 no-map;
420 };
421
422 cdsp_secure_heap: memory@80c00000 {
423 reg = <0x0 0x80c00000 0x0 0x4600000>;
424 no-map;
425 };
426
427 pil_camera_mem: mmeory@85200000 {
428 reg = <0x0 0x85200000 0x0 0x500000>;
429 no-map;
430 };
431
432 pil_video_mem: memory@85700000 {
433 reg = <0x0 0x85700000 0x0 0x500000>;
434 no-map;
435 };
436
437 pil_cvp_mem: memory@85c00000 {
438 reg = <0x0 0x85c00000 0x0 0x500000>;
439 no-map;
440 };
441
442 pil_adsp_mem: memory@86100000 {
443 reg = <0x0 0x86100000 0x0 0x2100000>;
444 no-map;
445 };
446
447 pil_slpi_mem: memory@88200000 {
448 reg = <0x0 0x88200000 0x0 0x1500000>;
449 no-map;
450 };
451
452 pil_cdsp_mem: memory@89700000 {
453 reg = <0x0 0x89700000 0x0 0x1e00000>;
454 no-map;
455 };
456
457 pil_ipa_fw_mem: memory@8b500000 {
458 reg = <0x0 0x8b500000 0x0 0x10000>;
459 no-map;
460 };
461
462 pil_ipa_gsi_mem: memory@8b510000 {
463 reg = <0x0 0x8b510000 0x0 0xa000>;
464 no-map;
465 };
466
467 pil_gpu_mem: memory@8b51a000 {
468 reg = <0x0 0x8b51a000 0x0 0x2000>;
469 no-map;
470 };
471
472 pil_spss_mem: memory@8b600000 {
473 reg = <0x0 0x8b600000 0x0 0x100000>;
474 no-map;
475 };
476
477 pil_modem_mem: memory@8b800000 {
478 reg = <0x0 0x8b800000 0x0 0x10000000>;
479 no-map;
480 };
481
774890c9
VK		 482 rmtfs_mem: memory@9b800000 {
483 compatible = "qcom,rmtfs-mem";
484 reg = <0x0 0x9b800000 0x0 0x280000>;
485 no-map;
486
487 qcom,client-id = <1>;
488 qcom,vmid = <15>;
489 };
490
b7e8f433
VK		 491 hyp_reserved_mem: memory@d0000000 {
492 reg = <0x0 0xd0000000 0x0 0x800000>;
493 no-map;
494 };
495
496 pil_trustedvm_mem: memory@d0800000 {
497 reg = <0x0 0xd0800000 0x0 0x76f7000>;
498 no-map;
499 };
500
501 qrtr_shbuf: memory@d7ef7000 {
502 reg = <0x0 0xd7ef7000 0x0 0x9000>;
503 no-map;
504 };
505
506 chan0_shbuf: memory@d7f00000 {
507 reg = <0x0 0xd7f00000 0x0 0x80000>;
508 no-map;
509 };
510
511 chan1_shbuf: memory@d7f80000 {
512 reg = <0x0 0xd7f80000 0x0 0x80000>;
513 no-map;
514 };
515
516 removed_mem: memory@d8800000 {
517 reg = <0x0 0xd8800000 0x0 0x6800000>;
518 no-map;
519 };
520 };
521
03a41991
VK		 522 smp2p-adsp {
523 compatible = "qcom,smp2p";
524 qcom,smem = <443>, <429>;
525 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
526 IPCC_MPROC_SIGNAL_SMP2P
527 IRQ_TYPE_EDGE_RISING>;
528 mboxes = <&ipcc IPCC_CLIENT_LPASS
529 IPCC_MPROC_SIGNAL_SMP2P>;
530
531 qcom,local-pid = <0>;
532 qcom,remote-pid = <2>;
533
534 smp2p_adsp_out: master-kernel {
535 qcom,entry-name = "master-kernel";
536 #qcom,smem-state-cells = <1>;
537 };
538
539 smp2p_adsp_in: slave-kernel {
540 qcom,entry-name = "slave-kernel";
541 interrupt-controller;
542 #interrupt-cells = <2>;
543 };
544 };
545
546 smp2p-cdsp {
547 compatible = "qcom,smp2p";
548 qcom,smem = <94>, <432>;
549 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
550 IPCC_MPROC_SIGNAL_SMP2P
551 IRQ_TYPE_EDGE_RISING>;
552 mboxes = <&ipcc IPCC_CLIENT_CDSP
553 IPCC_MPROC_SIGNAL_SMP2P>;
554
555 qcom,local-pid = <0>;
556 qcom,remote-pid = <5>;
557
558 smp2p_cdsp_out: master-kernel {
559 qcom,entry-name = "master-kernel";
560 #qcom,smem-state-cells = <1>;
561 };
562
563 smp2p_cdsp_in: slave-kernel {
564 qcom,entry-name = "slave-kernel";
565 interrupt-controller;
566 #interrupt-cells = <2>;
567 };
568 };
569
570 smp2p-modem {
571 compatible = "qcom,smp2p";
572 qcom,smem = <435>, <428>;
573 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
574 IPCC_MPROC_SIGNAL_SMP2P
575 IRQ_TYPE_EDGE_RISING>;
576 mboxes = <&ipcc IPCC_CLIENT_MPSS
577 IPCC_MPROC_SIGNAL_SMP2P>;
578
579 qcom,local-pid = <0>;
580 qcom,remote-pid = <1>;
581
582 smp2p_modem_out: master-kernel {
583 qcom,entry-name = "master-kernel";
584 #qcom,smem-state-cells = <1>;
585 };
586
587 smp2p_modem_in: slave-kernel {
588 qcom,entry-name = "slave-kernel";
589 interrupt-controller;
590 #interrupt-cells = <2>;
591 };
f11d3e7d
AE		 592
593 ipa_smp2p_out: ipa-ap-to-modem {
594 qcom,entry-name = "ipa";
595 #qcom,smem-state-cells = <1>;
596 };
597
598 ipa_smp2p_in: ipa-modem-to-ap {
599 qcom,entry-name = "ipa";
600 interrupt-controller;
601 #interrupt-cells = <2>;
602 };
03a41991
VK		 603 };
604
605 smp2p-slpi {
606 compatible = "qcom,smp2p";
607 qcom,smem = <481>, <430>;
608 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
609 IPCC_MPROC_SIGNAL_SMP2P
610 IRQ_TYPE_EDGE_RISING>;
611 mboxes = <&ipcc IPCC_CLIENT_SLPI
612 IPCC_MPROC_SIGNAL_SMP2P>;
613
614 qcom,local-pid = <0>;
615 qcom,remote-pid = <3>;
616
617 smp2p_slpi_out: master-kernel {
618 qcom,entry-name = "master-kernel";
619 #qcom,smem-state-cells = <1>;
620 };
621
622 smp2p_slpi_in: slave-kernel {
623 qcom,entry-name = "slave-kernel";
624 interrupt-controller;
625 #interrupt-cells = <2>;
626 };
627 };
628
b7e8f433
VK		 629 soc: soc@0 {
630 #address-cells = <2>;
631 #size-cells = <2>;
632 ranges = <0 0 0 0 0x10 0>;
633 dma-ranges = <0 0 0 0 0x10 0>;
634 compatible = "simple-bus";
635
636 gcc: clock-controller@100000 {
637 compatible = "qcom,gcc-sm8350";
638 reg = <0x0 0x00100000 0x0 0x1f0000>;
639 #clock-cells = <1>;
640 #reset-cells = <1>;
641 #power-domain-cells = <1>;
9ea9eb36
KD		 642 clock-names = "bi_tcxo",
643 "sleep_clk",
644 "pcie_0_pipe_clk",
645 "pcie_1_pipe_clk",
646 "ufs_card_rx_symbol_0_clk",
647 "ufs_card_rx_symbol_1_clk",
648 "ufs_card_tx_symbol_0_clk",
649 "ufs_phy_rx_symbol_0_clk",
650 "ufs_phy_rx_symbol_1_clk",
651 "ufs_phy_tx_symbol_0_clk",
652 "usb3_phy_wrapper_gcc_usb30_pipe_clk",
653 "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
654 clocks = <&rpmhcc RPMH_CXO_CLK>,
655 <&sleep_clk>,
6daee406
DB		 656 <&pcie0_phy>,
657 <&pcie1_phy>,
9ea9eb36
KD		 658 <0>,
659 <0>,
660 <0>,
86543bc6
DB		 661 <&ufs_mem_phy_lanes 0>,
662 <&ufs_mem_phy_lanes 1>,
663 <&ufs_mem_phy_lanes 2>,
9ea9eb36
KD		 664 <0>,
665 <0>;
b7e8f433
VK		 666 };
667
668 ipcc: mailbox@408000 {
669 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
670 reg = <0 0x00408000 0 0x1000>;
671 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
672 interrupt-controller;
673 #interrupt-cells = <3>;
674 #mbox-cells = <2>;
675 };
676
bc08fbf4 677 gpi_dma2: dma-controller@800000 {
b561e225 678 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 679 reg = <0 0x00800000 0 0x60000>;
680 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
692 dma-channels = <12>;
693 dma-channel-mask = <0xff>;
694 iommus = <&apps_smmu 0x5f6 0x0>;
695 #dma-cells = <3>;
696 status = "disabled";
697 };
698
e84d04a2
KD		 699 qupv3_id_2: geniqup@8c0000 {
700 compatible = "qcom,geni-se-qup";
701 reg = <0x0 0x008c0000 0x0 0x6000>;
702 clock-names = "m-ahb", "s-ahb";
703 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
704 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
9bc2c8fe 705 iommus = <&apps_smmu 0x5e3 0x0>;
e84d04a2
KD		 706 #address-cells = <2>;
707 #size-cells = <2>;
708 ranges;
709 status = "disabled";
98374e69
KD		 710
711 i2c14: i2c@880000 {
712 compatible = "qcom,geni-i2c";
713 reg = <0 0x00880000 0 0x4000>;
714 clock-names = "se";
715 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&qup_i2c14_default>;
718 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 719 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
720 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
721 dma-names = "tx", "rx";
98374e69
KD		 722 #address-cells = <1>;
723 #size-cells = <0>;
724 status = "disabled";
725 };
726
727 spi14: spi@880000 {
728 compatible = "qcom,geni-spi";
729 reg = <0 0x00880000 0 0x4000>;
730 clock-names = "se";
731 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
732 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
733 power-domains = <&rpmhpd SM8350_CX>;
734 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 735 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
736 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
737 dma-names = "tx", "rx";
98374e69
KD		 738 #address-cells = <1>;
739 #size-cells = <0>;
740 status = "disabled";
741 };
742
743 i2c15: i2c@884000 {
744 compatible = "qcom,geni-i2c";
745 reg = <0 0x00884000 0 0x4000>;
746 clock-names = "se";
747 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
748 pinctrl-names = "default";
749 pinctrl-0 = <&qup_i2c15_default>;
750 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 751 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
752 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
753 dma-names = "tx", "rx";
98374e69
KD		 754 #address-cells = <1>;
755 #size-cells = <0>;
756 status = "disabled";
757 };
758
759 spi15: spi@884000 {
760 compatible = "qcom,geni-spi";
761 reg = <0 0x00884000 0 0x4000>;
762 clock-names = "se";
763 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
764 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
765 power-domains = <&rpmhpd SM8350_CX>;
766 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 767 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
768 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
769 dma-names = "tx", "rx";
98374e69
KD		 770 #address-cells = <1>;
771 #size-cells = <0>;
772 status = "disabled";
773 };
774
775 i2c16: i2c@888000 {
776 compatible = "qcom,geni-i2c";
777 reg = <0 0x00888000 0 0x4000>;
778 clock-names = "se";
779 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
780 pinctrl-names = "default";
781 pinctrl-0 = <&qup_i2c16_default>;
782 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 783 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
784 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
785 dma-names = "tx", "rx";
98374e69
KD		 786 #address-cells = <1>;
787 #size-cells = <0>;
788 status = "disabled";
789 };
790
791 spi16: spi@888000 {
792 compatible = "qcom,geni-spi";
793 reg = <0 0x00888000 0 0x4000>;
794 clock-names = "se";
795 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
796 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
797 power-domains = <&rpmhpd SM8350_CX>;
798 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 799 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
800 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
801 dma-names = "tx", "rx";
98374e69
KD		 802 #address-cells = <1>;
803 #size-cells = <0>;
804 status = "disabled";
805 };
806
807 i2c17: i2c@88c000 {
808 compatible = "qcom,geni-i2c";
809 reg = <0 0x0088c000 0 0x4000>;
810 clock-names = "se";
811 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
812 pinctrl-names = "default";
813 pinctrl-0 = <&qup_i2c17_default>;
814 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 815 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
816 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
817 dma-names = "tx", "rx";
98374e69
KD		 818 #address-cells = <1>;
819 #size-cells = <0>;
820 status = "disabled";
821 };
822
823 spi17: spi@88c000 {
824 compatible = "qcom,geni-spi";
825 reg = <0 0x0088c000 0 0x4000>;
826 clock-names = "se";
827 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
828 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
829 power-domains = <&rpmhpd SM8350_CX>;
830 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 831 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
832 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
833 dma-names = "tx", "rx";
98374e69
KD		 834 #address-cells = <1>;
835 #size-cells = <0>;
836 status = "disabled";
837 };
838
839 /* QUP no. 18 seems to be strictly SPI/UART-only */
840
841 spi18: spi@890000 {
842 compatible = "qcom,geni-spi";
843 reg = <0 0x00890000 0 0x4000>;
844 clock-names = "se";
845 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
846 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
847 power-domains = <&rpmhpd SM8350_CX>;
848 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 849 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
850 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
851 dma-names = "tx", "rx";
98374e69
KD		 852 #address-cells = <1>;
853 #size-cells = <0>;
854 status = "disabled";
855 };
856
857 uart18: serial@890000 {
858 compatible = "qcom,geni-uart";
859 reg = <0 0x00890000 0 0x4000>;
860 clock-names = "se";
861 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
862 pinctrl-names = "default";
863 pinctrl-0 = <&qup_uart18_default>;
864 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
865 power-domains = <&rpmhpd SM8350_CX>;
866 operating-points-v2 = <&qup_opp_table_100mhz>;
867 status = "disabled";
868 };
869
870 i2c19: i2c@894000 {
871 compatible = "qcom,geni-i2c";
872 reg = <0 0x00894000 0 0x4000>;
873 clock-names = "se";
874 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
875 pinctrl-names = "default";
876 pinctrl-0 = <&qup_i2c19_default>;
877 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 878 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
879 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
880 dma-names = "tx", "rx";
98374e69
KD		 881 #address-cells = <1>;
882 #size-cells = <0>;
883 status = "disabled";
884 };
885
886 spi19: spi@894000 {
887 compatible = "qcom,geni-spi";
888 reg = <0 0x00894000 0 0x4000>;
889 clock-names = "se";
890 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
891 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
892 power-domains = <&rpmhpd SM8350_CX>;
893 operating-points-v2 = <&qup_opp_table_100mhz>;
bc08fbf4
BA		 894 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
895 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
896 dma-names = "tx", "rx";
98374e69
KD		 897 #address-cells = <1>;
898 #size-cells = <0>;
899 status = "disabled";
900 };
e84d04a2
KD		 901 };
902
bc08fbf4 903 gpi_dma0: dma-controller@900000 {
b561e225 904 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 905 reg = <0 0x09800000 0 0x60000>;
906 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
918 dma-channels = <12>;
919 dma-channel-mask = <0x7e>;
920 iommus = <&apps_smmu 0x5b6 0x0>;
921 #dma-cells = <3>;
922 status = "disabled";
923 };
924
87f0b434 925 qupv3_id_0: geniqup@9c0000 {
b7e8f433
VK		 926 compatible = "qcom,geni-se-qup";
927 reg = <0x0 0x009c0000 0x0 0x6000>;
928 clock-names = "m-ahb", "s-ahb";
6d91e201
VK		 929 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
930 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
9bc2c8fe 931 iommus = <&apps_smmu 0x5a3 0>;
b7e8f433
VK		 932 #address-cells = <2>;
933 #size-cells = <2>;
934 ranges;
935 status = "disabled";
936
cf03cd7e
KD		 937 i2c0: i2c@980000 {
938 compatible = "qcom,geni-i2c";
939 reg = <0 0x00980000 0 0x4000>;
940 clock-names = "se";
941 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
942 pinctrl-names = "default";
943 pinctrl-0 = <&qup_i2c0_default>;
944 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 945 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
946 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
947 dma-names = "tx", "rx";
cf03cd7e
KD		 948 #address-cells = <1>;
949 #size-cells = <0>;
950 status = "disabled";
951 };
952
953 spi0: spi@980000 {
954 compatible = "qcom,geni-spi";
955 reg = <0 0x00980000 0 0x4000>;
956 clock-names = "se";
957 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
958 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
959 power-domains = <&rpmhpd SM8350_CX>;
960 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 961 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
962 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
963 dma-names = "tx", "rx";
cf03cd7e
KD		 964 #address-cells = <1>;
965 #size-cells = <0>;
966 status = "disabled";
967 };
968
969 i2c1: i2c@984000 {
970 compatible = "qcom,geni-i2c";
971 reg = <0 0x00984000 0 0x4000>;
972 clock-names = "se";
973 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
974 pinctrl-names = "default";
975 pinctrl-0 = <&qup_i2c1_default>;
976 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 977 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
978 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
979 dma-names = "tx", "rx";
cf03cd7e
KD		 980 #address-cells = <1>;
981 #size-cells = <0>;
982 status = "disabled";
983 };
984
985 spi1: spi@984000 {
986 compatible = "qcom,geni-spi";
987 reg = <0 0x00984000 0 0x4000>;
988 clock-names = "se";
989 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
990 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
991 power-domains = <&rpmhpd SM8350_CX>;
992 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 993 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
994 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
995 dma-names = "tx", "rx";
cf03cd7e
KD		 996 #address-cells = <1>;
997 #size-cells = <0>;
998 status = "disabled";
999 };
1000
1001 i2c2: i2c@988000 {
1002 compatible = "qcom,geni-i2c";
1003 reg = <0 0x00988000 0 0x4000>;
1004 clock-names = "se";
1005 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&qup_i2c2_default>;
1008 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1009 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1010 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1011 dma-names = "tx", "rx";
cf03cd7e
KD		 1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 status = "disabled";
1015 };
1016
1017 spi2: spi@988000 {
1018 compatible = "qcom,geni-spi";
1019 reg = <0 0x00988000 0 0x4000>;
1020 clock-names = "se";
1021 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1023 power-domains = <&rpmhpd SM8350_CX>;
1024 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1025 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1026 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1027 dma-names = "tx", "rx";
cf03cd7e
KD		 1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 status = "disabled";
1031 };
1032
b7e8f433
VK		 1033 uart2: serial@98c000 {
1034 compatible = "qcom,geni-debug-uart";
1035 reg = <0 0x0098c000 0 0x4000>;
1036 clock-names = "se";
6d91e201 1037 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
b7e8f433
VK		 1038 pinctrl-names = "default";
1039 pinctrl-0 = <&qup_uart3_default_state>;
1040 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
cf03cd7e
KD		 1041 power-domains = <&rpmhpd SM8350_CX>;
1042 operating-points-v2 = <&qup_opp_table_100mhz>;
cf03cd7e
KD		 1043 status = "disabled";
1044 };
1045
1046 /* QUP no. 3 seems to be strictly SPI-only */
1047
1048 spi3: spi@98c000 {
1049 compatible = "qcom,geni-spi";
1050 reg = <0 0x0098c000 0 0x4000>;
1051 clock-names = "se";
1052 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1053 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1054 power-domains = <&rpmhpd SM8350_CX>;
1055 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1056 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1057 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1058 dma-names = "tx", "rx";
cf03cd7e
KD		 1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 status = "disabled";
1062 };
1063
1064 i2c4: i2c@990000 {
1065 compatible = "qcom,geni-i2c";
1066 reg = <0 0x00990000 0 0x4000>;
1067 clock-names = "se";
1068 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&qup_i2c4_default>;
1071 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1072 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1073 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1074 dma-names = "tx", "rx";
cf03cd7e
KD		 1075 #address-cells = <1>;
1076 #size-cells = <0>;
1077 status = "disabled";
1078 };
1079
1080 spi4: spi@990000 {
1081 compatible = "qcom,geni-spi";
1082 reg = <0 0x00990000 0 0x4000>;
1083 clock-names = "se";
1084 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1085 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1086 power-domains = <&rpmhpd SM8350_CX>;
1087 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1088 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1089 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1090 dma-names = "tx", "rx";
cf03cd7e
KD		 1091 #address-cells = <1>;
1092 #size-cells = <0>;
1093 status = "disabled";
1094 };
1095
1096 i2c5: i2c@994000 {
1097 compatible = "qcom,geni-i2c";
1098 reg = <0 0x00994000 0 0x4000>;
1099 clock-names = "se";
1100 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&qup_i2c5_default>;
1103 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1104 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1105 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1106 dma-names = "tx", "rx";
cf03cd7e
KD		 1107 #address-cells = <1>;
1108 #size-cells = <0>;
1109 status = "disabled";
1110 };
1111
1112 spi5: spi@994000 {
1113 compatible = "qcom,geni-spi";
1114 reg = <0 0x00994000 0 0x4000>;
1115 clock-names = "se";
1116 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1117 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1118 power-domains = <&rpmhpd SM8350_CX>;
1119 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1120 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1121 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1122 dma-names = "tx", "rx";
cf03cd7e
KD		 1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 status = "disabled";
1126 };
1127
1128 i2c6: i2c@998000 {
1129 compatible = "qcom,geni-i2c";
1130 reg = <0 0x00998000 0 0x4000>;
1131 clock-names = "se";
1132 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&qup_i2c6_default>;
1135 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1136 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1137 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1138 dma-names = "tx", "rx";
cf03cd7e
KD		 1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141 status = "disabled";
1142 };
1143
1144 spi6: spi@998000 {
1145 compatible = "qcom,geni-spi";
1146 reg = <0 0x00998000 0 0x4000>;
1147 clock-names = "se";
1148 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1149 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1150 power-domains = <&rpmhpd SM8350_CX>;
1151 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1152 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1153 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1154 dma-names = "tx", "rx";
cf03cd7e
KD		 1155 #address-cells = <1>;
1156 #size-cells = <0>;
1157 status = "disabled";
1158 };
1159
1160 uart6: serial@998000 {
1161 compatible = "qcom,geni-uart";
1162 reg = <0 0x00998000 0 0x4000>;
1163 clock-names = "se";
1164 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1165 pinctrl-names = "default";
1166 pinctrl-0 = <&qup_uart6_default>;
1167 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1168 power-domains = <&rpmhpd SM8350_CX>;
1169 operating-points-v2 = <&qup_opp_table_100mhz>;
1170 status = "disabled";
1171 };
1172
1173 i2c7: i2c@99c000 {
1174 compatible = "qcom,geni-i2c";
1175 reg = <0 0x0099c000 0 0x4000>;
1176 clock-names = "se";
1177 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1178 pinctrl-names = "default";
1179 pinctrl-0 = <&qup_i2c7_default>;
1180 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1181 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1182 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1183 dma-names = "tx", "rx";
cf03cd7e
KD		 1184 #address-cells = <1>;
1185 #size-cells = <0>;
1186 status = "disabled";
1187 };
1188
1189 spi7: spi@99c000 {
1190 compatible = "qcom,geni-spi";
1191 reg = <0 0x0099c000 0 0x4000>;
1192 clock-names = "se";
1193 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1194 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1195 power-domains = <&rpmhpd SM8350_CX>;
1196 operating-points-v2 = <&qup_opp_table_100mhz>;
bc08fbf4
BA		 1197 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1198 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1199 dma-names = "tx", "rx";
b7e8f433
VK		 1200 #address-cells = <1>;
1201 #size-cells = <0>;
1202 status = "disabled";
1203 };
1204 };
1205
bc08fbf4 1206 gpi_dma1: dma-controller@a00000 {
b561e225 1207 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 1208 reg = <0 0x00a00000 0 0x60000>;
1209 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1221 dma-channels = <12>;
1222 dma-channel-mask = <0xff>;
1223 iommus = <&apps_smmu 0x56 0x0>;
1224 #dma-cells = <3>;
1225 status = "disabled";
1226 };
1227
06bf656e
JM		 1228 qupv3_id_1: geniqup@ac0000 {
1229 compatible = "qcom,geni-se-qup";
1230 reg = <0x0 0x00ac0000 0x0 0x6000>;
1231 clock-names = "m-ahb", "s-ahb";
1232 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1233 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
9bc2c8fe 1234 iommus = <&apps_smmu 0x43 0>;
06bf656e
JM		 1235 #address-cells = <2>;
1236 #size-cells = <2>;
1237 ranges;
1238 status = "disabled";
1239
89345355
KD		 1240 i2c8: i2c@a80000 {
1241 compatible = "qcom,geni-i2c";
1242 reg = <0 0x00a80000 0 0x4000>;
1243 clock-names = "se";
1244 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1245 pinctrl-names = "default";
1246 pinctrl-0 = <&qup_i2c8_default>;
1247 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1248 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1249 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1250 dma-names = "tx", "rx";
89345355
KD		 1251 #address-cells = <1>;
1252 #size-cells = <0>;
1253 status = "disabled";
1254 };
1255
1256 spi8: spi@a80000 {
1257 compatible = "qcom,geni-spi";
1258 reg = <0 0x00a80000 0 0x4000>;
1259 clock-names = "se";
1260 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1261 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1262 power-domains = <&rpmhpd SM8350_CX>;
1263 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 1264 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1265 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1266 dma-names = "tx", "rx";
89345355
KD		 1267 #address-cells = <1>;
1268 #size-cells = <0>;
1269 status = "disabled";
1270 };
1271
1272 i2c9: i2c@a84000 {
1273 compatible = "qcom,geni-i2c";
1274 reg = <0 0x00a84000 0 0x4000>;
1275 clock-names = "se";
1276 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&qup_i2c9_default>;
1279 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1280 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1281 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1282 dma-names = "tx", "rx";
89345355
KD		 1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285 status = "disabled";
1286 };
1287
1288 spi9: spi@a84000 {
1289 compatible = "qcom,geni-spi";
1290 reg = <0 0x00a84000 0 0x4000>;
1291 clock-names = "se";
1292 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1293 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1294 power-domains = <&rpmhpd SM8350_CX>;
1295 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1296 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1297 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1298 dma-names = "tx", "rx";
89345355
KD		 1299 #address-cells = <1>;
1300 #size-cells = <0>;
1301 status = "disabled";
1302 };
1303
1304 i2c10: i2c@a88000 {
1305 compatible = "qcom,geni-i2c";
1306 reg = <0 0x00a88000 0 0x4000>;
1307 clock-names = "se";
1308 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1309 pinctrl-names = "default";
1310 pinctrl-0 = <&qup_i2c10_default>;
1311 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1312 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1313 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1314 dma-names = "tx", "rx";
89345355
KD		 1315 #address-cells = <1>;
1316 #size-cells = <0>;
1317 status = "disabled";
1318 };
1319
1320 spi10: spi@a88000 {
1321 compatible = "qcom,geni-spi";
1322 reg = <0 0x00a88000 0 0x4000>;
1323 clock-names = "se";
1324 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1325 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains = <&rpmhpd SM8350_CX>;
1327 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1328 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1329 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1330 dma-names = "tx", "rx";
89345355
KD		 1331 #address-cells = <1>;
1332 #size-cells = <0>;
1333 status = "disabled";
1334 };
1335
1336 i2c11: i2c@a8c000 {
1337 compatible = "qcom,geni-i2c";
1338 reg = <0 0x00a8c000 0 0x4000>;
1339 clock-names = "se";
1340 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1341 pinctrl-names = "default";
1342 pinctrl-0 = <&qup_i2c11_default>;
1343 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1344 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1345 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1346 dma-names = "tx", "rx";
89345355
KD		 1347 #address-cells = <1>;
1348 #size-cells = <0>;
1349 status = "disabled";
1350 };
1351
1352 spi11: spi@a8c000 {
1353 compatible = "qcom,geni-spi";
1354 reg = <0 0x00a8c000 0 0x4000>;
1355 clock-names = "se";
1356 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1357 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1358 power-domains = <&rpmhpd SM8350_CX>;
1359 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1360 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1361 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1362 dma-names = "tx", "rx";
89345355
KD		 1363 #address-cells = <1>;
1364 #size-cells = <0>;
1365 status = "disabled";
1366 };
1367
1368 i2c12: i2c@a90000 {
1369 compatible = "qcom,geni-i2c";
1370 reg = <0 0x00a90000 0 0x4000>;
1371 clock-names = "se";
1372 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1373 pinctrl-names = "default";
1374 pinctrl-0 = <&qup_i2c12_default>;
1375 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1376 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1377 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1378 dma-names = "tx", "rx";
89345355
KD		 1379 #address-cells = <1>;
1380 #size-cells = <0>;
1381 status = "disabled";
1382 };
1383
1384 spi12: spi@a90000 {
1385 compatible = "qcom,geni-spi";
1386 reg = <0 0x00a90000 0 0x4000>;
1387 clock-names = "se";
1388 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1389 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1390 power-domains = <&rpmhpd SM8350_CX>;
1391 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1392 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1393 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1394 dma-names = "tx", "rx";
89345355
KD		 1395 #address-cells = <1>;
1396 #size-cells = <0>;
1397 status = "disabled";
1398 };
1399
06bf656e
JM		 1400 i2c13: i2c@a94000 {
1401 compatible = "qcom,geni-i2c";
1402 reg = <0 0x00a94000 0 0x4000>;
1403 clock-names = "se";
1404 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1405 pinctrl-names = "default";
89345355 1406 pinctrl-0 = <&qup_i2c13_default>;
06bf656e 1407 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1408 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1409 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1410 dma-names = "tx", "rx";
06bf656e
JM		 1411 #address-cells = <1>;
1412 #size-cells = <0>;
1413 status = "disabled";
1414 };
89345355
KD		 1415
1416 spi13: spi@a94000 {
1417 compatible = "qcom,geni-spi";
1418 reg = <0 0x00a94000 0 0x4000>;
1419 clock-names = "se";
1420 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1421 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1422 power-domains = <&rpmhpd SM8350_CX>;
1423 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1424 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1425 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1426 dma-names = "tx", "rx";
89345355
KD		 1427 #address-cells = <1>;
1428 #size-cells = <0>;
1429 status = "disabled";
1430 };
06bf656e
JM		 1431 };
1432
1417372f
DB		 1433 rng: rng@10d3000 {
1434 compatible = "qcom,prng-ee";
1435 reg = <0 0x010d3000 0 0x1000>;
1436 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1437 clock-names = "core";
1438 };
1439
da6b2482
VK		 1440 config_noc: interconnect@1500000 {
1441 compatible = "qcom,sm8350-config-noc";
1442 reg = <0 0x01500000 0 0xa580>;
4f287e31 1443 #interconnect-cells = <2>;
da6b2482
VK		 1444 qcom,bcm-voters = <&apps_bcm_voter>;
1445 };
1446
1447 mc_virt: interconnect@1580000 {
1448 compatible = "qcom,sm8350-mc-virt";
1449 reg = <0 0x01580000 0 0x1000>;
4f287e31 1450 #interconnect-cells = <2>;
da6b2482
VK		 1451 qcom,bcm-voters = <&apps_bcm_voter>;
1452 };
1453
1454 system_noc: interconnect@1680000 {
1455 compatible = "qcom,sm8350-system-noc";
1456 reg = <0 0x01680000 0 0x1c200>;
4f287e31 1457 #interconnect-cells = <2>;
da6b2482
VK		 1458 qcom,bcm-voters = <&apps_bcm_voter>;
1459 };
1460
1461 aggre1_noc: interconnect@16e0000 {
1462 compatible = "qcom,sm8350-aggre1-noc";
1463 reg = <0 0x016e0000 0 0x1f180>;
4f287e31 1464 #interconnect-cells = <2>;
da6b2482
VK		 1465 qcom,bcm-voters = <&apps_bcm_voter>;
1466 };
1467
1468 aggre2_noc: interconnect@1700000 {
1469 compatible = "qcom,sm8350-aggre2-noc";
1470 reg = <0 0x01700000 0 0x33000>;
4f287e31 1471 #interconnect-cells = <2>;
da6b2482
VK		 1472 qcom,bcm-voters = <&apps_bcm_voter>;
1473 };
1474
1475 mmss_noc: interconnect@1740000 {
1476 compatible = "qcom,sm8350-mmss-noc";
1477 reg = <0 0x01740000 0 0x1f080>;
4f287e31 1478 #interconnect-cells = <2>;
da6b2482
VK		 1479 qcom,bcm-voters = <&apps_bcm_voter>;
1480 };
1481
6daee406
DB		 1482 pcie0: pci@1c00000 {
1483 compatible = "qcom,pcie-sm8350";
1484 reg = <0 0x01c00000 0 0x3000>,
1485 <0 0x60000000 0 0xf1d>,
1486 <0 0x60000f20 0 0xa8>,
1487 <0 0x60001000 0 0x1000>,
1488 <0 0x60100000 0 0x100000>;
1489 reg-names = "parf", "dbi", "elbi", "atu", "config";
1490 device_type = "pci";
1491 linux,pci-domain = <0>;
1492 bus-range = <0x00 0xff>;
1493 num-lanes = <1>;
1494
1495 #address-cells = <3>;
1496 #size-cells = <2>;
1497
1498 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1499 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1500
1501 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1508 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1509 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1510 "msi4", "msi5", "msi6", "msi7";
1511 #interrupt-cells = <1>;
1512 interrupt-map-mask = <0 0 0 0x7>;
1513 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1514 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1515 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1516 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1517
1518 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1519 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1520 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1521 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1522 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1523 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1524 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1525 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1526 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
1527 clock-names = "aux",
1528 "cfg",
1529 "bus_master",
1530 "bus_slave",
1531 "slave_q2a",
1532 "tbu",
1533 "ddrss_sf_tbu",
1534 "aggre1",
1535 "aggre0";
1536
1537 iommus = <&apps_smmu 0x1c00 0x7f>;
1538 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1539 <0x100 &apps_smmu 0x1c01 0x1>;
1540
1541 resets = <&gcc GCC_PCIE_0_BCR>;
1542 reset-names = "pci";
1543
1544 power-domains = <&gcc PCIE_0_GDSC>;
1545
1546 phys = <&pcie0_phy>;
1547 phy-names = "pciephy";
1548
1549 status = "disabled";
1550 };
1551
1552 pcie0_phy: phy@1c06000 {
1553 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1554 reg = <0 0x01c06000 0 0x2000>;
1555 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1556 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1557 <&gcc GCC_PCIE_0_CLKREF_EN>,
1558 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
1559 <&gcc GCC_PCIE_0_PIPE_CLK>;
1560 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1561
1562 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1563 reset-names = "phy";
1564
1565 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1566 assigned-clock-rates = <100000000>;
1567
1568 #clock-cells = <0>;
1569 clock-output-names = "pcie_0_pipe_clk";
1570
1571 #phy-cells = <0>;
1572
1573 status = "disabled";
1574 };
1575
1576 pcie1: pci@1c08000 {
1577 compatible = "qcom,pcie-sm8350";
1578 reg = <0 0x01c08000 0 0x3000>,
1579 <0 0x40000000 0 0xf1d>,
1580 <0 0x40000f20 0 0xa8>,
1581 <0 0x40001000 0 0x1000>,
1582 <0 0x40100000 0 0x100000>;
1583 reg-names = "parf", "dbi", "elbi", "atu", "config";
1584 device_type = "pci";
1585 linux,pci-domain = <1>;
1586 bus-range = <0x00 0xff>;
1587 num-lanes = <2>;
1588
1589 #address-cells = <3>;
1590 #size-cells = <2>;
1591
1592 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1593 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1594
1595 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1596 interrupt-names = "msi";
1597 #interrupt-cells = <1>;
1598 interrupt-map-mask = <0 0 0 0x7>;
1599 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1600 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1601 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1602 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1603
1604 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1605 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1606 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1607 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1608 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1609 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1610 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1611 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1612 clock-names = "aux",
1613 "cfg",
1614 "bus_master",
1615 "bus_slave",
1616 "slave_q2a",
1617 "tbu",
1618 "ddrss_sf_tbu",
1619 "aggre1";
1620
1621 iommus = <&apps_smmu 0x1c80 0x7f>;
1622 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1623 <0x100 &apps_smmu 0x1c81 0x1>;
1624
1625 resets = <&gcc GCC_PCIE_1_BCR>;
1626 reset-names = "pci";
1627
1628 power-domains = <&gcc PCIE_1_GDSC>;
1629
1630 phys = <&pcie1_phy>;
1631 phy-names = "pciephy";
1632
1633 status = "disabled";
1634 };
1635
1636 pcie1_phy: phy@1c0f000 {
1637 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1638 reg = <0 0x01c0e000 0 0x2000>;
1639 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1640 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1641 <&gcc GCC_PCIE_1_CLKREF_EN>,
1642 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
1643 <&gcc GCC_PCIE_1_PIPE_CLK>;
1644 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1645
1646 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1647 reset-names = "phy";
1648
1649 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1650 assigned-clock-rates = <100000000>;
1651
1652 #clock-cells = <0>;
1653 clock-output-names = "pcie_1_pipe_clk";
1654
1655 #phy-cells = <0>;
1656
1657 status = "disabled";
1658 };
1659
1417372f
DB		 1660 ufs_mem_hc: ufshc@1d84000 {
1661 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1662 "jedec,ufs-2.0";
1663 reg = <0 0x01d84000 0 0x3000>;
1664 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1665 phys = <&ufs_mem_phy_lanes>;
1666 phy-names = "ufsphy";
1667 lanes-per-direction = <2>;
1668 #reset-cells = <1>;
1669 resets = <&gcc GCC_UFS_PHY_BCR>;
1670 reset-names = "rst";
1671
1672 power-domains = <&gcc UFS_PHY_GDSC>;
1673
1674 iommus = <&apps_smmu 0xe0 0x0>;
1675
1676 clock-names =
1677 "core_clk",
1678 "bus_aggr_clk",
1679 "iface_clk",
1680 "core_clk_unipro",
1681 "ref_clk",
1682 "tx_lane0_sync_clk",
1683 "rx_lane0_sync_clk",
1684 "rx_lane1_sync_clk";
1685 clocks =
1686 <&gcc GCC_UFS_PHY_AXI_CLK>,
1687 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1688 <&gcc GCC_UFS_PHY_AHB_CLK>,
1689 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1690 <&rpmhcc RPMH_CXO_CLK>,
1691 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1692 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1693 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1694 freq-table-hz =
1695 <75000000 300000000>,
1696 <0 0>,
1697 <0 0>,
1698 <75000000 300000000>,
1699 <0 0>,
1700 <0 0>,
1701 <0 0>,
1702 <0 0>;
1703 status = "disabled";
da6b2482
VK		 1704 };
1705
1417372f
DB		 1706 ufs_mem_phy: phy@1d87000 {
1707 compatible = "qcom,sm8350-qmp-ufs-phy";
1708 reg = <0 0x01d87000 0 0x1c4>;
1709 #address-cells = <2>;
1710 #size-cells = <2>;
1711 ranges;
1712 clock-names = "ref",
1713 "ref_aux";
1714 clocks = <&rpmhcc RPMH_CXO_CLK>,
1715 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1716
1717 resets = <&ufs_mem_hc 0>;
1718 reset-names = "ufsphy";
1719 status = "disabled";
1720
1721 ufs_mem_phy_lanes: phy@1d87400 {
1722 reg = <0 0x01d87400 0 0x188>,
1723 <0 0x01d87600 0 0x200>,
1724 <0 0x01d87c00 0 0x200>,
1725 <0 0x01d87800 0 0x188>,
1726 <0 0x01d87a00 0 0x200>;
1727 #clock-cells = <1>;
1728 #phy-cells = <0>;
1729 };
da6b2482
VK		 1730 };
1731
f11d3e7d
AE		 1732 ipa: ipa@1e40000 {
1733 compatible = "qcom,sm8350-ipa";
1734
1735 iommus = <&apps_smmu 0x5c0 0x0>,
1736 <&apps_smmu 0x5c2 0x0>;
f3c08ae6
KD		 1737 reg = <0 0x01e40000 0 0x8000>,
1738 <0 0x01e50000 0 0x4b20>,
1739 <0 0x01e04000 0 0x23000>;
f11d3e7d
AE		 1740 reg-names = "ipa-reg",
1741 "ipa-shared",
1742 "gsi";
1743
1744 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1745 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1746 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1747 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1748 interrupt-names = "ipa",
1749 "gsi",
1750 "ipa-clock-query",
1751 "ipa-setup-ready";
1752
1753 clocks = <&rpmhcc RPMH_IPA_CLK>;
1754 clock-names = "core";
1755
4f287e31
RF		 1756 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1757 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
84173ca3
AE		 1758 interconnect-names = "memory",
1759 "config";
f11d3e7d 1760
73419e4d
AE		 1761 qcom,qmp = <&aoss_qmp>;
1762
f11d3e7d
AE		 1763 qcom,smem-states = <&ipa_smp2p_out 0>,
1764 <&ipa_smp2p_out 1>;
1765 qcom,smem-state-names = "ipa-clock-enabled-valid",
1766 "ipa-clock-enabled";
1767
1768 status = "disabled";
1769 };
1770
b7e8f433
VK		 1771 tcsr_mutex: hwlock@1f40000 {
1772 compatible = "qcom,tcsr-mutex";
1773 reg = <0x0 0x01f40000 0x0 0x40000>;
1774 #hwlock-cells = <1>;
1775 };
1776
54af0ceb
DB		 1777 gpu: gpu@3d00000 {
1778 compatible = "qcom,adreno-660.1", "qcom,adreno";
1779
1780 reg = <0 0x03d00000 0 0x40000>,
1781 <0 0x03d9e000 0 0x1000>,
1782 <0 0x03d61000 0 0x800>;
1783 reg-names = "kgsl_3d0_reg_memory",
1784 "cx_mem",
1785 "cx_dbgc";
1786
1787 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1788
1789 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1790
1791 operating-points-v2 = <&gpu_opp_table>;
1792
1793 qcom,gmu = <&gmu>;
1794
1795 status = "disabled";
1796
1797 zap-shader {
1798 memory-region = <&pil_gpu_mem>;
1799 };
1800
1801 /* note: downstream checks gpu binning for 670 Mhz */
1802 gpu_opp_table: opp-table {
1803 compatible = "operating-points-v2";
1804
1805 opp-840000000 {
1806 opp-hz = /bits/ 64 <840000000>;
1807 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1808 };
1809
1810 opp-778000000 {
1811 opp-hz = /bits/ 64 <778000000>;
1812 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1813 };
1814
1815 opp-738000000 {
1816 opp-hz = /bits/ 64 <738000000>;
1817 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1818 };
1819
1820 opp-676000000 {
1821 opp-hz = /bits/ 64 <676000000>;
1822 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1823 };
1824
1825 opp-608000000 {
1826 opp-hz = /bits/ 64 <608000000>;
1827 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1828 };
1829
1830 opp-540000000 {
1831 opp-hz = /bits/ 64 <540000000>;
1832 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1833 };
1834
1835 opp-491000000 {
1836 opp-hz = /bits/ 64 <491000000>;
1837 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1838 };
1839
1840 opp-443000000 {
1841 opp-hz = /bits/ 64 <443000000>;
1842 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1843 };
1844
1845 opp-379000000 {
1846 opp-hz = /bits/ 64 <379000000>;
1847 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1848 };
1849
1850 opp-315000000 {
1851 opp-hz = /bits/ 64 <315000000>;
1852 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1853 };
1854 };
1855 };
1856
1857 gmu: gmu@3d6a000 {
1858 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1859
1860 reg = <0 0x03d6a000 0 0x34000>,
1861 <0 0x03de0000 0 0x10000>,
1862 <0 0x0b290000 0 0x10000>;
1863 reg-names = "gmu", "rscc", "gmu_pdc";
1864
1865 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1866 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1867 interrupt-names = "hfi", "gmu";
1868
1869 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1870 <&gpucc GPU_CC_CXO_CLK>,
1871 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1872 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1873 <&gpucc GPU_CC_AHB_CLK>,
1874 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1875 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
1876 clock-names = "gmu",
1877 "cxo",
1878 "axi",
1879 "memnoc",
1880 "ahb",
1881 "hub",
1882 "smmu_vote";
1883
1884 power-domains = <&gpucc GPU_CX_GDSC>,
1885 <&gpucc GPU_GX_GDSC>;
1886 power-domain-names = "cx",
1887 "gx";
1888
1889 iommus = <&adreno_smmu 5 0x400>;
1890
1891 operating-points-v2 = <&gmu_opp_table>;
1892
1893 gmu_opp_table: opp-table {
1894 compatible = "operating-points-v2";
1895
1896 opp-200000000 {
1897 opp-hz = /bits/ 64 <200000000>;
1898 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1899 };
1900 };
1901 };
1902
1903 gpucc: clock-controller@3d90000 {
1904 compatible = "qcom,sm8350-gpucc";
1905 reg = <0 0x03d90000 0 0x9000>;
1906 clocks = <&rpmhcc RPMH_CXO_CLK>,
1907 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1908 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1909 clock-names = "bi_tcxo",
1910 "gcc_gpu_gpll0_clk_src",
1911 "gcc_gpu_gpll0_div_clk_src";
1912 #clock-cells = <1>;
1913 #reset-cells = <1>;
1914 #power-domain-cells = <1>;
1915 };
1916
1917 adreno_smmu: iommu@3da0000 {
78c61b6b
KD		 1918 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
1919 "qcom,smmu-500", "arm,mmu-500";
54af0ceb
DB		 1920 reg = <0 0x03da0000 0 0x20000>;
1921 #iommu-cells = <2>;
1922 #global-interrupts = <2>;
1923 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1930 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1932 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1933 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1934 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1935
1936 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1937 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1938 <&gpucc GPU_CC_AHB_CLK>,
1939 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1940 <&gpucc GPU_CC_CX_GMU_CLK>,
1941 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1942 <&gpucc GPU_CC_HUB_AON_CLK>;
1943 clock-names = "bus",
1944 "iface",
1945 "ahb",
1946 "hlos1_vote_gpu_smmu",
1947 "cx_gmu",
1948 "hub_cx_int",
1949 "hub_aon";
1950
1951 power-domains = <&gpucc GPU_CX_GDSC>;
1952 dma-coherent;
1953 };
1954
1417372f
DB		 1955 lpass_ag_noc: interconnect@3c40000 {
1956 compatible = "qcom,sm8350-lpass-ag-noc";
1957 reg = <0 0x03c40000 0 0xf080>;
1958 #interconnect-cells = <2>;
1959 qcom,bcm-voters = <&apps_bcm_voter>;
1960 };
1961
177fcf0a
VK		 1962 mpss: remoteproc@4080000 {
1963 compatible = "qcom,sm8350-mpss-pas";
1964 reg = <0x0 0x04080000 0x0 0x4040>;
1965
1966 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1967 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1968 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1969 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1970 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1971 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1972 interrupt-names = "wdog", "fatal", "ready", "handover",
1973 "stop-ack", "shutdown-ack";
1974
1975 clocks = <&rpmhcc RPMH_CXO_CLK>;
1976 clock-names = "xo";
1977
d0e285c3
RF		 1978 power-domains = <&rpmhpd SM8350_CX>,
1979 <&rpmhpd SM8350_MSS>;
6b7cb2d2 1980 power-domain-names = "cx", "mss";
177fcf0a 1981
4f287e31 1982 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
da6b2482 1983
177fcf0a
VK		 1984 memory-region = <&pil_modem_mem>;
1985
6b7cb2d2
SS		 1986 qcom,qmp = <&aoss_qmp>;
1987
177fcf0a
VK		 1988 qcom,smem-states = <&smp2p_modem_out 0>;
1989 qcom,smem-state-names = "stop";
1990
1991 status = "disabled";
1992
1993 glink-edge {
1994 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1995 IPCC_MPROC_SIGNAL_GLINK_QMP
1996 IRQ_TYPE_EDGE_RISING>;
1997 mboxes = <&ipcc IPCC_CLIENT_MPSS
1998 IPCC_MPROC_SIGNAL_GLINK_QMP>;
177fcf0a
VK		 1999 label = "modem";
2000 qcom,remote-pid = <1>;
2001 };
2002 };
2003
1417372f
DB		 2004 slpi: remoteproc@5c00000 {
2005 compatible = "qcom,sm8350-slpi-pas";
2006 reg = <0 0x05c00000 0 0x4000>;
2007
2008 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2009 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2010 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2011 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2012 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2013 interrupt-names = "wdog", "fatal", "ready",
2014 "handover", "stop-ack";
2015
2016 clocks = <&rpmhcc RPMH_CXO_CLK>;
2017 clock-names = "xo";
2018
2019 power-domains = <&rpmhpd SM8350_LCX>,
2020 <&rpmhpd SM8350_LMX>;
2021 power-domain-names = "lcx", "lmx";
2022
2023 memory-region = <&pil_slpi_mem>;
2024
2025 qcom,qmp = <&aoss_qmp>;
2026
2027 qcom,smem-states = <&smp2p_slpi_out 0>;
2028 qcom,smem-state-names = "stop";
2029
2030 status = "disabled";
2031
2032 glink-edge {
2033 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2034 IPCC_MPROC_SIGNAL_GLINK_QMP
2035 IRQ_TYPE_EDGE_RISING>;
2036 mboxes = <&ipcc IPCC_CLIENT_SLPI
2037 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2038
2039 label = "slpi";
2040 qcom,remote-pid = <3>;
2041
2042 fastrpc {
2043 compatible = "qcom,fastrpc";
2044 qcom,glink-channels = "fastrpcglink-apps-dsp";
2045 label = "sdsp";
2046 qcom,non-secure-domain;
2047 #address-cells = <1>;
2048 #size-cells = <0>;
2049
2050 compute-cb@1 {
2051 compatible = "qcom,fastrpc-compute-cb";
2052 reg = <1>;
2053 iommus = <&apps_smmu 0x0541 0x0>;
2054 };
2055
2056 compute-cb@2 {
2057 compatible = "qcom,fastrpc-compute-cb";
2058 reg = <2>;
2059 iommus = <&apps_smmu 0x0542 0x0>;
2060 };
2061
2062 compute-cb@3 {
2063 compatible = "qcom,fastrpc-compute-cb";
2064 reg = <3>;
2065 iommus = <&apps_smmu 0x0543 0x0>;
2066 /* note: shared-cb = <4> in downstream */
2067 };
2068 };
2069 };
2070 };
2071
f5f6bd58
DB		 2072 sdhc_2: mmc@8804000 {
2073 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2074 reg = <0 0x08804000 0 0x1000>;
177fcf0a 2075
f5f6bd58
DB		 2076 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2077 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2078 interrupt-names = "hc_irq", "pwr_irq";
177fcf0a 2079
f5f6bd58
DB		 2080 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2081 <&gcc GCC_SDCC2_APPS_CLK>,
2082 <&rpmhcc RPMH_CXO_CLK>;
2083 clock-names = "iface", "core", "xo";
2084 resets = <&gcc GCC_SDCC2_BCR>;
2085 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2086 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2087 interconnect-names = "sdhc-ddr","cpu-sdhc";
2088 iommus = <&apps_smmu 0x4a0 0x0>;
2089 power-domains = <&rpmhpd SM8350_CX>;
2090 operating-points-v2 = <&sdhc2_opp_table>;
2091 bus-width = <4>;
2092 dma-coherent;
177fcf0a 2093
f5f6bd58 2094 status = "disabled";
da6b2482 2095
f5f6bd58
DB		 2096 sdhc2_opp_table: opp-table {
2097 compatible = "operating-points-v2";
177fcf0a 2098
f5f6bd58
DB		 2099 opp-100000000 {
2100 opp-hz = /bits/ 64 <100000000>;
2101 required-opps = <&rpmhpd_opp_low_svs>;
2102 };
6b7cb2d2 2103
f5f6bd58
DB		 2104 opp-202000000 {
2105 opp-hz = /bits/ 64 <202000000>;
2106 required-opps = <&rpmhpd_opp_svs_l1>;
2107 };
2108 };
2109 };
177fcf0a 2110
f5f6bd58
DB		 2111 usb_1_hsphy: phy@88e3000 {
2112 compatible = "qcom,sm8350-usb-hs-phy",
2113 "qcom,usb-snps-hs-7nm-phy";
2114 reg = <0 0x088e3000 0 0x400>;
177fcf0a 2115 status = "disabled";
f5f6bd58 2116 #phy-cells = <0>;
177fcf0a 2117
f5f6bd58
DB		 2118 clocks = <&rpmhcc RPMH_CXO_CLK>;
2119 clock-names = "ref";
177fcf0a 2120
f5f6bd58
DB		 2121 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2122 };
178056a4 2123
f5f6bd58
DB		 2124 usb_2_hsphy: phy@88e4000 {
2125 compatible = "qcom,sm8250-usb-hs-phy",
2126 "qcom,usb-snps-hs-7nm-phy";
2127 reg = <0 0x088e4000 0 0x400>;
2128 status = "disabled";
2129 #phy-cells = <0>;
178056a4 2130
f5f6bd58
DB		 2131 clocks = <&rpmhcc RPMH_CXO_CLK>;
2132 clock-names = "ref";
e780fb31 2133
6d91e201 2134 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
e780fb31
JP		 2135 };
2136
2137 usb_1_qmpphy: phy-wrapper@88e9000 {
2138 compatible = "qcom,sm8350-qmp-usb3-phy";
2139 reg = <0 0x088e9000 0 0x200>,
2140 <0 0x088e8000 0 0x20>;
e780fb31 2141 status = "disabled";
e780fb31
JP		 2142 #address-cells = <2>;
2143 #size-cells = <2>;
2144 ranges;
2145
6d91e201 2146 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
e780fb31 2147 <&rpmhcc RPMH_CXO_CLK>,
6d91e201 2148 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
e780fb31
JP		 2149 clock-names = "aux", "ref_clk_src", "com_aux";
2150
6d91e201
VK		 2151 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2152 <&gcc GCC_USB3_PHY_PRIM_BCR>;
e780fb31
JP		 2153 reset-names = "phy", "common";
2154
2155 usb_1_ssphy: phy@88e9200 {
2156 reg = <0 0x088e9200 0 0x200>,
2157 <0 0x088e9400 0 0x200>,
2158 <0 0x088e9c00 0 0x400>,
2159 <0 0x088e9600 0 0x200>,
2160 <0 0x088e9800 0 0x200>,
2161 <0 0x088e9a00 0 0x100>;
2162 #phy-cells = <0>;
af551554 2163 #clock-cells = <0>;
6d91e201 2164 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
e780fb31
JP		 2165 clock-names = "pipe0";
2166 clock-output-names = "usb3_phy_pipe_clk_src";
2167 };
2168 };
2169
2170 usb_2_qmpphy: phy-wrapper@88eb000 {
2171 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2172 reg = <0 0x088eb000 0 0x200>;
2173 status = "disabled";
e780fb31
JP		 2174 #address-cells = <2>;
2175 #size-cells = <2>;
2176 ranges;
2177
6d91e201 2178 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
e780fb31 2179 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 2180 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2181 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
e780fb31
JP		 2182 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2183
6d91e201
VK		 2184 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2185 <&gcc GCC_USB3_PHY_SEC_BCR>;
e780fb31
JP		 2186 reset-names = "phy", "common";
2187
2188 usb_2_ssphy: phy@88ebe00 {
2189 reg = <0 0x088ebe00 0 0x200>,
2190 <0 0x088ec000 0 0x200>,
2191 <0 0x088eb200 0 0x1100>;
2192 #phy-cells = <0>;
af551554 2193 #clock-cells = <0>;
6d91e201 2194 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
e780fb31
JP		 2195 clock-names = "pipe0";
2196 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2197 };
2198 };
2199
1dee9e3b 2200 dc_noc: interconnect@90c0000 {
da6b2482
VK		 2201 compatible = "qcom,sm8350-dc-noc";
2202 reg = <0 0x090c0000 0 0x4200>;
4f287e31 2203 #interconnect-cells = <2>;
da6b2482
VK		 2204 qcom,bcm-voters = <&apps_bcm_voter>;
2205 };
2206
2207 gem_noc: interconnect@9100000 {
2208 compatible = "qcom,sm8350-gem-noc";
2209 reg = <0 0x09100000 0 0xb4000>;
4f287e31 2210 #interconnect-cells = <2>;
da6b2482
VK		 2211 qcom,bcm-voters = <&apps_bcm_voter>;
2212 };
2213
9ac8999e
KD		 2214 system-cache-controller@9200000 {
2215 compatible = "qcom,sm8350-llcc";
7ae317cb
MS		 2216 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2217 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2218 <0 0x09600000 0 0x58000>;
2219 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2220 "llcc3_base", "llcc_broadcast_base";
9ac8999e
KD		 2221 };
2222
1417372f
DB		 2223 compute_noc: interconnect@a0c0000 {
2224 compatible = "qcom,sm8350-compute-noc";
2225 reg = <0 0x0a0c0000 0 0xa180>;
2226 #interconnect-cells = <2>;
2227 qcom,bcm-voters = <&apps_bcm_voter>;
2228 };
2229
e780fb31
JP		 2230 usb_1: usb@a6f8800 {
2231 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2232 reg = <0 0x0a6f8800 0 0x400>;
2233 status = "disabled";
2234 #address-cells = <2>;
2235 #size-cells = <2>;
2236 ranges;
2237
6d91e201
VK		 2238 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2239 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2240 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
8d5fd4e4
KK		 2241 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2242 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2243 clock-names = "cfg_noc",
2244 "core",
2245 "iface",
2246 "sleep",
2247 "mock_utmi";
e780fb31 2248
6d91e201
VK		 2249 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2250 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
e780fb31
JP		 2251 assigned-clock-rates = <19200000>, <200000000>;
2252
2253 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
5b7e3499 2254 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
e780fb31 2255 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
5b7e3499
JH		 2256 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2257 interrupt-names = "hs_phy_irq",
2258 "ss_phy_irq",
2259 "dm_hs_phy_irq",
2260 "dp_hs_phy_irq";
e780fb31 2261
6d91e201 2262 power-domains = <&gcc USB30_PRIM_GDSC>;
e780fb31 2263
6d91e201 2264 resets = <&gcc GCC_USB30_PRIM_BCR>;
e780fb31 2265
2aa2b50d 2266 usb_1_dwc3: usb@a600000 {
e780fb31
JP		 2267 compatible = "snps,dwc3";
2268 reg = <0 0x0a600000 0 0xcd00>;
2269 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2270 iommus = <&apps_smmu 0x0 0x0>;
2271 snps,dis_u2_susphy_quirk;
2272 snps,dis_enblslpm_quirk;
2273 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2274 phy-names = "usb2-phy", "usb3-phy";
2275 };
2276 };
2277
2278 usb_2: usb@a8f8800 {
2279 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2280 reg = <0 0x0a8f8800 0 0x400>;
2281 status = "disabled";
2282 #address-cells = <2>;
2283 #size-cells = <2>;
2284 ranges;
2285
6d91e201
VK		 2286 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2287 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2288 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
6d91e201 2289 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
8d5fd4e4 2290 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
6d91e201 2291 <&gcc GCC_USB3_SEC_CLKREF_EN>;
8d5fd4e4
KK		 2292 clock-names = "cfg_noc",
2293 "core",
2294 "iface",
2295 "sleep",
2296 "mock_utmi",
2297 "xo";
e780fb31 2298
6d91e201
VK		 2299 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2300 <&gcc GCC_USB30_SEC_MASTER_CLK>;
e780fb31
JP		 2301 assigned-clock-rates = <19200000>, <200000000>;
2302
2303 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
5b7e3499 2304 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
e780fb31 2305 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
5b7e3499
JH		 2306 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2307 interrupt-names = "hs_phy_irq",
2308 "ss_phy_irq",
2309 "dm_hs_phy_irq",
2310 "dp_hs_phy_irq";
e780fb31 2311
6d91e201 2312 power-domains = <&gcc USB30_SEC_GDSC>;
e780fb31 2313
6d91e201 2314 resets = <&gcc GCC_USB30_SEC_BCR>;
e780fb31 2315
2aa2b50d 2316 usb_2_dwc3: usb@a800000 {
e780fb31
JP		 2317 compatible = "snps,dwc3";
2318 reg = <0 0x0a800000 0 0xcd00>;
2319 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2320 iommus = <&apps_smmu 0x20 0x0>;
2321 snps,dis_u2_susphy_quirk;
2322 snps,dis_enblslpm_quirk;
2323 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2324 phy-names = "usb2-phy", "usb3-phy";
2325 };
2326 };
177fcf0a 2327
d4a44105
RF		 2328 mdss: display-subsystem@ae00000 {
2329 compatible = "qcom,sm8350-mdss";
2330 reg = <0 0x0ae00000 0 0x1000>;
2331 reg-names = "mdss";
2332
2333 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2334 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2335 interconnect-names = "mdp0-mem", "mdp1-mem";
2336
2337 power-domains = <&dispcc MDSS_GDSC>;
2338 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2339
2340 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2341 <&gcc GCC_DISP_HF_AXI_CLK>,
2342 <&gcc GCC_DISP_SF_AXI_CLK>,
2343 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2344 clock-names = "iface", "bus", "nrt_bus", "core";
2345
2346 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2347 interrupt-controller;
2348 #interrupt-cells = <1>;
2349
2350 iommus = <&apps_smmu 0x820 0x402>;
2351
2352 status = "disabled";
2353
2354 #address-cells = <2>;
2355 #size-cells = <2>;
2356 ranges;
2357
2358 dpu_opp_table: opp-table {
2359 compatible = "operating-points-v2";
2360
2361 /* TODO: opp-200000000 should work with
2362 * &rpmhpd_opp_low_svs, but one some of
2363 * sm8350_hdk boards reboot using this
2364 * opp.
2365 */
2366 opp-200000000 {
2367 opp-hz = /bits/ 64 <200000000>;
2368 required-opps = <&rpmhpd_opp_svs>;
2369 };
2370
2371 opp-300000000 {
2372 opp-hz = /bits/ 64 <300000000>;
2373 required-opps = <&rpmhpd_opp_svs>;
2374 };
2375
2376 opp-345000000 {
2377 opp-hz = /bits/ 64 <345000000>;
2378 required-opps = <&rpmhpd_opp_svs_l1>;
2379 };
2380
2381 opp-460000000 {
2382 opp-hz = /bits/ 64 <460000000>;
2383 required-opps = <&rpmhpd_opp_nom>;
2384 };
2385 };
2386
2387 mdss_mdp: display-controller@ae01000 {
2388 compatible = "qcom,sm8350-dpu";
2389 reg = <0 0x0ae01000 0 0x8f000>,
2390 <0 0x0aeb0000 0 0x2008>;
2391 reg-names = "mdp", "vbif";
2392
2393 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2394 <&gcc GCC_DISP_SF_AXI_CLK>,
2395 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2396 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2397 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2398 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2399 clock-names = "bus",
2400 "nrt_bus",
2401 "iface",
2402 "lut",
2403 "core",
2404 "vsync";
2405
2406 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2407 assigned-clock-rates = <19200000>;
2408
2409 operating-points-v2 = <&dpu_opp_table>;
2410 power-domains = <&rpmhpd SM8350_MMCX>;
2411
2412 interrupt-parent = <&mdss>;
2413 interrupts = <0>;
2414
2415 ports {
2416 #address-cells = <1>;
2417 #size-cells = <0>;
2418
2419 port@0 {
2420 reg = <0>;
2421 dpu_intf1_out: endpoint {
2a07efb8 2422 remote-endpoint = <&mdss_dsi0_in>;
d4a44105
RF		 2423 };
2424 };
b904227a
KD		 2425
2426 port@1 {
2427 reg = <1>;
2428 dpu_intf2_out: endpoint {
2429 remote-endpoint = <&mdss_dsi1_in>;
2430 };
2431 };
d4a44105
RF		 2432 };
2433 };
2434
2435 mdss_dsi0: dsi@ae94000 {
d7133d6d 2436 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
d4a44105
RF		 2437 reg = <0 0x0ae94000 0 0x400>;
2438 reg-names = "dsi_ctrl";
2439
2440 interrupt-parent = <&mdss>;
2441 interrupts = <4>;
2442
2443 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2444 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2445 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2446 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2447 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2448 <&gcc GCC_DISP_HF_AXI_CLK>;
2449 clock-names = "byte",
2450 "byte_intf",
2451 "pixel",
2452 "core",
2453 "iface",
2454 "bus";
2455
2456 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2457 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2458 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2459 <&mdss_dsi0_phy 1>;
2460
2461 operating-points-v2 = <&dsi0_opp_table>;
2462 power-domains = <&rpmhpd SM8350_MMCX>;
2463
2464 phys = <&mdss_dsi0_phy>;
2465
6636818e
KD		 2466 #address-cells = <1>;
2467 #size-cells = <0>;
2468
d4a44105
RF		 2469 status = "disabled";
2470
2471 dsi0_opp_table: opp-table {
2472 compatible = "operating-points-v2";
2473
2474 /* TODO: opp-187500000 should work with
2475 * &rpmhpd_opp_low_svs, but one some of
2476 * sm8350_hdk boards reboot using this
2477 * opp.
2478 */
2479 opp-187500000 {
2480 opp-hz = /bits/ 64 <187500000>;
2481 required-opps = <&rpmhpd_opp_svs>;
2482 };
2483
2484 opp-300000000 {
2485 opp-hz = /bits/ 64 <300000000>;
2486 required-opps = <&rpmhpd_opp_svs>;
2487 };
2488
2489 opp-358000000 {
2490 opp-hz = /bits/ 64 <358000000>;
2491 required-opps = <&rpmhpd_opp_svs_l1>;
2492 };
2493 };
2494
2495 ports {
2496 #address-cells = <1>;
2497 #size-cells = <0>;
2498
2499 port@0 {
2500 reg = <0>;
2a07efb8 2501 mdss_dsi0_in: endpoint {
d4a44105
RF		 2502 remote-endpoint = <&dpu_intf1_out>;
2503 };
2504 };
2505
2506 port@1 {
2507 reg = <1>;
2a07efb8 2508 mdss_dsi0_out: endpoint {
d4a44105
RF		 2509 };
2510 };
2511 };
2512 };
2513
51f83fbb
DB		 2514 mdss_dsi0_phy: phy@ae94400 {
2515 compatible = "qcom,sm8350-dsi-phy-5nm";
2516 reg = <0 0x0ae94400 0 0x200>,
2517 <0 0x0ae94600 0 0x280>,
2518 <0 0x0ae94900 0 0x27c>;
2519 reg-names = "dsi_phy",
2520 "dsi_phy_lane",
2521 "dsi_pll";
2522
2523 #clock-cells = <1>;
2524 #phy-cells = <0>;
2525
2526 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2527 <&rpmhcc RPMH_CXO_CLK>;
2528 clock-names = "iface", "ref";
2529
2530 status = "disabled";
2531 };
2532
2533 mdss_dsi1: dsi@ae96000 {
2534 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2535 reg = <0 0x0ae96000 0 0x400>;
2536 reg-names = "dsi_ctrl";
2537
2538 interrupt-parent = <&mdss>;
2539 interrupts = <5>;
2540
2541 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2542 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2543 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2544 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2545 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2546 <&gcc GCC_DISP_HF_AXI_CLK>;
2547 clock-names = "byte",
2548 "byte_intf",
2549 "pixel",
2550 "core",
2551 "iface",
2552 "bus";
2553
2554 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2555 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2556 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2557 <&mdss_dsi1_phy 1>;
2558
2559 operating-points-v2 = <&dsi1_opp_table>;
2560 power-domains = <&rpmhpd SM8350_MMCX>;
2561
2562 phys = <&mdss_dsi1_phy>;
2563
2564 #address-cells = <1>;
2565 #size-cells = <0>;
2566
2567 status = "disabled";
2568
2569 dsi1_opp_table: opp-table {
2570 compatible = "operating-points-v2";
2571
2572 /* TODO: opp-187500000 should work with
2573 * &rpmhpd_opp_low_svs, but one some of
2574 * sm8350_hdk boards reboot using this
2575 * opp.
2576 */
2577 opp-187500000 {
2578 opp-hz = /bits/ 64 <187500000>;
2579 required-opps = <&rpmhpd_opp_svs>;
2580 };
2581
2582 opp-300000000 {
2583 opp-hz = /bits/ 64 <300000000>;
2584 required-opps = <&rpmhpd_opp_svs>;
2585 };
2586
2587 opp-358000000 {
2588 opp-hz = /bits/ 64 <358000000>;
2589 required-opps = <&rpmhpd_opp_svs_l1>;
2590 };
2591 };
2592
2593 ports {
2594 #address-cells = <1>;
2595 #size-cells = <0>;
2596
2597 port@0 {
2598 reg = <0>;
2599 mdss_dsi1_in: endpoint {
2600 remote-endpoint = <&dpu_intf2_out>;
2601 };
2602 };
2603
2604 port@1 {
2605 reg = <1>;
2606 mdss_dsi1_out: endpoint {
2607 };
2608 };
2609 };
2610 };
2611
2612 mdss_dsi1_phy: phy@ae96400 {
2613 compatible = "qcom,sm8350-dsi-phy-5nm";
2614 reg = <0 0x0ae96400 0 0x200>,
2615 <0 0x0ae96600 0 0x280>,
2616 <0 0x0ae96900 0 0x27c>;
2617 reg-names = "dsi_phy",
2618 "dsi_phy_lane",
2619 "dsi_pll";
2620
2621 #clock-cells = <1>;
2622 #phy-cells = <0>;
2623
2624 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2625 <&rpmhcc RPMH_CXO_CLK>;
2626 clock-names = "iface", "ref";
2627
2628 status = "disabled";
2629 };
2630 };
2631
2632 dispcc: clock-controller@af00000 {
2633 compatible = "qcom,sm8350-dispcc";
2634 reg = <0 0x0af00000 0 0x10000>;
2635 clocks = <&rpmhcc RPMH_CXO_CLK>,
2636 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2637 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2638 <0>,
2639 <0>;
2640 clock-names = "bi_tcxo",
2641 "dsi0_phy_pll_out_byteclk",
2642 "dsi0_phy_pll_out_dsiclk",
2643 "dsi1_phy_pll_out_byteclk",
2644 "dsi1_phy_pll_out_dsiclk",
2645 "dp_phy_pll_link_clk",
2646 "dp_phy_pll_vco_div_clk";
2647 #clock-cells = <1>;
2648 #reset-cells = <1>;
2649 #power-domain-cells = <1>;
2650
2651 power-domains = <&rpmhpd SM8350_MMCX>;
2652 };
2653
2654 pdc: interrupt-controller@b220000 {
2655 compatible = "qcom,sm8350-pdc", "qcom,pdc";
2656 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2657 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2658 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
2659 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
2660 <156 716 12>;
2661 #interrupt-cells = <2>;
2662 interrupt-parent = <&intc>;
2663 interrupt-controller;
2664 };
2665
2666 tsens0: thermal-sensor@c263000 {
2667 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2668 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2669 <0 0x0c222000 0 0x8>; /* SROT */
2670 #qcom,sensors = <15>;
2671 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2672 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2673 interrupt-names = "uplow", "critical";
2674 #thermal-sensor-cells = <1>;
2675 };
2676
2677 tsens1: thermal-sensor@c265000 {
2678 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2679 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2680 <0 0x0c223000 0 0x8>; /* SROT */
2681 #qcom,sensors = <14>;
2682 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2683 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2684 interrupt-names = "uplow", "critical";
2685 #thermal-sensor-cells = <1>;
2686 };
2687
2688 aoss_qmp: power-management@c300000 {
2689 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2690 reg = <0 0x0c300000 0 0x400>;
2691 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2692 IRQ_TYPE_EDGE_RISING>;
2693 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2694
2695 #clock-cells = <0>;
2696 };
2697
2698 sram@c3f0000 {
2699 compatible = "qcom,rpmh-stats";
2700 reg = <0 0x0c3f0000 0 0x400>;
2701 };
2702
2703 spmi_bus: spmi@c440000 {
2704 compatible = "qcom,spmi-pmic-arb";
2705 reg = <0x0 0x0c440000 0x0 0x1100>,
2706 <0x0 0x0c600000 0x0 0x2000000>,
2707 <0x0 0x0e600000 0x0 0x100000>,
2708 <0x0 0x0e700000 0x0 0xa0000>,
2709 <0x0 0x0c40a000 0x0 0x26000>;
2710 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2711 interrupt-names = "periph_irq";
2712 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2713 qcom,ee = <0>;
2714 qcom,channel = <0>;
2715 #address-cells = <2>;
2716 #size-cells = <0>;
2717 interrupt-controller;
2718 #interrupt-cells = <4>;
2719 };
2720
2721 tlmm: pinctrl@f100000 {
2722 compatible = "qcom,sm8350-tlmm";
2723 reg = <0 0x0f100000 0 0x300000>;
2724 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2725 gpio-controller;
2726 #gpio-cells = <2>;
2727 interrupt-controller;
2728 #interrupt-cells = <2>;
2729 gpio-ranges = <&tlmm 0 0 204>;
2730 wakeup-parent = <&pdc>;
2731
2732 sdc2_default_state: sdc2-default-state {
2733 clk-pins {
2734 pins = "sdc2_clk";
2735 drive-strength = <16>;
2736 bias-disable;
2737 };
2738
2739 cmd-pins {
2740 pins = "sdc2_cmd";
2741 drive-strength = <16>;
2742 bias-pull-up;
2743 };
2744
2745 data-pins {
2746 pins = "sdc2_data";
2747 drive-strength = <16>;
2748 bias-pull-up;
2749 };
2750 };
2751
2752 sdc2_sleep_state: sdc2-sleep-state {
2753 clk-pins {
2754 pins = "sdc2_clk";
2755 drive-strength = <2>;
2756 bias-disable;
2757 };
d4a44105 2758
51f83fbb
DB		 2759 cmd-pins {
2760 pins = "sdc2_cmd";
2761 drive-strength = <2>;
2762 bias-pull-up;
2763 };
d4a44105 2764
51f83fbb
DB		 2765 data-pins {
2766 pins = "sdc2_data";
2767 drive-strength = <2>;
2768 bias-pull-up;
2769 };
d4a44105
RF		 2770 };
2771
51f83fbb
DB		 2772 qup_uart3_default_state: qup-uart3-default-state {
2773 rx-pins {
2774 pins = "gpio18";
2775 function = "qup3";
2776 };
2777 tx-pins {
2778 pins = "gpio19";
2779 function = "qup3";
2780 };
2781 };
f5f6bd58 2782
51f83fbb
DB		 2783 qup_uart6_default: qup-uart6-default-state {
2784 pins = "gpio30", "gpio31";
2785 function = "qup6";
2786 drive-strength = <2>;
2787 bias-disable;
2788 };
f5f6bd58 2789
51f83fbb
DB		 2790 qup_uart18_default: qup-uart18-default-state {
2791 pins = "gpio58", "gpio59";
2792 function = "qup18";
2793 drive-strength = <2>;
2794 bias-disable;
2795 };
f5f6bd58 2796
51f83fbb
DB		 2797 qup_i2c0_default: qup-i2c0-default-state {
2798 pins = "gpio4", "gpio5";
2799 function = "qup0";
2800 drive-strength = <2>;
2801 bias-pull-up;
2802 };
f5f6bd58 2803
51f83fbb
DB		 2804 qup_i2c1_default: qup-i2c1-default-state {
2805 pins = "gpio8", "gpio9";
2806 function = "qup1";
2807 drive-strength = <2>;
2808 bias-pull-up;
2809 };
f5f6bd58 2810
51f83fbb
DB		 2811 qup_i2c2_default: qup-i2c2-default-state {
2812 pins = "gpio12", "gpio13";
2813 function = "qup2";
2814 drive-strength = <2>;
2815 bias-pull-up;
2816 };
f5f6bd58 2817
51f83fbb
DB		 2818 qup_i2c4_default: qup-i2c4-default-state {
2819 pins = "gpio20", "gpio21";
2820 function = "qup4";
2821 drive-strength = <2>;
2822 bias-pull-up;
2823 };
f5f6bd58 2824
51f83fbb
DB		 2825 qup_i2c5_default: qup-i2c5-default-state {
2826 pins = "gpio24", "gpio25";
2827 function = "qup5";
2828 drive-strength = <2>;
2829 bias-pull-up;
2830 };
f5f6bd58 2831
51f83fbb
DB		 2832 qup_i2c6_default: qup-i2c6-default-state {
2833 pins = "gpio28", "gpio29";
2834 function = "qup6";
2835 drive-strength = <2>;
2836 bias-pull-up;
2837 };
f5f6bd58 2838
51f83fbb
DB		 2839 qup_i2c7_default: qup-i2c7-default-state {
2840 pins = "gpio32", "gpio33";
2841 function = "qup7";
2842 drive-strength = <2>;
2843 bias-disable;
2844 };
f5f6bd58 2845
51f83fbb
DB		 2846 qup_i2c8_default: qup-i2c8-default-state {
2847 pins = "gpio36", "gpio37";
2848 function = "qup8";
2849 drive-strength = <2>;
2850 bias-pull-up;
2851 };
f5f6bd58 2852
51f83fbb
DB		 2853 qup_i2c9_default: qup-i2c9-default-state {
2854 pins = "gpio40", "gpio41";
2855 function = "qup9";
2856 drive-strength = <2>;
2857 bias-pull-up;
2858 };
f5f6bd58 2859
51f83fbb
DB		 2860 qup_i2c10_default: qup-i2c10-default-state {
2861 pins = "gpio44", "gpio45";
2862 function = "qup10";
2863 drive-strength = <2>;
2864 bias-pull-up;
2865 };
f5f6bd58 2866
51f83fbb
DB		 2867 qup_i2c11_default: qup-i2c11-default-state {
2868 pins = "gpio48", "gpio49";
2869 function = "qup11";
2870 drive-strength = <2>;
2871 bias-pull-up;
2872 };
f5f6bd58 2873
51f83fbb
DB		 2874 qup_i2c12_default: qup-i2c12-default-state {
2875 pins = "gpio52", "gpio53";
2876 function = "qup12";
2877 drive-strength = <2>;
2878 bias-pull-up;
f5f6bd58
DB		 2879 };
2880
51f83fbb
DB		 2881 qup_i2c13_default: qup-i2c13-default-state {
2882 pins = "gpio0", "gpio1";
2883 function = "qup13";
2884 drive-strength = <2>;
2885 bias-pull-up;
2886 };
f5f6bd58 2887
51f83fbb
DB		 2888 qup_i2c14_default: qup-i2c14-default-state {
2889 pins = "gpio56", "gpio57";
2890 function = "qup14";
2891 drive-strength = <2>;
2892 bias-disable;
2893 };
f5f6bd58 2894
51f83fbb
DB		 2895 qup_i2c15_default: qup-i2c15-default-state {
2896 pins = "gpio60", "gpio61";
2897 function = "qup15";
2898 drive-strength = <2>;
2899 bias-disable;
2900 };
f5f6bd58 2901
51f83fbb
DB		 2902 qup_i2c16_default: qup-i2c16-default-state {
2903 pins = "gpio64", "gpio65";
2904 function = "qup16";
2905 drive-strength = <2>;
2906 bias-disable;
f5f6bd58 2907 };
f5f6bd58 2908
51f83fbb
DB		 2909 qup_i2c17_default: qup-i2c17-default-state {
2910 pins = "gpio72", "gpio73";
2911 function = "qup17";
2912 drive-strength = <2>;
2913 bias-disable;
2914 };
f5f6bd58 2915
51f83fbb
DB		 2916 qup_i2c19_default: qup-i2c19-default-state {
2917 pins = "gpio76", "gpio77";
2918 function = "qup19";
2919 drive-strength = <2>;
2920 bias-disable;
2921 };
f5f6bd58
DB		 2922 };
2923
2924 apps_smmu: iommu@15000000 {
2925 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
2926 reg = <0 0x15000000 0 0x100000>;
2927 #iommu-cells = <2>;
2928 #global-interrupts = <2>;
2929 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2930 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2931 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2932 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2933 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2934 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2935 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2936 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2939 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2940 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2941 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2942 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2943 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2944 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2945 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2946 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2947 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2948 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2949 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2950 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2951 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2952 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2953 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2954 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2955 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2956 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2957 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2958 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2959 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2960 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2961 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2962 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2963 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2964 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2965 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2966 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2967 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2968 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2969 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2970 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2971 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2972 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2973 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2974 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2975 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2976 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2977 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2978 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2979 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2980 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2981 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2982 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2983 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2984 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2985 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2986 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2987 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2988 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2989 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2990 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2991 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2992 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2993 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2994 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2995 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2996 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2997 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2998 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2999 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3000 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3002 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3003 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3004 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3005 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3006 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3007 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3008 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3009 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3010 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3011 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3012 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3013 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3014 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3015 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3016 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3017 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3018 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3019 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3020 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3021 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3022 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3023 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3024 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3025 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3026 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3027 };
3028
3029 adsp: remoteproc@17300000 {
3030 compatible = "qcom,sm8350-adsp-pas";
3031 reg = <0 0x17300000 0 0x100>;
3032
3033 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3034 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3035 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3036 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3037 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3038 interrupt-names = "wdog", "fatal", "ready",
3039 "handover", "stop-ack";
3040
3041 clocks = <&rpmhcc RPMH_CXO_CLK>;
3042 clock-names = "xo";
3043
3044 power-domains = <&rpmhpd SM8350_LCX>,
3045 <&rpmhpd SM8350_LMX>;
3046 power-domain-names = "lcx", "lmx";
3047
3048 memory-region = <&pil_adsp_mem>;
3049
3050 qcom,qmp = <&aoss_qmp>;
3051
3052 qcom,smem-states = <&smp2p_adsp_out 0>;
3053 qcom,smem-state-names = "stop";
3054
3055 status = "disabled";
3056
3057 glink-edge {
3058 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3059 IPCC_MPROC_SIGNAL_GLINK_QMP
3060 IRQ_TYPE_EDGE_RISING>;
3061 mboxes = <&ipcc IPCC_CLIENT_LPASS
3062 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3063
3064 label = "lpass";
3065 qcom,remote-pid = <2>;
3066
3067 fastrpc {
3068 compatible = "qcom,fastrpc";
3069 qcom,glink-channels = "fastrpcglink-apps-dsp";
3070 label = "adsp";
3071 qcom,non-secure-domain;
3072 #address-cells = <1>;
3073 #size-cells = <0>;
3074
3075 compute-cb@3 {
3076 compatible = "qcom,fastrpc-compute-cb";
3077 reg = <3>;
3078 iommus = <&apps_smmu 0x1803 0x0>;
3079 };
3080
3081 compute-cb@4 {
3082 compatible = "qcom,fastrpc-compute-cb";
3083 reg = <4>;
3084 iommus = <&apps_smmu 0x1804 0x0>;
3085 };
3086
3087 compute-cb@5 {
3088 compatible = "qcom,fastrpc-compute-cb";
3089 reg = <5>;
3090 iommus = <&apps_smmu 0x1805 0x0>;
3091 };
3092 };
3093 };
3094 };
3095
3096 intc: interrupt-controller@17a00000 {
3097 compatible = "arm,gic-v3";
3098 #interrupt-cells = <3>;
3099 interrupt-controller;
3100 #redistributor-regions = <1>;
3101 redistributor-stride = <0 0x20000>;
3102 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3103 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3104 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3105 };
3106
3107 timer@17c20000 {
3108 compatible = "arm,armv7-timer-mem";
3109 #address-cells = <1>;
3110 #size-cells = <1>;
3111 ranges = <0 0 0 0x20000000>;
3112 reg = <0x0 0x17c20000 0x0 0x1000>;
3113 clock-frequency = <19200000>;
3114
3115 frame@17c21000 {
3116 frame-number = <0>;
3117 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3118 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3119 reg = <0x17c21000 0x1000>,
3120 <0x17c22000 0x1000>;
3121 };
3122
3123 frame@17c23000 {
3124 frame-number = <1>;
3125 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3126 reg = <0x17c23000 0x1000>;
3127 status = "disabled";
3128 };
3129
3130 frame@17c25000 {
3131 frame-number = <2>;
3132 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3133 reg = <0x17c25000 0x1000>;
3134 status = "disabled";
3135 };
3136
3137 frame@17c27000 {
3138 frame-number = <3>;
3139 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3140 reg = <0x17c27000 0x1000>;
3141 status = "disabled";
3142 };
3143
3144 frame@17c29000 {
3145 frame-number = <4>;
3146 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3147 reg = <0x17c29000 0x1000>;
3148 status = "disabled";
3149 };
3150
3151 frame@17c2b000 {
3152 frame-number = <5>;
3153 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3154 reg = <0x17c2b000 0x1000>;
3155 status = "disabled";
3156 };
3157
3158 frame@17c2d000 {
3159 frame-number = <6>;
3160 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3161 reg = <0x17c2d000 0x1000>;
3162 status = "disabled";
3163 };
3164 };
d4a44105 3165
f5f6bd58
DB		 3166 apps_rsc: rsc@18200000 {
3167 label = "apps_rsc";
3168 compatible = "qcom,rpmh-rsc";
3169 reg = <0x0 0x18200000 0x0 0x10000>,
3170 <0x0 0x18210000 0x0 0x10000>,
3171 <0x0 0x18220000 0x0 0x10000>;
3172 reg-names = "drv-0", "drv-1", "drv-2";
3173 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3174 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3175 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3176 qcom,tcs-offset = <0xd00>;
3177 qcom,drv-id = <2>;
3178 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3179 <WAKE_TCS 3>, <CONTROL_TCS 0>;
3180 power-domains = <&CLUSTER_PD>;
d4a44105 3181
f5f6bd58
DB		 3182 rpmhcc: clock-controller {
3183 compatible = "qcom,sm8350-rpmh-clk";
3184 #clock-cells = <1>;
3185 clock-names = "xo";
3186 clocks = <&xo_board>;
3187 };
d4a44105 3188
f5f6bd58
DB		 3189 rpmhpd: power-controller {
3190 compatible = "qcom,sm8350-rpmhpd";
3191 #power-domain-cells = <1>;
3192 operating-points-v2 = <&rpmhpd_opp_table>;
d4a44105 3193
f5f6bd58
DB		 3194 rpmhpd_opp_table: opp-table {
3195 compatible = "operating-points-v2";
d4a44105 3196
f5f6bd58
DB		 3197 rpmhpd_opp_ret: opp1 {
3198 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3199 };
d4a44105 3200
f5f6bd58
DB		 3201 rpmhpd_opp_min_svs: opp2 {
3202 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3203 };
6636818e 3204
f5f6bd58
DB		 3205 rpmhpd_opp_low_svs: opp3 {
3206 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3207 };
d4a44105 3208
f5f6bd58
DB		 3209 rpmhpd_opp_svs: opp4 {
3210 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3211 };
d4a44105 3212
f5f6bd58
DB		 3213 rpmhpd_opp_svs_l1: opp5 {
3214 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
d4a44105
RF		 3215 };
3216
f5f6bd58
DB		 3217 rpmhpd_opp_nom: opp6 {
3218 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
d4a44105
RF		 3219 };
3220
f5f6bd58
DB		 3221 rpmhpd_opp_nom_l1: opp7 {
3222 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
d4a44105 3223 };
d4a44105 3224
f5f6bd58
DB		 3225 rpmhpd_opp_nom_l2: opp8 {
3226 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3227 };
d4a44105 3228
f5f6bd58
DB		 3229 rpmhpd_opp_turbo: opp9 {
3230 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
d4a44105
RF		 3231 };
3232
f5f6bd58
DB		 3233 rpmhpd_opp_turbo_l1: opp10 {
3234 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
d4a44105
RF		 3235 };
3236 };
3237 };
3238
f5f6bd58
DB		 3239 apps_bcm_voter: bcm-voter {
3240 compatible = "qcom,bcm-voter";
d4a44105
RF		 3241 };
3242 };
3243
f5f6bd58
DB		 3244 cpufreq_hw: cpufreq@18591000 {
3245 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3246 reg = <0 0x18591000 0 0x1000>,
3247 <0 0x18592000 0 0x1000>,
3248 <0 0x18593000 0 0x1000>;
3249 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
9fd4887c 3250
f5f6bd58
DB		 3251 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3252 clock-names = "xo", "alternate";
3253
3254 #freq-domain-cells = <1>;
c2a18730 3255 #clock-cells = <1>;
9fd4887c
RF		 3256 };
3257
f5f6bd58
DB		 3258 cdsp: remoteproc@98900000 {
3259 compatible = "qcom,sm8350-cdsp-pas";
3260 reg = <0 0x98900000 0 0x1400000>;
177fcf0a 3261
f5f6bd58
DB		 3262 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3263 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3264 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3265 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3266 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
177fcf0a
VK		 3267 interrupt-names = "wdog", "fatal", "ready",
3268 "handover", "stop-ack";
3269
3270 clocks = <&rpmhcc RPMH_CXO_CLK>;
3271 clock-names = "xo";
3272
f5f6bd58
DB		 3273 power-domains = <&rpmhpd SM8350_CX>,
3274 <&rpmhpd SM8350_MXC>;
3275 power-domain-names = "cx", "mxc";
177fcf0a 3276
f5f6bd58
DB		 3277 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3278
3279 memory-region = <&pil_cdsp_mem>;
177fcf0a 3280
6b7cb2d2
SS		 3281 qcom,qmp = <&aoss_qmp>;
3282
f5f6bd58 3283 qcom,smem-states = <&smp2p_cdsp_out 0>;
177fcf0a
VK		 3284 qcom,smem-state-names = "stop";
3285
3286 status = "disabled";
3287
3288 glink-edge {
f5f6bd58 3289 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
177fcf0a
VK		 3290 IPCC_MPROC_SIGNAL_GLINK_QMP
3291 IRQ_TYPE_EDGE_RISING>;
f5f6bd58 3292 mboxes = <&ipcc IPCC_CLIENT_CDSP
177fcf0a
VK		 3293 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3294
f5f6bd58
DB		 3295 label = "cdsp";
3296 qcom,remote-pid = <5>;
178056a4
OJ		 3297
3298 fastrpc {
3299 compatible = "qcom,fastrpc";
3300 qcom,glink-channels = "fastrpcglink-apps-dsp";
f5f6bd58 3301 label = "cdsp";
8c8ce95b 3302 qcom,non-secure-domain;
178056a4
OJ		 3303 #address-cells = <1>;
3304 #size-cells = <0>;
3305
f5f6bd58
DB		 3306 compute-cb@1 {
3307 compatible = "qcom,fastrpc-compute-cb";
3308 reg = <1>;
3309 iommus = <&apps_smmu 0x2161 0x0400>,
3310 <&apps_smmu 0x1181 0x0420>;
3311 };
3312
3313 compute-cb@2 {
3314 compatible = "qcom,fastrpc-compute-cb";
3315 reg = <2>;
3316 iommus = <&apps_smmu 0x2162 0x0400>,
3317 <&apps_smmu 0x1182 0x0420>;
3318 };
3319
178056a4
OJ		 3320 compute-cb@3 {
3321 compatible = "qcom,fastrpc-compute-cb";
3322 reg = <3>;
f5f6bd58
DB		 3323 iommus = <&apps_smmu 0x2163 0x0400>,
3324 <&apps_smmu 0x1183 0x0420>;
178056a4
OJ		 3325 };
3326
3327 compute-cb@4 {
3328 compatible = "qcom,fastrpc-compute-cb";
3329 reg = <4>;
f5f6bd58
DB		 3330 iommus = <&apps_smmu 0x2164 0x0400>,
3331 <&apps_smmu 0x1184 0x0420>;
178056a4
OJ		 3332 };
3333
3334 compute-cb@5 {
3335 compatible = "qcom,fastrpc-compute-cb";
3336 reg = <5>;
f5f6bd58
DB		 3337 iommus = <&apps_smmu 0x2165 0x0400>,
3338 <&apps_smmu 0x1185 0x0420>;
3339 };
3340
3341 compute-cb@6 {
3342 compatible = "qcom,fastrpc-compute-cb";
3343 reg = <6>;
3344 iommus = <&apps_smmu 0x2166 0x0400>,
3345 <&apps_smmu 0x1186 0x0420>;
178056a4 3346 };
f5f6bd58
DB		 3347
3348 compute-cb@7 {
3349 compatible = "qcom,fastrpc-compute-cb";
3350 reg = <7>;
3351 iommus = <&apps_smmu 0x2167 0x0400>,
3352 <&apps_smmu 0x1187 0x0420>;
3353 };
3354
3355 compute-cb@8 {
3356 compatible = "qcom,fastrpc-compute-cb";
3357 reg = <8>;
3358 iommus = <&apps_smmu 0x2168 0x0400>,
3359 <&apps_smmu 0x1188 0x0420>;
3360 };
3361
3362 /* note: secure cb9 in downstream */
178056a4 3363 };
177fcf0a
VK		 3364 };
3365 };
b7e8f433
VK		 3366 };
3367
4dcaa68e 3368 thermal_zones: thermal-zones {
20f9d94e
RF		 3369 cpu0-thermal {
3370 polling-delay-passive = <250>;
3371 polling-delay = <1000>;
3372
3373 thermal-sensors = <&tsens0 1>;
3374
3375 trips {
3376 cpu0_alert0: trip-point0 {
3377 temperature = <90000>;
3378 hysteresis = <2000>;
3379 type = "passive";
3380 };
3381
3382 cpu0_alert1: trip-point1 {
3383 temperature = <95000>;
3384 hysteresis = <2000>;
3385 type = "passive";
3386 };
3387
1364acc3 3388 cpu0_crit: cpu-crit {
20f9d94e
RF		 3389 temperature = <110000>;
3390 hysteresis = <1000>;
3391 type = "critical";
3392 };
3393 };
3394
3395 cooling-maps {
3396 map0 {
3397 trip = <&cpu0_alert0>;
3398 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3399 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3400 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3401 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3402 };
3403 map1 {
3404 trip = <&cpu0_alert1>;
3405 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3406 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3407 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3408 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3409 };
3410 };
3411 };
3412
3413 cpu1-thermal {
3414 polling-delay-passive = <250>;
3415 polling-delay = <1000>;
3416
3417 thermal-sensors = <&tsens0 2>;
3418
3419 trips {
3420 cpu1_alert0: trip-point0 {
3421 temperature = <90000>;
3422 hysteresis = <2000>;
3423 type = "passive";
3424 };
3425
3426 cpu1_alert1: trip-point1 {
3427 temperature = <95000>;
3428 hysteresis = <2000>;
3429 type = "passive";
3430 };
3431
1364acc3 3432 cpu1_crit: cpu-crit {
20f9d94e
RF		 3433 temperature = <110000>;
3434 hysteresis = <1000>;
3435 type = "critical";
3436 };
3437 };
3438
3439 cooling-maps {
3440 map0 {
3441 trip = <&cpu1_alert0>;
3442 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3443 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3444 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3445 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3446 };
3447 map1 {
3448 trip = <&cpu1_alert1>;
3449 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3450 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3451 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3452 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3453 };
3454 };
3455 };
3456
3457 cpu2-thermal {
3458 polling-delay-passive = <250>;
3459 polling-delay = <1000>;
3460
3461 thermal-sensors = <&tsens0 3>;
3462
3463 trips {
3464 cpu2_alert0: trip-point0 {
3465 temperature = <90000>;
3466 hysteresis = <2000>;
3467 type = "passive";
3468 };
3469
3470 cpu2_alert1: trip-point1 {
3471 temperature = <95000>;
3472 hysteresis = <2000>;
3473 type = "passive";
3474 };
3475
1364acc3 3476 cpu2_crit: cpu-crit {
20f9d94e
RF		 3477 temperature = <110000>;
3478 hysteresis = <1000>;
3479 type = "critical";
3480 };
3481 };
3482
3483 cooling-maps {
3484 map0 {
3485 trip = <&cpu2_alert0>;
3486 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3487 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3488 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3489 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3490 };
3491 map1 {
3492 trip = <&cpu2_alert1>;
3493 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3494 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3495 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3496 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3497 };
3498 };
3499 };
3500
3501 cpu3-thermal {
3502 polling-delay-passive = <250>;
3503 polling-delay = <1000>;
3504
3505 thermal-sensors = <&tsens0 4>;
3506
3507 trips {
3508 cpu3_alert0: trip-point0 {
3509 temperature = <90000>;
3510 hysteresis = <2000>;
3511 type = "passive";
3512 };
3513
3514 cpu3_alert1: trip-point1 {
3515 temperature = <95000>;
3516 hysteresis = <2000>;
3517 type = "passive";
3518 };
3519
1364acc3 3520 cpu3_crit: cpu-crit {
20f9d94e
RF		 3521 temperature = <110000>;
3522 hysteresis = <1000>;
3523 type = "critical";
3524 };
3525 };
3526
3527 cooling-maps {
3528 map0 {
3529 trip = <&cpu3_alert0>;
3530 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3531 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3532 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3533 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3534 };
3535 map1 {
3536 trip = <&cpu3_alert1>;
3537 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3538 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3539 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3540 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3541 };
3542 };
3543 };
3544
3545 cpu4-top-thermal {
3546 polling-delay-passive = <250>;
3547 polling-delay = <1000>;
3548
3549 thermal-sensors = <&tsens0 7>;
3550
3551 trips {
3552 cpu4_top_alert0: trip-point0 {
3553 temperature = <90000>;
3554 hysteresis = <2000>;
3555 type = "passive";
3556 };
3557
3558 cpu4_top_alert1: trip-point1 {
3559 temperature = <95000>;
3560 hysteresis = <2000>;
3561 type = "passive";
3562 };
3563
1364acc3 3564 cpu4_top_crit: cpu-crit {
20f9d94e
RF		 3565 temperature = <110000>;
3566 hysteresis = <1000>;
3567 type = "critical";
3568 };
3569 };
3570
3571 cooling-maps {
3572 map0 {
3573 trip = <&cpu4_top_alert0>;
3574 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3575 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3576 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3577 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3578 };
3579 map1 {
3580 trip = <&cpu4_top_alert1>;
3581 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3582 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3583 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3584 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3585 };
3586 };
3587 };
3588
3589 cpu5-top-thermal {
3590 polling-delay-passive = <250>;
3591 polling-delay = <1000>;
3592
3593 thermal-sensors = <&tsens0 8>;
3594
3595 trips {
3596 cpu5_top_alert0: trip-point0 {
3597 temperature = <90000>;
3598 hysteresis = <2000>;
3599 type = "passive";
3600 };
3601
3602 cpu5_top_alert1: trip-point1 {
3603 temperature = <95000>;
3604 hysteresis = <2000>;
3605 type = "passive";
3606 };
3607
1364acc3 3608 cpu5_top_crit: cpu-crit {
20f9d94e
RF		 3609 temperature = <110000>;
3610 hysteresis = <1000>;
3611 type = "critical";
3612 };
3613 };
3614
3615 cooling-maps {
3616 map0 {
3617 trip = <&cpu5_top_alert0>;
3618 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3619 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3620 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3621 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3622 };
3623 map1 {
3624 trip = <&cpu5_top_alert1>;
3625 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3626 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3627 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3628 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3629 };
3630 };
3631 };
3632
3633 cpu6-top-thermal {
3634 polling-delay-passive = <250>;
3635 polling-delay = <1000>;
3636
3637 thermal-sensors = <&tsens0 9>;
3638
3639 trips {
3640 cpu6_top_alert0: trip-point0 {
3641 temperature = <90000>;
3642 hysteresis = <2000>;
3643 type = "passive";
3644 };
3645
3646 cpu6_top_alert1: trip-point1 {
3647 temperature = <95000>;
3648 hysteresis = <2000>;
3649 type = "passive";
3650 };
3651
1364acc3 3652 cpu6_top_crit: cpu-crit {
20f9d94e
RF		 3653 temperature = <110000>;
3654 hysteresis = <1000>;
3655 type = "critical";
3656 };
3657 };
3658
3659 cooling-maps {
3660 map0 {
3661 trip = <&cpu6_top_alert0>;
3662 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3663 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3664 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3665 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3666 };
3667 map1 {
3668 trip = <&cpu6_top_alert1>;
3669 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3670 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3671 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3672 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3673 };
3674 };
3675 };
3676
3677 cpu7-top-thermal {
3678 polling-delay-passive = <250>;
3679 polling-delay = <1000>;
3680
3681 thermal-sensors = <&tsens0 10>;
3682
3683 trips {
3684 cpu7_top_alert0: trip-point0 {
3685 temperature = <90000>;
3686 hysteresis = <2000>;
3687 type = "passive";
3688 };
3689
3690 cpu7_top_alert1: trip-point1 {
3691 temperature = <95000>;
3692 hysteresis = <2000>;
3693 type = "passive";
3694 };
3695
1364acc3 3696 cpu7_top_crit: cpu-crit {
20f9d94e
RF		 3697 temperature = <110000>;
3698 hysteresis = <1000>;
3699 type = "critical";
3700 };
3701 };
3702
3703 cooling-maps {
3704 map0 {
3705 trip = <&cpu7_top_alert0>;
3706 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3707 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3708 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3709 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3710 };
3711 map1 {
3712 trip = <&cpu7_top_alert1>;
3713 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3714 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3715 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3716 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3717 };
3718 };
3719 };
3720
3721 cpu4-bottom-thermal {
3722 polling-delay-passive = <250>;
3723 polling-delay = <1000>;
3724
3725 thermal-sensors = <&tsens0 11>;
3726
3727 trips {
3728 cpu4_bottom_alert0: trip-point0 {
3729 temperature = <90000>;
3730 hysteresis = <2000>;
3731 type = "passive";
3732 };
3733
3734 cpu4_bottom_alert1: trip-point1 {
3735 temperature = <95000>;
3736 hysteresis = <2000>;
3737 type = "passive";
3738 };
3739
1364acc3 3740 cpu4_bottom_crit: cpu-crit {
20f9d94e
RF		 3741 temperature = <110000>;
3742 hysteresis = <1000>;
3743 type = "critical";
3744 };
3745 };
3746
3747 cooling-maps {
3748 map0 {
3749 trip = <&cpu4_bottom_alert0>;
3750 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3751 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3752 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3753 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3754 };
3755 map1 {
3756 trip = <&cpu4_bottom_alert1>;
3757 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3758 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3759 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3760 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3761 };
3762 };
3763 };
3764
3765 cpu5-bottom-thermal {
3766 polling-delay-passive = <250>;
3767 polling-delay = <1000>;
3768
3769 thermal-sensors = <&tsens0 12>;
3770
3771 trips {
3772 cpu5_bottom_alert0: trip-point0 {
3773 temperature = <90000>;
3774 hysteresis = <2000>;
3775 type = "passive";
3776 };
3777
3778 cpu5_bottom_alert1: trip-point1 {
3779 temperature = <95000>;
3780 hysteresis = <2000>;
3781 type = "passive";
3782 };
3783
1364acc3 3784 cpu5_bottom_crit: cpu-crit {
20f9d94e
RF		 3785 temperature = <110000>;
3786 hysteresis = <1000>;
3787 type = "critical";
3788 };
3789 };
3790
3791 cooling-maps {
3792 map0 {
3793 trip = <&cpu5_bottom_alert0>;
3794 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3795 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3796 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3797 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3798 };
3799 map1 {
3800 trip = <&cpu5_bottom_alert1>;
3801 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3802 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3803 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3804 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3805 };
3806 };
3807 };
3808
3809 cpu6-bottom-thermal {
3810 polling-delay-passive = <250>;
3811 polling-delay = <1000>;
3812
3813 thermal-sensors = <&tsens0 13>;
3814
3815 trips {
3816 cpu6_bottom_alert0: trip-point0 {
3817 temperature = <90000>;
3818 hysteresis = <2000>;
3819 type = "passive";
3820 };
3821
3822 cpu6_bottom_alert1: trip-point1 {
3823 temperature = <95000>;
3824 hysteresis = <2000>;
3825 type = "passive";
3826 };
3827
1364acc3 3828 cpu6_bottom_crit: cpu-crit {
20f9d94e
RF		 3829 temperature = <110000>;
3830 hysteresis = <1000>;
3831 type = "critical";
3832 };
3833 };
3834
3835 cooling-maps {
3836 map0 {
3837 trip = <&cpu6_bottom_alert0>;
3838 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3839 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3840 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3841 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3842 };
3843 map1 {
3844 trip = <&cpu6_bottom_alert1>;
3845 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3846 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3847 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3848 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 };
3850 };
3851 };
3852
3853 cpu7-bottom-thermal {
3854 polling-delay-passive = <250>;
3855 polling-delay = <1000>;
3856
3857 thermal-sensors = <&tsens0 14>;
3858
3859 trips {
3860 cpu7_bottom_alert0: trip-point0 {
3861 temperature = <90000>;
3862 hysteresis = <2000>;
3863 type = "passive";
3864 };
3865
3866 cpu7_bottom_alert1: trip-point1 {
3867 temperature = <95000>;
3868 hysteresis = <2000>;
3869 type = "passive";
3870 };
3871
1364acc3 3872 cpu7_bottom_crit: cpu-crit {
20f9d94e
RF		 3873 temperature = <110000>;
3874 hysteresis = <1000>;
3875 type = "critical";
3876 };
3877 };
3878
3879 cooling-maps {
3880 map0 {
3881 trip = <&cpu7_bottom_alert0>;
3882 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3883 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3884 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3885 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3886 };
3887 map1 {
3888 trip = <&cpu7_bottom_alert1>;
3889 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3890 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3891 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3892 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3893 };
3894 };
3895 };
3896
3897 aoss0-thermal {
3898 polling-delay-passive = <250>;
3899 polling-delay = <1000>;
3900
3901 thermal-sensors = <&tsens0 0>;
3902
3903 trips {
3904 aoss0_alert0: trip-point0 {
3905 temperature = <90000>;
3906 hysteresis = <2000>;
3907 type = "hot";
3908 };
3909 };
3910 };
3911
3912 cluster0-thermal {
3913 polling-delay-passive = <250>;
3914 polling-delay = <1000>;
3915
3916 thermal-sensors = <&tsens0 5>;
3917
3918 trips {
3919 cluster0_alert0: trip-point0 {
3920 temperature = <90000>;
3921 hysteresis = <2000>;
3922 type = "hot";
3923 };
3924 cluster0_crit: cluster0_crit {
3925 temperature = <110000>;
3926 hysteresis = <2000>;
3927 type = "critical";
3928 };
3929 };
3930 };
3931
3932 cluster1-thermal {
3933 polling-delay-passive = <250>;
3934 polling-delay = <1000>;
3935
3936 thermal-sensors = <&tsens0 6>;
3937
3938 trips {
3939 cluster1_alert0: trip-point0 {
3940 temperature = <90000>;
3941 hysteresis = <2000>;
3942 type = "hot";
3943 };
3944 cluster1_crit: cluster1_crit {
3945 temperature = <110000>;
3946 hysteresis = <2000>;
3947 type = "critical";
3948 };
3949 };
3950 };
3951
3952 aoss1-thermal {
3953 polling-delay-passive = <250>;
3954 polling-delay = <1000>;
3955
3956 thermal-sensors = <&tsens1 0>;
3957
3958 trips {
3959 aoss1_alert0: trip-point0 {
3960 temperature = <90000>;
3961 hysteresis = <2000>;
3962 type = "hot";
3963 };
3964 };
3965 };
3966
7be1c395 3967 gpu-top-thermal {
20f9d94e
RF		 3968 polling-delay-passive = <250>;
3969 polling-delay = <1000>;
3970
3971 thermal-sensors = <&tsens1 1>;
3972
3973 trips {
3974 gpu1_alert0: trip-point0 {
3975 temperature = <90000>;
3976 hysteresis = <1000>;
3977 type = "hot";
3978 };
3979 };
3980 };
3981
7be1c395 3982 gpu-bottom-thermal {
20f9d94e
RF		 3983 polling-delay-passive = <250>;
3984 polling-delay = <1000>;
3985
3986 thermal-sensors = <&tsens1 2>;
3987
3988 trips {
3989 gpu2_alert0: trip-point0 {
3990 temperature = <90000>;
3991 hysteresis = <1000>;
3992 type = "hot";
3993 };
3994 };
3995 };
3996
3997 nspss1-thermal {
3998 polling-delay-passive = <250>;
3999 polling-delay = <1000>;
4000
4001 thermal-sensors = <&tsens1 3>;
4002
4003 trips {
4004 nspss1_alert0: trip-point0 {
4005 temperature = <90000>;
4006 hysteresis = <1000>;
4007 type = "hot";
4008 };
4009 };
4010 };
4011
4012 nspss2-thermal {
4013 polling-delay-passive = <250>;
4014 polling-delay = <1000>;
4015
4016 thermal-sensors = <&tsens1 4>;
4017
4018 trips {
4019 nspss2_alert0: trip-point0 {
4020 temperature = <90000>;
4021 hysteresis = <1000>;
4022 type = "hot";
4023 };
4024 };
4025 };
4026
4027 nspss3-thermal {
4028 polling-delay-passive = <250>;
4029 polling-delay = <1000>;
4030
4031 thermal-sensors = <&tsens1 5>;
4032
4033 trips {
4034 nspss3_alert0: trip-point0 {
4035 temperature = <90000>;
4036 hysteresis = <1000>;
4037 type = "hot";
4038 };
4039 };
4040 };
4041
4042 video-thermal {
4043 polling-delay-passive = <250>;
4044 polling-delay = <1000>;
4045
4046 thermal-sensors = <&tsens1 6>;
4047
4048 trips {
4049 video_alert0: trip-point0 {
4050 temperature = <90000>;
4051 hysteresis = <2000>;
4052 type = "hot";
4053 };
4054 };
4055 };
4056
4057 mem-thermal {
4058 polling-delay-passive = <250>;
4059 polling-delay = <1000>;
4060
4061 thermal-sensors = <&tsens1 7>;
4062
4063 trips {
4064 mem_alert0: trip-point0 {
4065 temperature = <90000>;
4066 hysteresis = <2000>;
4067 type = "hot";
4068 };
4069 };
4070 };
4071
7be1c395 4072 modem1-top-thermal {
20f9d94e
RF		 4073 polling-delay-passive = <250>;
4074 polling-delay = <1000>;
4075
4076 thermal-sensors = <&tsens1 8>;
4077
4078 trips {
4079 modem1_alert0: trip-point0 {
4080 temperature = <90000>;
4081 hysteresis = <2000>;
4082 type = "hot";
4083 };
4084 };
4085 };
4086
7be1c395 4087 modem2-top-thermal {
20f9d94e
RF		 4088 polling-delay-passive = <250>;
4089 polling-delay = <1000>;
4090
4091 thermal-sensors = <&tsens1 9>;
4092
4093 trips {
4094 modem2_alert0: trip-point0 {
4095 temperature = <90000>;
4096 hysteresis = <2000>;
4097 type = "hot";
4098 };
4099 };
4100 };
4101
7be1c395 4102 modem3-top-thermal {
20f9d94e
RF		 4103 polling-delay-passive = <250>;
4104 polling-delay = <1000>;
4105
4106 thermal-sensors = <&tsens1 10>;
4107
4108 trips {
4109 modem3_alert0: trip-point0 {
4110 temperature = <90000>;
4111 hysteresis = <2000>;
4112 type = "hot";
4113 };
4114 };
4115 };
4116
7be1c395 4117 modem4-top-thermal {
20f9d94e
RF		 4118 polling-delay-passive = <250>;
4119 polling-delay = <1000>;
4120
4121 thermal-sensors = <&tsens1 11>;
4122
4123 trips {
4124 modem4_alert0: trip-point0 {
4125 temperature = <90000>;
4126 hysteresis = <2000>;
4127 type = "hot";
4128 };
4129 };
4130 };
4131
7be1c395 4132 camera-top-thermal {
20f9d94e
RF		 4133 polling-delay-passive = <250>;
4134 polling-delay = <1000>;
4135
4136 thermal-sensors = <&tsens1 12>;
4137
4138 trips {
4139 camera1_alert0: trip-point0 {
4140 temperature = <90000>;
4141 hysteresis = <2000>;
4142 type = "hot";
4143 };
4144 };
4145 };
4146
7be1c395 4147 cam-bottom-thermal {
20f9d94e
RF		 4148 polling-delay-passive = <250>;
4149 polling-delay = <1000>;
4150
4151 thermal-sensors = <&tsens1 13>;
4152
4153 trips {
4154 camera2_alert0: trip-point0 {
4155 temperature = <90000>;
4156 hysteresis = <2000>;
4157 type = "hot";
4158 };
4159 };
4160 };
4161 };
4162
b7e8f433
VK		 4163 timer {
4164 compatible = "arm,armv8-timer";
4165 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4166 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4167 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4168 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4169 };
4170};
Linux 6.x block layer and io_uring tree(s)