Commit | Line | Data |
---|---|---|
b7e8f433 VK |
1 | // SPDX-License-Identifier: BSD-3-Clause |
2 | /* | |
4f23d2a5 | 3 | * Copyright (c) 2020, Linaro Limited |
b7e8f433 VK |
4 | */ |
5 | ||
d4a44105 | 6 | #include <dt-bindings/interconnect/qcom,sm8350.h> |
b7e8f433 | 7 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
9fd4887c | 8 | #include <dt-bindings/clock/qcom,dispcc-sm8350.h> |
6d91e201 | 9 | #include <dt-bindings/clock/qcom,gcc-sm8350.h> |
b7e8f433 | 10 | #include <dt-bindings/clock/qcom,rpmh.h> |
bc08fbf4 | 11 | #include <dt-bindings/dma/qcom-gpi.h> |
f0360a7c | 12 | #include <dt-bindings/gpio/gpio.h> |
84c856d0 | 13 | #include <dt-bindings/interconnect/qcom,sm8350.h> |
b7e8f433 | 14 | #include <dt-bindings/mailbox/qcom-ipcc.h> |
b7e8f433 VK |
15 | #include <dt-bindings/power/qcom-rpmpd.h> |
16 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> | |
20f9d94e | 17 | #include <dt-bindings/thermal/thermal.h> |
f11d3e7d | 18 | #include <dt-bindings/interconnect/qcom,sm8350.h> |
b7e8f433 VK |
19 | |
20 | / { | |
21 | interrupt-parent = <&intc>; | |
22 | ||
23 | #address-cells = <2>; | |
24 | #size-cells = <2>; | |
25 | ||
26 | chosen { }; | |
27 | ||
28 | clocks { | |
29 | xo_board: xo-board { | |
30 | compatible = "fixed-clock"; | |
31 | #clock-cells = <0>; | |
32 | clock-frequency = <38400000>; | |
33 | clock-output-names = "xo_board"; | |
34 | }; | |
35 | ||
36 | sleep_clk: sleep-clk { | |
37 | compatible = "fixed-clock"; | |
38 | clock-frequency = <32000>; | |
39 | #clock-cells = <0>; | |
40 | }; | |
41 | }; | |
42 | ||
43 | cpus { | |
44 | #address-cells = <2>; | |
45 | #size-cells = <0>; | |
46 | ||
47 | CPU0: cpu@0 { | |
48 | device_type = "cpu"; | |
49 | compatible = "qcom,kryo685"; | |
50 | reg = <0x0 0x0>; | |
51 | enable-method = "psci"; | |
52 | next-level-cache = <&L2_0>; | |
ccbb3abb | 53 | qcom,freq-domain = <&cpufreq_hw 0>; |
07ddb302 BA |
54 | power-domains = <&CPU_PD0>; |
55 | power-domain-names = "psci"; | |
20f9d94e | 56 | #cooling-cells = <2>; |
b7e8f433 VK |
57 | L2_0: l2-cache { |
58 | compatible = "cache"; | |
9435294c | 59 | cache-level = <2>; |
b7e8f433 VK |
60 | next-level-cache = <&L3_0>; |
61 | L3_0: l3-cache { | |
62 | compatible = "cache"; | |
9435294c | 63 | cache-level = <3>; |
b7e8f433 VK |
64 | }; |
65 | }; | |
66 | }; | |
67 | ||
68 | CPU1: cpu@100 { | |
69 | device_type = "cpu"; | |
70 | compatible = "qcom,kryo685"; | |
71 | reg = <0x0 0x100>; | |
72 | enable-method = "psci"; | |
73 | next-level-cache = <&L2_100>; | |
ccbb3abb | 74 | qcom,freq-domain = <&cpufreq_hw 0>; |
07ddb302 BA |
75 | power-domains = <&CPU_PD1>; |
76 | power-domain-names = "psci"; | |
20f9d94e | 77 | #cooling-cells = <2>; |
b7e8f433 VK |
78 | L2_100: l2-cache { |
79 | compatible = "cache"; | |
9435294c | 80 | cache-level = <2>; |
b7e8f433 VK |
81 | next-level-cache = <&L3_0>; |
82 | }; | |
83 | }; | |
84 | ||
85 | CPU2: cpu@200 { | |
86 | device_type = "cpu"; | |
87 | compatible = "qcom,kryo685"; | |
88 | reg = <0x0 0x200>; | |
89 | enable-method = "psci"; | |
90 | next-level-cache = <&L2_200>; | |
ccbb3abb | 91 | qcom,freq-domain = <&cpufreq_hw 0>; |
07ddb302 BA |
92 | power-domains = <&CPU_PD2>; |
93 | power-domain-names = "psci"; | |
20f9d94e | 94 | #cooling-cells = <2>; |
b7e8f433 VK |
95 | L2_200: l2-cache { |
96 | compatible = "cache"; | |
9435294c | 97 | cache-level = <2>; |
b7e8f433 VK |
98 | next-level-cache = <&L3_0>; |
99 | }; | |
100 | }; | |
101 | ||
102 | CPU3: cpu@300 { | |
103 | device_type = "cpu"; | |
104 | compatible = "qcom,kryo685"; | |
105 | reg = <0x0 0x300>; | |
106 | enable-method = "psci"; | |
107 | next-level-cache = <&L2_300>; | |
ccbb3abb | 108 | qcom,freq-domain = <&cpufreq_hw 0>; |
07ddb302 BA |
109 | power-domains = <&CPU_PD3>; |
110 | power-domain-names = "psci"; | |
20f9d94e | 111 | #cooling-cells = <2>; |
b7e8f433 VK |
112 | L2_300: l2-cache { |
113 | compatible = "cache"; | |
9435294c | 114 | cache-level = <2>; |
b7e8f433 VK |
115 | next-level-cache = <&L3_0>; |
116 | }; | |
117 | }; | |
118 | ||
119 | CPU4: cpu@400 { | |
120 | device_type = "cpu"; | |
121 | compatible = "qcom,kryo685"; | |
122 | reg = <0x0 0x400>; | |
123 | enable-method = "psci"; | |
124 | next-level-cache = <&L2_400>; | |
ccbb3abb | 125 | qcom,freq-domain = <&cpufreq_hw 1>; |
07ddb302 BA |
126 | power-domains = <&CPU_PD4>; |
127 | power-domain-names = "psci"; | |
20f9d94e | 128 | #cooling-cells = <2>; |
b7e8f433 VK |
129 | L2_400: l2-cache { |
130 | compatible = "cache"; | |
9435294c | 131 | cache-level = <2>; |
b7e8f433 VK |
132 | next-level-cache = <&L3_0>; |
133 | }; | |
134 | }; | |
135 | ||
136 | CPU5: cpu@500 { | |
137 | device_type = "cpu"; | |
138 | compatible = "qcom,kryo685"; | |
139 | reg = <0x0 0x500>; | |
140 | enable-method = "psci"; | |
141 | next-level-cache = <&L2_500>; | |
ccbb3abb | 142 | qcom,freq-domain = <&cpufreq_hw 1>; |
07ddb302 BA |
143 | power-domains = <&CPU_PD5>; |
144 | power-domain-names = "psci"; | |
20f9d94e | 145 | #cooling-cells = <2>; |
b7e8f433 VK |
146 | L2_500: l2-cache { |
147 | compatible = "cache"; | |
9435294c | 148 | cache-level = <2>; |
b7e8f433 VK |
149 | next-level-cache = <&L3_0>; |
150 | }; | |
151 | ||
152 | }; | |
153 | ||
154 | CPU6: cpu@600 { | |
155 | device_type = "cpu"; | |
156 | compatible = "qcom,kryo685"; | |
157 | reg = <0x0 0x600>; | |
158 | enable-method = "psci"; | |
159 | next-level-cache = <&L2_600>; | |
ccbb3abb | 160 | qcom,freq-domain = <&cpufreq_hw 1>; |
07ddb302 BA |
161 | power-domains = <&CPU_PD6>; |
162 | power-domain-names = "psci"; | |
20f9d94e | 163 | #cooling-cells = <2>; |
b7e8f433 VK |
164 | L2_600: l2-cache { |
165 | compatible = "cache"; | |
9435294c | 166 | cache-level = <2>; |
b7e8f433 VK |
167 | next-level-cache = <&L3_0>; |
168 | }; | |
169 | }; | |
170 | ||
171 | CPU7: cpu@700 { | |
172 | device_type = "cpu"; | |
173 | compatible = "qcom,kryo685"; | |
174 | reg = <0x0 0x700>; | |
175 | enable-method = "psci"; | |
176 | next-level-cache = <&L2_700>; | |
ccbb3abb | 177 | qcom,freq-domain = <&cpufreq_hw 2>; |
07ddb302 BA |
178 | power-domains = <&CPU_PD7>; |
179 | power-domain-names = "psci"; | |
20f9d94e | 180 | #cooling-cells = <2>; |
b7e8f433 VK |
181 | L2_700: l2-cache { |
182 | compatible = "cache"; | |
9435294c | 183 | cache-level = <2>; |
b7e8f433 VK |
184 | next-level-cache = <&L3_0>; |
185 | }; | |
186 | }; | |
07ddb302 BA |
187 | |
188 | cpu-map { | |
189 | cluster0 { | |
190 | core0 { | |
191 | cpu = <&CPU0>; | |
192 | }; | |
193 | ||
194 | core1 { | |
195 | cpu = <&CPU1>; | |
196 | }; | |
197 | ||
198 | core2 { | |
199 | cpu = <&CPU2>; | |
200 | }; | |
201 | ||
202 | core3 { | |
203 | cpu = <&CPU3>; | |
204 | }; | |
205 | ||
206 | core4 { | |
207 | cpu = <&CPU4>; | |
208 | }; | |
209 | ||
210 | core5 { | |
211 | cpu = <&CPU5>; | |
212 | }; | |
213 | ||
214 | core6 { | |
215 | cpu = <&CPU6>; | |
216 | }; | |
217 | ||
218 | core7 { | |
219 | cpu = <&CPU7>; | |
220 | }; | |
221 | }; | |
222 | }; | |
223 | ||
224 | idle-states { | |
225 | entry-method = "psci"; | |
226 | ||
227 | LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { | |
228 | compatible = "arm,idle-state"; | |
229 | idle-state-name = "silver-rail-power-collapse"; | |
230 | arm,psci-suspend-param = <0x40000004>; | |
231 | entry-latency-us = <355>; | |
232 | exit-latency-us = <909>; | |
233 | min-residency-us = <3934>; | |
234 | local-timer-stop; | |
235 | }; | |
236 | ||
237 | BIG_CPU_SLEEP_0: cpu-sleep-1-0 { | |
238 | compatible = "arm,idle-state"; | |
239 | idle-state-name = "gold-rail-power-collapse"; | |
240 | arm,psci-suspend-param = <0x40000004>; | |
241 | entry-latency-us = <241>; | |
242 | exit-latency-us = <1461>; | |
243 | min-residency-us = <4488>; | |
244 | local-timer-stop; | |
245 | }; | |
246 | }; | |
247 | ||
248 | domain-idle-states { | |
249 | CLUSTER_SLEEP_0: cluster-sleep-0 { | |
250 | compatible = "domain-idle-state"; | |
251 | idle-state-name = "cluster-power-collapse"; | |
252 | arm,psci-suspend-param = <0x4100c344>; | |
253 | entry-latency-us = <3263>; | |
254 | exit-latency-us = <6562>; | |
255 | min-residency-us = <9987>; | |
256 | local-timer-stop; | |
257 | }; | |
258 | }; | |
b7e8f433 VK |
259 | }; |
260 | ||
261 | firmware { | |
262 | scm: scm { | |
263 | compatible = "qcom,scm-sm8350", "qcom,scm"; | |
264 | #reset-cells = <1>; | |
265 | }; | |
266 | }; | |
267 | ||
268 | memory@80000000 { | |
269 | device_type = "memory"; | |
270 | /* We expect the bootloader to fill in the size */ | |
271 | reg = <0x0 0x80000000 0x0 0x0>; | |
272 | }; | |
273 | ||
274 | pmu { | |
275 | compatible = "arm,armv8-pmuv3"; | |
794d3e30 | 276 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
b7e8f433 VK |
277 | }; |
278 | ||
279 | psci { | |
280 | compatible = "arm,psci-1.0"; | |
281 | method = "smc"; | |
07ddb302 | 282 | |
a9371962 | 283 | CPU_PD0: power-domain-cpu0 { |
07ddb302 BA |
284 | #power-domain-cells = <0>; |
285 | power-domains = <&CLUSTER_PD>; | |
286 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
287 | }; | |
288 | ||
a9371962 | 289 | CPU_PD1: power-domain-cpu1 { |
07ddb302 BA |
290 | #power-domain-cells = <0>; |
291 | power-domains = <&CLUSTER_PD>; | |
292 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
293 | }; | |
294 | ||
a9371962 | 295 | CPU_PD2: power-domain-cpu2 { |
07ddb302 BA |
296 | #power-domain-cells = <0>; |
297 | power-domains = <&CLUSTER_PD>; | |
298 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
299 | }; | |
300 | ||
a9371962 | 301 | CPU_PD3: power-domain-cpu3 { |
07ddb302 BA |
302 | #power-domain-cells = <0>; |
303 | power-domains = <&CLUSTER_PD>; | |
304 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
305 | }; | |
306 | ||
a9371962 | 307 | CPU_PD4: power-domain-cpu4 { |
07ddb302 BA |
308 | #power-domain-cells = <0>; |
309 | power-domains = <&CLUSTER_PD>; | |
310 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
311 | }; | |
312 | ||
a9371962 | 313 | CPU_PD5: power-domain-cpu5 { |
07ddb302 BA |
314 | #power-domain-cells = <0>; |
315 | power-domains = <&CLUSTER_PD>; | |
316 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
317 | }; | |
318 | ||
a9371962 | 319 | CPU_PD6: power-domain-cpu6 { |
07ddb302 BA |
320 | #power-domain-cells = <0>; |
321 | power-domains = <&CLUSTER_PD>; | |
322 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
323 | }; | |
324 | ||
a9371962 | 325 | CPU_PD7: power-domain-cpu7 { |
07ddb302 BA |
326 | #power-domain-cells = <0>; |
327 | power-domains = <&CLUSTER_PD>; | |
328 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
329 | }; | |
330 | ||
a9371962 | 331 | CLUSTER_PD: power-domain-cpu-cluster0 { |
07ddb302 BA |
332 | #power-domain-cells = <0>; |
333 | domain-idle-states = <&CLUSTER_SLEEP_0>; | |
334 | }; | |
b7e8f433 VK |
335 | }; |
336 | ||
e2eedde4 VK |
337 | qup_opp_table_100mhz: opp-table-qup100mhz { |
338 | compatible = "operating-points-v2"; | |
339 | ||
340 | opp-50000000 { | |
341 | opp-hz = /bits/ 64 <50000000>; | |
342 | required-opps = <&rpmhpd_opp_min_svs>; | |
343 | }; | |
344 | ||
345 | opp-75000000 { | |
346 | opp-hz = /bits/ 64 <75000000>; | |
347 | required-opps = <&rpmhpd_opp_low_svs>; | |
348 | }; | |
349 | ||
350 | opp-100000000 { | |
351 | opp-hz = /bits/ 64 <100000000>; | |
352 | required-opps = <&rpmhpd_opp_svs>; | |
353 | }; | |
354 | }; | |
355 | ||
356 | qup_opp_table_120mhz: opp-table-qup120mhz { | |
357 | compatible = "operating-points-v2"; | |
358 | ||
359 | opp-50000000 { | |
360 | opp-hz = /bits/ 64 <50000000>; | |
361 | required-opps = <&rpmhpd_opp_min_svs>; | |
362 | }; | |
363 | ||
364 | opp-75000000 { | |
365 | opp-hz = /bits/ 64 <75000000>; | |
366 | required-opps = <&rpmhpd_opp_low_svs>; | |
367 | }; | |
368 | ||
369 | opp-120000000 { | |
370 | opp-hz = /bits/ 64 <120000000>; | |
371 | required-opps = <&rpmhpd_opp_svs>; | |
372 | }; | |
373 | }; | |
374 | ||
b7e8f433 VK |
375 | reserved_memory: reserved-memory { |
376 | #address-cells = <2>; | |
377 | #size-cells = <2>; | |
378 | ranges; | |
379 | ||
380 | hyp_mem: memory@80000000 { | |
381 | reg = <0x0 0x80000000 0x0 0x600000>; | |
382 | no-map; | |
383 | }; | |
384 | ||
385 | xbl_aop_mem: memory@80700000 { | |
386 | no-map; | |
387 | reg = <0x0 0x80700000 0x0 0x160000>; | |
388 | }; | |
389 | ||
390 | cmd_db: memory@80860000 { | |
391 | compatible = "qcom,cmd-db"; | |
392 | reg = <0x0 0x80860000 0x0 0x20000>; | |
393 | no-map; | |
394 | }; | |
395 | ||
396 | reserved_xbl_uefi_log: memory@80880000 { | |
397 | reg = <0x0 0x80880000 0x0 0x14000>; | |
398 | no-map; | |
399 | }; | |
400 | ||
8503babc KD |
401 | smem@80900000 { |
402 | compatible = "qcom,smem"; | |
b7e8f433 | 403 | reg = <0x0 0x80900000 0x0 0x200000>; |
8503babc | 404 | hwlocks = <&tcsr_mutex 3>; |
b7e8f433 VK |
405 | no-map; |
406 | }; | |
407 | ||
408 | cpucp_fw_mem: memory@80b00000 { | |
409 | reg = <0x0 0x80b00000 0x0 0x100000>; | |
410 | no-map; | |
411 | }; | |
412 | ||
413 | cdsp_secure_heap: memory@80c00000 { | |
414 | reg = <0x0 0x80c00000 0x0 0x4600000>; | |
415 | no-map; | |
416 | }; | |
417 | ||
418 | pil_camera_mem: mmeory@85200000 { | |
419 | reg = <0x0 0x85200000 0x0 0x500000>; | |
420 | no-map; | |
421 | }; | |
422 | ||
423 | pil_video_mem: memory@85700000 { | |
424 | reg = <0x0 0x85700000 0x0 0x500000>; | |
425 | no-map; | |
426 | }; | |
427 | ||
428 | pil_cvp_mem: memory@85c00000 { | |
429 | reg = <0x0 0x85c00000 0x0 0x500000>; | |
430 | no-map; | |
431 | }; | |
432 | ||
433 | pil_adsp_mem: memory@86100000 { | |
434 | reg = <0x0 0x86100000 0x0 0x2100000>; | |
435 | no-map; | |
436 | }; | |
437 | ||
438 | pil_slpi_mem: memory@88200000 { | |
439 | reg = <0x0 0x88200000 0x0 0x1500000>; | |
440 | no-map; | |
441 | }; | |
442 | ||
443 | pil_cdsp_mem: memory@89700000 { | |
444 | reg = <0x0 0x89700000 0x0 0x1e00000>; | |
445 | no-map; | |
446 | }; | |
447 | ||
448 | pil_ipa_fw_mem: memory@8b500000 { | |
449 | reg = <0x0 0x8b500000 0x0 0x10000>; | |
450 | no-map; | |
451 | }; | |
452 | ||
453 | pil_ipa_gsi_mem: memory@8b510000 { | |
454 | reg = <0x0 0x8b510000 0x0 0xa000>; | |
455 | no-map; | |
456 | }; | |
457 | ||
458 | pil_gpu_mem: memory@8b51a000 { | |
459 | reg = <0x0 0x8b51a000 0x0 0x2000>; | |
460 | no-map; | |
461 | }; | |
462 | ||
463 | pil_spss_mem: memory@8b600000 { | |
464 | reg = <0x0 0x8b600000 0x0 0x100000>; | |
465 | no-map; | |
466 | }; | |
467 | ||
468 | pil_modem_mem: memory@8b800000 { | |
469 | reg = <0x0 0x8b800000 0x0 0x10000000>; | |
470 | no-map; | |
471 | }; | |
472 | ||
774890c9 VK |
473 | rmtfs_mem: memory@9b800000 { |
474 | compatible = "qcom,rmtfs-mem"; | |
475 | reg = <0x0 0x9b800000 0x0 0x280000>; | |
476 | no-map; | |
477 | ||
478 | qcom,client-id = <1>; | |
479 | qcom,vmid = <15>; | |
480 | }; | |
481 | ||
b7e8f433 VK |
482 | hyp_reserved_mem: memory@d0000000 { |
483 | reg = <0x0 0xd0000000 0x0 0x800000>; | |
484 | no-map; | |
485 | }; | |
486 | ||
487 | pil_trustedvm_mem: memory@d0800000 { | |
488 | reg = <0x0 0xd0800000 0x0 0x76f7000>; | |
489 | no-map; | |
490 | }; | |
491 | ||
492 | qrtr_shbuf: memory@d7ef7000 { | |
493 | reg = <0x0 0xd7ef7000 0x0 0x9000>; | |
494 | no-map; | |
495 | }; | |
496 | ||
497 | chan0_shbuf: memory@d7f00000 { | |
498 | reg = <0x0 0xd7f00000 0x0 0x80000>; | |
499 | no-map; | |
500 | }; | |
501 | ||
502 | chan1_shbuf: memory@d7f80000 { | |
503 | reg = <0x0 0xd7f80000 0x0 0x80000>; | |
504 | no-map; | |
505 | }; | |
506 | ||
507 | removed_mem: memory@d8800000 { | |
508 | reg = <0x0 0xd8800000 0x0 0x6800000>; | |
509 | no-map; | |
510 | }; | |
511 | }; | |
512 | ||
03a41991 VK |
513 | smp2p-adsp { |
514 | compatible = "qcom,smp2p"; | |
515 | qcom,smem = <443>, <429>; | |
516 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
517 | IPCC_MPROC_SIGNAL_SMP2P | |
518 | IRQ_TYPE_EDGE_RISING>; | |
519 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
520 | IPCC_MPROC_SIGNAL_SMP2P>; | |
521 | ||
522 | qcom,local-pid = <0>; | |
523 | qcom,remote-pid = <2>; | |
524 | ||
525 | smp2p_adsp_out: master-kernel { | |
526 | qcom,entry-name = "master-kernel"; | |
527 | #qcom,smem-state-cells = <1>; | |
528 | }; | |
529 | ||
530 | smp2p_adsp_in: slave-kernel { | |
531 | qcom,entry-name = "slave-kernel"; | |
532 | interrupt-controller; | |
533 | #interrupt-cells = <2>; | |
534 | }; | |
535 | }; | |
536 | ||
537 | smp2p-cdsp { | |
538 | compatible = "qcom,smp2p"; | |
539 | qcom,smem = <94>, <432>; | |
540 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
541 | IPCC_MPROC_SIGNAL_SMP2P | |
542 | IRQ_TYPE_EDGE_RISING>; | |
543 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
544 | IPCC_MPROC_SIGNAL_SMP2P>; | |
545 | ||
546 | qcom,local-pid = <0>; | |
547 | qcom,remote-pid = <5>; | |
548 | ||
549 | smp2p_cdsp_out: master-kernel { | |
550 | qcom,entry-name = "master-kernel"; | |
551 | #qcom,smem-state-cells = <1>; | |
552 | }; | |
553 | ||
554 | smp2p_cdsp_in: slave-kernel { | |
555 | qcom,entry-name = "slave-kernel"; | |
556 | interrupt-controller; | |
557 | #interrupt-cells = <2>; | |
558 | }; | |
559 | }; | |
560 | ||
561 | smp2p-modem { | |
562 | compatible = "qcom,smp2p"; | |
563 | qcom,smem = <435>, <428>; | |
564 | interrupts-extended = <&ipcc IPCC_CLIENT_MPSS | |
565 | IPCC_MPROC_SIGNAL_SMP2P | |
566 | IRQ_TYPE_EDGE_RISING>; | |
567 | mboxes = <&ipcc IPCC_CLIENT_MPSS | |
568 | IPCC_MPROC_SIGNAL_SMP2P>; | |
569 | ||
570 | qcom,local-pid = <0>; | |
571 | qcom,remote-pid = <1>; | |
572 | ||
573 | smp2p_modem_out: master-kernel { | |
574 | qcom,entry-name = "master-kernel"; | |
575 | #qcom,smem-state-cells = <1>; | |
576 | }; | |
577 | ||
578 | smp2p_modem_in: slave-kernel { | |
579 | qcom,entry-name = "slave-kernel"; | |
580 | interrupt-controller; | |
581 | #interrupt-cells = <2>; | |
582 | }; | |
f11d3e7d AE |
583 | |
584 | ipa_smp2p_out: ipa-ap-to-modem { | |
585 | qcom,entry-name = "ipa"; | |
586 | #qcom,smem-state-cells = <1>; | |
587 | }; | |
588 | ||
589 | ipa_smp2p_in: ipa-modem-to-ap { | |
590 | qcom,entry-name = "ipa"; | |
591 | interrupt-controller; | |
592 | #interrupt-cells = <2>; | |
593 | }; | |
03a41991 VK |
594 | }; |
595 | ||
596 | smp2p-slpi { | |
597 | compatible = "qcom,smp2p"; | |
598 | qcom,smem = <481>, <430>; | |
599 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
600 | IPCC_MPROC_SIGNAL_SMP2P | |
601 | IRQ_TYPE_EDGE_RISING>; | |
602 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
603 | IPCC_MPROC_SIGNAL_SMP2P>; | |
604 | ||
605 | qcom,local-pid = <0>; | |
606 | qcom,remote-pid = <3>; | |
607 | ||
608 | smp2p_slpi_out: master-kernel { | |
609 | qcom,entry-name = "master-kernel"; | |
610 | #qcom,smem-state-cells = <1>; | |
611 | }; | |
612 | ||
613 | smp2p_slpi_in: slave-kernel { | |
614 | qcom,entry-name = "slave-kernel"; | |
615 | interrupt-controller; | |
616 | #interrupt-cells = <2>; | |
617 | }; | |
618 | }; | |
619 | ||
b7e8f433 VK |
620 | soc: soc@0 { |
621 | #address-cells = <2>; | |
622 | #size-cells = <2>; | |
623 | ranges = <0 0 0 0 0x10 0>; | |
624 | dma-ranges = <0 0 0 0 0x10 0>; | |
625 | compatible = "simple-bus"; | |
626 | ||
627 | gcc: clock-controller@100000 { | |
628 | compatible = "qcom,gcc-sm8350"; | |
629 | reg = <0x0 0x00100000 0x0 0x1f0000>; | |
630 | #clock-cells = <1>; | |
631 | #reset-cells = <1>; | |
632 | #power-domain-cells = <1>; | |
9ea9eb36 KD |
633 | clock-names = "bi_tcxo", |
634 | "sleep_clk", | |
635 | "pcie_0_pipe_clk", | |
636 | "pcie_1_pipe_clk", | |
637 | "ufs_card_rx_symbol_0_clk", | |
638 | "ufs_card_rx_symbol_1_clk", | |
639 | "ufs_card_tx_symbol_0_clk", | |
640 | "ufs_phy_rx_symbol_0_clk", | |
641 | "ufs_phy_rx_symbol_1_clk", | |
642 | "ufs_phy_tx_symbol_0_clk", | |
643 | "usb3_phy_wrapper_gcc_usb30_pipe_clk", | |
644 | "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; | |
645 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
646 | <&sleep_clk>, | |
6daee406 DB |
647 | <&pcie0_phy>, |
648 | <&pcie1_phy>, | |
9ea9eb36 KD |
649 | <0>, |
650 | <0>, | |
651 | <0>, | |
86543bc6 DB |
652 | <&ufs_mem_phy_lanes 0>, |
653 | <&ufs_mem_phy_lanes 1>, | |
654 | <&ufs_mem_phy_lanes 2>, | |
9ea9eb36 KD |
655 | <0>, |
656 | <0>; | |
b7e8f433 VK |
657 | }; |
658 | ||
659 | ipcc: mailbox@408000 { | |
660 | compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; | |
661 | reg = <0 0x00408000 0 0x1000>; | |
662 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; | |
663 | interrupt-controller; | |
664 | #interrupt-cells = <3>; | |
665 | #mbox-cells = <2>; | |
666 | }; | |
667 | ||
bc08fbf4 | 668 | gpi_dma2: dma-controller@800000 { |
b561e225 | 669 | compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; |
bc08fbf4 BA |
670 | reg = <0 0x00800000 0 0x60000>; |
671 | interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, | |
672 | <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, | |
673 | <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, | |
674 | <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, | |
675 | <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, | |
676 | <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, | |
677 | <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, | |
678 | <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, | |
679 | <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, | |
680 | <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, | |
681 | <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, | |
682 | <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; | |
683 | dma-channels = <12>; | |
684 | dma-channel-mask = <0xff>; | |
685 | iommus = <&apps_smmu 0x5f6 0x0>; | |
686 | #dma-cells = <3>; | |
687 | status = "disabled"; | |
688 | }; | |
689 | ||
e84d04a2 KD |
690 | qupv3_id_2: geniqup@8c0000 { |
691 | compatible = "qcom,geni-se-qup"; | |
692 | reg = <0x0 0x008c0000 0x0 0x6000>; | |
693 | clock-names = "m-ahb", "s-ahb"; | |
694 | clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, | |
695 | <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; | |
9bc2c8fe | 696 | iommus = <&apps_smmu 0x5e3 0x0>; |
e84d04a2 KD |
697 | #address-cells = <2>; |
698 | #size-cells = <2>; | |
699 | ranges; | |
700 | status = "disabled"; | |
98374e69 KD |
701 | |
702 | i2c14: i2c@880000 { | |
703 | compatible = "qcom,geni-i2c"; | |
704 | reg = <0 0x00880000 0 0x4000>; | |
705 | clock-names = "se"; | |
706 | clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; | |
707 | pinctrl-names = "default"; | |
708 | pinctrl-0 = <&qup_i2c14_default>; | |
709 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
710 | dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, |
711 | <&gpi_dma2 1 0 QCOM_GPI_I2C>; | |
712 | dma-names = "tx", "rx"; | |
98374e69 KD |
713 | #address-cells = <1>; |
714 | #size-cells = <0>; | |
715 | status = "disabled"; | |
716 | }; | |
717 | ||
718 | spi14: spi@880000 { | |
719 | compatible = "qcom,geni-spi"; | |
720 | reg = <0 0x00880000 0 0x4000>; | |
721 | clock-names = "se"; | |
722 | clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; | |
723 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
724 | power-domains = <&rpmhpd SM8350_CX>; | |
725 | operating-points-v2 = <&qup_opp_table_120mhz>; | |
ddc97e7d BA |
726 | dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, |
727 | <&gpi_dma2 1 0 QCOM_GPI_SPI>; | |
728 | dma-names = "tx", "rx"; | |
98374e69 KD |
729 | #address-cells = <1>; |
730 | #size-cells = <0>; | |
731 | status = "disabled"; | |
732 | }; | |
733 | ||
734 | i2c15: i2c@884000 { | |
735 | compatible = "qcom,geni-i2c"; | |
736 | reg = <0 0x00884000 0 0x4000>; | |
737 | clock-names = "se"; | |
738 | clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; | |
739 | pinctrl-names = "default"; | |
740 | pinctrl-0 = <&qup_i2c15_default>; | |
741 | interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
742 | dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, |
743 | <&gpi_dma2 1 1 QCOM_GPI_I2C>; | |
744 | dma-names = "tx", "rx"; | |
98374e69 KD |
745 | #address-cells = <1>; |
746 | #size-cells = <0>; | |
747 | status = "disabled"; | |
748 | }; | |
749 | ||
750 | spi15: spi@884000 { | |
751 | compatible = "qcom,geni-spi"; | |
752 | reg = <0 0x00884000 0 0x4000>; | |
753 | clock-names = "se"; | |
754 | clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; | |
755 | interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; | |
756 | power-domains = <&rpmhpd SM8350_CX>; | |
757 | operating-points-v2 = <&qup_opp_table_120mhz>; | |
ddc97e7d BA |
758 | dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, |
759 | <&gpi_dma2 1 1 QCOM_GPI_SPI>; | |
760 | dma-names = "tx", "rx"; | |
98374e69 KD |
761 | #address-cells = <1>; |
762 | #size-cells = <0>; | |
763 | status = "disabled"; | |
764 | }; | |
765 | ||
766 | i2c16: i2c@888000 { | |
767 | compatible = "qcom,geni-i2c"; | |
768 | reg = <0 0x00888000 0 0x4000>; | |
769 | clock-names = "se"; | |
770 | clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; | |
771 | pinctrl-names = "default"; | |
772 | pinctrl-0 = <&qup_i2c16_default>; | |
773 | interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
774 | dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, |
775 | <&gpi_dma2 1 2 QCOM_GPI_I2C>; | |
776 | dma-names = "tx", "rx"; | |
98374e69 KD |
777 | #address-cells = <1>; |
778 | #size-cells = <0>; | |
779 | status = "disabled"; | |
780 | }; | |
781 | ||
782 | spi16: spi@888000 { | |
783 | compatible = "qcom,geni-spi"; | |
784 | reg = <0 0x00888000 0 0x4000>; | |
785 | clock-names = "se"; | |
786 | clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; | |
787 | interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; | |
788 | power-domains = <&rpmhpd SM8350_CX>; | |
789 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
790 | dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, |
791 | <&gpi_dma2 1 2 QCOM_GPI_SPI>; | |
792 | dma-names = "tx", "rx"; | |
98374e69 KD |
793 | #address-cells = <1>; |
794 | #size-cells = <0>; | |
795 | status = "disabled"; | |
796 | }; | |
797 | ||
798 | i2c17: i2c@88c000 { | |
799 | compatible = "qcom,geni-i2c"; | |
800 | reg = <0 0x0088c000 0 0x4000>; | |
801 | clock-names = "se"; | |
802 | clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; | |
803 | pinctrl-names = "default"; | |
804 | pinctrl-0 = <&qup_i2c17_default>; | |
805 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
806 | dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, |
807 | <&gpi_dma2 1 3 QCOM_GPI_I2C>; | |
808 | dma-names = "tx", "rx"; | |
98374e69 KD |
809 | #address-cells = <1>; |
810 | #size-cells = <0>; | |
811 | status = "disabled"; | |
812 | }; | |
813 | ||
814 | spi17: spi@88c000 { | |
815 | compatible = "qcom,geni-spi"; | |
816 | reg = <0 0x0088c000 0 0x4000>; | |
817 | clock-names = "se"; | |
818 | clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; | |
819 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; | |
820 | power-domains = <&rpmhpd SM8350_CX>; | |
821 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
822 | dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, |
823 | <&gpi_dma2 1 3 QCOM_GPI_SPI>; | |
824 | dma-names = "tx", "rx"; | |
98374e69 KD |
825 | #address-cells = <1>; |
826 | #size-cells = <0>; | |
827 | status = "disabled"; | |
828 | }; | |
829 | ||
830 | /* QUP no. 18 seems to be strictly SPI/UART-only */ | |
831 | ||
832 | spi18: spi@890000 { | |
833 | compatible = "qcom,geni-spi"; | |
834 | reg = <0 0x00890000 0 0x4000>; | |
835 | clock-names = "se"; | |
836 | clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; | |
837 | interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | |
838 | power-domains = <&rpmhpd SM8350_CX>; | |
839 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
840 | dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, |
841 | <&gpi_dma2 1 4 QCOM_GPI_SPI>; | |
842 | dma-names = "tx", "rx"; | |
98374e69 KD |
843 | #address-cells = <1>; |
844 | #size-cells = <0>; | |
845 | status = "disabled"; | |
846 | }; | |
847 | ||
848 | uart18: serial@890000 { | |
849 | compatible = "qcom,geni-uart"; | |
850 | reg = <0 0x00890000 0 0x4000>; | |
851 | clock-names = "se"; | |
852 | clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; | |
853 | pinctrl-names = "default"; | |
854 | pinctrl-0 = <&qup_uart18_default>; | |
855 | interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | |
856 | power-domains = <&rpmhpd SM8350_CX>; | |
857 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
858 | status = "disabled"; | |
859 | }; | |
860 | ||
861 | i2c19: i2c@894000 { | |
862 | compatible = "qcom,geni-i2c"; | |
863 | reg = <0 0x00894000 0 0x4000>; | |
864 | clock-names = "se"; | |
865 | clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; | |
866 | pinctrl-names = "default"; | |
867 | pinctrl-0 = <&qup_i2c19_default>; | |
868 | interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
869 | dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, |
870 | <&gpi_dma2 1 5 QCOM_GPI_I2C>; | |
871 | dma-names = "tx", "rx"; | |
98374e69 KD |
872 | #address-cells = <1>; |
873 | #size-cells = <0>; | |
874 | status = "disabled"; | |
875 | }; | |
876 | ||
877 | spi19: spi@894000 { | |
878 | compatible = "qcom,geni-spi"; | |
879 | reg = <0 0x00894000 0 0x4000>; | |
880 | clock-names = "se"; | |
881 | clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; | |
882 | interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; | |
883 | power-domains = <&rpmhpd SM8350_CX>; | |
884 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
bc08fbf4 BA |
885 | dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, |
886 | <&gpi_dma2 1 5 QCOM_GPI_SPI>; | |
887 | dma-names = "tx", "rx"; | |
98374e69 KD |
888 | #address-cells = <1>; |
889 | #size-cells = <0>; | |
890 | status = "disabled"; | |
891 | }; | |
e84d04a2 KD |
892 | }; |
893 | ||
bc08fbf4 | 894 | gpi_dma0: dma-controller@900000 { |
b561e225 | 895 | compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; |
bc08fbf4 BA |
896 | reg = <0 0x09800000 0 0x60000>; |
897 | interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, | |
898 | <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
899 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
900 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
901 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, | |
902 | <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, | |
903 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
904 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
905 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, | |
906 | <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, | |
907 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
908 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; | |
909 | dma-channels = <12>; | |
910 | dma-channel-mask = <0x7e>; | |
911 | iommus = <&apps_smmu 0x5b6 0x0>; | |
912 | #dma-cells = <3>; | |
913 | status = "disabled"; | |
914 | }; | |
915 | ||
87f0b434 | 916 | qupv3_id_0: geniqup@9c0000 { |
b7e8f433 VK |
917 | compatible = "qcom,geni-se-qup"; |
918 | reg = <0x0 0x009c0000 0x0 0x6000>; | |
919 | clock-names = "m-ahb", "s-ahb"; | |
6d91e201 VK |
920 | clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
921 | <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; | |
9bc2c8fe | 922 | iommus = <&apps_smmu 0x5a3 0>; |
b7e8f433 VK |
923 | #address-cells = <2>; |
924 | #size-cells = <2>; | |
925 | ranges; | |
926 | status = "disabled"; | |
927 | ||
cf03cd7e KD |
928 | i2c0: i2c@980000 { |
929 | compatible = "qcom,geni-i2c"; | |
930 | reg = <0 0x00980000 0 0x4000>; | |
931 | clock-names = "se"; | |
932 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
933 | pinctrl-names = "default"; | |
934 | pinctrl-0 = <&qup_i2c0_default>; | |
935 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
936 | dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, |
937 | <&gpi_dma0 1 0 QCOM_GPI_I2C>; | |
938 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
939 | #address-cells = <1>; |
940 | #size-cells = <0>; | |
941 | status = "disabled"; | |
942 | }; | |
943 | ||
944 | spi0: spi@980000 { | |
945 | compatible = "qcom,geni-spi"; | |
946 | reg = <0 0x00980000 0 0x4000>; | |
947 | clock-names = "se"; | |
948 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
949 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
950 | power-domains = <&rpmhpd SM8350_CX>; | |
951 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
952 | dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, |
953 | <&gpi_dma0 1 0 QCOM_GPI_SPI>; | |
954 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
955 | #address-cells = <1>; |
956 | #size-cells = <0>; | |
957 | status = "disabled"; | |
958 | }; | |
959 | ||
960 | i2c1: i2c@984000 { | |
961 | compatible = "qcom,geni-i2c"; | |
962 | reg = <0 0x00984000 0 0x4000>; | |
963 | clock-names = "se"; | |
964 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
965 | pinctrl-names = "default"; | |
966 | pinctrl-0 = <&qup_i2c1_default>; | |
967 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
968 | dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, |
969 | <&gpi_dma0 1 1 QCOM_GPI_I2C>; | |
970 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
971 | #address-cells = <1>; |
972 | #size-cells = <0>; | |
973 | status = "disabled"; | |
974 | }; | |
975 | ||
976 | spi1: spi@984000 { | |
977 | compatible = "qcom,geni-spi"; | |
978 | reg = <0 0x00984000 0 0x4000>; | |
979 | clock-names = "se"; | |
980 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
981 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
982 | power-domains = <&rpmhpd SM8350_CX>; | |
983 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
984 | dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, |
985 | <&gpi_dma0 1 1 QCOM_GPI_SPI>; | |
986 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
987 | #address-cells = <1>; |
988 | #size-cells = <0>; | |
989 | status = "disabled"; | |
990 | }; | |
991 | ||
992 | i2c2: i2c@988000 { | |
993 | compatible = "qcom,geni-i2c"; | |
994 | reg = <0 0x00988000 0 0x4000>; | |
995 | clock-names = "se"; | |
996 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
997 | pinctrl-names = "default"; | |
998 | pinctrl-0 = <&qup_i2c2_default>; | |
999 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1000 | dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, |
1001 | <&gpi_dma0 1 2 QCOM_GPI_I2C>; | |
1002 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1003 | #address-cells = <1>; |
1004 | #size-cells = <0>; | |
1005 | status = "disabled"; | |
1006 | }; | |
1007 | ||
1008 | spi2: spi@988000 { | |
1009 | compatible = "qcom,geni-spi"; | |
1010 | reg = <0 0x00988000 0 0x4000>; | |
1011 | clock-names = "se"; | |
1012 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
1013 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
1014 | power-domains = <&rpmhpd SM8350_CX>; | |
1015 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1016 | dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, |
1017 | <&gpi_dma0 1 2 QCOM_GPI_SPI>; | |
1018 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1019 | #address-cells = <1>; |
1020 | #size-cells = <0>; | |
1021 | status = "disabled"; | |
1022 | }; | |
1023 | ||
b7e8f433 VK |
1024 | uart2: serial@98c000 { |
1025 | compatible = "qcom,geni-debug-uart"; | |
1026 | reg = <0 0x0098c000 0 0x4000>; | |
1027 | clock-names = "se"; | |
6d91e201 | 1028 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
b7e8f433 VK |
1029 | pinctrl-names = "default"; |
1030 | pinctrl-0 = <&qup_uart3_default_state>; | |
1031 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
cf03cd7e KD |
1032 | power-domains = <&rpmhpd SM8350_CX>; |
1033 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
1034 | #address-cells = <1>; | |
1035 | #size-cells = <0>; | |
1036 | status = "disabled"; | |
1037 | }; | |
1038 | ||
1039 | /* QUP no. 3 seems to be strictly SPI-only */ | |
1040 | ||
1041 | spi3: spi@98c000 { | |
1042 | compatible = "qcom,geni-spi"; | |
1043 | reg = <0 0x0098c000 0 0x4000>; | |
1044 | clock-names = "se"; | |
1045 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; | |
1046 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
1047 | power-domains = <&rpmhpd SM8350_CX>; | |
1048 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1049 | dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, |
1050 | <&gpi_dma0 1 3 QCOM_GPI_SPI>; | |
1051 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1052 | #address-cells = <1>; |
1053 | #size-cells = <0>; | |
1054 | status = "disabled"; | |
1055 | }; | |
1056 | ||
1057 | i2c4: i2c@990000 { | |
1058 | compatible = "qcom,geni-i2c"; | |
1059 | reg = <0 0x00990000 0 0x4000>; | |
1060 | clock-names = "se"; | |
1061 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
1062 | pinctrl-names = "default"; | |
1063 | pinctrl-0 = <&qup_i2c4_default>; | |
1064 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1065 | dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, |
1066 | <&gpi_dma0 1 4 QCOM_GPI_I2C>; | |
1067 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1068 | #address-cells = <1>; |
1069 | #size-cells = <0>; | |
1070 | status = "disabled"; | |
1071 | }; | |
1072 | ||
1073 | spi4: spi@990000 { | |
1074 | compatible = "qcom,geni-spi"; | |
1075 | reg = <0 0x00990000 0 0x4000>; | |
1076 | clock-names = "se"; | |
1077 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
1078 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
1079 | power-domains = <&rpmhpd SM8350_CX>; | |
1080 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1081 | dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, |
1082 | <&gpi_dma0 1 4 QCOM_GPI_SPI>; | |
1083 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1084 | #address-cells = <1>; |
1085 | #size-cells = <0>; | |
1086 | status = "disabled"; | |
1087 | }; | |
1088 | ||
1089 | i2c5: i2c@994000 { | |
1090 | compatible = "qcom,geni-i2c"; | |
1091 | reg = <0 0x00994000 0 0x4000>; | |
1092 | clock-names = "se"; | |
1093 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
1094 | pinctrl-names = "default"; | |
1095 | pinctrl-0 = <&qup_i2c5_default>; | |
1096 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1097 | dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, |
1098 | <&gpi_dma0 1 5 QCOM_GPI_I2C>; | |
1099 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1100 | #address-cells = <1>; |
1101 | #size-cells = <0>; | |
1102 | status = "disabled"; | |
1103 | }; | |
1104 | ||
1105 | spi5: spi@994000 { | |
1106 | compatible = "qcom,geni-spi"; | |
1107 | reg = <0 0x00994000 0 0x4000>; | |
1108 | clock-names = "se"; | |
1109 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
1110 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
1111 | power-domains = <&rpmhpd SM8350_CX>; | |
1112 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1113 | dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, |
1114 | <&gpi_dma0 1 5 QCOM_GPI_SPI>; | |
1115 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1116 | #address-cells = <1>; |
1117 | #size-cells = <0>; | |
1118 | status = "disabled"; | |
1119 | }; | |
1120 | ||
1121 | i2c6: i2c@998000 { | |
1122 | compatible = "qcom,geni-i2c"; | |
1123 | reg = <0 0x00998000 0 0x4000>; | |
1124 | clock-names = "se"; | |
1125 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
1126 | pinctrl-names = "default"; | |
1127 | pinctrl-0 = <&qup_i2c6_default>; | |
1128 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1129 | dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, |
1130 | <&gpi_dma0 1 6 QCOM_GPI_I2C>; | |
1131 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1132 | #address-cells = <1>; |
1133 | #size-cells = <0>; | |
1134 | status = "disabled"; | |
1135 | }; | |
1136 | ||
1137 | spi6: spi@998000 { | |
1138 | compatible = "qcom,geni-spi"; | |
1139 | reg = <0 0x00998000 0 0x4000>; | |
1140 | clock-names = "se"; | |
1141 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
1142 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
1143 | power-domains = <&rpmhpd SM8350_CX>; | |
1144 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1145 | dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, |
1146 | <&gpi_dma0 1 6 QCOM_GPI_SPI>; | |
1147 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1148 | #address-cells = <1>; |
1149 | #size-cells = <0>; | |
1150 | status = "disabled"; | |
1151 | }; | |
1152 | ||
1153 | uart6: serial@998000 { | |
1154 | compatible = "qcom,geni-uart"; | |
1155 | reg = <0 0x00998000 0 0x4000>; | |
1156 | clock-names = "se"; | |
1157 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
1158 | pinctrl-names = "default"; | |
1159 | pinctrl-0 = <&qup_uart6_default>; | |
1160 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
1161 | power-domains = <&rpmhpd SM8350_CX>; | |
1162 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
1163 | status = "disabled"; | |
1164 | }; | |
1165 | ||
1166 | i2c7: i2c@99c000 { | |
1167 | compatible = "qcom,geni-i2c"; | |
1168 | reg = <0 0x0099c000 0 0x4000>; | |
1169 | clock-names = "se"; | |
1170 | clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; | |
1171 | pinctrl-names = "default"; | |
1172 | pinctrl-0 = <&qup_i2c7_default>; | |
1173 | interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1174 | dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, |
1175 | <&gpi_dma0 1 7 QCOM_GPI_I2C>; | |
1176 | dma-names = "tx", "rx"; | |
cf03cd7e KD |
1177 | #address-cells = <1>; |
1178 | #size-cells = <0>; | |
1179 | status = "disabled"; | |
1180 | }; | |
1181 | ||
1182 | spi7: spi@99c000 { | |
1183 | compatible = "qcom,geni-spi"; | |
1184 | reg = <0 0x0099c000 0 0x4000>; | |
1185 | clock-names = "se"; | |
1186 | clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; | |
1187 | interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; | |
1188 | power-domains = <&rpmhpd SM8350_CX>; | |
1189 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
bc08fbf4 BA |
1190 | dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, |
1191 | <&gpi_dma0 1 7 QCOM_GPI_SPI>; | |
1192 | dma-names = "tx", "rx"; | |
b7e8f433 VK |
1193 | #address-cells = <1>; |
1194 | #size-cells = <0>; | |
1195 | status = "disabled"; | |
1196 | }; | |
1197 | }; | |
1198 | ||
bc08fbf4 | 1199 | gpi_dma1: dma-controller@a00000 { |
b561e225 | 1200 | compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; |
bc08fbf4 BA |
1201 | reg = <0 0x00a00000 0 0x60000>; |
1202 | interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
1203 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, | |
1204 | <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, | |
1205 | <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, | |
1206 | <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, | |
1207 | <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, | |
1208 | <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, | |
1209 | <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, | |
1210 | <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, | |
1211 | <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, | |
1212 | <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, | |
1213 | <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; | |
1214 | dma-channels = <12>; | |
1215 | dma-channel-mask = <0xff>; | |
1216 | iommus = <&apps_smmu 0x56 0x0>; | |
1217 | #dma-cells = <3>; | |
1218 | status = "disabled"; | |
1219 | }; | |
1220 | ||
06bf656e JM |
1221 | qupv3_id_1: geniqup@ac0000 { |
1222 | compatible = "qcom,geni-se-qup"; | |
1223 | reg = <0x0 0x00ac0000 0x0 0x6000>; | |
1224 | clock-names = "m-ahb", "s-ahb"; | |
1225 | clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, | |
1226 | <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; | |
9bc2c8fe | 1227 | iommus = <&apps_smmu 0x43 0>; |
06bf656e JM |
1228 | #address-cells = <2>; |
1229 | #size-cells = <2>; | |
1230 | ranges; | |
1231 | status = "disabled"; | |
1232 | ||
89345355 KD |
1233 | i2c8: i2c@a80000 { |
1234 | compatible = "qcom,geni-i2c"; | |
1235 | reg = <0 0x00a80000 0 0x4000>; | |
1236 | clock-names = "se"; | |
1237 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
1238 | pinctrl-names = "default"; | |
1239 | pinctrl-0 = <&qup_i2c8_default>; | |
1240 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1241 | dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, |
1242 | <&gpi_dma1 1 0 QCOM_GPI_I2C>; | |
1243 | dma-names = "tx", "rx"; | |
89345355 KD |
1244 | #address-cells = <1>; |
1245 | #size-cells = <0>; | |
1246 | status = "disabled"; | |
1247 | }; | |
1248 | ||
1249 | spi8: spi@a80000 { | |
1250 | compatible = "qcom,geni-spi"; | |
1251 | reg = <0 0x00a80000 0 0x4000>; | |
1252 | clock-names = "se"; | |
1253 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
1254 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
1255 | power-domains = <&rpmhpd SM8350_CX>; | |
1256 | operating-points-v2 = <&qup_opp_table_120mhz>; | |
ddc97e7d BA |
1257 | dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, |
1258 | <&gpi_dma1 1 0 QCOM_GPI_SPI>; | |
1259 | dma-names = "tx", "rx"; | |
89345355 KD |
1260 | #address-cells = <1>; |
1261 | #size-cells = <0>; | |
1262 | status = "disabled"; | |
1263 | }; | |
1264 | ||
1265 | i2c9: i2c@a84000 { | |
1266 | compatible = "qcom,geni-i2c"; | |
1267 | reg = <0 0x00a84000 0 0x4000>; | |
1268 | clock-names = "se"; | |
1269 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
1270 | pinctrl-names = "default"; | |
1271 | pinctrl-0 = <&qup_i2c9_default>; | |
1272 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1273 | dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, |
1274 | <&gpi_dma1 1 1 QCOM_GPI_I2C>; | |
1275 | dma-names = "tx", "rx"; | |
89345355 KD |
1276 | #address-cells = <1>; |
1277 | #size-cells = <0>; | |
1278 | status = "disabled"; | |
1279 | }; | |
1280 | ||
1281 | spi9: spi@a84000 { | |
1282 | compatible = "qcom,geni-spi"; | |
1283 | reg = <0 0x00a84000 0 0x4000>; | |
1284 | clock-names = "se"; | |
1285 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
1286 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
1287 | power-domains = <&rpmhpd SM8350_CX>; | |
1288 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1289 | dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, |
1290 | <&gpi_dma1 1 1 QCOM_GPI_SPI>; | |
1291 | dma-names = "tx", "rx"; | |
89345355 KD |
1292 | #address-cells = <1>; |
1293 | #size-cells = <0>; | |
1294 | status = "disabled"; | |
1295 | }; | |
1296 | ||
1297 | i2c10: i2c@a88000 { | |
1298 | compatible = "qcom,geni-i2c"; | |
1299 | reg = <0 0x00a88000 0 0x4000>; | |
1300 | clock-names = "se"; | |
1301 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
1302 | pinctrl-names = "default"; | |
1303 | pinctrl-0 = <&qup_i2c10_default>; | |
1304 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1305 | dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, |
1306 | <&gpi_dma1 1 2 QCOM_GPI_I2C>; | |
1307 | dma-names = "tx", "rx"; | |
89345355 KD |
1308 | #address-cells = <1>; |
1309 | #size-cells = <0>; | |
1310 | status = "disabled"; | |
1311 | }; | |
1312 | ||
1313 | spi10: spi@a88000 { | |
1314 | compatible = "qcom,geni-spi"; | |
1315 | reg = <0 0x00a88000 0 0x4000>; | |
1316 | clock-names = "se"; | |
1317 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
1318 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
1319 | power-domains = <&rpmhpd SM8350_CX>; | |
1320 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1321 | dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, |
1322 | <&gpi_dma1 1 2 QCOM_GPI_SPI>; | |
1323 | dma-names = "tx", "rx"; | |
89345355 KD |
1324 | #address-cells = <1>; |
1325 | #size-cells = <0>; | |
1326 | status = "disabled"; | |
1327 | }; | |
1328 | ||
1329 | i2c11: i2c@a8c000 { | |
1330 | compatible = "qcom,geni-i2c"; | |
1331 | reg = <0 0x00a8c000 0 0x4000>; | |
1332 | clock-names = "se"; | |
1333 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
1334 | pinctrl-names = "default"; | |
1335 | pinctrl-0 = <&qup_i2c11_default>; | |
1336 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1337 | dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, |
1338 | <&gpi_dma1 1 3 QCOM_GPI_I2C>; | |
1339 | dma-names = "tx", "rx"; | |
89345355 KD |
1340 | #address-cells = <1>; |
1341 | #size-cells = <0>; | |
1342 | status = "disabled"; | |
1343 | }; | |
1344 | ||
1345 | spi11: spi@a8c000 { | |
1346 | compatible = "qcom,geni-spi"; | |
1347 | reg = <0 0x00a8c000 0 0x4000>; | |
1348 | clock-names = "se"; | |
1349 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
1350 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
1351 | power-domains = <&rpmhpd SM8350_CX>; | |
1352 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1353 | dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, |
1354 | <&gpi_dma1 1 3 QCOM_GPI_SPI>; | |
1355 | dma-names = "tx", "rx"; | |
89345355 KD |
1356 | #address-cells = <1>; |
1357 | #size-cells = <0>; | |
1358 | status = "disabled"; | |
1359 | }; | |
1360 | ||
1361 | i2c12: i2c@a90000 { | |
1362 | compatible = "qcom,geni-i2c"; | |
1363 | reg = <0 0x00a90000 0 0x4000>; | |
1364 | clock-names = "se"; | |
1365 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
1366 | pinctrl-names = "default"; | |
1367 | pinctrl-0 = <&qup_i2c12_default>; | |
1368 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
ddc97e7d BA |
1369 | dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, |
1370 | <&gpi_dma1 1 4 QCOM_GPI_I2C>; | |
1371 | dma-names = "tx", "rx"; | |
89345355 KD |
1372 | #address-cells = <1>; |
1373 | #size-cells = <0>; | |
1374 | status = "disabled"; | |
1375 | }; | |
1376 | ||
1377 | spi12: spi@a90000 { | |
1378 | compatible = "qcom,geni-spi"; | |
1379 | reg = <0 0x00a90000 0 0x4000>; | |
1380 | clock-names = "se"; | |
1381 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
1382 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
1383 | power-domains = <&rpmhpd SM8350_CX>; | |
1384 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1385 | dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, |
1386 | <&gpi_dma1 1 4 QCOM_GPI_SPI>; | |
1387 | dma-names = "tx", "rx"; | |
89345355 KD |
1388 | #address-cells = <1>; |
1389 | #size-cells = <0>; | |
1390 | status = "disabled"; | |
1391 | }; | |
1392 | ||
06bf656e JM |
1393 | i2c13: i2c@a94000 { |
1394 | compatible = "qcom,geni-i2c"; | |
1395 | reg = <0 0x00a94000 0 0x4000>; | |
1396 | clock-names = "se"; | |
1397 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
1398 | pinctrl-names = "default"; | |
89345355 | 1399 | pinctrl-0 = <&qup_i2c13_default>; |
06bf656e | 1400 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
ddc97e7d BA |
1401 | dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, |
1402 | <&gpi_dma1 1 5 QCOM_GPI_I2C>; | |
1403 | dma-names = "tx", "rx"; | |
06bf656e JM |
1404 | #address-cells = <1>; |
1405 | #size-cells = <0>; | |
1406 | status = "disabled"; | |
1407 | }; | |
89345355 KD |
1408 | |
1409 | spi13: spi@a94000 { | |
1410 | compatible = "qcom,geni-spi"; | |
1411 | reg = <0 0x00a94000 0 0x4000>; | |
1412 | clock-names = "se"; | |
1413 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
1414 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
1415 | power-domains = <&rpmhpd SM8350_CX>; | |
1416 | operating-points-v2 = <&qup_opp_table_100mhz>; | |
ddc97e7d BA |
1417 | dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, |
1418 | <&gpi_dma1 1 5 QCOM_GPI_SPI>; | |
1419 | dma-names = "tx", "rx"; | |
89345355 KD |
1420 | #address-cells = <1>; |
1421 | #size-cells = <0>; | |
1422 | status = "disabled"; | |
1423 | }; | |
06bf656e JM |
1424 | }; |
1425 | ||
187f65b7 VK |
1426 | apps_smmu: iommu@15000000 { |
1427 | compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; | |
1428 | reg = <0 0x15000000 0 0x100000>; | |
1429 | #iommu-cells = <2>; | |
1430 | #global-interrupts = <2>; | |
1431 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, | |
1432 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, | |
1433 | <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, | |
1434 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, | |
1435 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, | |
1436 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
1437 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, | |
1438 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
1439 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, | |
1440 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
1441 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
1442 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
1443 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
1444 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
1445 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
1446 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
1447 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
1448 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
1449 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
1450 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
1451 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
1452 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
1453 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
1454 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
1455 | <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, | |
1456 | <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, | |
1457 | <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, | |
1458 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, | |
1459 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, | |
1460 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, | |
1461 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, | |
1462 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, | |
1463 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, | |
1464 | <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, | |
1465 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, | |
1466 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, | |
1467 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, | |
1468 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, | |
1469 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, | |
1470 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, | |
1471 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, | |
1472 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
1473 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, | |
1474 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, | |
1475 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, | |
1476 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, | |
1477 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, | |
1478 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
1479 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, | |
1480 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, | |
1481 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
1482 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, | |
1483 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, | |
1484 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, | |
1485 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, | |
1486 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
1487 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
1488 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
1489 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
1490 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
1491 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
1492 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
1493 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, | |
1494 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, | |
1495 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, | |
1496 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
1497 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
1498 | <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, | |
1499 | <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, | |
1500 | <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, | |
1501 | <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
1502 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
1503 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
1504 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
1505 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
1506 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, | |
1507 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
1508 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, | |
1509 | <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, | |
1510 | <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, | |
1511 | <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, | |
1512 | <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, | |
1513 | <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, | |
1514 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
1515 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
1516 | <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, | |
1517 | <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, | |
1518 | <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, | |
1519 | <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, | |
1520 | <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, | |
1521 | <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, | |
1522 | <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, | |
1523 | <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, | |
1524 | <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, | |
1525 | <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, | |
1526 | <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, | |
1527 | <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, | |
1528 | <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; | |
1529 | }; | |
1530 | ||
da6b2482 VK |
1531 | config_noc: interconnect@1500000 { |
1532 | compatible = "qcom,sm8350-config-noc"; | |
1533 | reg = <0 0x01500000 0 0xa580>; | |
4f287e31 | 1534 | #interconnect-cells = <2>; |
da6b2482 VK |
1535 | qcom,bcm-voters = <&apps_bcm_voter>; |
1536 | }; | |
1537 | ||
1538 | mc_virt: interconnect@1580000 { | |
1539 | compatible = "qcom,sm8350-mc-virt"; | |
1540 | reg = <0 0x01580000 0 0x1000>; | |
4f287e31 | 1541 | #interconnect-cells = <2>; |
da6b2482 VK |
1542 | qcom,bcm-voters = <&apps_bcm_voter>; |
1543 | }; | |
1544 | ||
1545 | system_noc: interconnect@1680000 { | |
1546 | compatible = "qcom,sm8350-system-noc"; | |
1547 | reg = <0 0x01680000 0 0x1c200>; | |
4f287e31 | 1548 | #interconnect-cells = <2>; |
da6b2482 VK |
1549 | qcom,bcm-voters = <&apps_bcm_voter>; |
1550 | }; | |
1551 | ||
1552 | aggre1_noc: interconnect@16e0000 { | |
1553 | compatible = "qcom,sm8350-aggre1-noc"; | |
1554 | reg = <0 0x016e0000 0 0x1f180>; | |
4f287e31 | 1555 | #interconnect-cells = <2>; |
da6b2482 VK |
1556 | qcom,bcm-voters = <&apps_bcm_voter>; |
1557 | }; | |
1558 | ||
1559 | aggre2_noc: interconnect@1700000 { | |
1560 | compatible = "qcom,sm8350-aggre2-noc"; | |
1561 | reg = <0 0x01700000 0 0x33000>; | |
4f287e31 | 1562 | #interconnect-cells = <2>; |
da6b2482 VK |
1563 | qcom,bcm-voters = <&apps_bcm_voter>; |
1564 | }; | |
1565 | ||
1566 | mmss_noc: interconnect@1740000 { | |
1567 | compatible = "qcom,sm8350-mmss-noc"; | |
1568 | reg = <0 0x01740000 0 0x1f080>; | |
4f287e31 | 1569 | #interconnect-cells = <2>; |
da6b2482 VK |
1570 | qcom,bcm-voters = <&apps_bcm_voter>; |
1571 | }; | |
1572 | ||
6daee406 DB |
1573 | pcie0: pci@1c00000 { |
1574 | compatible = "qcom,pcie-sm8350"; | |
1575 | reg = <0 0x01c00000 0 0x3000>, | |
1576 | <0 0x60000000 0 0xf1d>, | |
1577 | <0 0x60000f20 0 0xa8>, | |
1578 | <0 0x60001000 0 0x1000>, | |
1579 | <0 0x60100000 0 0x100000>; | |
1580 | reg-names = "parf", "dbi", "elbi", "atu", "config"; | |
1581 | device_type = "pci"; | |
1582 | linux,pci-domain = <0>; | |
1583 | bus-range = <0x00 0xff>; | |
1584 | num-lanes = <1>; | |
1585 | ||
1586 | #address-cells = <3>; | |
1587 | #size-cells = <2>; | |
1588 | ||
1589 | ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, | |
1590 | <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; | |
1591 | ||
1592 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
1593 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
1594 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, | |
1595 | <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, | |
1596 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
1597 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
1598 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, | |
1599 | <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
1600 | interrupt-names = "msi0", "msi1", "msi2", "msi3", | |
1601 | "msi4", "msi5", "msi6", "msi7"; | |
1602 | #interrupt-cells = <1>; | |
1603 | interrupt-map-mask = <0 0 0 0x7>; | |
1604 | interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
1605 | <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
1606 | <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
1607 | <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
1608 | ||
1609 | clocks = <&gcc GCC_PCIE_0_AUX_CLK>, | |
1610 | <&gcc GCC_PCIE_0_CFG_AHB_CLK>, | |
1611 | <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, | |
1612 | <&gcc GCC_PCIE_0_SLV_AXI_CLK>, | |
1613 | <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, | |
1614 | <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, | |
1615 | <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, | |
1616 | <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, | |
1617 | <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; | |
1618 | clock-names = "aux", | |
1619 | "cfg", | |
1620 | "bus_master", | |
1621 | "bus_slave", | |
1622 | "slave_q2a", | |
1623 | "tbu", | |
1624 | "ddrss_sf_tbu", | |
1625 | "aggre1", | |
1626 | "aggre0"; | |
1627 | ||
1628 | iommus = <&apps_smmu 0x1c00 0x7f>; | |
1629 | iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, | |
1630 | <0x100 &apps_smmu 0x1c01 0x1>; | |
1631 | ||
1632 | resets = <&gcc GCC_PCIE_0_BCR>; | |
1633 | reset-names = "pci"; | |
1634 | ||
1635 | power-domains = <&gcc PCIE_0_GDSC>; | |
1636 | ||
1637 | phys = <&pcie0_phy>; | |
1638 | phy-names = "pciephy"; | |
1639 | ||
1640 | status = "disabled"; | |
1641 | }; | |
1642 | ||
1643 | pcie0_phy: phy@1c06000 { | |
1644 | compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; | |
1645 | reg = <0 0x01c06000 0 0x2000>; | |
1646 | clocks = <&gcc GCC_PCIE_0_AUX_CLK>, | |
1647 | <&gcc GCC_PCIE_0_CFG_AHB_CLK>, | |
1648 | <&gcc GCC_PCIE_0_CLKREF_EN>, | |
1649 | <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, | |
1650 | <&gcc GCC_PCIE_0_PIPE_CLK>; | |
1651 | clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; | |
1652 | ||
1653 | resets = <&gcc GCC_PCIE_0_PHY_BCR>; | |
1654 | reset-names = "phy"; | |
1655 | ||
1656 | assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; | |
1657 | assigned-clock-rates = <100000000>; | |
1658 | ||
1659 | #clock-cells = <0>; | |
1660 | clock-output-names = "pcie_0_pipe_clk"; | |
1661 | ||
1662 | #phy-cells = <0>; | |
1663 | ||
1664 | status = "disabled"; | |
1665 | }; | |
1666 | ||
1667 | pcie1: pci@1c08000 { | |
1668 | compatible = "qcom,pcie-sm8350"; | |
1669 | reg = <0 0x01c08000 0 0x3000>, | |
1670 | <0 0x40000000 0 0xf1d>, | |
1671 | <0 0x40000f20 0 0xa8>, | |
1672 | <0 0x40001000 0 0x1000>, | |
1673 | <0 0x40100000 0 0x100000>; | |
1674 | reg-names = "parf", "dbi", "elbi", "atu", "config"; | |
1675 | device_type = "pci"; | |
1676 | linux,pci-domain = <1>; | |
1677 | bus-range = <0x00 0xff>; | |
1678 | num-lanes = <2>; | |
1679 | ||
1680 | #address-cells = <3>; | |
1681 | #size-cells = <2>; | |
1682 | ||
1683 | ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, | |
1684 | <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; | |
1685 | ||
1686 | interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; | |
1687 | interrupt-names = "msi"; | |
1688 | #interrupt-cells = <1>; | |
1689 | interrupt-map-mask = <0 0 0 0x7>; | |
1690 | interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
1691 | <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
1692 | <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
1693 | <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
1694 | ||
1695 | clocks = <&gcc GCC_PCIE_1_AUX_CLK>, | |
1696 | <&gcc GCC_PCIE_1_CFG_AHB_CLK>, | |
1697 | <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, | |
1698 | <&gcc GCC_PCIE_1_SLV_AXI_CLK>, | |
1699 | <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, | |
1700 | <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, | |
1701 | <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, | |
1702 | <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; | |
1703 | clock-names = "aux", | |
1704 | "cfg", | |
1705 | "bus_master", | |
1706 | "bus_slave", | |
1707 | "slave_q2a", | |
1708 | "tbu", | |
1709 | "ddrss_sf_tbu", | |
1710 | "aggre1"; | |
1711 | ||
1712 | iommus = <&apps_smmu 0x1c80 0x7f>; | |
1713 | iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, | |
1714 | <0x100 &apps_smmu 0x1c81 0x1>; | |
1715 | ||
1716 | resets = <&gcc GCC_PCIE_1_BCR>; | |
1717 | reset-names = "pci"; | |
1718 | ||
1719 | power-domains = <&gcc PCIE_1_GDSC>; | |
1720 | ||
1721 | phys = <&pcie1_phy>; | |
1722 | phy-names = "pciephy"; | |
1723 | ||
1724 | status = "disabled"; | |
1725 | }; | |
1726 | ||
1727 | pcie1_phy: phy@1c0f000 { | |
1728 | compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; | |
1729 | reg = <0 0x01c0e000 0 0x2000>; | |
1730 | clocks = <&gcc GCC_PCIE_1_AUX_CLK>, | |
1731 | <&gcc GCC_PCIE_1_CFG_AHB_CLK>, | |
1732 | <&gcc GCC_PCIE_1_CLKREF_EN>, | |
1733 | <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, | |
1734 | <&gcc GCC_PCIE_1_PIPE_CLK>; | |
1735 | clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; | |
1736 | ||
1737 | resets = <&gcc GCC_PCIE_1_PHY_BCR>; | |
1738 | reset-names = "phy"; | |
1739 | ||
1740 | assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; | |
1741 | assigned-clock-rates = <100000000>; | |
1742 | ||
1743 | #clock-cells = <0>; | |
1744 | clock-output-names = "pcie_1_pipe_clk"; | |
1745 | ||
1746 | #phy-cells = <0>; | |
1747 | ||
1748 | status = "disabled"; | |
1749 | }; | |
1750 | ||
da6b2482 VK |
1751 | lpass_ag_noc: interconnect@3c40000 { |
1752 | compatible = "qcom,sm8350-lpass-ag-noc"; | |
1753 | reg = <0 0x03c40000 0 0xf080>; | |
4f287e31 | 1754 | #interconnect-cells = <2>; |
da6b2482 VK |
1755 | qcom,bcm-voters = <&apps_bcm_voter>; |
1756 | }; | |
1757 | ||
66b14154 | 1758 | compute_noc: interconnect@a0c0000 { |
da6b2482 VK |
1759 | compatible = "qcom,sm8350-compute-noc"; |
1760 | reg = <0 0x0a0c0000 0 0xa180>; | |
4f287e31 | 1761 | #interconnect-cells = <2>; |
da6b2482 VK |
1762 | qcom,bcm-voters = <&apps_bcm_voter>; |
1763 | }; | |
1764 | ||
f11d3e7d AE |
1765 | ipa: ipa@1e40000 { |
1766 | compatible = "qcom,sm8350-ipa"; | |
1767 | ||
1768 | iommus = <&apps_smmu 0x5c0 0x0>, | |
1769 | <&apps_smmu 0x5c2 0x0>; | |
f3c08ae6 KD |
1770 | reg = <0 0x01e40000 0 0x8000>, |
1771 | <0 0x01e50000 0 0x4b20>, | |
1772 | <0 0x01e04000 0 0x23000>; | |
f11d3e7d AE |
1773 | reg-names = "ipa-reg", |
1774 | "ipa-shared", | |
1775 | "gsi"; | |
1776 | ||
1777 | interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, | |
1778 | <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, | |
1779 | <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
1780 | <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; | |
1781 | interrupt-names = "ipa", | |
1782 | "gsi", | |
1783 | "ipa-clock-query", | |
1784 | "ipa-setup-ready"; | |
1785 | ||
1786 | clocks = <&rpmhcc RPMH_IPA_CLK>; | |
1787 | clock-names = "core"; | |
1788 | ||
4f287e31 RF |
1789 | interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, |
1790 | <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; | |
84173ca3 AE |
1791 | interconnect-names = "memory", |
1792 | "config"; | |
f11d3e7d | 1793 | |
73419e4d AE |
1794 | qcom,qmp = <&aoss_qmp>; |
1795 | ||
f11d3e7d AE |
1796 | qcom,smem-states = <&ipa_smp2p_out 0>, |
1797 | <&ipa_smp2p_out 1>; | |
1798 | qcom,smem-state-names = "ipa-clock-enabled-valid", | |
1799 | "ipa-clock-enabled"; | |
1800 | ||
1801 | status = "disabled"; | |
1802 | }; | |
1803 | ||
b7e8f433 VK |
1804 | tcsr_mutex: hwlock@1f40000 { |
1805 | compatible = "qcom,tcsr-mutex"; | |
1806 | reg = <0x0 0x01f40000 0x0 0x40000>; | |
1807 | #hwlock-cells = <1>; | |
1808 | }; | |
1809 | ||
177fcf0a VK |
1810 | mpss: remoteproc@4080000 { |
1811 | compatible = "qcom,sm8350-mpss-pas"; | |
1812 | reg = <0x0 0x04080000 0x0 0x4040>; | |
1813 | ||
1814 | interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, | |
1815 | <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, | |
1816 | <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, | |
1817 | <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, | |
1818 | <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, | |
1819 | <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; | |
1820 | interrupt-names = "wdog", "fatal", "ready", "handover", | |
1821 | "stop-ack", "shutdown-ack"; | |
1822 | ||
1823 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
1824 | clock-names = "xo"; | |
1825 | ||
d0e285c3 RF |
1826 | power-domains = <&rpmhpd SM8350_CX>, |
1827 | <&rpmhpd SM8350_MSS>; | |
6b7cb2d2 | 1828 | power-domain-names = "cx", "mss"; |
177fcf0a | 1829 | |
4f287e31 | 1830 | interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; |
da6b2482 | 1831 | |
177fcf0a VK |
1832 | memory-region = <&pil_modem_mem>; |
1833 | ||
6b7cb2d2 SS |
1834 | qcom,qmp = <&aoss_qmp>; |
1835 | ||
177fcf0a VK |
1836 | qcom,smem-states = <&smp2p_modem_out 0>; |
1837 | qcom,smem-state-names = "stop"; | |
1838 | ||
1839 | status = "disabled"; | |
1840 | ||
1841 | glink-edge { | |
1842 | interrupts-extended = <&ipcc IPCC_CLIENT_MPSS | |
1843 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
1844 | IRQ_TYPE_EDGE_RISING>; | |
1845 | mboxes = <&ipcc IPCC_CLIENT_MPSS | |
1846 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
177fcf0a VK |
1847 | label = "modem"; |
1848 | qcom,remote-pid = <1>; | |
1849 | }; | |
1850 | }; | |
1851 | ||
b7e8f433 VK |
1852 | pdc: interrupt-controller@b220000 { |
1853 | compatible = "qcom,sm8350-pdc", "qcom,pdc"; | |
1854 | reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; | |
1855 | qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, | |
1856 | <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, | |
1857 | <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, | |
1858 | <156 716 12>; | |
1859 | #interrupt-cells = <2>; | |
1860 | interrupt-parent = <&intc>; | |
1861 | interrupt-controller; | |
1862 | }; | |
1863 | ||
1dee9e3b | 1864 | tsens0: thermal-sensor@c263000 { |
20f9d94e RF |
1865 | compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; |
1866 | reg = <0 0x0c263000 0 0x1ff>, /* TM */ | |
1867 | <0 0x0c222000 0 0x8>; /* SROT */ | |
1868 | #qcom,sensors = <15>; | |
9e7f7b65 | 1869 | interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, |
20f9d94e RF |
1870 | <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; |
1871 | interrupt-names = "uplow", "critical"; | |
1872 | #thermal-sensor-cells = <1>; | |
1873 | }; | |
1874 | ||
1dee9e3b | 1875 | tsens1: thermal-sensor@c265000 { |
20f9d94e RF |
1876 | compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; |
1877 | reg = <0 0x0c265000 0 0x1ff>, /* TM */ | |
1878 | <0 0x0c223000 0 0x8>; /* SROT */ | |
1879 | #qcom,sensors = <14>; | |
9e7f7b65 | 1880 | interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, |
20f9d94e RF |
1881 | <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; |
1882 | interrupt-names = "uplow", "critical"; | |
1883 | #thermal-sensor-cells = <1>; | |
1884 | }; | |
1885 | ||
bb99820d | 1886 | aoss_qmp: power-management@c300000 { |
6ba93ba9 | 1887 | compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; |
47cb6a06 | 1888 | reg = <0 0x0c300000 0 0x400>; |
b7e8f433 VK |
1889 | interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP |
1890 | IRQ_TYPE_EDGE_RISING>; | |
1891 | mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
1892 | ||
1893 | #clock-cells = <0>; | |
b7e8f433 VK |
1894 | }; |
1895 | ||
47cb6a06 MS |
1896 | sram@c3f0000 { |
1897 | compatible = "qcom,rpmh-stats"; | |
1898 | reg = <0 0x0c3f0000 0 0x400>; | |
1899 | }; | |
1900 | ||
389cd7ac VK |
1901 | spmi_bus: spmi@c440000 { |
1902 | compatible = "qcom,spmi-pmic-arb"; | |
f3c08ae6 KD |
1903 | reg = <0x0 0x0c440000 0x0 0x1100>, |
1904 | <0x0 0x0c600000 0x0 0x2000000>, | |
1905 | <0x0 0x0e600000 0x0 0x100000>, | |
1906 | <0x0 0x0e700000 0x0 0xa0000>, | |
1907 | <0x0 0x0c40a000 0x0 0x26000>; | |
389cd7ac VK |
1908 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
1909 | interrupt-names = "periph_irq"; | |
1910 | interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; | |
1911 | qcom,ee = <0>; | |
1912 | qcom,channel = <0>; | |
1913 | #address-cells = <2>; | |
1914 | #size-cells = <0>; | |
1915 | interrupt-controller; | |
1916 | #interrupt-cells = <4>; | |
1917 | }; | |
1918 | ||
b7e8f433 VK |
1919 | tlmm: pinctrl@f100000 { |
1920 | compatible = "qcom,sm8350-tlmm"; | |
1921 | reg = <0 0x0f100000 0 0x300000>; | |
1922 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
1923 | gpio-controller; | |
1924 | #gpio-cells = <2>; | |
1925 | interrupt-controller; | |
1926 | #interrupt-cells = <2>; | |
79015857 | 1927 | gpio-ranges = <&tlmm 0 0 204>; |
67146f07 | 1928 | wakeup-parent = <&pdc>; |
b7e8f433 | 1929 | |
60477435 KD |
1930 | sdc2_default_state: sdc2-default-state { |
1931 | clk-pins { | |
1932 | pins = "sdc2_clk"; | |
1933 | drive-strength = <16>; | |
1934 | bias-disable; | |
1935 | }; | |
1936 | ||
1937 | cmd-pins { | |
1938 | pins = "sdc2_cmd"; | |
1939 | drive-strength = <16>; | |
1940 | bias-pull-up; | |
1941 | }; | |
1942 | ||
1943 | data-pins { | |
1944 | pins = "sdc2_data"; | |
1945 | drive-strength = <16>; | |
1946 | bias-pull-up; | |
1947 | }; | |
1948 | }; | |
1949 | ||
1950 | sdc2_sleep_state: sdc2-sleep-state { | |
1951 | clk-pins { | |
1952 | pins = "sdc2_clk"; | |
1953 | drive-strength = <2>; | |
1954 | bias-disable; | |
1955 | }; | |
1956 | ||
1957 | cmd-pins { | |
1958 | pins = "sdc2_cmd"; | |
1959 | drive-strength = <2>; | |
1960 | bias-pull-up; | |
1961 | }; | |
1962 | ||
1963 | data-pins { | |
1964 | pins = "sdc2_data"; | |
1965 | drive-strength = <2>; | |
1966 | bias-pull-up; | |
1967 | }; | |
1968 | }; | |
1969 | ||
b7e8f433 | 1970 | qup_uart3_default_state: qup-uart3-default-state { |
e227fa29 | 1971 | rx-pins { |
b7e8f433 VK |
1972 | pins = "gpio18"; |
1973 | function = "qup3"; | |
1974 | }; | |
e227fa29 | 1975 | tx-pins { |
b7e8f433 VK |
1976 | pins = "gpio19"; |
1977 | function = "qup3"; | |
1978 | }; | |
1979 | }; | |
06bf656e | 1980 | |
e227fa29 | 1981 | qup_uart6_default: qup-uart6-default-state { |
cf03cd7e KD |
1982 | pins = "gpio30", "gpio31"; |
1983 | function = "qup6"; | |
1984 | drive-strength = <2>; | |
1985 | bias-disable; | |
1986 | }; | |
1987 | ||
e227fa29 | 1988 | qup_uart18_default: qup-uart18-default-state { |
98374e69 KD |
1989 | pins = "gpio58", "gpio59"; |
1990 | function = "qup18"; | |
1991 | drive-strength = <2>; | |
1992 | bias-disable; | |
1993 | }; | |
1994 | ||
e227fa29 | 1995 | qup_i2c0_default: qup-i2c0-default-state { |
cf03cd7e KD |
1996 | pins = "gpio4", "gpio5"; |
1997 | function = "qup0"; | |
1998 | drive-strength = <2>; | |
1999 | bias-pull-up; | |
2000 | }; | |
2001 | ||
e227fa29 | 2002 | qup_i2c1_default: qup-i2c1-default-state { |
cf03cd7e KD |
2003 | pins = "gpio8", "gpio9"; |
2004 | function = "qup1"; | |
2005 | drive-strength = <2>; | |
2006 | bias-pull-up; | |
2007 | }; | |
2008 | ||
e227fa29 | 2009 | qup_i2c2_default: qup-i2c2-default-state { |
cf03cd7e KD |
2010 | pins = "gpio12", "gpio13"; |
2011 | function = "qup2"; | |
2012 | drive-strength = <2>; | |
2013 | bias-pull-up; | |
2014 | }; | |
2015 | ||
e227fa29 | 2016 | qup_i2c4_default: qup-i2c4-default-state { |
cf03cd7e KD |
2017 | pins = "gpio20", "gpio21"; |
2018 | function = "qup4"; | |
2019 | drive-strength = <2>; | |
2020 | bias-pull-up; | |
2021 | }; | |
2022 | ||
e227fa29 | 2023 | qup_i2c5_default: qup-i2c5-default-state { |
cf03cd7e KD |
2024 | pins = "gpio24", "gpio25"; |
2025 | function = "qup5"; | |
2026 | drive-strength = <2>; | |
2027 | bias-pull-up; | |
2028 | }; | |
2029 | ||
e227fa29 | 2030 | qup_i2c6_default: qup-i2c6-default-state { |
cf03cd7e KD |
2031 | pins = "gpio28", "gpio29"; |
2032 | function = "qup6"; | |
2033 | drive-strength = <2>; | |
2034 | bias-pull-up; | |
2035 | }; | |
2036 | ||
e227fa29 | 2037 | qup_i2c7_default: qup-i2c7-default-state { |
cf03cd7e KD |
2038 | pins = "gpio32", "gpio33"; |
2039 | function = "qup7"; | |
2040 | drive-strength = <2>; | |
2041 | bias-disable; | |
2042 | }; | |
2043 | ||
e227fa29 | 2044 | qup_i2c8_default: qup-i2c8-default-state { |
89345355 KD |
2045 | pins = "gpio36", "gpio37"; |
2046 | function = "qup8"; | |
2047 | drive-strength = <2>; | |
2048 | bias-pull-up; | |
2049 | }; | |
06bf656e | 2050 | |
e227fa29 | 2051 | qup_i2c9_default: qup-i2c9-default-state { |
89345355 KD |
2052 | pins = "gpio40", "gpio41"; |
2053 | function = "qup9"; | |
2054 | drive-strength = <2>; | |
2055 | bias-pull-up; | |
2056 | }; | |
2057 | ||
e227fa29 | 2058 | qup_i2c10_default: qup-i2c10-default-state { |
89345355 KD |
2059 | pins = "gpio44", "gpio45"; |
2060 | function = "qup10"; | |
2061 | drive-strength = <2>; | |
2062 | bias-pull-up; | |
2063 | }; | |
2064 | ||
e227fa29 | 2065 | qup_i2c11_default: qup-i2c11-default-state { |
89345355 KD |
2066 | pins = "gpio48", "gpio49"; |
2067 | function = "qup11"; | |
2068 | drive-strength = <2>; | |
2069 | bias-pull-up; | |
2070 | }; | |
2071 | ||
e227fa29 | 2072 | qup_i2c12_default: qup-i2c12-default-state { |
89345355 KD |
2073 | pins = "gpio52", "gpio53"; |
2074 | function = "qup12"; | |
2075 | drive-strength = <2>; | |
2076 | bias-pull-up; | |
2077 | }; | |
2078 | ||
e227fa29 | 2079 | qup_i2c13_default: qup-i2c13-default-state { |
89345355 KD |
2080 | pins = "gpio0", "gpio1"; |
2081 | function = "qup13"; | |
2082 | drive-strength = <2>; | |
2083 | bias-pull-up; | |
06bf656e | 2084 | }; |
98374e69 | 2085 | |
e227fa29 | 2086 | qup_i2c14_default: qup-i2c14-default-state { |
98374e69 KD |
2087 | pins = "gpio56", "gpio57"; |
2088 | function = "qup14"; | |
2089 | drive-strength = <2>; | |
2090 | bias-disable; | |
2091 | }; | |
2092 | ||
e227fa29 | 2093 | qup_i2c15_default: qup-i2c15-default-state { |
98374e69 KD |
2094 | pins = "gpio60", "gpio61"; |
2095 | function = "qup15"; | |
2096 | drive-strength = <2>; | |
2097 | bias-disable; | |
2098 | }; | |
2099 | ||
e227fa29 | 2100 | qup_i2c16_default: qup-i2c16-default-state { |
98374e69 KD |
2101 | pins = "gpio64", "gpio65"; |
2102 | function = "qup16"; | |
2103 | drive-strength = <2>; | |
2104 | bias-disable; | |
2105 | }; | |
2106 | ||
e227fa29 | 2107 | qup_i2c17_default: qup-i2c17-default-state { |
98374e69 KD |
2108 | pins = "gpio72", "gpio73"; |
2109 | function = "qup17"; | |
2110 | drive-strength = <2>; | |
2111 | bias-disable; | |
2112 | }; | |
2113 | ||
e227fa29 | 2114 | qup_i2c19_default: qup-i2c19-default-state { |
98374e69 KD |
2115 | pins = "gpio76", "gpio77"; |
2116 | function = "qup19"; | |
2117 | drive-strength = <2>; | |
2118 | bias-disable; | |
2119 | }; | |
b7e8f433 VK |
2120 | }; |
2121 | ||
24e3eb2e RF |
2122 | rng: rng@10d3000 { |
2123 | compatible = "qcom,prng-ee"; | |
2124 | reg = <0 0x010d3000 0 0x1000>; | |
2125 | clocks = <&rpmhcc RPMH_HWKM_CLK>; | |
2126 | clock-names = "core"; | |
2127 | }; | |
2128 | ||
b7e8f433 VK |
2129 | intc: interrupt-controller@17a00000 { |
2130 | compatible = "arm,gic-v3"; | |
2131 | #interrupt-cells = <3>; | |
2132 | interrupt-controller; | |
f4d4ca9f KD |
2133 | #redistributor-regions = <1>; |
2134 | redistributor-stride = <0 0x20000>; | |
b7e8f433 VK |
2135 | reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ |
2136 | <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ | |
2137 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
2138 | }; | |
2139 | ||
2140 | timer@17c20000 { | |
2141 | compatible = "arm,armv7-timer-mem"; | |
458ebdbb DH |
2142 | #address-cells = <1>; |
2143 | #size-cells = <1>; | |
2144 | ranges = <0 0 0 0x20000000>; | |
b7e8f433 VK |
2145 | reg = <0x0 0x17c20000 0x0 0x1000>; |
2146 | clock-frequency = <19200000>; | |
2147 | ||
2148 | frame@17c21000 { | |
2149 | frame-number = <0>; | |
2150 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
2151 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
458ebdbb DH |
2152 | reg = <0x17c21000 0x1000>, |
2153 | <0x17c22000 0x1000>; | |
b7e8f433 VK |
2154 | }; |
2155 | ||
2156 | frame@17c23000 { | |
2157 | frame-number = <1>; | |
2158 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
458ebdbb | 2159 | reg = <0x17c23000 0x1000>; |
b7e8f433 VK |
2160 | status = "disabled"; |
2161 | }; | |
2162 | ||
2163 | frame@17c25000 { | |
2164 | frame-number = <2>; | |
2165 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
458ebdbb | 2166 | reg = <0x17c25000 0x1000>; |
b7e8f433 VK |
2167 | status = "disabled"; |
2168 | }; | |
2169 | ||
2170 | frame@17c27000 { | |
2171 | frame-number = <3>; | |
2172 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
458ebdbb | 2173 | reg = <0x17c27000 0x1000>; |
b7e8f433 VK |
2174 | status = "disabled"; |
2175 | }; | |
2176 | ||
2177 | frame@17c29000 { | |
2178 | frame-number = <4>; | |
2179 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
458ebdbb | 2180 | reg = <0x17c29000 0x1000>; |
b7e8f433 VK |
2181 | status = "disabled"; |
2182 | }; | |
2183 | ||
2184 | frame@17c2b000 { | |
2185 | frame-number = <5>; | |
2186 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
458ebdbb | 2187 | reg = <0x17c2b000 0x1000>; |
b7e8f433 VK |
2188 | status = "disabled"; |
2189 | }; | |
2190 | ||
2191 | frame@17c2d000 { | |
2192 | frame-number = <6>; | |
2193 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
458ebdbb | 2194 | reg = <0x17c2d000 0x1000>; |
b7e8f433 VK |
2195 | status = "disabled"; |
2196 | }; | |
2197 | }; | |
2198 | ||
2199 | apps_rsc: rsc@18200000 { | |
2200 | label = "apps_rsc"; | |
2201 | compatible = "qcom,rpmh-rsc"; | |
2202 | reg = <0x0 0x18200000 0x0 0x10000>, | |
2203 | <0x0 0x18210000 0x0 0x10000>, | |
2204 | <0x0 0x18220000 0x0 0x10000>; | |
2205 | reg-names = "drv-0", "drv-1", "drv-2"; | |
2206 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
2207 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
2208 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
2209 | qcom,tcs-offset = <0xd00>; | |
2210 | qcom,drv-id = <2>; | |
2211 | qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, | |
a131255e | 2212 | <WAKE_TCS 3>, <CONTROL_TCS 0>; |
2ffa0ca4 | 2213 | power-domains = <&CLUSTER_PD>; |
b7e8f433 VK |
2214 | |
2215 | rpmhcc: clock-controller { | |
2216 | compatible = "qcom,sm8350-rpmh-clk"; | |
2217 | #clock-cells = <1>; | |
2218 | clock-names = "xo"; | |
2219 | clocks = <&xo_board>; | |
2220 | }; | |
2221 | ||
90f57509 VK |
2222 | rpmhpd: power-controller { |
2223 | compatible = "qcom,sm8350-rpmhpd"; | |
2224 | #power-domain-cells = <1>; | |
2225 | operating-points-v2 = <&rpmhpd_opp_table>; | |
2226 | ||
2227 | rpmhpd_opp_table: opp-table { | |
2228 | compatible = "operating-points-v2"; | |
2229 | ||
2230 | rpmhpd_opp_ret: opp1 { | |
2231 | opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; | |
2232 | }; | |
2233 | ||
2234 | rpmhpd_opp_min_svs: opp2 { | |
2235 | opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; | |
2236 | }; | |
2237 | ||
2238 | rpmhpd_opp_low_svs: opp3 { | |
2239 | opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; | |
2240 | }; | |
2241 | ||
2242 | rpmhpd_opp_svs: opp4 { | |
2243 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; | |
2244 | }; | |
2245 | ||
2246 | rpmhpd_opp_svs_l1: opp5 { | |
2247 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; | |
2248 | }; | |
2249 | ||
2250 | rpmhpd_opp_nom: opp6 { | |
2251 | opp-level = <RPMH_REGULATOR_LEVEL_NOM>; | |
2252 | }; | |
2253 | ||
2254 | rpmhpd_opp_nom_l1: opp7 { | |
2255 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; | |
2256 | }; | |
2257 | ||
2258 | rpmhpd_opp_nom_l2: opp8 { | |
2259 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; | |
2260 | }; | |
2261 | ||
2262 | rpmhpd_opp_turbo: opp9 { | |
2263 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; | |
2264 | }; | |
2265 | ||
2266 | rpmhpd_opp_turbo_l1: opp10 { | |
2267 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; | |
2268 | }; | |
2269 | }; | |
2270 | }; | |
da6b2482 | 2271 | |
fc0e7dd6 | 2272 | apps_bcm_voter: bcm-voter { |
da6b2482 VK |
2273 | compatible = "qcom,bcm-voter"; |
2274 | }; | |
b7e8f433 | 2275 | }; |
e780fb31 | 2276 | |
ccbb3abb VK |
2277 | cpufreq_hw: cpufreq@18591000 { |
2278 | compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; | |
2279 | reg = <0 0x18591000 0 0x1000>, | |
2280 | <0 0x18592000 0 0x1000>, | |
2281 | <0 0x18593000 0 0x1000>; | |
2282 | reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; | |
2283 | ||
2284 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; | |
2285 | clock-names = "xo", "alternate"; | |
2286 | ||
2287 | #freq-domain-cells = <1>; | |
2288 | }; | |
2289 | ||
59c7cf81 VK |
2290 | ufs_mem_hc: ufshc@1d84000 { |
2291 | compatible = "qcom,sm8350-ufshc", "qcom,ufshc", | |
2292 | "jedec,ufs-2.0"; | |
2293 | reg = <0 0x01d84000 0 0x3000>; | |
2294 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; | |
2295 | phys = <&ufs_mem_phy_lanes>; | |
2296 | phy-names = "ufsphy"; | |
2297 | lanes-per-direction = <2>; | |
2298 | #reset-cells = <1>; | |
6d91e201 | 2299 | resets = <&gcc GCC_UFS_PHY_BCR>; |
59c7cf81 VK |
2300 | reset-names = "rst"; |
2301 | ||
6d91e201 | 2302 | power-domains = <&gcc UFS_PHY_GDSC>; |
59c7cf81 VK |
2303 | |
2304 | iommus = <&apps_smmu 0xe0 0x0>; | |
2305 | ||
2306 | clock-names = | |
59c7cf81 VK |
2307 | "core_clk", |
2308 | "bus_aggr_clk", | |
2309 | "iface_clk", | |
2310 | "core_clk_unipro", | |
2311 | "ref_clk", | |
2312 | "tx_lane0_sync_clk", | |
2313 | "rx_lane0_sync_clk", | |
2314 | "rx_lane1_sync_clk"; | |
2315 | clocks = | |
6d91e201 VK |
2316 | <&gcc GCC_UFS_PHY_AXI_CLK>, |
2317 | <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
2318 | <&gcc GCC_UFS_PHY_AHB_CLK>, | |
2319 | <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, | |
59c7cf81 | 2320 | <&rpmhcc RPMH_CXO_CLK>, |
6d91e201 VK |
2321 | <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
2322 | <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, | |
2323 | <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; | |
59c7cf81 | 2324 | freq-table-hz = |
59c7cf81 VK |
2325 | <75000000 300000000>, |
2326 | <0 0>, | |
2327 | <0 0>, | |
2328 | <75000000 300000000>, | |
2329 | <0 0>, | |
2330 | <0 0>, | |
0fd4dcb6 BA |
2331 | <0 0>, |
2332 | <0 0>; | |
59c7cf81 VK |
2333 | status = "disabled"; |
2334 | }; | |
2335 | ||
2336 | ufs_mem_phy: phy@1d87000 { | |
2337 | compatible = "qcom,sm8350-qmp-ufs-phy"; | |
40e95419 | 2338 | reg = <0 0x01d87000 0 0x1c4>; |
59c7cf81 VK |
2339 | #address-cells = <2>; |
2340 | #size-cells = <2>; | |
59c7cf81 VK |
2341 | ranges; |
2342 | clock-names = "ref", | |
2343 | "ref_aux"; | |
2344 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
6d91e201 | 2345 | <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
59c7cf81 VK |
2346 | |
2347 | resets = <&ufs_mem_hc 0>; | |
2348 | reset-names = "ufsphy"; | |
2349 | status = "disabled"; | |
2350 | ||
1351512f | 2351 | ufs_mem_phy_lanes: phy@1d87400 { |
b3c7839b JH |
2352 | reg = <0 0x01d87400 0 0x188>, |
2353 | <0 0x01d87600 0 0x200>, | |
2354 | <0 0x01d87c00 0 0x200>, | |
2355 | <0 0x01d87800 0 0x188>, | |
2356 | <0 0x01d87a00 0 0x200>; | |
86543bc6 | 2357 | #clock-cells = <1>; |
59c7cf81 | 2358 | #phy-cells = <0>; |
59c7cf81 VK |
2359 | }; |
2360 | }; | |
2361 | ||
177fcf0a VK |
2362 | slpi: remoteproc@5c00000 { |
2363 | compatible = "qcom,sm8350-slpi-pas"; | |
2364 | reg = <0 0x05c00000 0 0x4000>; | |
2365 | ||
2366 | interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, | |
2367 | <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, | |
2368 | <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, | |
2369 | <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, | |
2370 | <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; | |
2371 | interrupt-names = "wdog", "fatal", "ready", | |
2372 | "handover", "stop-ack"; | |
2373 | ||
2374 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
2375 | clock-names = "xo"; | |
2376 | ||
d0e285c3 RF |
2377 | power-domains = <&rpmhpd SM8350_LCX>, |
2378 | <&rpmhpd SM8350_LMX>; | |
6b7cb2d2 | 2379 | power-domain-names = "lcx", "lmx"; |
177fcf0a VK |
2380 | |
2381 | memory-region = <&pil_slpi_mem>; | |
2382 | ||
6b7cb2d2 SS |
2383 | qcom,qmp = <&aoss_qmp>; |
2384 | ||
177fcf0a VK |
2385 | qcom,smem-states = <&smp2p_slpi_out 0>; |
2386 | qcom,smem-state-names = "stop"; | |
2387 | ||
2388 | status = "disabled"; | |
2389 | ||
2390 | glink-edge { | |
2391 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
2392 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
2393 | IRQ_TYPE_EDGE_RISING>; | |
2394 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
2395 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
2396 | ||
2397 | label = "slpi"; | |
2398 | qcom,remote-pid = <3>; | |
2399 | ||
178056a4 OJ |
2400 | fastrpc { |
2401 | compatible = "qcom,fastrpc"; | |
2402 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
2403 | label = "sdsp"; | |
8c8ce95b | 2404 | qcom,non-secure-domain; |
178056a4 OJ |
2405 | #address-cells = <1>; |
2406 | #size-cells = <0>; | |
2407 | ||
2408 | compute-cb@1 { | |
2409 | compatible = "qcom,fastrpc-compute-cb"; | |
2410 | reg = <1>; | |
2411 | iommus = <&apps_smmu 0x0541 0x0>; | |
2412 | }; | |
2413 | ||
2414 | compute-cb@2 { | |
2415 | compatible = "qcom,fastrpc-compute-cb"; | |
2416 | reg = <2>; | |
2417 | iommus = <&apps_smmu 0x0542 0x0>; | |
2418 | }; | |
2419 | ||
2420 | compute-cb@3 { | |
2421 | compatible = "qcom,fastrpc-compute-cb"; | |
2422 | reg = <3>; | |
2423 | iommus = <&apps_smmu 0x0543 0x0>; | |
2424 | /* note: shared-cb = <4> in downstream */ | |
2425 | }; | |
2426 | }; | |
177fcf0a VK |
2427 | }; |
2428 | }; | |
2429 | ||
2430 | cdsp: remoteproc@98900000 { | |
2431 | compatible = "qcom,sm8350-cdsp-pas"; | |
22dbcfd6 | 2432 | reg = <0 0x98900000 0 0x1400000>; |
177fcf0a VK |
2433 | |
2434 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, | |
2435 | <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
2436 | <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
2437 | <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
2438 | <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
2439 | interrupt-names = "wdog", "fatal", "ready", | |
2440 | "handover", "stop-ack"; | |
2441 | ||
2442 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
2443 | clock-names = "xo"; | |
2444 | ||
d0e285c3 RF |
2445 | power-domains = <&rpmhpd SM8350_CX>, |
2446 | <&rpmhpd SM8350_MXC>; | |
6b7cb2d2 | 2447 | power-domain-names = "cx", "mxc"; |
177fcf0a | 2448 | |
4f287e31 | 2449 | interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; |
da6b2482 | 2450 | |
177fcf0a VK |
2451 | memory-region = <&pil_cdsp_mem>; |
2452 | ||
6b7cb2d2 SS |
2453 | qcom,qmp = <&aoss_qmp>; |
2454 | ||
177fcf0a VK |
2455 | qcom,smem-states = <&smp2p_cdsp_out 0>; |
2456 | qcom,smem-state-names = "stop"; | |
2457 | ||
2458 | status = "disabled"; | |
2459 | ||
2460 | glink-edge { | |
2461 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
2462 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
2463 | IRQ_TYPE_EDGE_RISING>; | |
2464 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
2465 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
2466 | ||
2467 | label = "cdsp"; | |
2468 | qcom,remote-pid = <5>; | |
178056a4 OJ |
2469 | |
2470 | fastrpc { | |
2471 | compatible = "qcom,fastrpc"; | |
2472 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
2473 | label = "cdsp"; | |
8c8ce95b | 2474 | qcom,non-secure-domain; |
178056a4 OJ |
2475 | #address-cells = <1>; |
2476 | #size-cells = <0>; | |
2477 | ||
2478 | compute-cb@1 { | |
2479 | compatible = "qcom,fastrpc-compute-cb"; | |
2480 | reg = <1>; | |
2481 | iommus = <&apps_smmu 0x2161 0x0400>, | |
2482 | <&apps_smmu 0x1181 0x0420>; | |
2483 | }; | |
2484 | ||
2485 | compute-cb@2 { | |
2486 | compatible = "qcom,fastrpc-compute-cb"; | |
2487 | reg = <2>; | |
2488 | iommus = <&apps_smmu 0x2162 0x0400>, | |
2489 | <&apps_smmu 0x1182 0x0420>; | |
2490 | }; | |
2491 | ||
2492 | compute-cb@3 { | |
2493 | compatible = "qcom,fastrpc-compute-cb"; | |
2494 | reg = <3>; | |
2495 | iommus = <&apps_smmu 0x2163 0x0400>, | |
2496 | <&apps_smmu 0x1183 0x0420>; | |
2497 | }; | |
2498 | ||
2499 | compute-cb@4 { | |
2500 | compatible = "qcom,fastrpc-compute-cb"; | |
2501 | reg = <4>; | |
2502 | iommus = <&apps_smmu 0x2164 0x0400>, | |
2503 | <&apps_smmu 0x1184 0x0420>; | |
2504 | }; | |
2505 | ||
2506 | compute-cb@5 { | |
2507 | compatible = "qcom,fastrpc-compute-cb"; | |
2508 | reg = <5>; | |
2509 | iommus = <&apps_smmu 0x2165 0x0400>, | |
2510 | <&apps_smmu 0x1185 0x0420>; | |
2511 | }; | |
2512 | ||
2513 | compute-cb@6 { | |
2514 | compatible = "qcom,fastrpc-compute-cb"; | |
2515 | reg = <6>; | |
2516 | iommus = <&apps_smmu 0x2166 0x0400>, | |
2517 | <&apps_smmu 0x1186 0x0420>; | |
2518 | }; | |
2519 | ||
2520 | compute-cb@7 { | |
2521 | compatible = "qcom,fastrpc-compute-cb"; | |
2522 | reg = <7>; | |
2523 | iommus = <&apps_smmu 0x2167 0x0400>, | |
2524 | <&apps_smmu 0x1187 0x0420>; | |
2525 | }; | |
2526 | ||
2527 | compute-cb@8 { | |
2528 | compatible = "qcom,fastrpc-compute-cb"; | |
2529 | reg = <8>; | |
2530 | iommus = <&apps_smmu 0x2168 0x0400>, | |
2531 | <&apps_smmu 0x1188 0x0420>; | |
2532 | }; | |
2533 | ||
2534 | /* note: secure cb9 in downstream */ | |
2535 | }; | |
60477435 KD |
2536 | }; |
2537 | }; | |
2538 | ||
06a0676b | 2539 | sdhc_2: mmc@8804000 { |
60477435 KD |
2540 | compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; |
2541 | reg = <0 0x08804000 0 0x1000>; | |
2542 | ||
2543 | interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, | |
2544 | <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; | |
2545 | interrupt-names = "hc_irq", "pwr_irq"; | |
2546 | ||
2547 | clocks = <&gcc GCC_SDCC2_AHB_CLK>, | |
2548 | <&gcc GCC_SDCC2_APPS_CLK>, | |
2549 | <&rpmhcc RPMH_CXO_CLK>; | |
2550 | clock-names = "iface", "core", "xo"; | |
2551 | resets = <&gcc GCC_SDCC2_BCR>; | |
74b91a1b KK |
2552 | interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, |
2553 | <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; | |
60477435 KD |
2554 | interconnect-names = "sdhc-ddr","cpu-sdhc"; |
2555 | iommus = <&apps_smmu 0x4a0 0x0>; | |
2556 | power-domains = <&rpmhpd SM8350_CX>; | |
2557 | operating-points-v2 = <&sdhc2_opp_table>; | |
2558 | bus-width = <4>; | |
2559 | dma-coherent; | |
2560 | ||
2561 | status = "disabled"; | |
2562 | ||
2563 | sdhc2_opp_table: opp-table { | |
2564 | compatible = "operating-points-v2"; | |
2565 | ||
2566 | opp-100000000 { | |
2567 | opp-hz = /bits/ 64 <100000000>; | |
2568 | required-opps = <&rpmhpd_opp_low_svs>; | |
2569 | }; | |
2570 | ||
2571 | opp-202000000 { | |
2572 | opp-hz = /bits/ 64 <202000000>; | |
2573 | required-opps = <&rpmhpd_opp_svs_l1>; | |
2574 | }; | |
177fcf0a VK |
2575 | }; |
2576 | }; | |
2577 | ||
e780fb31 JP |
2578 | usb_1_hsphy: phy@88e3000 { |
2579 | compatible = "qcom,sm8350-usb-hs-phy", | |
2580 | "qcom,usb-snps-hs-7nm-phy"; | |
2581 | reg = <0 0x088e3000 0 0x400>; | |
2582 | status = "disabled"; | |
2583 | #phy-cells = <0>; | |
2584 | ||
2585 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
2586 | clock-names = "ref"; | |
2587 | ||
6d91e201 | 2588 | resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
e780fb31 JP |
2589 | }; |
2590 | ||
2591 | usb_2_hsphy: phy@88e4000 { | |
2592 | compatible = "qcom,sm8250-usb-hs-phy", | |
2593 | "qcom,usb-snps-hs-7nm-phy"; | |
2594 | reg = <0 0x088e4000 0 0x400>; | |
2595 | status = "disabled"; | |
2596 | #phy-cells = <0>; | |
2597 | ||
2598 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
2599 | clock-names = "ref"; | |
2600 | ||
6d91e201 | 2601 | resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
e780fb31 JP |
2602 | }; |
2603 | ||
2604 | usb_1_qmpphy: phy-wrapper@88e9000 { | |
2605 | compatible = "qcom,sm8350-qmp-usb3-phy"; | |
2606 | reg = <0 0x088e9000 0 0x200>, | |
2607 | <0 0x088e8000 0 0x20>; | |
e780fb31 | 2608 | status = "disabled"; |
e780fb31 JP |
2609 | #address-cells = <2>; |
2610 | #size-cells = <2>; | |
2611 | ranges; | |
2612 | ||
6d91e201 | 2613 | clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
e780fb31 | 2614 | <&rpmhcc RPMH_CXO_CLK>, |
6d91e201 | 2615 | <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
e780fb31 JP |
2616 | clock-names = "aux", "ref_clk_src", "com_aux"; |
2617 | ||
6d91e201 VK |
2618 | resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
2619 | <&gcc GCC_USB3_PHY_PRIM_BCR>; | |
e780fb31 JP |
2620 | reset-names = "phy", "common"; |
2621 | ||
2622 | usb_1_ssphy: phy@88e9200 { | |
2623 | reg = <0 0x088e9200 0 0x200>, | |
2624 | <0 0x088e9400 0 0x200>, | |
2625 | <0 0x088e9c00 0 0x400>, | |
2626 | <0 0x088e9600 0 0x200>, | |
2627 | <0 0x088e9800 0 0x200>, | |
2628 | <0 0x088e9a00 0 0x100>; | |
2629 | #phy-cells = <0>; | |
af551554 | 2630 | #clock-cells = <0>; |
6d91e201 | 2631 | clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
e780fb31 JP |
2632 | clock-names = "pipe0"; |
2633 | clock-output-names = "usb3_phy_pipe_clk_src"; | |
2634 | }; | |
2635 | }; | |
2636 | ||
2637 | usb_2_qmpphy: phy-wrapper@88eb000 { | |
2638 | compatible = "qcom,sm8350-qmp-usb3-uni-phy"; | |
2639 | reg = <0 0x088eb000 0 0x200>; | |
2640 | status = "disabled"; | |
e780fb31 JP |
2641 | #address-cells = <2>; |
2642 | #size-cells = <2>; | |
2643 | ranges; | |
2644 | ||
6d91e201 | 2645 | clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
e780fb31 | 2646 | <&rpmhcc RPMH_CXO_CLK>, |
6d91e201 VK |
2647 | <&gcc GCC_USB3_SEC_CLKREF_EN>, |
2648 | <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; | |
e780fb31 JP |
2649 | clock-names = "aux", "ref_clk_src", "ref", "com_aux"; |
2650 | ||
6d91e201 VK |
2651 | resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
2652 | <&gcc GCC_USB3_PHY_SEC_BCR>; | |
e780fb31 JP |
2653 | reset-names = "phy", "common"; |
2654 | ||
2655 | usb_2_ssphy: phy@88ebe00 { | |
2656 | reg = <0 0x088ebe00 0 0x200>, | |
2657 | <0 0x088ec000 0 0x200>, | |
2658 | <0 0x088eb200 0 0x1100>; | |
2659 | #phy-cells = <0>; | |
af551554 | 2660 | #clock-cells = <0>; |
6d91e201 | 2661 | clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
e780fb31 JP |
2662 | clock-names = "pipe0"; |
2663 | clock-output-names = "usb3_uni_phy_pipe_clk_src"; | |
2664 | }; | |
2665 | }; | |
2666 | ||
1dee9e3b | 2667 | dc_noc: interconnect@90c0000 { |
da6b2482 VK |
2668 | compatible = "qcom,sm8350-dc-noc"; |
2669 | reg = <0 0x090c0000 0 0x4200>; | |
4f287e31 | 2670 | #interconnect-cells = <2>; |
da6b2482 VK |
2671 | qcom,bcm-voters = <&apps_bcm_voter>; |
2672 | }; | |
2673 | ||
2674 | gem_noc: interconnect@9100000 { | |
2675 | compatible = "qcom,sm8350-gem-noc"; | |
2676 | reg = <0 0x09100000 0 0xb4000>; | |
4f287e31 | 2677 | #interconnect-cells = <2>; |
da6b2482 VK |
2678 | qcom,bcm-voters = <&apps_bcm_voter>; |
2679 | }; | |
2680 | ||
9ac8999e KD |
2681 | system-cache-controller@9200000 { |
2682 | compatible = "qcom,sm8350-llcc"; | |
2683 | reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; | |
2684 | reg-names = "llcc_base", "llcc_broadcast_base"; | |
2685 | }; | |
2686 | ||
e780fb31 JP |
2687 | usb_1: usb@a6f8800 { |
2688 | compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; | |
2689 | reg = <0 0x0a6f8800 0 0x400>; | |
2690 | status = "disabled"; | |
2691 | #address-cells = <2>; | |
2692 | #size-cells = <2>; | |
2693 | ranges; | |
2694 | ||
6d91e201 VK |
2695 | clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
2696 | <&gcc GCC_USB30_PRIM_MASTER_CLK>, | |
2697 | <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, | |
8d5fd4e4 KK |
2698 | <&gcc GCC_USB30_PRIM_SLEEP_CLK>, |
2699 | <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; | |
2700 | clock-names = "cfg_noc", | |
2701 | "core", | |
2702 | "iface", | |
2703 | "sleep", | |
2704 | "mock_utmi"; | |
e780fb31 | 2705 | |
6d91e201 VK |
2706 | assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
2707 | <&gcc GCC_USB30_PRIM_MASTER_CLK>; | |
e780fb31 JP |
2708 | assigned-clock-rates = <19200000>, <200000000>; |
2709 | ||
2710 | interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
5b7e3499 | 2711 | <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, |
e780fb31 | 2712 | <&pdc 15 IRQ_TYPE_EDGE_BOTH>, |
5b7e3499 JH |
2713 | <&pdc 14 IRQ_TYPE_EDGE_BOTH>; |
2714 | interrupt-names = "hs_phy_irq", | |
2715 | "ss_phy_irq", | |
2716 | "dm_hs_phy_irq", | |
2717 | "dp_hs_phy_irq"; | |
e780fb31 | 2718 | |
6d91e201 | 2719 | power-domains = <&gcc USB30_PRIM_GDSC>; |
e780fb31 | 2720 | |
6d91e201 | 2721 | resets = <&gcc GCC_USB30_PRIM_BCR>; |
e780fb31 | 2722 | |
2aa2b50d | 2723 | usb_1_dwc3: usb@a600000 { |
e780fb31 JP |
2724 | compatible = "snps,dwc3"; |
2725 | reg = <0 0x0a600000 0 0xcd00>; | |
2726 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
2727 | iommus = <&apps_smmu 0x0 0x0>; | |
2728 | snps,dis_u2_susphy_quirk; | |
2729 | snps,dis_enblslpm_quirk; | |
2730 | phys = <&usb_1_hsphy>, <&usb_1_ssphy>; | |
2731 | phy-names = "usb2-phy", "usb3-phy"; | |
2732 | }; | |
2733 | }; | |
2734 | ||
2735 | usb_2: usb@a8f8800 { | |
2736 | compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; | |
2737 | reg = <0 0x0a8f8800 0 0x400>; | |
2738 | status = "disabled"; | |
2739 | #address-cells = <2>; | |
2740 | #size-cells = <2>; | |
2741 | ranges; | |
2742 | ||
6d91e201 VK |
2743 | clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
2744 | <&gcc GCC_USB30_SEC_MASTER_CLK>, | |
2745 | <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, | |
6d91e201 | 2746 | <&gcc GCC_USB30_SEC_SLEEP_CLK>, |
8d5fd4e4 | 2747 | <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
6d91e201 | 2748 | <&gcc GCC_USB3_SEC_CLKREF_EN>; |
8d5fd4e4 KK |
2749 | clock-names = "cfg_noc", |
2750 | "core", | |
2751 | "iface", | |
2752 | "sleep", | |
2753 | "mock_utmi", | |
2754 | "xo"; | |
e780fb31 | 2755 | |
6d91e201 VK |
2756 | assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
2757 | <&gcc GCC_USB30_SEC_MASTER_CLK>; | |
e780fb31 JP |
2758 | assigned-clock-rates = <19200000>, <200000000>; |
2759 | ||
2760 | interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
5b7e3499 | 2761 | <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, |
e780fb31 | 2762 | <&pdc 13 IRQ_TYPE_EDGE_BOTH>, |
5b7e3499 JH |
2763 | <&pdc 12 IRQ_TYPE_EDGE_BOTH>; |
2764 | interrupt-names = "hs_phy_irq", | |
2765 | "ss_phy_irq", | |
2766 | "dm_hs_phy_irq", | |
2767 | "dp_hs_phy_irq"; | |
e780fb31 | 2768 | |
6d91e201 | 2769 | power-domains = <&gcc USB30_SEC_GDSC>; |
e780fb31 | 2770 | |
6d91e201 | 2771 | resets = <&gcc GCC_USB30_SEC_BCR>; |
e780fb31 | 2772 | |
2aa2b50d | 2773 | usb_2_dwc3: usb@a800000 { |
e780fb31 JP |
2774 | compatible = "snps,dwc3"; |
2775 | reg = <0 0x0a800000 0 0xcd00>; | |
2776 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
2777 | iommus = <&apps_smmu 0x20 0x0>; | |
2778 | snps,dis_u2_susphy_quirk; | |
2779 | snps,dis_enblslpm_quirk; | |
2780 | phys = <&usb_2_hsphy>, <&usb_2_ssphy>; | |
2781 | phy-names = "usb2-phy", "usb3-phy"; | |
2782 | }; | |
2783 | }; | |
177fcf0a | 2784 | |
d4a44105 RF |
2785 | mdss: display-subsystem@ae00000 { |
2786 | compatible = "qcom,sm8350-mdss"; | |
2787 | reg = <0 0x0ae00000 0 0x1000>; | |
2788 | reg-names = "mdss"; | |
2789 | ||
2790 | interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, | |
2791 | <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; | |
2792 | interconnect-names = "mdp0-mem", "mdp1-mem"; | |
2793 | ||
2794 | power-domains = <&dispcc MDSS_GDSC>; | |
2795 | resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; | |
2796 | ||
2797 | clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
2798 | <&gcc GCC_DISP_HF_AXI_CLK>, | |
2799 | <&gcc GCC_DISP_SF_AXI_CLK>, | |
2800 | <&dispcc DISP_CC_MDSS_MDP_CLK>; | |
2801 | clock-names = "iface", "bus", "nrt_bus", "core"; | |
2802 | ||
2803 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
2804 | interrupt-controller; | |
2805 | #interrupt-cells = <1>; | |
2806 | ||
2807 | iommus = <&apps_smmu 0x820 0x402>; | |
2808 | ||
2809 | status = "disabled"; | |
2810 | ||
2811 | #address-cells = <2>; | |
2812 | #size-cells = <2>; | |
2813 | ranges; | |
2814 | ||
2815 | dpu_opp_table: opp-table { | |
2816 | compatible = "operating-points-v2"; | |
2817 | ||
2818 | /* TODO: opp-200000000 should work with | |
2819 | * &rpmhpd_opp_low_svs, but one some of | |
2820 | * sm8350_hdk boards reboot using this | |
2821 | * opp. | |
2822 | */ | |
2823 | opp-200000000 { | |
2824 | opp-hz = /bits/ 64 <200000000>; | |
2825 | required-opps = <&rpmhpd_opp_svs>; | |
2826 | }; | |
2827 | ||
2828 | opp-300000000 { | |
2829 | opp-hz = /bits/ 64 <300000000>; | |
2830 | required-opps = <&rpmhpd_opp_svs>; | |
2831 | }; | |
2832 | ||
2833 | opp-345000000 { | |
2834 | opp-hz = /bits/ 64 <345000000>; | |
2835 | required-opps = <&rpmhpd_opp_svs_l1>; | |
2836 | }; | |
2837 | ||
2838 | opp-460000000 { | |
2839 | opp-hz = /bits/ 64 <460000000>; | |
2840 | required-opps = <&rpmhpd_opp_nom>; | |
2841 | }; | |
2842 | }; | |
2843 | ||
2844 | mdss_mdp: display-controller@ae01000 { | |
2845 | compatible = "qcom,sm8350-dpu"; | |
2846 | reg = <0 0x0ae01000 0 0x8f000>, | |
2847 | <0 0x0aeb0000 0 0x2008>; | |
2848 | reg-names = "mdp", "vbif"; | |
2849 | ||
2850 | clocks = <&gcc GCC_DISP_HF_AXI_CLK>, | |
2851 | <&gcc GCC_DISP_SF_AXI_CLK>, | |
2852 | <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
2853 | <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, | |
2854 | <&dispcc DISP_CC_MDSS_MDP_CLK>, | |
2855 | <&dispcc DISP_CC_MDSS_VSYNC_CLK>; | |
2856 | clock-names = "bus", | |
2857 | "nrt_bus", | |
2858 | "iface", | |
2859 | "lut", | |
2860 | "core", | |
2861 | "vsync"; | |
2862 | ||
2863 | assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; | |
2864 | assigned-clock-rates = <19200000>; | |
2865 | ||
2866 | operating-points-v2 = <&dpu_opp_table>; | |
2867 | power-domains = <&rpmhpd SM8350_MMCX>; | |
2868 | ||
2869 | interrupt-parent = <&mdss>; | |
2870 | interrupts = <0>; | |
2871 | ||
2872 | ports { | |
2873 | #address-cells = <1>; | |
2874 | #size-cells = <0>; | |
2875 | ||
2876 | port@0 { | |
2877 | reg = <0>; | |
2878 | dpu_intf1_out: endpoint { | |
2879 | remote-endpoint = <&dsi0_in>; | |
2880 | }; | |
2881 | }; | |
2882 | }; | |
2883 | }; | |
2884 | ||
2885 | mdss_dsi0: dsi@ae94000 { | |
2886 | compatible = "qcom,mdss-dsi-ctrl"; | |
2887 | reg = <0 0x0ae94000 0 0x400>; | |
2888 | reg-names = "dsi_ctrl"; | |
2889 | ||
2890 | interrupt-parent = <&mdss>; | |
2891 | interrupts = <4>; | |
2892 | ||
2893 | clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, | |
2894 | <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, | |
2895 | <&dispcc DISP_CC_MDSS_PCLK0_CLK>, | |
2896 | <&dispcc DISP_CC_MDSS_ESC0_CLK>, | |
2897 | <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
2898 | <&gcc GCC_DISP_HF_AXI_CLK>; | |
2899 | clock-names = "byte", | |
2900 | "byte_intf", | |
2901 | "pixel", | |
2902 | "core", | |
2903 | "iface", | |
2904 | "bus"; | |
2905 | ||
2906 | assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, | |
2907 | <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; | |
2908 | assigned-clock-parents = <&mdss_dsi0_phy 0>, | |
2909 | <&mdss_dsi0_phy 1>; | |
2910 | ||
2911 | operating-points-v2 = <&dsi0_opp_table>; | |
2912 | power-domains = <&rpmhpd SM8350_MMCX>; | |
2913 | ||
2914 | phys = <&mdss_dsi0_phy>; | |
2915 | ||
2916 | status = "disabled"; | |
2917 | ||
2918 | dsi0_opp_table: opp-table { | |
2919 | compatible = "operating-points-v2"; | |
2920 | ||
2921 | /* TODO: opp-187500000 should work with | |
2922 | * &rpmhpd_opp_low_svs, but one some of | |
2923 | * sm8350_hdk boards reboot using this | |
2924 | * opp. | |
2925 | */ | |
2926 | opp-187500000 { | |
2927 | opp-hz = /bits/ 64 <187500000>; | |
2928 | required-opps = <&rpmhpd_opp_svs>; | |
2929 | }; | |
2930 | ||
2931 | opp-300000000 { | |
2932 | opp-hz = /bits/ 64 <300000000>; | |
2933 | required-opps = <&rpmhpd_opp_svs>; | |
2934 | }; | |
2935 | ||
2936 | opp-358000000 { | |
2937 | opp-hz = /bits/ 64 <358000000>; | |
2938 | required-opps = <&rpmhpd_opp_svs_l1>; | |
2939 | }; | |
2940 | }; | |
2941 | ||
2942 | ports { | |
2943 | #address-cells = <1>; | |
2944 | #size-cells = <0>; | |
2945 | ||
2946 | port@0 { | |
2947 | reg = <0>; | |
2948 | dsi0_in: endpoint { | |
2949 | remote-endpoint = <&dpu_intf1_out>; | |
2950 | }; | |
2951 | }; | |
2952 | ||
2953 | port@1 { | |
2954 | reg = <1>; | |
2955 | dsi0_out: endpoint { | |
2956 | }; | |
2957 | }; | |
2958 | }; | |
2959 | }; | |
2960 | ||
2961 | mdss_dsi0_phy: phy@ae94400 { | |
2962 | compatible = "qcom,dsi-phy-5nm-8350"; | |
2963 | reg = <0 0x0ae94400 0 0x200>, | |
2964 | <0 0x0ae94600 0 0x280>, | |
2965 | <0 0x0ae94900 0 0x260>; | |
2966 | reg-names = "dsi_phy", | |
2967 | "dsi_phy_lane", | |
2968 | "dsi_pll"; | |
2969 | ||
2970 | #clock-cells = <1>; | |
2971 | #phy-cells = <0>; | |
2972 | ||
2973 | clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
2974 | <&rpmhcc RPMH_CXO_CLK>; | |
2975 | clock-names = "iface", "ref"; | |
2976 | ||
2977 | status = "disabled"; | |
2978 | }; | |
2979 | ||
2980 | mdss_dsi1: dsi@ae96000 { | |
2981 | compatible = "qcom,mdss-dsi-ctrl"; | |
2982 | reg = <0 0x0ae96000 0 0x400>; | |
2983 | reg-names = "dsi_ctrl"; | |
2984 | ||
2985 | interrupt-parent = <&mdss>; | |
2986 | interrupts = <4>; | |
2987 | ||
2988 | clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, | |
2989 | <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, | |
2990 | <&dispcc DISP_CC_MDSS_PCLK1_CLK>, | |
2991 | <&dispcc DISP_CC_MDSS_ESC1_CLK>, | |
2992 | <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
2993 | <&gcc GCC_DISP_HF_AXI_CLK>; | |
2994 | clock-names = "byte", | |
2995 | "byte_intf", | |
2996 | "pixel", | |
2997 | "core", | |
2998 | "iface", | |
2999 | "bus"; | |
3000 | ||
3001 | assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, | |
3002 | <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; | |
3003 | assigned-clock-parents = <&mdss_dsi1_phy 0>, | |
3004 | <&mdss_dsi1_phy 1>; | |
3005 | ||
3006 | operating-points-v2 = <&dsi1_opp_table>; | |
3007 | power-domains = <&rpmhpd SM8350_MMCX>; | |
3008 | ||
3009 | phys = <&mdss_dsi1_phy>; | |
3010 | ||
3011 | status = "disabled"; | |
3012 | ||
3013 | dsi1_opp_table: opp-table { | |
3014 | compatible = "operating-points-v2"; | |
3015 | ||
3016 | /* TODO: opp-187500000 should work with | |
3017 | * &rpmhpd_opp_low_svs, but one some of | |
3018 | * sm8350_hdk boards reboot using this | |
3019 | * opp. | |
3020 | */ | |
3021 | opp-187500000 { | |
3022 | opp-hz = /bits/ 64 <187500000>; | |
3023 | required-opps = <&rpmhpd_opp_svs>; | |
3024 | }; | |
3025 | ||
3026 | opp-300000000 { | |
3027 | opp-hz = /bits/ 64 <300000000>; | |
3028 | required-opps = <&rpmhpd_opp_svs>; | |
3029 | }; | |
3030 | ||
3031 | opp-358000000 { | |
3032 | opp-hz = /bits/ 64 <358000000>; | |
3033 | required-opps = <&rpmhpd_opp_svs_l1>; | |
3034 | }; | |
3035 | }; | |
3036 | ||
3037 | ports { | |
3038 | #address-cells = <1>; | |
3039 | #size-cells = <0>; | |
3040 | ||
3041 | port@0 { | |
3042 | reg = <0>; | |
3043 | dsi1_in: endpoint { | |
3044 | }; | |
3045 | }; | |
3046 | ||
3047 | port@1 { | |
3048 | reg = <1>; | |
3049 | dsi1_out: endpoint { | |
3050 | }; | |
3051 | }; | |
3052 | }; | |
3053 | }; | |
3054 | ||
3055 | mdss_dsi1_phy: phy@ae96400 { | |
3056 | compatible = "qcom,dsi-phy-5nm-8350"; | |
3057 | reg = <0 0x0ae96400 0 0x200>, | |
3058 | <0 0x0ae96600 0 0x280>, | |
3059 | <0 0x0ae96900 0 0x260>; | |
3060 | reg-names = "dsi_phy", | |
3061 | "dsi_phy_lane", | |
3062 | "dsi_pll"; | |
3063 | ||
3064 | #clock-cells = <1>; | |
3065 | #phy-cells = <0>; | |
3066 | ||
3067 | clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
3068 | <&rpmhcc RPMH_CXO_CLK>; | |
3069 | clock-names = "iface", "ref"; | |
3070 | ||
3071 | status = "disabled"; | |
3072 | }; | |
3073 | }; | |
3074 | ||
9fd4887c RF |
3075 | dispcc: clock-controller@af00000 { |
3076 | compatible = "qcom,sm8350-dispcc"; | |
3077 | reg = <0 0x0af00000 0 0x10000>; | |
3078 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
d4a44105 RF |
3079 | <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, |
3080 | <0>, <0>, | |
9fd4887c RF |
3081 | <0>, |
3082 | <0>; | |
3083 | clock-names = "bi_tcxo", | |
3084 | "dsi0_phy_pll_out_byteclk", | |
3085 | "dsi0_phy_pll_out_dsiclk", | |
3086 | "dsi1_phy_pll_out_byteclk", | |
3087 | "dsi1_phy_pll_out_dsiclk", | |
3088 | "dp_phy_pll_link_clk", | |
3089 | "dp_phy_pll_vco_div_clk"; | |
3090 | #clock-cells = <1>; | |
3091 | #reset-cells = <1>; | |
3092 | #power-domain-cells = <1>; | |
3093 | ||
3094 | power-domains = <&rpmhpd SM8350_MMCX>; | |
9fd4887c RF |
3095 | }; |
3096 | ||
177fcf0a VK |
3097 | adsp: remoteproc@17300000 { |
3098 | compatible = "qcom,sm8350-adsp-pas"; | |
3099 | reg = <0 0x17300000 0 0x100>; | |
3100 | ||
3101 | interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, | |
3102 | <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
3103 | <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
3104 | <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
3105 | <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
3106 | interrupt-names = "wdog", "fatal", "ready", | |
3107 | "handover", "stop-ack"; | |
3108 | ||
3109 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
3110 | clock-names = "xo"; | |
3111 | ||
d0e285c3 RF |
3112 | power-domains = <&rpmhpd SM8350_LCX>, |
3113 | <&rpmhpd SM8350_LMX>; | |
6b7cb2d2 | 3114 | power-domain-names = "lcx", "lmx"; |
177fcf0a VK |
3115 | |
3116 | memory-region = <&pil_adsp_mem>; | |
3117 | ||
6b7cb2d2 SS |
3118 | qcom,qmp = <&aoss_qmp>; |
3119 | ||
177fcf0a VK |
3120 | qcom,smem-states = <&smp2p_adsp_out 0>; |
3121 | qcom,smem-state-names = "stop"; | |
3122 | ||
3123 | status = "disabled"; | |
3124 | ||
3125 | glink-edge { | |
3126 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
3127 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
3128 | IRQ_TYPE_EDGE_RISING>; | |
3129 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
3130 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
3131 | ||
3132 | label = "lpass"; | |
3133 | qcom,remote-pid = <2>; | |
178056a4 OJ |
3134 | |
3135 | fastrpc { | |
3136 | compatible = "qcom,fastrpc"; | |
3137 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
3138 | label = "adsp"; | |
8c8ce95b | 3139 | qcom,non-secure-domain; |
178056a4 OJ |
3140 | #address-cells = <1>; |
3141 | #size-cells = <0>; | |
3142 | ||
3143 | compute-cb@3 { | |
3144 | compatible = "qcom,fastrpc-compute-cb"; | |
3145 | reg = <3>; | |
3146 | iommus = <&apps_smmu 0x1803 0x0>; | |
3147 | }; | |
3148 | ||
3149 | compute-cb@4 { | |
3150 | compatible = "qcom,fastrpc-compute-cb"; | |
3151 | reg = <4>; | |
3152 | iommus = <&apps_smmu 0x1804 0x0>; | |
3153 | }; | |
3154 | ||
3155 | compute-cb@5 { | |
3156 | compatible = "qcom,fastrpc-compute-cb"; | |
3157 | reg = <5>; | |
3158 | iommus = <&apps_smmu 0x1805 0x0>; | |
3159 | }; | |
3160 | }; | |
177fcf0a VK |
3161 | }; |
3162 | }; | |
b7e8f433 VK |
3163 | }; |
3164 | ||
4dcaa68e | 3165 | thermal_zones: thermal-zones { |
20f9d94e RF |
3166 | cpu0-thermal { |
3167 | polling-delay-passive = <250>; | |
3168 | polling-delay = <1000>; | |
3169 | ||
3170 | thermal-sensors = <&tsens0 1>; | |
3171 | ||
3172 | trips { | |
3173 | cpu0_alert0: trip-point0 { | |
3174 | temperature = <90000>; | |
3175 | hysteresis = <2000>; | |
3176 | type = "passive"; | |
3177 | }; | |
3178 | ||
3179 | cpu0_alert1: trip-point1 { | |
3180 | temperature = <95000>; | |
3181 | hysteresis = <2000>; | |
3182 | type = "passive"; | |
3183 | }; | |
3184 | ||
1364acc3 | 3185 | cpu0_crit: cpu-crit { |
20f9d94e RF |
3186 | temperature = <110000>; |
3187 | hysteresis = <1000>; | |
3188 | type = "critical"; | |
3189 | }; | |
3190 | }; | |
3191 | ||
3192 | cooling-maps { | |
3193 | map0 { | |
3194 | trip = <&cpu0_alert0>; | |
3195 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3196 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3197 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3198 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3199 | }; | |
3200 | map1 { | |
3201 | trip = <&cpu0_alert1>; | |
3202 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3203 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3204 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3205 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3206 | }; | |
3207 | }; | |
3208 | }; | |
3209 | ||
3210 | cpu1-thermal { | |
3211 | polling-delay-passive = <250>; | |
3212 | polling-delay = <1000>; | |
3213 | ||
3214 | thermal-sensors = <&tsens0 2>; | |
3215 | ||
3216 | trips { | |
3217 | cpu1_alert0: trip-point0 { | |
3218 | temperature = <90000>; | |
3219 | hysteresis = <2000>; | |
3220 | type = "passive"; | |
3221 | }; | |
3222 | ||
3223 | cpu1_alert1: trip-point1 { | |
3224 | temperature = <95000>; | |
3225 | hysteresis = <2000>; | |
3226 | type = "passive"; | |
3227 | }; | |
3228 | ||
1364acc3 | 3229 | cpu1_crit: cpu-crit { |
20f9d94e RF |
3230 | temperature = <110000>; |
3231 | hysteresis = <1000>; | |
3232 | type = "critical"; | |
3233 | }; | |
3234 | }; | |
3235 | ||
3236 | cooling-maps { | |
3237 | map0 { | |
3238 | trip = <&cpu1_alert0>; | |
3239 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3240 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3241 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3242 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3243 | }; | |
3244 | map1 { | |
3245 | trip = <&cpu1_alert1>; | |
3246 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3247 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3248 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3249 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3250 | }; | |
3251 | }; | |
3252 | }; | |
3253 | ||
3254 | cpu2-thermal { | |
3255 | polling-delay-passive = <250>; | |
3256 | polling-delay = <1000>; | |
3257 | ||
3258 | thermal-sensors = <&tsens0 3>; | |
3259 | ||
3260 | trips { | |
3261 | cpu2_alert0: trip-point0 { | |
3262 | temperature = <90000>; | |
3263 | hysteresis = <2000>; | |
3264 | type = "passive"; | |
3265 | }; | |
3266 | ||
3267 | cpu2_alert1: trip-point1 { | |
3268 | temperature = <95000>; | |
3269 | hysteresis = <2000>; | |
3270 | type = "passive"; | |
3271 | }; | |
3272 | ||
1364acc3 | 3273 | cpu2_crit: cpu-crit { |
20f9d94e RF |
3274 | temperature = <110000>; |
3275 | hysteresis = <1000>; | |
3276 | type = "critical"; | |
3277 | }; | |
3278 | }; | |
3279 | ||
3280 | cooling-maps { | |
3281 | map0 { | |
3282 | trip = <&cpu2_alert0>; | |
3283 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3284 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3285 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3286 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3287 | }; | |
3288 | map1 { | |
3289 | trip = <&cpu2_alert1>; | |
3290 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3291 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3292 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3293 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3294 | }; | |
3295 | }; | |
3296 | }; | |
3297 | ||
3298 | cpu3-thermal { | |
3299 | polling-delay-passive = <250>; | |
3300 | polling-delay = <1000>; | |
3301 | ||
3302 | thermal-sensors = <&tsens0 4>; | |
3303 | ||
3304 | trips { | |
3305 | cpu3_alert0: trip-point0 { | |
3306 | temperature = <90000>; | |
3307 | hysteresis = <2000>; | |
3308 | type = "passive"; | |
3309 | }; | |
3310 | ||
3311 | cpu3_alert1: trip-point1 { | |
3312 | temperature = <95000>; | |
3313 | hysteresis = <2000>; | |
3314 | type = "passive"; | |
3315 | }; | |
3316 | ||
1364acc3 | 3317 | cpu3_crit: cpu-crit { |
20f9d94e RF |
3318 | temperature = <110000>; |
3319 | hysteresis = <1000>; | |
3320 | type = "critical"; | |
3321 | }; | |
3322 | }; | |
3323 | ||
3324 | cooling-maps { | |
3325 | map0 { | |
3326 | trip = <&cpu3_alert0>; | |
3327 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3328 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3329 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3330 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3331 | }; | |
3332 | map1 { | |
3333 | trip = <&cpu3_alert1>; | |
3334 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3335 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3336 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3337 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3338 | }; | |
3339 | }; | |
3340 | }; | |
3341 | ||
3342 | cpu4-top-thermal { | |
3343 | polling-delay-passive = <250>; | |
3344 | polling-delay = <1000>; | |
3345 | ||
3346 | thermal-sensors = <&tsens0 7>; | |
3347 | ||
3348 | trips { | |
3349 | cpu4_top_alert0: trip-point0 { | |
3350 | temperature = <90000>; | |
3351 | hysteresis = <2000>; | |
3352 | type = "passive"; | |
3353 | }; | |
3354 | ||
3355 | cpu4_top_alert1: trip-point1 { | |
3356 | temperature = <95000>; | |
3357 | hysteresis = <2000>; | |
3358 | type = "passive"; | |
3359 | }; | |
3360 | ||
1364acc3 | 3361 | cpu4_top_crit: cpu-crit { |
20f9d94e RF |
3362 | temperature = <110000>; |
3363 | hysteresis = <1000>; | |
3364 | type = "critical"; | |
3365 | }; | |
3366 | }; | |
3367 | ||
3368 | cooling-maps { | |
3369 | map0 { | |
3370 | trip = <&cpu4_top_alert0>; | |
3371 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3372 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3373 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3374 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3375 | }; | |
3376 | map1 { | |
3377 | trip = <&cpu4_top_alert1>; | |
3378 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3379 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3380 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3381 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3382 | }; | |
3383 | }; | |
3384 | }; | |
3385 | ||
3386 | cpu5-top-thermal { | |
3387 | polling-delay-passive = <250>; | |
3388 | polling-delay = <1000>; | |
3389 | ||
3390 | thermal-sensors = <&tsens0 8>; | |
3391 | ||
3392 | trips { | |
3393 | cpu5_top_alert0: trip-point0 { | |
3394 | temperature = <90000>; | |
3395 | hysteresis = <2000>; | |
3396 | type = "passive"; | |
3397 | }; | |
3398 | ||
3399 | cpu5_top_alert1: trip-point1 { | |
3400 | temperature = <95000>; | |
3401 | hysteresis = <2000>; | |
3402 | type = "passive"; | |
3403 | }; | |
3404 | ||
1364acc3 | 3405 | cpu5_top_crit: cpu-crit { |
20f9d94e RF |
3406 | temperature = <110000>; |
3407 | hysteresis = <1000>; | |
3408 | type = "critical"; | |
3409 | }; | |
3410 | }; | |
3411 | ||
3412 | cooling-maps { | |
3413 | map0 { | |
3414 | trip = <&cpu5_top_alert0>; | |
3415 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3416 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3417 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3418 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3419 | }; | |
3420 | map1 { | |
3421 | trip = <&cpu5_top_alert1>; | |
3422 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3423 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3424 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3425 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3426 | }; | |
3427 | }; | |
3428 | }; | |
3429 | ||
3430 | cpu6-top-thermal { | |
3431 | polling-delay-passive = <250>; | |
3432 | polling-delay = <1000>; | |
3433 | ||
3434 | thermal-sensors = <&tsens0 9>; | |
3435 | ||
3436 | trips { | |
3437 | cpu6_top_alert0: trip-point0 { | |
3438 | temperature = <90000>; | |
3439 | hysteresis = <2000>; | |
3440 | type = "passive"; | |
3441 | }; | |
3442 | ||
3443 | cpu6_top_alert1: trip-point1 { | |
3444 | temperature = <95000>; | |
3445 | hysteresis = <2000>; | |
3446 | type = "passive"; | |
3447 | }; | |
3448 | ||
1364acc3 | 3449 | cpu6_top_crit: cpu-crit { |
20f9d94e RF |
3450 | temperature = <110000>; |
3451 | hysteresis = <1000>; | |
3452 | type = "critical"; | |
3453 | }; | |
3454 | }; | |
3455 | ||
3456 | cooling-maps { | |
3457 | map0 { | |
3458 | trip = <&cpu6_top_alert0>; | |
3459 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3460 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3461 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3462 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3463 | }; | |
3464 | map1 { | |
3465 | trip = <&cpu6_top_alert1>; | |
3466 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3467 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3468 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3469 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3470 | }; | |
3471 | }; | |
3472 | }; | |
3473 | ||
3474 | cpu7-top-thermal { | |
3475 | polling-delay-passive = <250>; | |
3476 | polling-delay = <1000>; | |
3477 | ||
3478 | thermal-sensors = <&tsens0 10>; | |
3479 | ||
3480 | trips { | |
3481 | cpu7_top_alert0: trip-point0 { | |
3482 | temperature = <90000>; | |
3483 | hysteresis = <2000>; | |
3484 | type = "passive"; | |
3485 | }; | |
3486 | ||
3487 | cpu7_top_alert1: trip-point1 { | |
3488 | temperature = <95000>; | |
3489 | hysteresis = <2000>; | |
3490 | type = "passive"; | |
3491 | }; | |
3492 | ||
1364acc3 | 3493 | cpu7_top_crit: cpu-crit { |
20f9d94e RF |
3494 | temperature = <110000>; |
3495 | hysteresis = <1000>; | |
3496 | type = "critical"; | |
3497 | }; | |
3498 | }; | |
3499 | ||
3500 | cooling-maps { | |
3501 | map0 { | |
3502 | trip = <&cpu7_top_alert0>; | |
3503 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3504 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3505 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3506 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3507 | }; | |
3508 | map1 { | |
3509 | trip = <&cpu7_top_alert1>; | |
3510 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3511 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3512 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3513 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3514 | }; | |
3515 | }; | |
3516 | }; | |
3517 | ||
3518 | cpu4-bottom-thermal { | |
3519 | polling-delay-passive = <250>; | |
3520 | polling-delay = <1000>; | |
3521 | ||
3522 | thermal-sensors = <&tsens0 11>; | |
3523 | ||
3524 | trips { | |
3525 | cpu4_bottom_alert0: trip-point0 { | |
3526 | temperature = <90000>; | |
3527 | hysteresis = <2000>; | |
3528 | type = "passive"; | |
3529 | }; | |
3530 | ||
3531 | cpu4_bottom_alert1: trip-point1 { | |
3532 | temperature = <95000>; | |
3533 | hysteresis = <2000>; | |
3534 | type = "passive"; | |
3535 | }; | |
3536 | ||
1364acc3 | 3537 | cpu4_bottom_crit: cpu-crit { |
20f9d94e RF |
3538 | temperature = <110000>; |
3539 | hysteresis = <1000>; | |
3540 | type = "critical"; | |
3541 | }; | |
3542 | }; | |
3543 | ||
3544 | cooling-maps { | |
3545 | map0 { | |
3546 | trip = <&cpu4_bottom_alert0>; | |
3547 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3548 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3549 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3550 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3551 | }; | |
3552 | map1 { | |
3553 | trip = <&cpu4_bottom_alert1>; | |
3554 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3555 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3556 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3557 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3558 | }; | |
3559 | }; | |
3560 | }; | |
3561 | ||
3562 | cpu5-bottom-thermal { | |
3563 | polling-delay-passive = <250>; | |
3564 | polling-delay = <1000>; | |
3565 | ||
3566 | thermal-sensors = <&tsens0 12>; | |
3567 | ||
3568 | trips { | |
3569 | cpu5_bottom_alert0: trip-point0 { | |
3570 | temperature = <90000>; | |
3571 | hysteresis = <2000>; | |
3572 | type = "passive"; | |
3573 | }; | |
3574 | ||
3575 | cpu5_bottom_alert1: trip-point1 { | |
3576 | temperature = <95000>; | |
3577 | hysteresis = <2000>; | |
3578 | type = "passive"; | |
3579 | }; | |
3580 | ||
1364acc3 | 3581 | cpu5_bottom_crit: cpu-crit { |
20f9d94e RF |
3582 | temperature = <110000>; |
3583 | hysteresis = <1000>; | |
3584 | type = "critical"; | |
3585 | }; | |
3586 | }; | |
3587 | ||
3588 | cooling-maps { | |
3589 | map0 { | |
3590 | trip = <&cpu5_bottom_alert0>; | |
3591 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3592 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3593 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3594 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3595 | }; | |
3596 | map1 { | |
3597 | trip = <&cpu5_bottom_alert1>; | |
3598 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3599 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3600 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3601 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3602 | }; | |
3603 | }; | |
3604 | }; | |
3605 | ||
3606 | cpu6-bottom-thermal { | |
3607 | polling-delay-passive = <250>; | |
3608 | polling-delay = <1000>; | |
3609 | ||
3610 | thermal-sensors = <&tsens0 13>; | |
3611 | ||
3612 | trips { | |
3613 | cpu6_bottom_alert0: trip-point0 { | |
3614 | temperature = <90000>; | |
3615 | hysteresis = <2000>; | |
3616 | type = "passive"; | |
3617 | }; | |
3618 | ||
3619 | cpu6_bottom_alert1: trip-point1 { | |
3620 | temperature = <95000>; | |
3621 | hysteresis = <2000>; | |
3622 | type = "passive"; | |
3623 | }; | |
3624 | ||
1364acc3 | 3625 | cpu6_bottom_crit: cpu-crit { |
20f9d94e RF |
3626 | temperature = <110000>; |
3627 | hysteresis = <1000>; | |
3628 | type = "critical"; | |
3629 | }; | |
3630 | }; | |
3631 | ||
3632 | cooling-maps { | |
3633 | map0 { | |
3634 | trip = <&cpu6_bottom_alert0>; | |
3635 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3636 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3637 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3638 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3639 | }; | |
3640 | map1 { | |
3641 | trip = <&cpu6_bottom_alert1>; | |
3642 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3643 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3644 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3645 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3646 | }; | |
3647 | }; | |
3648 | }; | |
3649 | ||
3650 | cpu7-bottom-thermal { | |
3651 | polling-delay-passive = <250>; | |
3652 | polling-delay = <1000>; | |
3653 | ||
3654 | thermal-sensors = <&tsens0 14>; | |
3655 | ||
3656 | trips { | |
3657 | cpu7_bottom_alert0: trip-point0 { | |
3658 | temperature = <90000>; | |
3659 | hysteresis = <2000>; | |
3660 | type = "passive"; | |
3661 | }; | |
3662 | ||
3663 | cpu7_bottom_alert1: trip-point1 { | |
3664 | temperature = <95000>; | |
3665 | hysteresis = <2000>; | |
3666 | type = "passive"; | |
3667 | }; | |
3668 | ||
1364acc3 | 3669 | cpu7_bottom_crit: cpu-crit { |
20f9d94e RF |
3670 | temperature = <110000>; |
3671 | hysteresis = <1000>; | |
3672 | type = "critical"; | |
3673 | }; | |
3674 | }; | |
3675 | ||
3676 | cooling-maps { | |
3677 | map0 { | |
3678 | trip = <&cpu7_bottom_alert0>; | |
3679 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3680 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3681 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3682 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3683 | }; | |
3684 | map1 { | |
3685 | trip = <&cpu7_bottom_alert1>; | |
3686 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3687 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3688 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3689 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3690 | }; | |
3691 | }; | |
3692 | }; | |
3693 | ||
3694 | aoss0-thermal { | |
3695 | polling-delay-passive = <250>; | |
3696 | polling-delay = <1000>; | |
3697 | ||
3698 | thermal-sensors = <&tsens0 0>; | |
3699 | ||
3700 | trips { | |
3701 | aoss0_alert0: trip-point0 { | |
3702 | temperature = <90000>; | |
3703 | hysteresis = <2000>; | |
3704 | type = "hot"; | |
3705 | }; | |
3706 | }; | |
3707 | }; | |
3708 | ||
3709 | cluster0-thermal { | |
3710 | polling-delay-passive = <250>; | |
3711 | polling-delay = <1000>; | |
3712 | ||
3713 | thermal-sensors = <&tsens0 5>; | |
3714 | ||
3715 | trips { | |
3716 | cluster0_alert0: trip-point0 { | |
3717 | temperature = <90000>; | |
3718 | hysteresis = <2000>; | |
3719 | type = "hot"; | |
3720 | }; | |
3721 | cluster0_crit: cluster0_crit { | |
3722 | temperature = <110000>; | |
3723 | hysteresis = <2000>; | |
3724 | type = "critical"; | |
3725 | }; | |
3726 | }; | |
3727 | }; | |
3728 | ||
3729 | cluster1-thermal { | |
3730 | polling-delay-passive = <250>; | |
3731 | polling-delay = <1000>; | |
3732 | ||
3733 | thermal-sensors = <&tsens0 6>; | |
3734 | ||
3735 | trips { | |
3736 | cluster1_alert0: trip-point0 { | |
3737 | temperature = <90000>; | |
3738 | hysteresis = <2000>; | |
3739 | type = "hot"; | |
3740 | }; | |
3741 | cluster1_crit: cluster1_crit { | |
3742 | temperature = <110000>; | |
3743 | hysteresis = <2000>; | |
3744 | type = "critical"; | |
3745 | }; | |
3746 | }; | |
3747 | }; | |
3748 | ||
3749 | aoss1-thermal { | |
3750 | polling-delay-passive = <250>; | |
3751 | polling-delay = <1000>; | |
3752 | ||
3753 | thermal-sensors = <&tsens1 0>; | |
3754 | ||
3755 | trips { | |
3756 | aoss1_alert0: trip-point0 { | |
3757 | temperature = <90000>; | |
3758 | hysteresis = <2000>; | |
3759 | type = "hot"; | |
3760 | }; | |
3761 | }; | |
3762 | }; | |
3763 | ||
7be1c395 | 3764 | gpu-top-thermal { |
20f9d94e RF |
3765 | polling-delay-passive = <250>; |
3766 | polling-delay = <1000>; | |
3767 | ||
3768 | thermal-sensors = <&tsens1 1>; | |
3769 | ||
3770 | trips { | |
3771 | gpu1_alert0: trip-point0 { | |
3772 | temperature = <90000>; | |
3773 | hysteresis = <1000>; | |
3774 | type = "hot"; | |
3775 | }; | |
3776 | }; | |
3777 | }; | |
3778 | ||
7be1c395 | 3779 | gpu-bottom-thermal { |
20f9d94e RF |
3780 | polling-delay-passive = <250>; |
3781 | polling-delay = <1000>; | |
3782 | ||
3783 | thermal-sensors = <&tsens1 2>; | |
3784 | ||
3785 | trips { | |
3786 | gpu2_alert0: trip-point0 { | |
3787 | temperature = <90000>; | |
3788 | hysteresis = <1000>; | |
3789 | type = "hot"; | |
3790 | }; | |
3791 | }; | |
3792 | }; | |
3793 | ||
3794 | nspss1-thermal { | |
3795 | polling-delay-passive = <250>; | |
3796 | polling-delay = <1000>; | |
3797 | ||
3798 | thermal-sensors = <&tsens1 3>; | |
3799 | ||
3800 | trips { | |
3801 | nspss1_alert0: trip-point0 { | |
3802 | temperature = <90000>; | |
3803 | hysteresis = <1000>; | |
3804 | type = "hot"; | |
3805 | }; | |
3806 | }; | |
3807 | }; | |
3808 | ||
3809 | nspss2-thermal { | |
3810 | polling-delay-passive = <250>; | |
3811 | polling-delay = <1000>; | |
3812 | ||
3813 | thermal-sensors = <&tsens1 4>; | |
3814 | ||
3815 | trips { | |
3816 | nspss2_alert0: trip-point0 { | |
3817 | temperature = <90000>; | |
3818 | hysteresis = <1000>; | |
3819 | type = "hot"; | |
3820 | }; | |
3821 | }; | |
3822 | }; | |
3823 | ||
3824 | nspss3-thermal { | |
3825 | polling-delay-passive = <250>; | |
3826 | polling-delay = <1000>; | |
3827 | ||
3828 | thermal-sensors = <&tsens1 5>; | |
3829 | ||
3830 | trips { | |
3831 | nspss3_alert0: trip-point0 { | |
3832 | temperature = <90000>; | |
3833 | hysteresis = <1000>; | |
3834 | type = "hot"; | |
3835 | }; | |
3836 | }; | |
3837 | }; | |
3838 | ||
3839 | video-thermal { | |
3840 | polling-delay-passive = <250>; | |
3841 | polling-delay = <1000>; | |
3842 | ||
3843 | thermal-sensors = <&tsens1 6>; | |
3844 | ||
3845 | trips { | |
3846 | video_alert0: trip-point0 { | |
3847 | temperature = <90000>; | |
3848 | hysteresis = <2000>; | |
3849 | type = "hot"; | |
3850 | }; | |
3851 | }; | |
3852 | }; | |
3853 | ||
3854 | mem-thermal { | |
3855 | polling-delay-passive = <250>; | |
3856 | polling-delay = <1000>; | |
3857 | ||
3858 | thermal-sensors = <&tsens1 7>; | |
3859 | ||
3860 | trips { | |
3861 | mem_alert0: trip-point0 { | |
3862 | temperature = <90000>; | |
3863 | hysteresis = <2000>; | |
3864 | type = "hot"; | |
3865 | }; | |
3866 | }; | |
3867 | }; | |
3868 | ||
7be1c395 | 3869 | modem1-top-thermal { |
20f9d94e RF |
3870 | polling-delay-passive = <250>; |
3871 | polling-delay = <1000>; | |
3872 | ||
3873 | thermal-sensors = <&tsens1 8>; | |
3874 | ||
3875 | trips { | |
3876 | modem1_alert0: trip-point0 { | |
3877 | temperature = <90000>; | |
3878 | hysteresis = <2000>; | |
3879 | type = "hot"; | |
3880 | }; | |
3881 | }; | |
3882 | }; | |
3883 | ||
7be1c395 | 3884 | modem2-top-thermal { |
20f9d94e RF |
3885 | polling-delay-passive = <250>; |
3886 | polling-delay = <1000>; | |
3887 | ||
3888 | thermal-sensors = <&tsens1 9>; | |
3889 | ||
3890 | trips { | |
3891 | modem2_alert0: trip-point0 { | |
3892 | temperature = <90000>; | |
3893 | hysteresis = <2000>; | |
3894 | type = "hot"; | |
3895 | }; | |
3896 | }; | |
3897 | }; | |
3898 | ||
7be1c395 | 3899 | modem3-top-thermal { |
20f9d94e RF |
3900 | polling-delay-passive = <250>; |
3901 | polling-delay = <1000>; | |
3902 | ||
3903 | thermal-sensors = <&tsens1 10>; | |
3904 | ||
3905 | trips { | |
3906 | modem3_alert0: trip-point0 { | |
3907 | temperature = <90000>; | |
3908 | hysteresis = <2000>; | |
3909 | type = "hot"; | |
3910 | }; | |
3911 | }; | |
3912 | }; | |
3913 | ||
7be1c395 | 3914 | modem4-top-thermal { |
20f9d94e RF |
3915 | polling-delay-passive = <250>; |
3916 | polling-delay = <1000>; | |
3917 | ||
3918 | thermal-sensors = <&tsens1 11>; | |
3919 | ||
3920 | trips { | |
3921 | modem4_alert0: trip-point0 { | |
3922 | temperature = <90000>; | |
3923 | hysteresis = <2000>; | |
3924 | type = "hot"; | |
3925 | }; | |
3926 | }; | |
3927 | }; | |
3928 | ||
7be1c395 | 3929 | camera-top-thermal { |
20f9d94e RF |
3930 | polling-delay-passive = <250>; |
3931 | polling-delay = <1000>; | |
3932 | ||
3933 | thermal-sensors = <&tsens1 12>; | |
3934 | ||
3935 | trips { | |
3936 | camera1_alert0: trip-point0 { | |
3937 | temperature = <90000>; | |
3938 | hysteresis = <2000>; | |
3939 | type = "hot"; | |
3940 | }; | |
3941 | }; | |
3942 | }; | |
3943 | ||
7be1c395 | 3944 | cam-bottom-thermal { |
20f9d94e RF |
3945 | polling-delay-passive = <250>; |
3946 | polling-delay = <1000>; | |
3947 | ||
3948 | thermal-sensors = <&tsens1 13>; | |
3949 | ||
3950 | trips { | |
3951 | camera2_alert0: trip-point0 { | |
3952 | temperature = <90000>; | |
3953 | hysteresis = <2000>; | |
3954 | type = "hot"; | |
3955 | }; | |
3956 | }; | |
3957 | }; | |
3958 | }; | |
3959 | ||
b7e8f433 VK |
3960 | timer { |
3961 | compatible = "arm,armv8-timer"; | |
3962 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
3963 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
3964 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
3965 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; | |
3966 | }; | |
3967 | }; |