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Merge branches 'acpi-bus' and 'acpi-video'
[linux-block.git] / arch / arm64 / boot / dts / qcom / sm8350.dtsi
CommitLineData
b7e8f433
VK		 1// SPDX-License-Identifier: BSD-3-Clause
2/*
4f23d2a5 3 * Copyright (c) 2020, Linaro Limited
b7e8f433
VK		 4 */
5
d4a44105 6#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433 7#include <dt-bindings/interrupt-controller/arm-gic.h>
9fd4887c 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
6d91e201 9#include <dt-bindings/clock/qcom,gcc-sm8350.h>
54af0ceb 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
b7e8f433 11#include <dt-bindings/clock/qcom,rpmh.h>
bc08fbf4 12#include <dt-bindings/dma/qcom-gpi.h>
f0360a7c 13#include <dt-bindings/gpio/gpio.h>
84c856d0 14#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433 15#include <dt-bindings/mailbox/qcom-ipcc.h>
2458a305 16#include <dt-bindings/phy/phy-qcom-qmp.h>
b7e8f433
VK		 17#include <dt-bindings/power/qcom-rpmpd.h>
18#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20f9d94e 19#include <dt-bindings/thermal/thermal.h>
f11d3e7d 20#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433
VK		 21
22/ {
23 interrupt-parent = <&intc>;
24
25 #address-cells = <2>;
26 #size-cells = <2>;
27
28 chosen { };
29
30 clocks {
31 xo_board: xo-board {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <38400000>;
35 clock-output-names = "xo_board";
36 };
37
38 sleep_clk: sleep-clk {
39 compatible = "fixed-clock";
40 clock-frequency = <32000>;
41 #clock-cells = <0>;
42 };
43 };
44
45 cpus {
46 #address-cells = <2>;
47 #size-cells = <0>;
48
49 CPU0: cpu@0 {
50 device_type = "cpu";
51 compatible = "qcom,kryo685";
52 reg = <0x0 0x0>;
c2a18730 53 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 54 enable-method = "psci";
55 next-level-cache = <&L2_0>;
ccbb3abb 56 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 57 power-domains = <&CPU_PD0>;
58 power-domain-names = "psci";
20f9d94e 59 #cooling-cells = <2>;
b7e8f433 60 L2_0: l2-cache {
f34fbb71
KK		 61 compatible = "cache";
62 cache-level = <2>;
9c6e72fb 63 cache-unified;
f34fbb71 64 next-level-cache = <&L3_0>;
b7e8f433 65 L3_0: l3-cache {
f34fbb71
KK		 66 compatible = "cache";
67 cache-level = <3>;
9c6e72fb 68 cache-unified;
b7e8f433
VK		 69 };
70 };
71 };
72
73 CPU1: cpu@100 {
74 device_type = "cpu";
75 compatible = "qcom,kryo685";
76 reg = <0x0 0x100>;
c2a18730 77 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 78 enable-method = "psci";
79 next-level-cache = <&L2_100>;
ccbb3abb 80 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 81 power-domains = <&CPU_PD1>;
82 power-domain-names = "psci";
20f9d94e 83 #cooling-cells = <2>;
b7e8f433 84 L2_100: l2-cache {
f34fbb71
KK		 85 compatible = "cache";
86 cache-level = <2>;
9c6e72fb 87 cache-unified;
f34fbb71 88 next-level-cache = <&L3_0>;
b7e8f433
VK		 89 };
90 };
91
92 CPU2: cpu@200 {
93 device_type = "cpu";
94 compatible = "qcom,kryo685";
95 reg = <0x0 0x200>;
c2a18730 96 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 97 enable-method = "psci";
98 next-level-cache = <&L2_200>;
ccbb3abb 99 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 100 power-domains = <&CPU_PD2>;
101 power-domain-names = "psci";
20f9d94e 102 #cooling-cells = <2>;
b7e8f433 103 L2_200: l2-cache {
f34fbb71
KK		 104 compatible = "cache";
105 cache-level = <2>;
9c6e72fb 106 cache-unified;
f34fbb71 107 next-level-cache = <&L3_0>;
b7e8f433
VK		 108 };
109 };
110
111 CPU3: cpu@300 {
112 device_type = "cpu";
113 compatible = "qcom,kryo685";
114 reg = <0x0 0x300>;
c2a18730 115 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 116 enable-method = "psci";
117 next-level-cache = <&L2_300>;
ccbb3abb 118 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 119 power-domains = <&CPU_PD3>;
120 power-domain-names = "psci";
20f9d94e 121 #cooling-cells = <2>;
b7e8f433 122 L2_300: l2-cache {
f34fbb71
KK		 123 compatible = "cache";
124 cache-level = <2>;
9c6e72fb 125 cache-unified;
f34fbb71 126 next-level-cache = <&L3_0>;
b7e8f433
VK		 127 };
128 };
129
130 CPU4: cpu@400 {
131 device_type = "cpu";
132 compatible = "qcom,kryo685";
133 reg = <0x0 0x400>;
c2a18730 134 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 135 enable-method = "psci";
136 next-level-cache = <&L2_400>;
ccbb3abb 137 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 138 power-domains = <&CPU_PD4>;
139 power-domain-names = "psci";
20f9d94e 140 #cooling-cells = <2>;
b7e8f433 141 L2_400: l2-cache {
f34fbb71
KK		 142 compatible = "cache";
143 cache-level = <2>;
9c6e72fb 144 cache-unified;
f34fbb71 145 next-level-cache = <&L3_0>;
b7e8f433
VK		 146 };
147 };
148
149 CPU5: cpu@500 {
150 device_type = "cpu";
151 compatible = "qcom,kryo685";
152 reg = <0x0 0x500>;
c2a18730 153 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 154 enable-method = "psci";
155 next-level-cache = <&L2_500>;
ccbb3abb 156 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 157 power-domains = <&CPU_PD5>;
158 power-domain-names = "psci";
20f9d94e 159 #cooling-cells = <2>;
b7e8f433 160 L2_500: l2-cache {
f34fbb71
KK		 161 compatible = "cache";
162 cache-level = <2>;
9c6e72fb 163 cache-unified;
f34fbb71 164 next-level-cache = <&L3_0>;
b7e8f433 165 };
b7e8f433
VK		 166 };
167
168 CPU6: cpu@600 {
169 device_type = "cpu";
170 compatible = "qcom,kryo685";
171 reg = <0x0 0x600>;
c2a18730 172 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 173 enable-method = "psci";
174 next-level-cache = <&L2_600>;
ccbb3abb 175 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 176 power-domains = <&CPU_PD6>;
177 power-domain-names = "psci";
20f9d94e 178 #cooling-cells = <2>;
b7e8f433 179 L2_600: l2-cache {
f34fbb71
KK		 180 compatible = "cache";
181 cache-level = <2>;
9c6e72fb 182 cache-unified;
f34fbb71 183 next-level-cache = <&L3_0>;
b7e8f433
VK		 184 };
185 };
186
187 CPU7: cpu@700 {
188 device_type = "cpu";
189 compatible = "qcom,kryo685";
190 reg = <0x0 0x700>;
c2a18730 191 clocks = <&cpufreq_hw 2>;
b7e8f433
VK		 192 enable-method = "psci";
193 next-level-cache = <&L2_700>;
ccbb3abb 194 qcom,freq-domain = <&cpufreq_hw 2>;
07ddb302
BA		 195 power-domains = <&CPU_PD7>;
196 power-domain-names = "psci";
20f9d94e 197 #cooling-cells = <2>;
b7e8f433 198 L2_700: l2-cache {
f34fbb71
KK		 199 compatible = "cache";
200 cache-level = <2>;
9c6e72fb 201 cache-unified;
f34fbb71 202 next-level-cache = <&L3_0>;
b7e8f433
VK		 203 };
204 };
07ddb302
BA		 205
206 cpu-map {
207 cluster0 {
208 core0 {
209 cpu = <&CPU0>;
210 };
211
212 core1 {
213 cpu = <&CPU1>;
214 };
215
216 core2 {
217 cpu = <&CPU2>;
218 };
219
220 core3 {
221 cpu = <&CPU3>;
222 };
223
224 core4 {
225 cpu = <&CPU4>;
226 };
227
228 core5 {
229 cpu = <&CPU5>;
230 };
231
232 core6 {
233 cpu = <&CPU6>;
234 };
235
236 core7 {
237 cpu = <&CPU7>;
238 };
239 };
240 };
241
242 idle-states {
243 entry-method = "psci";
244
245 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
246 compatible = "arm,idle-state";
247 idle-state-name = "silver-rail-power-collapse";
248 arm,psci-suspend-param = <0x40000004>;
249 entry-latency-us = <355>;
250 exit-latency-us = <909>;
251 min-residency-us = <3934>;
252 local-timer-stop;
253 };
254
255 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
256 compatible = "arm,idle-state";
257 idle-state-name = "gold-rail-power-collapse";
258 arm,psci-suspend-param = <0x40000004>;
259 entry-latency-us = <241>;
260 exit-latency-us = <1461>;
261 min-residency-us = <4488>;
262 local-timer-stop;
263 };
264 };
265
266 domain-idle-states {
267 CLUSTER_SLEEP_0: cluster-sleep-0 {
268 compatible = "domain-idle-state";
07ddb302
BA		 269 arm,psci-suspend-param = <0x4100c344>;
270 entry-latency-us = <3263>;
271 exit-latency-us = <6562>;
272 min-residency-us = <9987>;
07ddb302
BA		 273 };
274 };
b7e8f433
VK		 275 };
276
277 firmware {
278 scm: scm {
279 compatible = "qcom,scm-sm8350", "qcom,scm";
280 #reset-cells = <1>;
281 };
282 };
283
284 memory@80000000 {
285 device_type = "memory";
286 /* We expect the bootloader to fill in the size */
287 reg = <0x0 0x80000000 0x0 0x0>;
288 };
289
290 pmu {
291 compatible = "arm,armv8-pmuv3";
794d3e30 292 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
b7e8f433
VK		 293 };
294
295 psci {
296 compatible = "arm,psci-1.0";
297 method = "smc";
07ddb302 298
a9371962 299 CPU_PD0: power-domain-cpu0 {
07ddb302
BA		 300 #power-domain-cells = <0>;
301 power-domains = <&CLUSTER_PD>;
302 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
303 };
304
a9371962 305 CPU_PD1: power-domain-cpu1 {
07ddb302
BA		 306 #power-domain-cells = <0>;
307 power-domains = <&CLUSTER_PD>;
308 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
309 };
310
a9371962 311 CPU_PD2: power-domain-cpu2 {
07ddb302
BA		 312 #power-domain-cells = <0>;
313 power-domains = <&CLUSTER_PD>;
314 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
315 };
316
a9371962 317 CPU_PD3: power-domain-cpu3 {
07ddb302
BA		 318 #power-domain-cells = <0>;
319 power-domains = <&CLUSTER_PD>;
320 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
321 };
322
a9371962 323 CPU_PD4: power-domain-cpu4 {
07ddb302
BA		 324 #power-domain-cells = <0>;
325 power-domains = <&CLUSTER_PD>;
326 domain-idle-states = <&BIG_CPU_SLEEP_0>;
327 };
328
a9371962 329 CPU_PD5: power-domain-cpu5 {
07ddb302
BA		 330 #power-domain-cells = <0>;
331 power-domains = <&CLUSTER_PD>;
332 domain-idle-states = <&BIG_CPU_SLEEP_0>;
333 };
334
a9371962 335 CPU_PD6: power-domain-cpu6 {
07ddb302
BA		 336 #power-domain-cells = <0>;
337 power-domains = <&CLUSTER_PD>;
338 domain-idle-states = <&BIG_CPU_SLEEP_0>;
339 };
340
a9371962 341 CPU_PD7: power-domain-cpu7 {
07ddb302
BA		 342 #power-domain-cells = <0>;
343 power-domains = <&CLUSTER_PD>;
344 domain-idle-states = <&BIG_CPU_SLEEP_0>;
345 };
346
a9371962 347 CLUSTER_PD: power-domain-cpu-cluster0 {
07ddb302
BA		 348 #power-domain-cells = <0>;
349 domain-idle-states = <&CLUSTER_SLEEP_0>;
350 };
b7e8f433
VK		 351 };
352
e2eedde4
VK		 353 qup_opp_table_100mhz: opp-table-qup100mhz {
354 compatible = "operating-points-v2";
355
356 opp-50000000 {
357 opp-hz = /bits/ 64 <50000000>;
358 required-opps = <&rpmhpd_opp_min_svs>;
359 };
360
361 opp-75000000 {
362 opp-hz = /bits/ 64 <75000000>;
363 required-opps = <&rpmhpd_opp_low_svs>;
364 };
365
366 opp-100000000 {
367 opp-hz = /bits/ 64 <100000000>;
368 required-opps = <&rpmhpd_opp_svs>;
369 };
370 };
371
372 qup_opp_table_120mhz: opp-table-qup120mhz {
373 compatible = "operating-points-v2";
374
375 opp-50000000 {
376 opp-hz = /bits/ 64 <50000000>;
377 required-opps = <&rpmhpd_opp_min_svs>;
378 };
379
380 opp-75000000 {
381 opp-hz = /bits/ 64 <75000000>;
382 required-opps = <&rpmhpd_opp_low_svs>;
383 };
384
385 opp-120000000 {
386 opp-hz = /bits/ 64 <120000000>;
387 required-opps = <&rpmhpd_opp_svs>;
388 };
389 };
390
b7e8f433
VK		 391 reserved_memory: reserved-memory {
392 #address-cells = <2>;
393 #size-cells = <2>;
394 ranges;
395
396 hyp_mem: memory@80000000 {
397 reg = <0x0 0x80000000 0x0 0x600000>;
398 no-map;
399 };
400
401 xbl_aop_mem: memory@80700000 {
402 no-map;
403 reg = <0x0 0x80700000 0x0 0x160000>;
404 };
405
406 cmd_db: memory@80860000 {
407 compatible = "qcom,cmd-db";
408 reg = <0x0 0x80860000 0x0 0x20000>;
409 no-map;
410 };
411
412 reserved_xbl_uefi_log: memory@80880000 {
413 reg = <0x0 0x80880000 0x0 0x14000>;
414 no-map;
415 };
416
8503babc
KD		 417 smem@80900000 {
418 compatible = "qcom,smem";
b7e8f433 419 reg = <0x0 0x80900000 0x0 0x200000>;
8503babc 420 hwlocks = <&tcsr_mutex 3>;
b7e8f433
VK		 421 no-map;
422 };
423
424 cpucp_fw_mem: memory@80b00000 {
425 reg = <0x0 0x80b00000 0x0 0x100000>;
426 no-map;
427 };
428
429 cdsp_secure_heap: memory@80c00000 {
430 reg = <0x0 0x80c00000 0x0 0x4600000>;
431 no-map;
432 };
433
434 pil_camera_mem: mmeory@85200000 {
435 reg = <0x0 0x85200000 0x0 0x500000>;
436 no-map;
437 };
438
439 pil_video_mem: memory@85700000 {
440 reg = <0x0 0x85700000 0x0 0x500000>;
441 no-map;
442 };
443
444 pil_cvp_mem: memory@85c00000 {
445 reg = <0x0 0x85c00000 0x0 0x500000>;
446 no-map;
447 };
448
449 pil_adsp_mem: memory@86100000 {
450 reg = <0x0 0x86100000 0x0 0x2100000>;
451 no-map;
452 };
453
454 pil_slpi_mem: memory@88200000 {
455 reg = <0x0 0x88200000 0x0 0x1500000>;
456 no-map;
457 };
458
459 pil_cdsp_mem: memory@89700000 {
460 reg = <0x0 0x89700000 0x0 0x1e00000>;
461 no-map;
462 };
463
464 pil_ipa_fw_mem: memory@8b500000 {
465 reg = <0x0 0x8b500000 0x0 0x10000>;
466 no-map;
467 };
468
469 pil_ipa_gsi_mem: memory@8b510000 {
470 reg = <0x0 0x8b510000 0x0 0xa000>;
471 no-map;
472 };
473
474 pil_gpu_mem: memory@8b51a000 {
475 reg = <0x0 0x8b51a000 0x0 0x2000>;
476 no-map;
477 };
478
479 pil_spss_mem: memory@8b600000 {
480 reg = <0x0 0x8b600000 0x0 0x100000>;
481 no-map;
482 };
483
484 pil_modem_mem: memory@8b800000 {
485 reg = <0x0 0x8b800000 0x0 0x10000000>;
486 no-map;
487 };
488
774890c9
VK		 489 rmtfs_mem: memory@9b800000 {
490 compatible = "qcom,rmtfs-mem";
491 reg = <0x0 0x9b800000 0x0 0x280000>;
492 no-map;
493
494 qcom,client-id = <1>;
495 qcom,vmid = <15>;
496 };
497
b7e8f433
VK		 498 hyp_reserved_mem: memory@d0000000 {
499 reg = <0x0 0xd0000000 0x0 0x800000>;
500 no-map;
501 };
502
503 pil_trustedvm_mem: memory@d0800000 {
504 reg = <0x0 0xd0800000 0x0 0x76f7000>;
505 no-map;
506 };
507
508 qrtr_shbuf: memory@d7ef7000 {
509 reg = <0x0 0xd7ef7000 0x0 0x9000>;
510 no-map;
511 };
512
513 chan0_shbuf: memory@d7f00000 {
514 reg = <0x0 0xd7f00000 0x0 0x80000>;
515 no-map;
516 };
517
518 chan1_shbuf: memory@d7f80000 {
519 reg = <0x0 0xd7f80000 0x0 0x80000>;
520 no-map;
521 };
522
523 removed_mem: memory@d8800000 {
524 reg = <0x0 0xd8800000 0x0 0x6800000>;
525 no-map;
526 };
527 };
528
03a41991
VK		 529 smp2p-adsp {
530 compatible = "qcom,smp2p";
531 qcom,smem = <443>, <429>;
532 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
533 IPCC_MPROC_SIGNAL_SMP2P
534 IRQ_TYPE_EDGE_RISING>;
535 mboxes = <&ipcc IPCC_CLIENT_LPASS
536 IPCC_MPROC_SIGNAL_SMP2P>;
537
538 qcom,local-pid = <0>;
539 qcom,remote-pid = <2>;
540
541 smp2p_adsp_out: master-kernel {
542 qcom,entry-name = "master-kernel";
543 #qcom,smem-state-cells = <1>;
544 };
545
546 smp2p_adsp_in: slave-kernel {
547 qcom,entry-name = "slave-kernel";
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 };
551 };
552
553 smp2p-cdsp {
554 compatible = "qcom,smp2p";
555 qcom,smem = <94>, <432>;
556 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
557 IPCC_MPROC_SIGNAL_SMP2P
558 IRQ_TYPE_EDGE_RISING>;
559 mboxes = <&ipcc IPCC_CLIENT_CDSP
560 IPCC_MPROC_SIGNAL_SMP2P>;
561
562 qcom,local-pid = <0>;
563 qcom,remote-pid = <5>;
564
565 smp2p_cdsp_out: master-kernel {
566 qcom,entry-name = "master-kernel";
567 #qcom,smem-state-cells = <1>;
568 };
569
570 smp2p_cdsp_in: slave-kernel {
571 qcom,entry-name = "slave-kernel";
572 interrupt-controller;
573 #interrupt-cells = <2>;
574 };
575 };
576
577 smp2p-modem {
578 compatible = "qcom,smp2p";
579 qcom,smem = <435>, <428>;
580 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
581 IPCC_MPROC_SIGNAL_SMP2P
582 IRQ_TYPE_EDGE_RISING>;
583 mboxes = <&ipcc IPCC_CLIENT_MPSS
584 IPCC_MPROC_SIGNAL_SMP2P>;
585
586 qcom,local-pid = <0>;
587 qcom,remote-pid = <1>;
588
589 smp2p_modem_out: master-kernel {
590 qcom,entry-name = "master-kernel";
591 #qcom,smem-state-cells = <1>;
592 };
593
594 smp2p_modem_in: slave-kernel {
595 qcom,entry-name = "slave-kernel";
596 interrupt-controller;
597 #interrupt-cells = <2>;
598 };
f11d3e7d
AE		 599
600 ipa_smp2p_out: ipa-ap-to-modem {
601 qcom,entry-name = "ipa";
602 #qcom,smem-state-cells = <1>;
603 };
604
605 ipa_smp2p_in: ipa-modem-to-ap {
606 qcom,entry-name = "ipa";
607 interrupt-controller;
608 #interrupt-cells = <2>;
609 };
03a41991
VK		 610 };
611
612 smp2p-slpi {
613 compatible = "qcom,smp2p";
614 qcom,smem = <481>, <430>;
615 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
616 IPCC_MPROC_SIGNAL_SMP2P
617 IRQ_TYPE_EDGE_RISING>;
618 mboxes = <&ipcc IPCC_CLIENT_SLPI
619 IPCC_MPROC_SIGNAL_SMP2P>;
620
621 qcom,local-pid = <0>;
622 qcom,remote-pid = <3>;
623
624 smp2p_slpi_out: master-kernel {
625 qcom,entry-name = "master-kernel";
626 #qcom,smem-state-cells = <1>;
627 };
628
629 smp2p_slpi_in: slave-kernel {
630 qcom,entry-name = "slave-kernel";
631 interrupt-controller;
632 #interrupt-cells = <2>;
633 };
634 };
635
b7e8f433
VK		 636 soc: soc@0 {
637 #address-cells = <2>;
638 #size-cells = <2>;
639 ranges = <0 0 0 0 0x10 0>;
640 dma-ranges = <0 0 0 0 0x10 0>;
641 compatible = "simple-bus";
642
643 gcc: clock-controller@100000 {
644 compatible = "qcom,gcc-sm8350";
645 reg = <0x0 0x00100000 0x0 0x1f0000>;
646 #clock-cells = <1>;
647 #reset-cells = <1>;
648 #power-domain-cells = <1>;
9ea9eb36
KD		 649 clock-names = "bi_tcxo",
650 "sleep_clk",
651 "pcie_0_pipe_clk",
652 "pcie_1_pipe_clk",
653 "ufs_card_rx_symbol_0_clk",
654 "ufs_card_rx_symbol_1_clk",
655 "ufs_card_tx_symbol_0_clk",
656 "ufs_phy_rx_symbol_0_clk",
657 "ufs_phy_rx_symbol_1_clk",
658 "ufs_phy_tx_symbol_0_clk",
659 "usb3_phy_wrapper_gcc_usb30_pipe_clk",
660 "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
661 clocks = <&rpmhcc RPMH_CXO_CLK>,
662 <&sleep_clk>,
6daee406
DB		 663 <&pcie0_phy>,
664 <&pcie1_phy>,
9ea9eb36
KD		 665 <0>,
666 <0>,
667 <0>,
86543bc6
DB		 668 <&ufs_mem_phy_lanes 0>,
669 <&ufs_mem_phy_lanes 1>,
670 <&ufs_mem_phy_lanes 2>,
2458a305 671 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
9ea9eb36 672 <0>;
b7e8f433
VK		 673 };
674
675 ipcc: mailbox@408000 {
676 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
677 reg = <0 0x00408000 0 0x1000>;
678 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
679 interrupt-controller;
680 #interrupt-cells = <3>;
681 #mbox-cells = <2>;
682 };
683
bc08fbf4 684 gpi_dma2: dma-controller@800000 {
b561e225 685 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 686 reg = <0 0x00800000 0 0x60000>;
687 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
699 dma-channels = <12>;
700 dma-channel-mask = <0xff>;
701 iommus = <&apps_smmu 0x5f6 0x0>;
702 #dma-cells = <3>;
703 status = "disabled";
704 };
705
e84d04a2
KD		 706 qupv3_id_2: geniqup@8c0000 {
707 compatible = "qcom,geni-se-qup";
708 reg = <0x0 0x008c0000 0x0 0x6000>;
709 clock-names = "m-ahb", "s-ahb";
710 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
711 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
9bc2c8fe 712 iommus = <&apps_smmu 0x5e3 0x0>;
e84d04a2
KD		 713 #address-cells = <2>;
714 #size-cells = <2>;
715 ranges;
716 status = "disabled";
98374e69
KD		 717
718 i2c14: i2c@880000 {
719 compatible = "qcom,geni-i2c";
720 reg = <0 0x00880000 0 0x4000>;
721 clock-names = "se";
722 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&qup_i2c14_default>;
725 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 726 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
727 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
728 dma-names = "tx", "rx";
98374e69
KD		 729 #address-cells = <1>;
730 #size-cells = <0>;
731 status = "disabled";
732 };
733
734 spi14: spi@880000 {
735 compatible = "qcom,geni-spi";
736 reg = <0 0x00880000 0 0x4000>;
737 clock-names = "se";
738 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
739 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
740 power-domains = <&rpmhpd SM8350_CX>;
741 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 742 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
743 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
744 dma-names = "tx", "rx";
98374e69
KD		 745 #address-cells = <1>;
746 #size-cells = <0>;
747 status = "disabled";
748 };
749
750 i2c15: i2c@884000 {
751 compatible = "qcom,geni-i2c";
752 reg = <0 0x00884000 0 0x4000>;
753 clock-names = "se";
754 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
755 pinctrl-names = "default";
756 pinctrl-0 = <&qup_i2c15_default>;
757 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 758 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
759 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
760 dma-names = "tx", "rx";
98374e69
KD		 761 #address-cells = <1>;
762 #size-cells = <0>;
763 status = "disabled";
764 };
765
766 spi15: spi@884000 {
767 compatible = "qcom,geni-spi";
768 reg = <0 0x00884000 0 0x4000>;
769 clock-names = "se";
770 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
771 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
772 power-domains = <&rpmhpd SM8350_CX>;
773 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 774 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
775 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
776 dma-names = "tx", "rx";
98374e69
KD		 777 #address-cells = <1>;
778 #size-cells = <0>;
779 status = "disabled";
780 };
781
782 i2c16: i2c@888000 {
783 compatible = "qcom,geni-i2c";
784 reg = <0 0x00888000 0 0x4000>;
785 clock-names = "se";
786 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
787 pinctrl-names = "default";
788 pinctrl-0 = <&qup_i2c16_default>;
789 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 790 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
791 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
792 dma-names = "tx", "rx";
98374e69
KD		 793 #address-cells = <1>;
794 #size-cells = <0>;
795 status = "disabled";
796 };
797
798 spi16: spi@888000 {
799 compatible = "qcom,geni-spi";
800 reg = <0 0x00888000 0 0x4000>;
801 clock-names = "se";
802 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
803 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
804 power-domains = <&rpmhpd SM8350_CX>;
805 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 806 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
807 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
808 dma-names = "tx", "rx";
98374e69
KD		 809 #address-cells = <1>;
810 #size-cells = <0>;
811 status = "disabled";
812 };
813
814 i2c17: i2c@88c000 {
815 compatible = "qcom,geni-i2c";
816 reg = <0 0x0088c000 0 0x4000>;
817 clock-names = "se";
818 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
819 pinctrl-names = "default";
820 pinctrl-0 = <&qup_i2c17_default>;
821 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 822 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
823 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
824 dma-names = "tx", "rx";
98374e69
KD		 825 #address-cells = <1>;
826 #size-cells = <0>;
827 status = "disabled";
828 };
829
830 spi17: spi@88c000 {
831 compatible = "qcom,geni-spi";
832 reg = <0 0x0088c000 0 0x4000>;
833 clock-names = "se";
834 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
835 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
836 power-domains = <&rpmhpd SM8350_CX>;
837 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 838 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
839 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
840 dma-names = "tx", "rx";
98374e69
KD		 841 #address-cells = <1>;
842 #size-cells = <0>;
843 status = "disabled";
844 };
845
846 /* QUP no. 18 seems to be strictly SPI/UART-only */
847
848 spi18: spi@890000 {
849 compatible = "qcom,geni-spi";
850 reg = <0 0x00890000 0 0x4000>;
851 clock-names = "se";
852 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
853 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
854 power-domains = <&rpmhpd SM8350_CX>;
855 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 856 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
857 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
858 dma-names = "tx", "rx";
98374e69
KD		 859 #address-cells = <1>;
860 #size-cells = <0>;
861 status = "disabled";
862 };
863
864 uart18: serial@890000 {
865 compatible = "qcom,geni-uart";
866 reg = <0 0x00890000 0 0x4000>;
867 clock-names = "se";
868 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&qup_uart18_default>;
871 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
872 power-domains = <&rpmhpd SM8350_CX>;
873 operating-points-v2 = <&qup_opp_table_100mhz>;
874 status = "disabled";
875 };
876
877 i2c19: i2c@894000 {
878 compatible = "qcom,geni-i2c";
879 reg = <0 0x00894000 0 0x4000>;
880 clock-names = "se";
881 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
882 pinctrl-names = "default";
883 pinctrl-0 = <&qup_i2c19_default>;
884 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 885 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
886 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
887 dma-names = "tx", "rx";
98374e69
KD		 888 #address-cells = <1>;
889 #size-cells = <0>;
890 status = "disabled";
891 };
892
893 spi19: spi@894000 {
894 compatible = "qcom,geni-spi";
895 reg = <0 0x00894000 0 0x4000>;
896 clock-names = "se";
897 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
898 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
899 power-domains = <&rpmhpd SM8350_CX>;
900 operating-points-v2 = <&qup_opp_table_100mhz>;
bc08fbf4
BA		 901 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
902 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
903 dma-names = "tx", "rx";
98374e69
KD		 904 #address-cells = <1>;
905 #size-cells = <0>;
906 status = "disabled";
907 };
e84d04a2
KD		 908 };
909
41d6bca7 910 gpi_dma0: dma-controller@9800000 {
b561e225 911 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 912 reg = <0 0x09800000 0 0x60000>;
913 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
925 dma-channels = <12>;
926 dma-channel-mask = <0x7e>;
927 iommus = <&apps_smmu 0x5b6 0x0>;
928 #dma-cells = <3>;
929 status = "disabled";
930 };
931
87f0b434 932 qupv3_id_0: geniqup@9c0000 {
b7e8f433
VK		 933 compatible = "qcom,geni-se-qup";
934 reg = <0x0 0x009c0000 0x0 0x6000>;
935 clock-names = "m-ahb", "s-ahb";
6d91e201
VK		 936 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
937 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
9bc2c8fe 938 iommus = <&apps_smmu 0x5a3 0>;
b7e8f433
VK		 939 #address-cells = <2>;
940 #size-cells = <2>;
941 ranges;
942 status = "disabled";
943
cf03cd7e
KD		 944 i2c0: i2c@980000 {
945 compatible = "qcom,geni-i2c";
946 reg = <0 0x00980000 0 0x4000>;
947 clock-names = "se";
948 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
949 pinctrl-names = "default";
950 pinctrl-0 = <&qup_i2c0_default>;
951 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 952 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
953 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
954 dma-names = "tx", "rx";
cf03cd7e
KD		 955 #address-cells = <1>;
956 #size-cells = <0>;
957 status = "disabled";
958 };
959
960 spi0: spi@980000 {
961 compatible = "qcom,geni-spi";
962 reg = <0 0x00980000 0 0x4000>;
963 clock-names = "se";
964 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
965 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
966 power-domains = <&rpmhpd SM8350_CX>;
967 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 968 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
969 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
970 dma-names = "tx", "rx";
cf03cd7e
KD		 971 #address-cells = <1>;
972 #size-cells = <0>;
973 status = "disabled";
974 };
975
976 i2c1: i2c@984000 {
977 compatible = "qcom,geni-i2c";
978 reg = <0 0x00984000 0 0x4000>;
979 clock-names = "se";
980 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
981 pinctrl-names = "default";
982 pinctrl-0 = <&qup_i2c1_default>;
983 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 984 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
985 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
986 dma-names = "tx", "rx";
cf03cd7e
KD		 987 #address-cells = <1>;
988 #size-cells = <0>;
989 status = "disabled";
990 };
991
992 spi1: spi@984000 {
993 compatible = "qcom,geni-spi";
994 reg = <0 0x00984000 0 0x4000>;
995 clock-names = "se";
996 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
997 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
998 power-domains = <&rpmhpd SM8350_CX>;
999 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1000 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1001 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1002 dma-names = "tx", "rx";
cf03cd7e
KD		 1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 status = "disabled";
1006 };
1007
1008 i2c2: i2c@988000 {
1009 compatible = "qcom,geni-i2c";
1010 reg = <0 0x00988000 0 0x4000>;
1011 clock-names = "se";
1012 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&qup_i2c2_default>;
1015 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1016 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1017 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1018 dma-names = "tx", "rx";
cf03cd7e
KD		 1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 status = "disabled";
1022 };
1023
1024 spi2: spi@988000 {
1025 compatible = "qcom,geni-spi";
1026 reg = <0 0x00988000 0 0x4000>;
1027 clock-names = "se";
1028 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1029 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1030 power-domains = <&rpmhpd SM8350_CX>;
1031 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1032 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1033 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1034 dma-names = "tx", "rx";
cf03cd7e
KD		 1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 status = "disabled";
1038 };
1039
b7e8f433
VK		 1040 uart2: serial@98c000 {
1041 compatible = "qcom,geni-debug-uart";
1042 reg = <0 0x0098c000 0 0x4000>;
1043 clock-names = "se";
6d91e201 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
b7e8f433
VK		 1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_uart3_default_state>;
1047 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
cf03cd7e
KD		 1048 power-domains = <&rpmhpd SM8350_CX>;
1049 operating-points-v2 = <&qup_opp_table_100mhz>;
cf03cd7e
KD		 1050 status = "disabled";
1051 };
1052
1053 /* QUP no. 3 seems to be strictly SPI-only */
1054
1055 spi3: spi@98c000 {
1056 compatible = "qcom,geni-spi";
1057 reg = <0 0x0098c000 0 0x4000>;
1058 clock-names = "se";
1059 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1060 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 power-domains = <&rpmhpd SM8350_CX>;
1062 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1063 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1064 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1065 dma-names = "tx", "rx";
cf03cd7e
KD		 1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 status = "disabled";
1069 };
1070
1071 i2c4: i2c@990000 {
1072 compatible = "qcom,geni-i2c";
1073 reg = <0 0x00990000 0 0x4000>;
1074 clock-names = "se";
1075 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_i2c4_default>;
1078 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1079 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1080 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1081 dma-names = "tx", "rx";
cf03cd7e
KD		 1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 status = "disabled";
1085 };
1086
1087 spi4: spi@990000 {
1088 compatible = "qcom,geni-spi";
1089 reg = <0 0x00990000 0 0x4000>;
1090 clock-names = "se";
1091 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1093 power-domains = <&rpmhpd SM8350_CX>;
1094 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1095 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1096 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1097 dma-names = "tx", "rx";
cf03cd7e
KD		 1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 status = "disabled";
1101 };
1102
1103 i2c5: i2c@994000 {
1104 compatible = "qcom,geni-i2c";
1105 reg = <0 0x00994000 0 0x4000>;
1106 clock-names = "se";
1107 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&qup_i2c5_default>;
1110 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1111 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1112 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1113 dma-names = "tx", "rx";
cf03cd7e
KD		 1114 #address-cells = <1>;
1115 #size-cells = <0>;
1116 status = "disabled";
1117 };
1118
1119 spi5: spi@994000 {
1120 compatible = "qcom,geni-spi";
1121 reg = <0 0x00994000 0 0x4000>;
1122 clock-names = "se";
1123 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1124 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1125 power-domains = <&rpmhpd SM8350_CX>;
1126 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1127 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1128 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1129 dma-names = "tx", "rx";
cf03cd7e
KD		 1130 #address-cells = <1>;
1131 #size-cells = <0>;
1132 status = "disabled";
1133 };
1134
1135 i2c6: i2c@998000 {
1136 compatible = "qcom,geni-i2c";
1137 reg = <0 0x00998000 0 0x4000>;
1138 clock-names = "se";
1139 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&qup_i2c6_default>;
1142 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1143 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1144 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1145 dma-names = "tx", "rx";
cf03cd7e
KD		 1146 #address-cells = <1>;
1147 #size-cells = <0>;
1148 status = "disabled";
1149 };
1150
1151 spi6: spi@998000 {
1152 compatible = "qcom,geni-spi";
1153 reg = <0 0x00998000 0 0x4000>;
1154 clock-names = "se";
1155 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1156 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1157 power-domains = <&rpmhpd SM8350_CX>;
1158 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1159 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1160 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1161 dma-names = "tx", "rx";
cf03cd7e
KD		 1162 #address-cells = <1>;
1163 #size-cells = <0>;
1164 status = "disabled";
1165 };
1166
1167 uart6: serial@998000 {
1168 compatible = "qcom,geni-uart";
1169 reg = <0 0x00998000 0 0x4000>;
1170 clock-names = "se";
1171 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1172 pinctrl-names = "default";
1173 pinctrl-0 = <&qup_uart6_default>;
1174 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1175 power-domains = <&rpmhpd SM8350_CX>;
1176 operating-points-v2 = <&qup_opp_table_100mhz>;
1177 status = "disabled";
1178 };
1179
1180 i2c7: i2c@99c000 {
1181 compatible = "qcom,geni-i2c";
1182 reg = <0 0x0099c000 0 0x4000>;
1183 clock-names = "se";
1184 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&qup_i2c7_default>;
1187 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1188 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1189 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1190 dma-names = "tx", "rx";
cf03cd7e
KD		 1191 #address-cells = <1>;
1192 #size-cells = <0>;
1193 status = "disabled";
1194 };
1195
1196 spi7: spi@99c000 {
1197 compatible = "qcom,geni-spi";
1198 reg = <0 0x0099c000 0 0x4000>;
1199 clock-names = "se";
1200 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1201 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1202 power-domains = <&rpmhpd SM8350_CX>;
1203 operating-points-v2 = <&qup_opp_table_100mhz>;
bc08fbf4
BA		 1204 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1205 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1206 dma-names = "tx", "rx";
b7e8f433
VK		 1207 #address-cells = <1>;
1208 #size-cells = <0>;
1209 status = "disabled";
1210 };
1211 };
1212
bc08fbf4 1213 gpi_dma1: dma-controller@a00000 {
b561e225 1214 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 1215 reg = <0 0x00a00000 0 0x60000>;
1216 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1228 dma-channels = <12>;
1229 dma-channel-mask = <0xff>;
1230 iommus = <&apps_smmu 0x56 0x0>;
1231 #dma-cells = <3>;
1232 status = "disabled";
1233 };
1234
06bf656e
JM		 1235 qupv3_id_1: geniqup@ac0000 {
1236 compatible = "qcom,geni-se-qup";
1237 reg = <0x0 0x00ac0000 0x0 0x6000>;
1238 clock-names = "m-ahb", "s-ahb";
1239 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1240 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
9bc2c8fe 1241 iommus = <&apps_smmu 0x43 0>;
06bf656e
JM		 1242 #address-cells = <2>;
1243 #size-cells = <2>;
1244 ranges;
1245 status = "disabled";
1246
89345355
KD		 1247 i2c8: i2c@a80000 {
1248 compatible = "qcom,geni-i2c";
1249 reg = <0 0x00a80000 0 0x4000>;
1250 clock-names = "se";
1251 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1252 pinctrl-names = "default";
1253 pinctrl-0 = <&qup_i2c8_default>;
1254 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1255 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1256 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1257 dma-names = "tx", "rx";
89345355
KD		 1258 #address-cells = <1>;
1259 #size-cells = <0>;
1260 status = "disabled";
1261 };
1262
1263 spi8: spi@a80000 {
1264 compatible = "qcom,geni-spi";
1265 reg = <0 0x00a80000 0 0x4000>;
1266 clock-names = "se";
1267 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1268 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1269 power-domains = <&rpmhpd SM8350_CX>;
1270 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 1271 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1272 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1273 dma-names = "tx", "rx";
89345355
KD		 1274 #address-cells = <1>;
1275 #size-cells = <0>;
1276 status = "disabled";
1277 };
1278
1279 i2c9: i2c@a84000 {
1280 compatible = "qcom,geni-i2c";
1281 reg = <0 0x00a84000 0 0x4000>;
1282 clock-names = "se";
1283 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&qup_i2c9_default>;
1286 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1287 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1288 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1289 dma-names = "tx", "rx";
89345355
KD		 1290 #address-cells = <1>;
1291 #size-cells = <0>;
1292 status = "disabled";
1293 };
1294
1295 spi9: spi@a84000 {
1296 compatible = "qcom,geni-spi";
1297 reg = <0 0x00a84000 0 0x4000>;
1298 clock-names = "se";
1299 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1300 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1301 power-domains = <&rpmhpd SM8350_CX>;
1302 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1303 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1304 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1305 dma-names = "tx", "rx";
89345355
KD		 1306 #address-cells = <1>;
1307 #size-cells = <0>;
1308 status = "disabled";
1309 };
1310
1311 i2c10: i2c@a88000 {
1312 compatible = "qcom,geni-i2c";
1313 reg = <0 0x00a88000 0 0x4000>;
1314 clock-names = "se";
1315 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1316 pinctrl-names = "default";
1317 pinctrl-0 = <&qup_i2c10_default>;
1318 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1319 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1320 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1321 dma-names = "tx", "rx";
89345355
KD		 1322 #address-cells = <1>;
1323 #size-cells = <0>;
1324 status = "disabled";
1325 };
1326
1327 spi10: spi@a88000 {
1328 compatible = "qcom,geni-spi";
1329 reg = <0 0x00a88000 0 0x4000>;
1330 clock-names = "se";
1331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1332 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1333 power-domains = <&rpmhpd SM8350_CX>;
1334 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1335 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1336 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1337 dma-names = "tx", "rx";
89345355
KD		 1338 #address-cells = <1>;
1339 #size-cells = <0>;
1340 status = "disabled";
1341 };
1342
1343 i2c11: i2c@a8c000 {
1344 compatible = "qcom,geni-i2c";
1345 reg = <0 0x00a8c000 0 0x4000>;
1346 clock-names = "se";
1347 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&qup_i2c11_default>;
1350 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1351 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1352 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1353 dma-names = "tx", "rx";
89345355
KD		 1354 #address-cells = <1>;
1355 #size-cells = <0>;
1356 status = "disabled";
1357 };
1358
1359 spi11: spi@a8c000 {
1360 compatible = "qcom,geni-spi";
1361 reg = <0 0x00a8c000 0 0x4000>;
1362 clock-names = "se";
1363 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1364 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1365 power-domains = <&rpmhpd SM8350_CX>;
1366 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1367 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1368 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1369 dma-names = "tx", "rx";
89345355
KD		 1370 #address-cells = <1>;
1371 #size-cells = <0>;
1372 status = "disabled";
1373 };
1374
1375 i2c12: i2c@a90000 {
1376 compatible = "qcom,geni-i2c";
1377 reg = <0 0x00a90000 0 0x4000>;
1378 clock-names = "se";
1379 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1380 pinctrl-names = "default";
1381 pinctrl-0 = <&qup_i2c12_default>;
1382 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1383 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1384 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1385 dma-names = "tx", "rx";
89345355
KD		 1386 #address-cells = <1>;
1387 #size-cells = <0>;
1388 status = "disabled";
1389 };
1390
1391 spi12: spi@a90000 {
1392 compatible = "qcom,geni-spi";
1393 reg = <0 0x00a90000 0 0x4000>;
1394 clock-names = "se";
1395 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1396 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1397 power-domains = <&rpmhpd SM8350_CX>;
1398 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1399 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1400 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1401 dma-names = "tx", "rx";
89345355
KD		 1402 #address-cells = <1>;
1403 #size-cells = <0>;
1404 status = "disabled";
1405 };
1406
06bf656e
JM		 1407 i2c13: i2c@a94000 {
1408 compatible = "qcom,geni-i2c";
1409 reg = <0 0x00a94000 0 0x4000>;
1410 clock-names = "se";
1411 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1412 pinctrl-names = "default";
89345355 1413 pinctrl-0 = <&qup_i2c13_default>;
06bf656e 1414 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1415 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1416 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1417 dma-names = "tx", "rx";
06bf656e
JM		 1418 #address-cells = <1>;
1419 #size-cells = <0>;
1420 status = "disabled";
1421 };
89345355
KD		 1422
1423 spi13: spi@a94000 {
1424 compatible = "qcom,geni-spi";
1425 reg = <0 0x00a94000 0 0x4000>;
1426 clock-names = "se";
1427 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1428 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1429 power-domains = <&rpmhpd SM8350_CX>;
1430 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1431 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1432 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1433 dma-names = "tx", "rx";
89345355
KD		 1434 #address-cells = <1>;
1435 #size-cells = <0>;
1436 status = "disabled";
1437 };
06bf656e
JM		 1438 };
1439
1417372f
DB		 1440 rng: rng@10d3000 {
1441 compatible = "qcom,prng-ee";
1442 reg = <0 0x010d3000 0 0x1000>;
1443 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1444 clock-names = "core";
1445 };
1446
da6b2482
VK		 1447 config_noc: interconnect@1500000 {
1448 compatible = "qcom,sm8350-config-noc";
1449 reg = <0 0x01500000 0 0xa580>;
4f287e31 1450 #interconnect-cells = <2>;
da6b2482
VK		 1451 qcom,bcm-voters = <&apps_bcm_voter>;
1452 };
1453
1454 mc_virt: interconnect@1580000 {
1455 compatible = "qcom,sm8350-mc-virt";
1456 reg = <0 0x01580000 0 0x1000>;
4f287e31 1457 #interconnect-cells = <2>;
da6b2482
VK		 1458 qcom,bcm-voters = <&apps_bcm_voter>;
1459 };
1460
1461 system_noc: interconnect@1680000 {
1462 compatible = "qcom,sm8350-system-noc";
1463 reg = <0 0x01680000 0 0x1c200>;
4f287e31 1464 #interconnect-cells = <2>;
da6b2482
VK		 1465 qcom,bcm-voters = <&apps_bcm_voter>;
1466 };
1467
1468 aggre1_noc: interconnect@16e0000 {
1469 compatible = "qcom,sm8350-aggre1-noc";
1470 reg = <0 0x016e0000 0 0x1f180>;
4f287e31 1471 #interconnect-cells = <2>;
da6b2482
VK		 1472 qcom,bcm-voters = <&apps_bcm_voter>;
1473 };
1474
1475 aggre2_noc: interconnect@1700000 {
1476 compatible = "qcom,sm8350-aggre2-noc";
1477 reg = <0 0x01700000 0 0x33000>;
4f287e31 1478 #interconnect-cells = <2>;
da6b2482
VK		 1479 qcom,bcm-voters = <&apps_bcm_voter>;
1480 };
1481
1482 mmss_noc: interconnect@1740000 {
1483 compatible = "qcom,sm8350-mmss-noc";
1484 reg = <0 0x01740000 0 0x1f080>;
4f287e31 1485 #interconnect-cells = <2>;
da6b2482
VK		 1486 qcom,bcm-voters = <&apps_bcm_voter>;
1487 };
1488
6daee406
DB		 1489 pcie0: pci@1c00000 {
1490 compatible = "qcom,pcie-sm8350";
1491 reg = <0 0x01c00000 0 0x3000>,
1492 <0 0x60000000 0 0xf1d>,
1493 <0 0x60000f20 0 0xa8>,
1494 <0 0x60001000 0 0x1000>,
1495 <0 0x60100000 0 0x100000>;
1496 reg-names = "parf", "dbi", "elbi", "atu", "config";
1497 device_type = "pci";
1498 linux,pci-domain = <0>;
1499 bus-range = <0x00 0xff>;
1500 num-lanes = <1>;
1501
1502 #address-cells = <3>;
1503 #size-cells = <2>;
1504
cf4e716e
MS		 1505 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1506 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
6daee406
DB		 1507
1508 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1509 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1510 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1516 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1517 "msi4", "msi5", "msi6", "msi7";
1518 #interrupt-cells = <1>;
1519 interrupt-map-mask = <0 0 0 0x7>;
1520 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1521 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1522 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1523 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1524
1525 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1526 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1527 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1528 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1529 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1530 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1531 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1532 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1533 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
1534 clock-names = "aux",
1535 "cfg",
1536 "bus_master",
1537 "bus_slave",
1538 "slave_q2a",
1539 "tbu",
1540 "ddrss_sf_tbu",
1541 "aggre1",
1542 "aggre0";
1543
6daee406
DB		 1544 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1545 <0x100 &apps_smmu 0x1c01 0x1>;
1546
1547 resets = <&gcc GCC_PCIE_0_BCR>;
1548 reset-names = "pci";
1549
1550 power-domains = <&gcc PCIE_0_GDSC>;
1551
1552 phys = <&pcie0_phy>;
1553 phy-names = "pciephy";
1554
1555 status = "disabled";
1556 };
1557
1558 pcie0_phy: phy@1c06000 {
1559 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1560 reg = <0 0x01c06000 0 0x2000>;
1561 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1562 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1563 <&gcc GCC_PCIE_0_CLKREF_EN>,
1564 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
1565 <&gcc GCC_PCIE_0_PIPE_CLK>;
1566 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1567
1568 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1569 reset-names = "phy";
1570
1571 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1572 assigned-clock-rates = <100000000>;
1573
1574 #clock-cells = <0>;
1575 clock-output-names = "pcie_0_pipe_clk";
1576
1577 #phy-cells = <0>;
1578
1579 status = "disabled";
1580 };
1581
1582 pcie1: pci@1c08000 {
1583 compatible = "qcom,pcie-sm8350";
1584 reg = <0 0x01c08000 0 0x3000>,
1585 <0 0x40000000 0 0xf1d>,
1586 <0 0x40000f20 0 0xa8>,
1587 <0 0x40001000 0 0x1000>,
1588 <0 0x40100000 0 0x100000>;
1589 reg-names = "parf", "dbi", "elbi", "atu", "config";
1590 device_type = "pci";
1591 linux,pci-domain = <1>;
1592 bus-range = <0x00 0xff>;
1593 num-lanes = <2>;
1594
1595 #address-cells = <3>;
1596 #size-cells = <2>;
1597
cf4e716e
MS		 1598 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1599 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
6daee406
DB		 1600
1601 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1602 interrupt-names = "msi";
1603 #interrupt-cells = <1>;
1604 interrupt-map-mask = <0 0 0 0x7>;
1605 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1606 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1607 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1608 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1609
1610 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1611 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1612 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1613 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1614 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1615 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1616 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1617 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1618 clock-names = "aux",
1619 "cfg",
1620 "bus_master",
1621 "bus_slave",
1622 "slave_q2a",
1623 "tbu",
1624 "ddrss_sf_tbu",
1625 "aggre1";
1626
6daee406
DB		 1627 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1628 <0x100 &apps_smmu 0x1c81 0x1>;
1629
1630 resets = <&gcc GCC_PCIE_1_BCR>;
1631 reset-names = "pci";
1632
1633 power-domains = <&gcc PCIE_1_GDSC>;
1634
1635 phys = <&pcie1_phy>;
1636 phy-names = "pciephy";
1637
1638 status = "disabled";
1639 };
1640
ab98c21b 1641 pcie1_phy: phy@1c0e000 {
6daee406
DB		 1642 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1643 reg = <0 0x01c0e000 0 0x2000>;
1644 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1645 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1646 <&gcc GCC_PCIE_1_CLKREF_EN>,
1647 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
1648 <&gcc GCC_PCIE_1_PIPE_CLK>;
1649 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1650
1651 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1652 reset-names = "phy";
1653
1654 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1655 assigned-clock-rates = <100000000>;
1656
1657 #clock-cells = <0>;
1658 clock-output-names = "pcie_1_pipe_clk";
1659
1660 #phy-cells = <0>;
1661
1662 status = "disabled";
1663 };
1664
1417372f
DB		 1665 ufs_mem_hc: ufshc@1d84000 {
1666 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1667 "jedec,ufs-2.0";
1668 reg = <0 0x01d84000 0 0x3000>;
1669 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1670 phys = <&ufs_mem_phy_lanes>;
1671 phy-names = "ufsphy";
1672 lanes-per-direction = <2>;
1673 #reset-cells = <1>;
1674 resets = <&gcc GCC_UFS_PHY_BCR>;
1675 reset-names = "rst";
1676
1677 power-domains = <&gcc UFS_PHY_GDSC>;
1678
1679 iommus = <&apps_smmu 0xe0 0x0>;
e607b3c1 1680 dma-coherent;
1417372f
DB		 1681
1682 clock-names =
1683 "core_clk",
1684 "bus_aggr_clk",
1685 "iface_clk",
1686 "core_clk_unipro",
1687 "ref_clk",
1688 "tx_lane0_sync_clk",
1689 "rx_lane0_sync_clk",
1690 "rx_lane1_sync_clk";
1691 clocks =
1692 <&gcc GCC_UFS_PHY_AXI_CLK>,
1693 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1694 <&gcc GCC_UFS_PHY_AHB_CLK>,
1695 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1696 <&rpmhcc RPMH_CXO_CLK>,
1697 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1698 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1699 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1700 freq-table-hz =
1701 <75000000 300000000>,
1702 <0 0>,
1703 <0 0>,
1704 <75000000 300000000>,
1705 <0 0>,
1706 <0 0>,
1707 <0 0>,
1708 <0 0>;
1709 status = "disabled";
da6b2482
VK		 1710 };
1711
1417372f
DB		 1712 ufs_mem_phy: phy@1d87000 {
1713 compatible = "qcom,sm8350-qmp-ufs-phy";
1714 reg = <0 0x01d87000 0 0x1c4>;
1715 #address-cells = <2>;
1716 #size-cells = <2>;
1717 ranges;
1718 clock-names = "ref",
1719 "ref_aux";
1720 clocks = <&rpmhcc RPMH_CXO_CLK>,
1721 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1722
1723 resets = <&ufs_mem_hc 0>;
1724 reset-names = "ufsphy";
1725 status = "disabled";
1726
1727 ufs_mem_phy_lanes: phy@1d87400 {
1728 reg = <0 0x01d87400 0 0x188>,
1729 <0 0x01d87600 0 0x200>,
1730 <0 0x01d87c00 0 0x200>,
1731 <0 0x01d87800 0 0x188>,
1732 <0 0x01d87a00 0 0x200>;
1733 #clock-cells = <1>;
1734 #phy-cells = <0>;
1735 };
da6b2482
VK		 1736 };
1737
f1040a7f
BS		 1738 cryptobam: dma-controller@1dc4000 {
1739 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1740 reg = <0 0x01dc4000 0 0x24000>;
1741 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1742 #dma-cells = <1>;
1743 qcom,ee = <0>;
1744 qcom,controlled-remotely;
1745 iommus = <&apps_smmu 0x594 0x0011>,
1746 <&apps_smmu 0x596 0x0011>;
4d29db20
KK		 1747 /* FIXME: Probing BAM DMA causes some abort and system hang */
1748 status = "fail";
f1040a7f
BS		 1749 };
1750
1751 crypto: crypto@1dfa000 {
1752 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1753 reg = <0 0x01dfa000 0 0x6000>;
1754 dmas = <&cryptobam 4>, <&cryptobam 5>;
1755 dma-names = "rx", "tx";
1756 iommus = <&apps_smmu 0x594 0x0011>,
1757 <&apps_smmu 0x596 0x0011>;
1758 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1759 interconnect-names = "memory";
4d29db20
KK		 1760 /* FIXME: dependency BAM DMA is disabled */
1761 status = "disabled";
f1040a7f
BS		 1762 };
1763
f11d3e7d
AE		 1764 ipa: ipa@1e40000 {
1765 compatible = "qcom,sm8350-ipa";
1766
1767 iommus = <&apps_smmu 0x5c0 0x0>,
1768 <&apps_smmu 0x5c2 0x0>;
f3c08ae6
KD		 1769 reg = <0 0x01e40000 0 0x8000>,
1770 <0 0x01e50000 0 0x4b20>,
1771 <0 0x01e04000 0 0x23000>;
f11d3e7d
AE		 1772 reg-names = "ipa-reg",
1773 "ipa-shared",
1774 "gsi";
1775
1776 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1777 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1778 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1779 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1780 interrupt-names = "ipa",
1781 "gsi",
1782 "ipa-clock-query",
1783 "ipa-setup-ready";
1784
1785 clocks = <&rpmhcc RPMH_IPA_CLK>;
1786 clock-names = "core";
1787
4f287e31
RF		 1788 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1789 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
84173ca3
AE		 1790 interconnect-names = "memory",
1791 "config";
f11d3e7d 1792
73419e4d
AE		 1793 qcom,qmp = <&aoss_qmp>;
1794
f11d3e7d
AE		 1795 qcom,smem-states = <&ipa_smp2p_out 0>,
1796 <&ipa_smp2p_out 1>;
1797 qcom,smem-state-names = "ipa-clock-enabled-valid",
1798 "ipa-clock-enabled";
1799
1800 status = "disabled";
1801 };
1802
b7e8f433
VK		 1803 tcsr_mutex: hwlock@1f40000 {
1804 compatible = "qcom,tcsr-mutex";
1805 reg = <0x0 0x01f40000 0x0 0x40000>;
1806 #hwlock-cells = <1>;
1807 };
1808
54af0ceb
DB		 1809 gpu: gpu@3d00000 {
1810 compatible = "qcom,adreno-660.1", "qcom,adreno";
1811
1812 reg = <0 0x03d00000 0 0x40000>,
1813 <0 0x03d9e000 0 0x1000>,
1814 <0 0x03d61000 0 0x800>;
1815 reg-names = "kgsl_3d0_reg_memory",
1816 "cx_mem",
1817 "cx_dbgc";
1818
1819 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1820
1821 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1822
1823 operating-points-v2 = <&gpu_opp_table>;
1824
1825 qcom,gmu = <&gmu>;
1826
1827 status = "disabled";
1828
1829 zap-shader {
1830 memory-region = <&pil_gpu_mem>;
1831 };
1832
1833 /* note: downstream checks gpu binning for 670 Mhz */
1834 gpu_opp_table: opp-table {
1835 compatible = "operating-points-v2";
1836
1837 opp-840000000 {
1838 opp-hz = /bits/ 64 <840000000>;
1839 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1840 };
1841
1842 opp-778000000 {
1843 opp-hz = /bits/ 64 <778000000>;
1844 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1845 };
1846
1847 opp-738000000 {
1848 opp-hz = /bits/ 64 <738000000>;
1849 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1850 };
1851
1852 opp-676000000 {
1853 opp-hz = /bits/ 64 <676000000>;
1854 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1855 };
1856
1857 opp-608000000 {
1858 opp-hz = /bits/ 64 <608000000>;
1859 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1860 };
1861
1862 opp-540000000 {
1863 opp-hz = /bits/ 64 <540000000>;
1864 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1865 };
1866
1867 opp-491000000 {
1868 opp-hz = /bits/ 64 <491000000>;
1869 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1870 };
1871
1872 opp-443000000 {
1873 opp-hz = /bits/ 64 <443000000>;
1874 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1875 };
1876
1877 opp-379000000 {
1878 opp-hz = /bits/ 64 <379000000>;
1879 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1880 };
1881
1882 opp-315000000 {
1883 opp-hz = /bits/ 64 <315000000>;
1884 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1885 };
1886 };
1887 };
1888
1889 gmu: gmu@3d6a000 {
1890 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1891
1892 reg = <0 0x03d6a000 0 0x34000>,
1893 <0 0x03de0000 0 0x10000>,
1894 <0 0x0b290000 0 0x10000>;
1895 reg-names = "gmu", "rscc", "gmu_pdc";
1896
1897 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1898 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1899 interrupt-names = "hfi", "gmu";
1900
1901 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1902 <&gpucc GPU_CC_CXO_CLK>,
1903 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1904 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1905 <&gpucc GPU_CC_AHB_CLK>,
1906 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1907 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
1908 clock-names = "gmu",
1909 "cxo",
1910 "axi",
1911 "memnoc",
1912 "ahb",
1913 "hub",
1914 "smmu_vote";
1915
1916 power-domains = <&gpucc GPU_CX_GDSC>,
1917 <&gpucc GPU_GX_GDSC>;
1918 power-domain-names = "cx",
1919 "gx";
1920
1921 iommus = <&adreno_smmu 5 0x400>;
1922
1923 operating-points-v2 = <&gmu_opp_table>;
1924
1925 gmu_opp_table: opp-table {
1926 compatible = "operating-points-v2";
1927
1928 opp-200000000 {
1929 opp-hz = /bits/ 64 <200000000>;
1930 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1931 };
1932 };
1933 };
1934
1935 gpucc: clock-controller@3d90000 {
1936 compatible = "qcom,sm8350-gpucc";
1937 reg = <0 0x03d90000 0 0x9000>;
1938 clocks = <&rpmhcc RPMH_CXO_CLK>,
1939 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1940 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1941 clock-names = "bi_tcxo",
1942 "gcc_gpu_gpll0_clk_src",
1943 "gcc_gpu_gpll0_div_clk_src";
1944 #clock-cells = <1>;
1945 #reset-cells = <1>;
1946 #power-domain-cells = <1>;
1947 };
1948
1949 adreno_smmu: iommu@3da0000 {
78c61b6b
KD		 1950 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
1951 "qcom,smmu-500", "arm,mmu-500";
54af0ceb
DB		 1952 reg = <0 0x03da0000 0 0x20000>;
1953 #iommu-cells = <2>;
1954 #global-interrupts = <2>;
1955 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1964 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1967
1968 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1969 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1970 <&gpucc GPU_CC_AHB_CLK>,
1971 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1972 <&gpucc GPU_CC_CX_GMU_CLK>,
1973 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1974 <&gpucc GPU_CC_HUB_AON_CLK>;
1975 clock-names = "bus",
1976 "iface",
1977 "ahb",
1978 "hlos1_vote_gpu_smmu",
1979 "cx_gmu",
1980 "hub_cx_int",
1981 "hub_aon";
1982
1983 power-domains = <&gpucc GPU_CX_GDSC>;
1984 dma-coherent;
1985 };
1986
1417372f
DB		 1987 lpass_ag_noc: interconnect@3c40000 {
1988 compatible = "qcom,sm8350-lpass-ag-noc";
1989 reg = <0 0x03c40000 0 0xf080>;
1990 #interconnect-cells = <2>;
1991 qcom,bcm-voters = <&apps_bcm_voter>;
1992 };
1993
177fcf0a
VK		 1994 mpss: remoteproc@4080000 {
1995 compatible = "qcom,sm8350-mpss-pas";
1996 reg = <0x0 0x04080000 0x0 0x4040>;
1997
1998 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1999 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2000 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2001 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2002 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2003 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2004 interrupt-names = "wdog", "fatal", "ready", "handover",
2005 "stop-ack", "shutdown-ack";
2006
2007 clocks = <&rpmhcc RPMH_CXO_CLK>;
2008 clock-names = "xo";
2009
d0e285c3
RF		 2010 power-domains = <&rpmhpd SM8350_CX>,
2011 <&rpmhpd SM8350_MSS>;
6b7cb2d2 2012 power-domain-names = "cx", "mss";
177fcf0a 2013
4f287e31 2014 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
da6b2482 2015
177fcf0a
VK		 2016 memory-region = <&pil_modem_mem>;
2017
6b7cb2d2
SS		 2018 qcom,qmp = <&aoss_qmp>;
2019
177fcf0a
VK		 2020 qcom,smem-states = <&smp2p_modem_out 0>;
2021 qcom,smem-state-names = "stop";
2022
2023 status = "disabled";
2024
2025 glink-edge {
2026 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2027 IPCC_MPROC_SIGNAL_GLINK_QMP
2028 IRQ_TYPE_EDGE_RISING>;
2029 mboxes = <&ipcc IPCC_CLIENT_MPSS
2030 IPCC_MPROC_SIGNAL_GLINK_QMP>;
177fcf0a
VK		 2031 label = "modem";
2032 qcom,remote-pid = <1>;
2033 };
2034 };
2035
1417372f
DB		 2036 slpi: remoteproc@5c00000 {
2037 compatible = "qcom,sm8350-slpi-pas";
2038 reg = <0 0x05c00000 0 0x4000>;
2039
2040 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2041 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2042 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2043 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2044 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2045 interrupt-names = "wdog", "fatal", "ready",
2046 "handover", "stop-ack";
2047
2048 clocks = <&rpmhcc RPMH_CXO_CLK>;
2049 clock-names = "xo";
2050
2051 power-domains = <&rpmhpd SM8350_LCX>,
2052 <&rpmhpd SM8350_LMX>;
2053 power-domain-names = "lcx", "lmx";
2054
2055 memory-region = <&pil_slpi_mem>;
2056
2057 qcom,qmp = <&aoss_qmp>;
2058
2059 qcom,smem-states = <&smp2p_slpi_out 0>;
2060 qcom,smem-state-names = "stop";
2061
2062 status = "disabled";
2063
2064 glink-edge {
2065 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2066 IPCC_MPROC_SIGNAL_GLINK_QMP
2067 IRQ_TYPE_EDGE_RISING>;
2068 mboxes = <&ipcc IPCC_CLIENT_SLPI
2069 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2070
2071 label = "slpi";
2072 qcom,remote-pid = <3>;
2073
2074 fastrpc {
2075 compatible = "qcom,fastrpc";
2076 qcom,glink-channels = "fastrpcglink-apps-dsp";
2077 label = "sdsp";
2078 qcom,non-secure-domain;
2079 #address-cells = <1>;
2080 #size-cells = <0>;
2081
2082 compute-cb@1 {
2083 compatible = "qcom,fastrpc-compute-cb";
2084 reg = <1>;
2085 iommus = <&apps_smmu 0x0541 0x0>;
2086 };
2087
2088 compute-cb@2 {
2089 compatible = "qcom,fastrpc-compute-cb";
2090 reg = <2>;
2091 iommus = <&apps_smmu 0x0542 0x0>;
2092 };
2093
2094 compute-cb@3 {
2095 compatible = "qcom,fastrpc-compute-cb";
2096 reg = <3>;
2097 iommus = <&apps_smmu 0x0543 0x0>;
2098 /* note: shared-cb = <4> in downstream */
2099 };
2100 };
2101 };
2102 };
2103
f5f6bd58
DB		 2104 sdhc_2: mmc@8804000 {
2105 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2106 reg = <0 0x08804000 0 0x1000>;
177fcf0a 2107
f5f6bd58
DB		 2108 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2109 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2110 interrupt-names = "hc_irq", "pwr_irq";
177fcf0a 2111
f5f6bd58
DB		 2112 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2113 <&gcc GCC_SDCC2_APPS_CLK>,
2114 <&rpmhcc RPMH_CXO_CLK>;
2115 clock-names = "iface", "core", "xo";
2116 resets = <&gcc GCC_SDCC2_BCR>;
2117 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2118 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2119 interconnect-names = "sdhc-ddr","cpu-sdhc";
2120 iommus = <&apps_smmu 0x4a0 0x0>;
2121 power-domains = <&rpmhpd SM8350_CX>;
2122 operating-points-v2 = <&sdhc2_opp_table>;
2123 bus-width = <4>;
2124 dma-coherent;
177fcf0a 2125
f5f6bd58 2126 status = "disabled";
da6b2482 2127
f5f6bd58
DB		 2128 sdhc2_opp_table: opp-table {
2129 compatible = "operating-points-v2";
177fcf0a 2130
f5f6bd58
DB		 2131 opp-100000000 {
2132 opp-hz = /bits/ 64 <100000000>;
2133 required-opps = <&rpmhpd_opp_low_svs>;
2134 };
6b7cb2d2 2135
f5f6bd58
DB		 2136 opp-202000000 {
2137 opp-hz = /bits/ 64 <202000000>;
2138 required-opps = <&rpmhpd_opp_svs_l1>;
2139 };
2140 };
2141 };
177fcf0a 2142
f5f6bd58
DB		 2143 usb_1_hsphy: phy@88e3000 {
2144 compatible = "qcom,sm8350-usb-hs-phy",
2145 "qcom,usb-snps-hs-7nm-phy";
2146 reg = <0 0x088e3000 0 0x400>;
177fcf0a 2147 status = "disabled";
f5f6bd58 2148 #phy-cells = <0>;
177fcf0a 2149
f5f6bd58
DB		 2150 clocks = <&rpmhcc RPMH_CXO_CLK>;
2151 clock-names = "ref";
177fcf0a 2152
f5f6bd58
DB		 2153 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2154 };
178056a4 2155
f5f6bd58
DB		 2156 usb_2_hsphy: phy@88e4000 {
2157 compatible = "qcom,sm8250-usb-hs-phy",
2158 "qcom,usb-snps-hs-7nm-phy";
2159 reg = <0 0x088e4000 0 0x400>;
2160 status = "disabled";
2161 #phy-cells = <0>;
178056a4 2162
f5f6bd58
DB		 2163 clocks = <&rpmhcc RPMH_CXO_CLK>;
2164 clock-names = "ref";
e780fb31 2165
6d91e201 2166 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
e780fb31
JP		 2167 };
2168
a560ab70 2169 usb_1_qmpphy: phy@88e8000 {
2458a305
NA		 2170 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2171 reg = <0 0x088e8000 0 0x3000>;
e780fb31 2172
6d91e201 2173 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
e780fb31 2174 <&rpmhcc RPMH_CXO_CLK>,
2458a305
NA		 2175 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2176 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2177 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
e780fb31 2178
6d91e201
VK		 2179 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2180 <&gcc GCC_USB3_PHY_PRIM_BCR>;
e780fb31
JP		 2181 reset-names = "phy", "common";
2182
2458a305
NA		 2183 #clock-cells = <1>;
2184 #phy-cells = <1>;
2185
2186 status = "disabled";
d8313125
NA		 2187
2188 ports {
2189 #address-cells = <1>;
2190 #size-cells = <0>;
2191
2192 port@0 {
2193 reg = <0>;
2194
2195 usb_1_qmpphy_out: endpoint {
2196 };
2197 };
2198
2199 port@1 {
2200 reg = <1>;
2201
2202 usb_1_qmpphy_usb_ss_in: endpoint {
2203 };
2204 };
2205
2206 port@2 {
2207 reg = <2>;
2208
2209 usb_1_qmpphy_dp_in: endpoint {
2210 };
2211 };
2212 };
e780fb31
JP		 2213 };
2214
2215 usb_2_qmpphy: phy-wrapper@88eb000 {
2216 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2217 reg = <0 0x088eb000 0 0x200>;
2218 status = "disabled";
e780fb31
JP		 2219 #address-cells = <2>;
2220 #size-cells = <2>;
2221 ranges;
2222
6d91e201 2223 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
e780fb31 2224 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 2225 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2226 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
e780fb31
JP		 2227 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2228
6d91e201
VK		 2229 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2230 <&gcc GCC_USB3_PHY_SEC_BCR>;
e780fb31
JP		 2231 reset-names = "phy", "common";
2232
2233 usb_2_ssphy: phy@88ebe00 {
2234 reg = <0 0x088ebe00 0 0x200>,
2235 <0 0x088ec000 0 0x200>,
2236 <0 0x088eb200 0 0x1100>;
2237 #phy-cells = <0>;
af551554 2238 #clock-cells = <0>;
6d91e201 2239 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
e780fb31
JP		 2240 clock-names = "pipe0";
2241 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2242 };
2243 };
2244
1dee9e3b 2245 dc_noc: interconnect@90c0000 {
da6b2482
VK		 2246 compatible = "qcom,sm8350-dc-noc";
2247 reg = <0 0x090c0000 0 0x4200>;
4f287e31 2248 #interconnect-cells = <2>;
da6b2482
VK		 2249 qcom,bcm-voters = <&apps_bcm_voter>;
2250 };
2251
2252 gem_noc: interconnect@9100000 {
2253 compatible = "qcom,sm8350-gem-noc";
2254 reg = <0 0x09100000 0 0xb4000>;
4f287e31 2255 #interconnect-cells = <2>;
da6b2482
VK		 2256 qcom,bcm-voters = <&apps_bcm_voter>;
2257 };
2258
9ac8999e
KD		 2259 system-cache-controller@9200000 {
2260 compatible = "qcom,sm8350-llcc";
7ae317cb
MS		 2261 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2262 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2263 <0 0x09600000 0 0x58000>;
2264 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2265 "llcc3_base", "llcc_broadcast_base";
9ac8999e
KD		 2266 };
2267
1417372f
DB		 2268 compute_noc: interconnect@a0c0000 {
2269 compatible = "qcom,sm8350-compute-noc";
2270 reg = <0 0x0a0c0000 0 0xa180>;
2271 #interconnect-cells = <2>;
2272 qcom,bcm-voters = <&apps_bcm_voter>;
2273 };
2274
e780fb31
JP		 2275 usb_1: usb@a6f8800 {
2276 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2277 reg = <0 0x0a6f8800 0 0x400>;
2278 status = "disabled";
2279 #address-cells = <2>;
2280 #size-cells = <2>;
2281 ranges;
2282
6d91e201
VK		 2283 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2284 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2285 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
8d5fd4e4
KK		 2286 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2287 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2288 clock-names = "cfg_noc",
2289 "core",
2290 "iface",
2291 "sleep",
2292 "mock_utmi";
e780fb31 2293
6d91e201
VK		 2294 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2295 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
e780fb31
JP		 2296 assigned-clock-rates = <19200000>, <200000000>;
2297
2298 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
5b7e3499 2299 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
e780fb31 2300 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
5b7e3499
JH		 2301 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2302 interrupt-names = "hs_phy_irq",
2303 "ss_phy_irq",
2304 "dm_hs_phy_irq",
2305 "dp_hs_phy_irq";
e780fb31 2306
6d91e201 2307 power-domains = <&gcc USB30_PRIM_GDSC>;
e780fb31 2308
6d91e201 2309 resets = <&gcc GCC_USB30_PRIM_BCR>;
e780fb31 2310
8b51dc86
AV		 2311 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2312 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2313 interconnect-names = "usb-ddr", "apps-usb";
2314
2aa2b50d 2315 usb_1_dwc3: usb@a600000 {
e780fb31
JP		 2316 compatible = "snps,dwc3";
2317 reg = <0 0x0a600000 0 0xcd00>;
2318 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2319 iommus = <&apps_smmu 0x0 0x0>;
2320 snps,dis_u2_susphy_quirk;
2321 snps,dis_enblslpm_quirk;
2458a305 2322 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
e780fb31 2323 phy-names = "usb2-phy", "usb3-phy";
75b81e5a
NA		 2324
2325 ports {
2326 #address-cells = <1>;
2327 #size-cells = <0>;
2328
2329 port@0 {
2330 reg = <0>;
2331
2332 usb_1_dwc3_hs: endpoint {
2333 };
2334 };
2335
2336 port@1 {
2337 reg = <1>;
2338
2339 usb_1_dwc3_ss: endpoint {
2340 };
2341 };
2342 };
e780fb31
JP		 2343 };
2344 };
2345
2346 usb_2: usb@a8f8800 {
2347 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2348 reg = <0 0x0a8f8800 0 0x400>;
2349 status = "disabled";
2350 #address-cells = <2>;
2351 #size-cells = <2>;
2352 ranges;
2353
6d91e201
VK		 2354 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2355 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2356 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
6d91e201 2357 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
8d5fd4e4 2358 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
6d91e201 2359 <&gcc GCC_USB3_SEC_CLKREF_EN>;
8d5fd4e4
KK		 2360 clock-names = "cfg_noc",
2361 "core",
2362 "iface",
2363 "sleep",
2364 "mock_utmi",
2365 "xo";
e780fb31 2366
6d91e201
VK		 2367 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2368 <&gcc GCC_USB30_SEC_MASTER_CLK>;
e780fb31
JP		 2369 assigned-clock-rates = <19200000>, <200000000>;
2370
2371 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
5b7e3499 2372 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
e780fb31 2373 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
5b7e3499
JH		 2374 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2375 interrupt-names = "hs_phy_irq",
2376 "ss_phy_irq",
2377 "dm_hs_phy_irq",
2378 "dp_hs_phy_irq";
e780fb31 2379
6d91e201 2380 power-domains = <&gcc USB30_SEC_GDSC>;
e780fb31 2381
6d91e201 2382 resets = <&gcc GCC_USB30_SEC_BCR>;
e780fb31 2383
8b51dc86
AV		 2384 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2386 interconnect-names = "usb-ddr", "apps-usb";
2387
2aa2b50d 2388 usb_2_dwc3: usb@a800000 {
e780fb31
JP		 2389 compatible = "snps,dwc3";
2390 reg = <0 0x0a800000 0 0xcd00>;
2391 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2392 iommus = <&apps_smmu 0x20 0x0>;
2393 snps,dis_u2_susphy_quirk;
2394 snps,dis_enblslpm_quirk;
2395 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2396 phy-names = "usb2-phy", "usb3-phy";
2397 };
2398 };
177fcf0a 2399
d4a44105
RF		 2400 mdss: display-subsystem@ae00000 {
2401 compatible = "qcom,sm8350-mdss";
2402 reg = <0 0x0ae00000 0 0x1000>;
2403 reg-names = "mdss";
2404
2405 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2406 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2407 interconnect-names = "mdp0-mem", "mdp1-mem";
2408
2409 power-domains = <&dispcc MDSS_GDSC>;
2410 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2411
2412 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2413 <&gcc GCC_DISP_HF_AXI_CLK>,
2414 <&gcc GCC_DISP_SF_AXI_CLK>,
2415 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2416 clock-names = "iface", "bus", "nrt_bus", "core";
2417
2418 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2419 interrupt-controller;
2420 #interrupt-cells = <1>;
2421
2422 iommus = <&apps_smmu 0x820 0x402>;
2423
2424 status = "disabled";
2425
2426 #address-cells = <2>;
2427 #size-cells = <2>;
2428 ranges;
2429
2430 dpu_opp_table: opp-table {
2431 compatible = "operating-points-v2";
2432
2433 /* TODO: opp-200000000 should work with
2434 * &rpmhpd_opp_low_svs, but one some of
2435 * sm8350_hdk boards reboot using this
2436 * opp.
2437 */
2438 opp-200000000 {
2439 opp-hz = /bits/ 64 <200000000>;
2440 required-opps = <&rpmhpd_opp_svs>;
2441 };
2442
2443 opp-300000000 {
2444 opp-hz = /bits/ 64 <300000000>;
2445 required-opps = <&rpmhpd_opp_svs>;
2446 };
2447
2448 opp-345000000 {
2449 opp-hz = /bits/ 64 <345000000>;
2450 required-opps = <&rpmhpd_opp_svs_l1>;
2451 };
2452
2453 opp-460000000 {
2454 opp-hz = /bits/ 64 <460000000>;
2455 required-opps = <&rpmhpd_opp_nom>;
2456 };
2457 };
2458
2459 mdss_mdp: display-controller@ae01000 {
2460 compatible = "qcom,sm8350-dpu";
2461 reg = <0 0x0ae01000 0 0x8f000>,
2462 <0 0x0aeb0000 0 0x2008>;
2463 reg-names = "mdp", "vbif";
2464
2465 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2466 <&gcc GCC_DISP_SF_AXI_CLK>,
2467 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2468 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2469 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2470 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2471 clock-names = "bus",
2472 "nrt_bus",
2473 "iface",
2474 "lut",
2475 "core",
2476 "vsync";
2477
2478 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2479 assigned-clock-rates = <19200000>;
2480
2481 operating-points-v2 = <&dpu_opp_table>;
2482 power-domains = <&rpmhpd SM8350_MMCX>;
2483
2484 interrupt-parent = <&mdss>;
2485 interrupts = <0>;
2486
2487 ports {
2488 #address-cells = <1>;
2489 #size-cells = <0>;
2490
2491 port@0 {
2492 reg = <0>;
2493 dpu_intf1_out: endpoint {
2a07efb8 2494 remote-endpoint = <&mdss_dsi0_in>;
d4a44105
RF		 2495 };
2496 };
b904227a
KD		 2497
2498 port@1 {
2499 reg = <1>;
2500 dpu_intf2_out: endpoint {
2501 remote-endpoint = <&mdss_dsi1_in>;
2502 };
2503 };
a2802008
NA		 2504
2505 port@2 {
2506 reg = <2>;
2507 dpu_intf0_out: endpoint {
2508 remote-endpoint = <&mdss_dp_in>;
2509 };
2510 };
2511 };
2512 };
2513
2514 mdss_dp: displayport-controller@ae90000 {
2515 compatible = "qcom,sm8350-dp";
2516 reg = <0 0xae90000 0 0x200>,
2517 <0 0xae90200 0 0x200>,
2518 <0 0xae90400 0 0x600>,
2519 <0 0xae91000 0 0x400>,
2520 <0 0xae91400 0 0x400>;
2521 interrupt-parent = <&mdss>;
2522 interrupts = <12>;
2523 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2524 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2525 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2526 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
2527 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
2528 clock-names = "core_iface",
2529 "core_aux",
2530 "ctrl_link",
2531 "ctrl_link_iface",
2532 "stream_pixel";
2533
2534 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2535 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
2536 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2537 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2538
2539 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2540 phy-names = "dp";
2541
2542 #sound-dai-cells = <0>;
2543
2544 operating-points-v2 = <&dp_opp_table>;
2545 power-domains = <&rpmhpd SM8350_MMCX>;
2546
2547 status = "disabled";
2548
2549 ports {
2550 #address-cells = <1>;
2551 #size-cells = <0>;
2552
2553 port@0 {
2554 reg = <0>;
2555 mdss_dp_in: endpoint {
2556 remote-endpoint = <&dpu_intf0_out>;
2557 };
2558 };
2559 };
2560
2561 dp_opp_table: opp-table {
2562 compatible = "operating-points-v2";
2563
2564 opp-160000000 {
2565 opp-hz = /bits/ 64 <160000000>;
2566 required-opps = <&rpmhpd_opp_low_svs>;
2567 };
2568
2569 opp-270000000 {
2570 opp-hz = /bits/ 64 <270000000>;
2571 required-opps = <&rpmhpd_opp_svs>;
2572 };
2573
2574 opp-540000000 {
2575 opp-hz = /bits/ 64 <540000000>;
2576 required-opps = <&rpmhpd_opp_svs_l1>;
2577 };
2578
2579 opp-810000000 {
2580 opp-hz = /bits/ 64 <810000000>;
2581 required-opps = <&rpmhpd_opp_nom>;
2582 };
d4a44105
RF		 2583 };
2584 };
2585
2586 mdss_dsi0: dsi@ae94000 {
d7133d6d 2587 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
d4a44105
RF		 2588 reg = <0 0x0ae94000 0 0x400>;
2589 reg-names = "dsi_ctrl";
2590
2591 interrupt-parent = <&mdss>;
2592 interrupts = <4>;
2593
2594 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2595 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2596 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2597 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2598 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2599 <&gcc GCC_DISP_HF_AXI_CLK>;
2600 clock-names = "byte",
2601 "byte_intf",
2602 "pixel",
2603 "core",
2604 "iface",
2605 "bus";
2606
2607 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2608 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2609 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2610 <&mdss_dsi0_phy 1>;
2611
2612 operating-points-v2 = <&dsi0_opp_table>;
2613 power-domains = <&rpmhpd SM8350_MMCX>;
2614
2615 phys = <&mdss_dsi0_phy>;
2616
6636818e
KD		 2617 #address-cells = <1>;
2618 #size-cells = <0>;
2619
d4a44105
RF		 2620 status = "disabled";
2621
2622 dsi0_opp_table: opp-table {
2623 compatible = "operating-points-v2";
2624
2625 /* TODO: opp-187500000 should work with
2626 * &rpmhpd_opp_low_svs, but one some of
2627 * sm8350_hdk boards reboot using this
2628 * opp.
2629 */
2630 opp-187500000 {
2631 opp-hz = /bits/ 64 <187500000>;
2632 required-opps = <&rpmhpd_opp_svs>;
2633 };
2634
2635 opp-300000000 {
2636 opp-hz = /bits/ 64 <300000000>;
2637 required-opps = <&rpmhpd_opp_svs>;
2638 };
2639
2640 opp-358000000 {
2641 opp-hz = /bits/ 64 <358000000>;
2642 required-opps = <&rpmhpd_opp_svs_l1>;
2643 };
2644 };
2645
2646 ports {
2647 #address-cells = <1>;
2648 #size-cells = <0>;
2649
2650 port@0 {
2651 reg = <0>;
2a07efb8 2652 mdss_dsi0_in: endpoint {
d4a44105
RF		 2653 remote-endpoint = <&dpu_intf1_out>;
2654 };
2655 };
2656
2657 port@1 {
2658 reg = <1>;
2a07efb8 2659 mdss_dsi0_out: endpoint {
d4a44105
RF		 2660 };
2661 };
2662 };
2663 };
2664
51f83fbb
DB		 2665 mdss_dsi0_phy: phy@ae94400 {
2666 compatible = "qcom,sm8350-dsi-phy-5nm";
2667 reg = <0 0x0ae94400 0 0x200>,
2668 <0 0x0ae94600 0 0x280>,
2669 <0 0x0ae94900 0 0x27c>;
2670 reg-names = "dsi_phy",
2671 "dsi_phy_lane",
2672 "dsi_pll";
2673
2674 #clock-cells = <1>;
2675 #phy-cells = <0>;
2676
2677 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2678 <&rpmhcc RPMH_CXO_CLK>;
2679 clock-names = "iface", "ref";
2680
2681 status = "disabled";
2682 };
2683
2684 mdss_dsi1: dsi@ae96000 {
2685 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2686 reg = <0 0x0ae96000 0 0x400>;
2687 reg-names = "dsi_ctrl";
2688
2689 interrupt-parent = <&mdss>;
2690 interrupts = <5>;
2691
2692 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2693 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2694 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2695 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2696 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2697 <&gcc GCC_DISP_HF_AXI_CLK>;
2698 clock-names = "byte",
2699 "byte_intf",
2700 "pixel",
2701 "core",
2702 "iface",
2703 "bus";
2704
2705 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2706 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2707 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2708 <&mdss_dsi1_phy 1>;
2709
2710 operating-points-v2 = <&dsi1_opp_table>;
2711 power-domains = <&rpmhpd SM8350_MMCX>;
2712
2713 phys = <&mdss_dsi1_phy>;
2714
2715 #address-cells = <1>;
2716 #size-cells = <0>;
2717
2718 status = "disabled";
2719
2720 dsi1_opp_table: opp-table {
2721 compatible = "operating-points-v2";
2722
2723 /* TODO: opp-187500000 should work with
2724 * &rpmhpd_opp_low_svs, but one some of
2725 * sm8350_hdk boards reboot using this
2726 * opp.
2727 */
2728 opp-187500000 {
2729 opp-hz = /bits/ 64 <187500000>;
2730 required-opps = <&rpmhpd_opp_svs>;
2731 };
2732
2733 opp-300000000 {
2734 opp-hz = /bits/ 64 <300000000>;
2735 required-opps = <&rpmhpd_opp_svs>;
2736 };
2737
2738 opp-358000000 {
2739 opp-hz = /bits/ 64 <358000000>;
2740 required-opps = <&rpmhpd_opp_svs_l1>;
2741 };
2742 };
2743
2744 ports {
2745 #address-cells = <1>;
2746 #size-cells = <0>;
2747
2748 port@0 {
2749 reg = <0>;
2750 mdss_dsi1_in: endpoint {
2751 remote-endpoint = <&dpu_intf2_out>;
2752 };
2753 };
2754
2755 port@1 {
2756 reg = <1>;
2757 mdss_dsi1_out: endpoint {
2758 };
2759 };
2760 };
2761 };
2762
2763 mdss_dsi1_phy: phy@ae96400 {
2764 compatible = "qcom,sm8350-dsi-phy-5nm";
2765 reg = <0 0x0ae96400 0 0x200>,
2766 <0 0x0ae96600 0 0x280>,
2767 <0 0x0ae96900 0 0x27c>;
2768 reg-names = "dsi_phy",
2769 "dsi_phy_lane",
2770 "dsi_pll";
2771
2772 #clock-cells = <1>;
2773 #phy-cells = <0>;
2774
2775 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2776 <&rpmhcc RPMH_CXO_CLK>;
2777 clock-names = "iface", "ref";
2778
2779 status = "disabled";
2780 };
2781 };
2782
2783 dispcc: clock-controller@af00000 {
2784 compatible = "qcom,sm8350-dispcc";
2785 reg = <0 0x0af00000 0 0x10000>;
2786 clocks = <&rpmhcc RPMH_CXO_CLK>,
2787 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2788 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2458a305
NA		 2789 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2790 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
51f83fbb
DB		 2791 clock-names = "bi_tcxo",
2792 "dsi0_phy_pll_out_byteclk",
2793 "dsi0_phy_pll_out_dsiclk",
2794 "dsi1_phy_pll_out_byteclk",
2795 "dsi1_phy_pll_out_dsiclk",
2796 "dp_phy_pll_link_clk",
2797 "dp_phy_pll_vco_div_clk";
2798 #clock-cells = <1>;
2799 #reset-cells = <1>;
2800 #power-domain-cells = <1>;
2801
2802 power-domains = <&rpmhpd SM8350_MMCX>;
2803 };
2804
2805 pdc: interrupt-controller@b220000 {
2806 compatible = "qcom,sm8350-pdc", "qcom,pdc";
2807 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2808 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2809 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
2810 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
2811 <156 716 12>;
2812 #interrupt-cells = <2>;
2813 interrupt-parent = <&intc>;
2814 interrupt-controller;
2815 };
2816
2817 tsens0: thermal-sensor@c263000 {
2818 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2819 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2820 <0 0x0c222000 0 0x8>; /* SROT */
2821 #qcom,sensors = <15>;
2822 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2823 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2824 interrupt-names = "uplow", "critical";
2825 #thermal-sensor-cells = <1>;
2826 };
2827
2828 tsens1: thermal-sensor@c265000 {
2829 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2830 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2831 <0 0x0c223000 0 0x8>; /* SROT */
2832 #qcom,sensors = <14>;
2833 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2834 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2835 interrupt-names = "uplow", "critical";
2836 #thermal-sensor-cells = <1>;
2837 };
2838
2839 aoss_qmp: power-management@c300000 {
2840 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2841 reg = <0 0x0c300000 0 0x400>;
2842 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2843 IRQ_TYPE_EDGE_RISING>;
2844 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2845
2846 #clock-cells = <0>;
2847 };
2848
2849 sram@c3f0000 {
2850 compatible = "qcom,rpmh-stats";
2851 reg = <0 0x0c3f0000 0 0x400>;
2852 };
2853
2854 spmi_bus: spmi@c440000 {
2855 compatible = "qcom,spmi-pmic-arb";
2856 reg = <0x0 0x0c440000 0x0 0x1100>,
2857 <0x0 0x0c600000 0x0 0x2000000>,
2858 <0x0 0x0e600000 0x0 0x100000>,
2859 <0x0 0x0e700000 0x0 0xa0000>,
2860 <0x0 0x0c40a000 0x0 0x26000>;
2861 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2862 interrupt-names = "periph_irq";
2863 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2864 qcom,ee = <0>;
2865 qcom,channel = <0>;
2866 #address-cells = <2>;
2867 #size-cells = <0>;
2868 interrupt-controller;
2869 #interrupt-cells = <4>;
2870 };
2871
2872 tlmm: pinctrl@f100000 {
2873 compatible = "qcom,sm8350-tlmm";
2874 reg = <0 0x0f100000 0 0x300000>;
2875 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2876 gpio-controller;
2877 #gpio-cells = <2>;
2878 interrupt-controller;
2879 #interrupt-cells = <2>;
2880 gpio-ranges = <&tlmm 0 0 204>;
2881 wakeup-parent = <&pdc>;
2882
2883 sdc2_default_state: sdc2-default-state {
2884 clk-pins {
2885 pins = "sdc2_clk";
2886 drive-strength = <16>;
2887 bias-disable;
2888 };
2889
2890 cmd-pins {
2891 pins = "sdc2_cmd";
2892 drive-strength = <16>;
2893 bias-pull-up;
2894 };
2895
2896 data-pins {
2897 pins = "sdc2_data";
2898 drive-strength = <16>;
2899 bias-pull-up;
2900 };
2901 };
2902
2903 sdc2_sleep_state: sdc2-sleep-state {
2904 clk-pins {
2905 pins = "sdc2_clk";
2906 drive-strength = <2>;
2907 bias-disable;
2908 };
d4a44105 2909
51f83fbb
DB		 2910 cmd-pins {
2911 pins = "sdc2_cmd";
2912 drive-strength = <2>;
2913 bias-pull-up;
2914 };
d4a44105 2915
51f83fbb
DB		 2916 data-pins {
2917 pins = "sdc2_data";
2918 drive-strength = <2>;
2919 bias-pull-up;
2920 };
d4a44105
RF		 2921 };
2922
51f83fbb
DB		 2923 qup_uart3_default_state: qup-uart3-default-state {
2924 rx-pins {
2925 pins = "gpio18";
2926 function = "qup3";
2927 };
2928 tx-pins {
2929 pins = "gpio19";
2930 function = "qup3";
2931 };
2932 };
f5f6bd58 2933
51f83fbb
DB		 2934 qup_uart6_default: qup-uart6-default-state {
2935 pins = "gpio30", "gpio31";
2936 function = "qup6";
2937 drive-strength = <2>;
2938 bias-disable;
2939 };
f5f6bd58 2940
51f83fbb
DB		 2941 qup_uart18_default: qup-uart18-default-state {
2942 pins = "gpio58", "gpio59";
2943 function = "qup18";
2944 drive-strength = <2>;
2945 bias-disable;
2946 };
f5f6bd58 2947
51f83fbb
DB		 2948 qup_i2c0_default: qup-i2c0-default-state {
2949 pins = "gpio4", "gpio5";
2950 function = "qup0";
2951 drive-strength = <2>;
2952 bias-pull-up;
2953 };
f5f6bd58 2954
51f83fbb
DB		 2955 qup_i2c1_default: qup-i2c1-default-state {
2956 pins = "gpio8", "gpio9";
2957 function = "qup1";
2958 drive-strength = <2>;
2959 bias-pull-up;
2960 };
f5f6bd58 2961
51f83fbb
DB		 2962 qup_i2c2_default: qup-i2c2-default-state {
2963 pins = "gpio12", "gpio13";
2964 function = "qup2";
2965 drive-strength = <2>;
2966 bias-pull-up;
2967 };
f5f6bd58 2968
51f83fbb
DB		 2969 qup_i2c4_default: qup-i2c4-default-state {
2970 pins = "gpio20", "gpio21";
2971 function = "qup4";
2972 drive-strength = <2>;
2973 bias-pull-up;
2974 };
f5f6bd58 2975
51f83fbb
DB		 2976 qup_i2c5_default: qup-i2c5-default-state {
2977 pins = "gpio24", "gpio25";
2978 function = "qup5";
2979 drive-strength = <2>;
2980 bias-pull-up;
2981 };
f5f6bd58 2982
51f83fbb
DB		 2983 qup_i2c6_default: qup-i2c6-default-state {
2984 pins = "gpio28", "gpio29";
2985 function = "qup6";
2986 drive-strength = <2>;
2987 bias-pull-up;
2988 };
f5f6bd58 2989
51f83fbb
DB		 2990 qup_i2c7_default: qup-i2c7-default-state {
2991 pins = "gpio32", "gpio33";
2992 function = "qup7";
2993 drive-strength = <2>;
2994 bias-disable;
2995 };
f5f6bd58 2996
51f83fbb
DB		 2997 qup_i2c8_default: qup-i2c8-default-state {
2998 pins = "gpio36", "gpio37";
2999 function = "qup8";
3000 drive-strength = <2>;
3001 bias-pull-up;
3002 };
f5f6bd58 3003
51f83fbb
DB		 3004 qup_i2c9_default: qup-i2c9-default-state {
3005 pins = "gpio40", "gpio41";
3006 function = "qup9";
3007 drive-strength = <2>;
3008 bias-pull-up;
3009 };
f5f6bd58 3010
51f83fbb
DB		 3011 qup_i2c10_default: qup-i2c10-default-state {
3012 pins = "gpio44", "gpio45";
3013 function = "qup10";
3014 drive-strength = <2>;
3015 bias-pull-up;
3016 };
f5f6bd58 3017
51f83fbb
DB		 3018 qup_i2c11_default: qup-i2c11-default-state {
3019 pins = "gpio48", "gpio49";
3020 function = "qup11";
3021 drive-strength = <2>;
3022 bias-pull-up;
3023 };
f5f6bd58 3024
51f83fbb
DB		 3025 qup_i2c12_default: qup-i2c12-default-state {
3026 pins = "gpio52", "gpio53";
3027 function = "qup12";
3028 drive-strength = <2>;
3029 bias-pull-up;
f5f6bd58
DB		 3030 };
3031
51f83fbb
DB		 3032 qup_i2c13_default: qup-i2c13-default-state {
3033 pins = "gpio0", "gpio1";
3034 function = "qup13";
3035 drive-strength = <2>;
3036 bias-pull-up;
3037 };
f5f6bd58 3038
51f83fbb
DB		 3039 qup_i2c14_default: qup-i2c14-default-state {
3040 pins = "gpio56", "gpio57";
3041 function = "qup14";
3042 drive-strength = <2>;
3043 bias-disable;
3044 };
f5f6bd58 3045
51f83fbb
DB		 3046 qup_i2c15_default: qup-i2c15-default-state {
3047 pins = "gpio60", "gpio61";
3048 function = "qup15";
3049 drive-strength = <2>;
3050 bias-disable;
3051 };
f5f6bd58 3052
51f83fbb
DB		 3053 qup_i2c16_default: qup-i2c16-default-state {
3054 pins = "gpio64", "gpio65";
3055 function = "qup16";
3056 drive-strength = <2>;
3057 bias-disable;
f5f6bd58 3058 };
f5f6bd58 3059
51f83fbb
DB		 3060 qup_i2c17_default: qup-i2c17-default-state {
3061 pins = "gpio72", "gpio73";
3062 function = "qup17";
3063 drive-strength = <2>;
3064 bias-disable;
3065 };
f5f6bd58 3066
51f83fbb
DB		 3067 qup_i2c19_default: qup-i2c19-default-state {
3068 pins = "gpio76", "gpio77";
3069 function = "qup19";
3070 drive-strength = <2>;
3071 bias-disable;
3072 };
f5f6bd58
DB		 3073 };
3074
3075 apps_smmu: iommu@15000000 {
3076 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3077 reg = <0 0x15000000 0 0x100000>;
3078 #iommu-cells = <2>;
3079 #global-interrupts = <2>;
3080 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3081 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3082 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3083 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3084 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3085 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3086 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3087 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3088 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3089 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3090 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3091 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3092 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3093 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3113 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3114 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3115 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3116 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3117 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3118 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3119 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3120 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3121 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3122 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3123 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3124 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3125 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3126 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3127 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3128 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3129 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3130 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3131 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3132 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3133 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3134 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3135 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3136 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3137 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3138 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3139 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3140 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3141 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3142 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3143 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3144 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3145 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3146 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3147 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3148 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3149 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3150 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3151 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3152 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3153 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3154 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3155 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3156 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3157 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3158 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3159 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3160 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3161 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3162 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3163 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3164 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3165 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3166 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3168 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3169 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3170 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3171 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3172 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3173 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3174 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3175 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3176 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3177 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3178 };
3179
3180 adsp: remoteproc@17300000 {
3181 compatible = "qcom,sm8350-adsp-pas";
3182 reg = <0 0x17300000 0 0x100>;
3183
3184 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3185 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3186 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3187 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3188 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3189 interrupt-names = "wdog", "fatal", "ready",
3190 "handover", "stop-ack";
3191
3192 clocks = <&rpmhcc RPMH_CXO_CLK>;
3193 clock-names = "xo";
3194
3195 power-domains = <&rpmhpd SM8350_LCX>,
3196 <&rpmhpd SM8350_LMX>;
3197 power-domain-names = "lcx", "lmx";
3198
3199 memory-region = <&pil_adsp_mem>;
3200
3201 qcom,qmp = <&aoss_qmp>;
3202
3203 qcom,smem-states = <&smp2p_adsp_out 0>;
3204 qcom,smem-state-names = "stop";
3205
3206 status = "disabled";
3207
3208 glink-edge {
3209 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3210 IPCC_MPROC_SIGNAL_GLINK_QMP
3211 IRQ_TYPE_EDGE_RISING>;
3212 mboxes = <&ipcc IPCC_CLIENT_LPASS
3213 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3214
3215 label = "lpass";
3216 qcom,remote-pid = <2>;
3217
3218 fastrpc {
3219 compatible = "qcom,fastrpc";
3220 qcom,glink-channels = "fastrpcglink-apps-dsp";
3221 label = "adsp";
3222 qcom,non-secure-domain;
3223 #address-cells = <1>;
3224 #size-cells = <0>;
3225
3226 compute-cb@3 {
3227 compatible = "qcom,fastrpc-compute-cb";
3228 reg = <3>;
3229 iommus = <&apps_smmu 0x1803 0x0>;
3230 };
3231
3232 compute-cb@4 {
3233 compatible = "qcom,fastrpc-compute-cb";
3234 reg = <4>;
3235 iommus = <&apps_smmu 0x1804 0x0>;
3236 };
3237
3238 compute-cb@5 {
3239 compatible = "qcom,fastrpc-compute-cb";
3240 reg = <5>;
3241 iommus = <&apps_smmu 0x1805 0x0>;
3242 };
3243 };
3244 };
3245 };
3246
3247 intc: interrupt-controller@17a00000 {
3248 compatible = "arm,gic-v3";
3249 #interrupt-cells = <3>;
3250 interrupt-controller;
3251 #redistributor-regions = <1>;
3252 redistributor-stride = <0 0x20000>;
3253 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3254 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3255 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3256 };
3257
3258 timer@17c20000 {
3259 compatible = "arm,armv7-timer-mem";
3260 #address-cells = <1>;
3261 #size-cells = <1>;
3262 ranges = <0 0 0 0x20000000>;
3263 reg = <0x0 0x17c20000 0x0 0x1000>;
3264 clock-frequency = <19200000>;
3265
3266 frame@17c21000 {
3267 frame-number = <0>;
3268 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3269 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3270 reg = <0x17c21000 0x1000>,
3271 <0x17c22000 0x1000>;
3272 };
3273
3274 frame@17c23000 {
3275 frame-number = <1>;
3276 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3277 reg = <0x17c23000 0x1000>;
3278 status = "disabled";
3279 };
3280
3281 frame@17c25000 {
3282 frame-number = <2>;
3283 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3284 reg = <0x17c25000 0x1000>;
3285 status = "disabled";
3286 };
3287
3288 frame@17c27000 {
3289 frame-number = <3>;
3290 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3291 reg = <0x17c27000 0x1000>;
3292 status = "disabled";
3293 };
3294
3295 frame@17c29000 {
3296 frame-number = <4>;
3297 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3298 reg = <0x17c29000 0x1000>;
3299 status = "disabled";
3300 };
3301
3302 frame@17c2b000 {
3303 frame-number = <5>;
3304 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3305 reg = <0x17c2b000 0x1000>;
3306 status = "disabled";
3307 };
3308
3309 frame@17c2d000 {
3310 frame-number = <6>;
3311 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3312 reg = <0x17c2d000 0x1000>;
3313 status = "disabled";
3314 };
3315 };
d4a44105 3316
f5f6bd58
DB		 3317 apps_rsc: rsc@18200000 {
3318 label = "apps_rsc";
3319 compatible = "qcom,rpmh-rsc";
3320 reg = <0x0 0x18200000 0x0 0x10000>,
3321 <0x0 0x18210000 0x0 0x10000>,
3322 <0x0 0x18220000 0x0 0x10000>;
3323 reg-names = "drv-0", "drv-1", "drv-2";
3324 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3325 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3326 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3327 qcom,tcs-offset = <0xd00>;
3328 qcom,drv-id = <2>;
3329 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3330 <WAKE_TCS 3>, <CONTROL_TCS 0>;
3331 power-domains = <&CLUSTER_PD>;
d4a44105 3332
f5f6bd58
DB		 3333 rpmhcc: clock-controller {
3334 compatible = "qcom,sm8350-rpmh-clk";
3335 #clock-cells = <1>;
3336 clock-names = "xo";
3337 clocks = <&xo_board>;
3338 };
d4a44105 3339
f5f6bd58
DB		 3340 rpmhpd: power-controller {
3341 compatible = "qcom,sm8350-rpmhpd";
3342 #power-domain-cells = <1>;
3343 operating-points-v2 = <&rpmhpd_opp_table>;
d4a44105 3344
f5f6bd58
DB		 3345 rpmhpd_opp_table: opp-table {
3346 compatible = "operating-points-v2";
d4a44105 3347
f5f6bd58
DB		 3348 rpmhpd_opp_ret: opp1 {
3349 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3350 };
d4a44105 3351
f5f6bd58
DB		 3352 rpmhpd_opp_min_svs: opp2 {
3353 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3354 };
6636818e 3355
f5f6bd58
DB		 3356 rpmhpd_opp_low_svs: opp3 {
3357 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3358 };
d4a44105 3359
f5f6bd58
DB		 3360 rpmhpd_opp_svs: opp4 {
3361 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3362 };
d4a44105 3363
f5f6bd58
DB		 3364 rpmhpd_opp_svs_l1: opp5 {
3365 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
d4a44105
RF		 3366 };
3367
f5f6bd58
DB		 3368 rpmhpd_opp_nom: opp6 {
3369 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
d4a44105
RF		 3370 };
3371
f5f6bd58
DB		 3372 rpmhpd_opp_nom_l1: opp7 {
3373 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
d4a44105 3374 };
d4a44105 3375
f5f6bd58
DB		 3376 rpmhpd_opp_nom_l2: opp8 {
3377 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3378 };
d4a44105 3379
f5f6bd58
DB		 3380 rpmhpd_opp_turbo: opp9 {
3381 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
d4a44105
RF		 3382 };
3383
f5f6bd58
DB		 3384 rpmhpd_opp_turbo_l1: opp10 {
3385 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
d4a44105
RF		 3386 };
3387 };
3388 };
3389
f5f6bd58
DB		 3390 apps_bcm_voter: bcm-voter {
3391 compatible = "qcom,bcm-voter";
d4a44105
RF		 3392 };
3393 };
3394
f5f6bd58
DB		 3395 cpufreq_hw: cpufreq@18591000 {
3396 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3397 reg = <0 0x18591000 0 0x1000>,
3398 <0 0x18592000 0 0x1000>,
3399 <0 0x18593000 0 0x1000>;
3400 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
9fd4887c 3401
f5f6bd58
DB		 3402 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3403 clock-names = "xo", "alternate";
3404
3405 #freq-domain-cells = <1>;
c2a18730 3406 #clock-cells = <1>;
9fd4887c
RF		 3407 };
3408
f5f6bd58
DB		 3409 cdsp: remoteproc@98900000 {
3410 compatible = "qcom,sm8350-cdsp-pas";
3411 reg = <0 0x98900000 0 0x1400000>;
177fcf0a 3412
f5f6bd58
DB		 3413 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3414 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3415 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3416 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3417 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
177fcf0a
VK		 3418 interrupt-names = "wdog", "fatal", "ready",
3419 "handover", "stop-ack";
3420
3421 clocks = <&rpmhcc RPMH_CXO_CLK>;
3422 clock-names = "xo";
3423
f5f6bd58
DB		 3424 power-domains = <&rpmhpd SM8350_CX>,
3425 <&rpmhpd SM8350_MXC>;
3426 power-domain-names = "cx", "mxc";
177fcf0a 3427
f5f6bd58
DB		 3428 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3429
3430 memory-region = <&pil_cdsp_mem>;
177fcf0a 3431
6b7cb2d2
SS		 3432 qcom,qmp = <&aoss_qmp>;
3433
f5f6bd58 3434 qcom,smem-states = <&smp2p_cdsp_out 0>;
177fcf0a
VK		 3435 qcom,smem-state-names = "stop";
3436
3437 status = "disabled";
3438
3439 glink-edge {
f5f6bd58 3440 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
177fcf0a
VK		 3441 IPCC_MPROC_SIGNAL_GLINK_QMP
3442 IRQ_TYPE_EDGE_RISING>;
f5f6bd58 3443 mboxes = <&ipcc IPCC_CLIENT_CDSP
177fcf0a
VK		 3444 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3445
f5f6bd58
DB		 3446 label = "cdsp";
3447 qcom,remote-pid = <5>;
178056a4
OJ		 3448
3449 fastrpc {
3450 compatible = "qcom,fastrpc";
3451 qcom,glink-channels = "fastrpcglink-apps-dsp";
f5f6bd58 3452 label = "cdsp";
8c8ce95b 3453 qcom,non-secure-domain;
178056a4
OJ		 3454 #address-cells = <1>;
3455 #size-cells = <0>;
3456
f5f6bd58
DB		 3457 compute-cb@1 {
3458 compatible = "qcom,fastrpc-compute-cb";
3459 reg = <1>;
3460 iommus = <&apps_smmu 0x2161 0x0400>,
3461 <&apps_smmu 0x1181 0x0420>;
3462 };
3463
3464 compute-cb@2 {
3465 compatible = "qcom,fastrpc-compute-cb";
3466 reg = <2>;
3467 iommus = <&apps_smmu 0x2162 0x0400>,
3468 <&apps_smmu 0x1182 0x0420>;
3469 };
3470
178056a4
OJ		 3471 compute-cb@3 {
3472 compatible = "qcom,fastrpc-compute-cb";
3473 reg = <3>;
f5f6bd58
DB		 3474 iommus = <&apps_smmu 0x2163 0x0400>,
3475 <&apps_smmu 0x1183 0x0420>;
178056a4
OJ		 3476 };
3477
3478 compute-cb@4 {
3479 compatible = "qcom,fastrpc-compute-cb";
3480 reg = <4>;
f5f6bd58
DB		 3481 iommus = <&apps_smmu 0x2164 0x0400>,
3482 <&apps_smmu 0x1184 0x0420>;
178056a4
OJ		 3483 };
3484
3485 compute-cb@5 {
3486 compatible = "qcom,fastrpc-compute-cb";
3487 reg = <5>;
f5f6bd58
DB		 3488 iommus = <&apps_smmu 0x2165 0x0400>,
3489 <&apps_smmu 0x1185 0x0420>;
3490 };
3491
3492 compute-cb@6 {
3493 compatible = "qcom,fastrpc-compute-cb";
3494 reg = <6>;
3495 iommus = <&apps_smmu 0x2166 0x0400>,
3496 <&apps_smmu 0x1186 0x0420>;
178056a4 3497 };
f5f6bd58
DB		 3498
3499 compute-cb@7 {
3500 compatible = "qcom,fastrpc-compute-cb";
3501 reg = <7>;
3502 iommus = <&apps_smmu 0x2167 0x0400>,
3503 <&apps_smmu 0x1187 0x0420>;
3504 };
3505
3506 compute-cb@8 {
3507 compatible = "qcom,fastrpc-compute-cb";
3508 reg = <8>;
3509 iommus = <&apps_smmu 0x2168 0x0400>,
3510 <&apps_smmu 0x1188 0x0420>;
3511 };
3512
3513 /* note: secure cb9 in downstream */
178056a4 3514 };
177fcf0a
VK		 3515 };
3516 };
b7e8f433
VK		 3517 };
3518
4dcaa68e 3519 thermal_zones: thermal-zones {
20f9d94e
RF		 3520 cpu0-thermal {
3521 polling-delay-passive = <250>;
3522 polling-delay = <1000>;
3523
3524 thermal-sensors = <&tsens0 1>;
3525
3526 trips {
3527 cpu0_alert0: trip-point0 {
3528 temperature = <90000>;
3529 hysteresis = <2000>;
3530 type = "passive";
3531 };
3532
3533 cpu0_alert1: trip-point1 {
3534 temperature = <95000>;
3535 hysteresis = <2000>;
3536 type = "passive";
3537 };
3538
1364acc3 3539 cpu0_crit: cpu-crit {
20f9d94e
RF		 3540 temperature = <110000>;
3541 hysteresis = <1000>;
3542 type = "critical";
3543 };
3544 };
3545
3546 cooling-maps {
3547 map0 {
3548 trip = <&cpu0_alert0>;
3549 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3550 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3551 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3552 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3553 };
3554 map1 {
3555 trip = <&cpu0_alert1>;
3556 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3557 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3558 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3559 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3560 };
3561 };
3562 };
3563
3564 cpu1-thermal {
3565 polling-delay-passive = <250>;
3566 polling-delay = <1000>;
3567
3568 thermal-sensors = <&tsens0 2>;
3569
3570 trips {
3571 cpu1_alert0: trip-point0 {
3572 temperature = <90000>;
3573 hysteresis = <2000>;
3574 type = "passive";
3575 };
3576
3577 cpu1_alert1: trip-point1 {
3578 temperature = <95000>;
3579 hysteresis = <2000>;
3580 type = "passive";
3581 };
3582
1364acc3 3583 cpu1_crit: cpu-crit {
20f9d94e
RF		 3584 temperature = <110000>;
3585 hysteresis = <1000>;
3586 type = "critical";
3587 };
3588 };
3589
3590 cooling-maps {
3591 map0 {
3592 trip = <&cpu1_alert0>;
3593 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3594 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3595 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3596 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3597 };
3598 map1 {
3599 trip = <&cpu1_alert1>;
3600 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3601 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3602 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3603 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3604 };
3605 };
3606 };
3607
3608 cpu2-thermal {
3609 polling-delay-passive = <250>;
3610 polling-delay = <1000>;
3611
3612 thermal-sensors = <&tsens0 3>;
3613
3614 trips {
3615 cpu2_alert0: trip-point0 {
3616 temperature = <90000>;
3617 hysteresis = <2000>;
3618 type = "passive";
3619 };
3620
3621 cpu2_alert1: trip-point1 {
3622 temperature = <95000>;
3623 hysteresis = <2000>;
3624 type = "passive";
3625 };
3626
1364acc3 3627 cpu2_crit: cpu-crit {
20f9d94e
RF		 3628 temperature = <110000>;
3629 hysteresis = <1000>;
3630 type = "critical";
3631 };
3632 };
3633
3634 cooling-maps {
3635 map0 {
3636 trip = <&cpu2_alert0>;
3637 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3638 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3639 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3640 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3641 };
3642 map1 {
3643 trip = <&cpu2_alert1>;
3644 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3645 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3646 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3647 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3648 };
3649 };
3650 };
3651
3652 cpu3-thermal {
3653 polling-delay-passive = <250>;
3654 polling-delay = <1000>;
3655
3656 thermal-sensors = <&tsens0 4>;
3657
3658 trips {
3659 cpu3_alert0: trip-point0 {
3660 temperature = <90000>;
3661 hysteresis = <2000>;
3662 type = "passive";
3663 };
3664
3665 cpu3_alert1: trip-point1 {
3666 temperature = <95000>;
3667 hysteresis = <2000>;
3668 type = "passive";
3669 };
3670
1364acc3 3671 cpu3_crit: cpu-crit {
20f9d94e
RF		 3672 temperature = <110000>;
3673 hysteresis = <1000>;
3674 type = "critical";
3675 };
3676 };
3677
3678 cooling-maps {
3679 map0 {
3680 trip = <&cpu3_alert0>;
3681 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3682 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3683 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3684 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3685 };
3686 map1 {
3687 trip = <&cpu3_alert1>;
3688 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3689 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3690 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3691 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3692 };
3693 };
3694 };
3695
3696 cpu4-top-thermal {
3697 polling-delay-passive = <250>;
3698 polling-delay = <1000>;
3699
3700 thermal-sensors = <&tsens0 7>;
3701
3702 trips {
3703 cpu4_top_alert0: trip-point0 {
3704 temperature = <90000>;
3705 hysteresis = <2000>;
3706 type = "passive";
3707 };
3708
3709 cpu4_top_alert1: trip-point1 {
3710 temperature = <95000>;
3711 hysteresis = <2000>;
3712 type = "passive";
3713 };
3714
1364acc3 3715 cpu4_top_crit: cpu-crit {
20f9d94e
RF		 3716 temperature = <110000>;
3717 hysteresis = <1000>;
3718 type = "critical";
3719 };
3720 };
3721
3722 cooling-maps {
3723 map0 {
3724 trip = <&cpu4_top_alert0>;
3725 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3726 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3727 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3728 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3729 };
3730 map1 {
3731 trip = <&cpu4_top_alert1>;
3732 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3733 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3734 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3735 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3736 };
3737 };
3738 };
3739
3740 cpu5-top-thermal {
3741 polling-delay-passive = <250>;
3742 polling-delay = <1000>;
3743
3744 thermal-sensors = <&tsens0 8>;
3745
3746 trips {
3747 cpu5_top_alert0: trip-point0 {
3748 temperature = <90000>;
3749 hysteresis = <2000>;
3750 type = "passive";
3751 };
3752
3753 cpu5_top_alert1: trip-point1 {
3754 temperature = <95000>;
3755 hysteresis = <2000>;
3756 type = "passive";
3757 };
3758
1364acc3 3759 cpu5_top_crit: cpu-crit {
20f9d94e
RF		 3760 temperature = <110000>;
3761 hysteresis = <1000>;
3762 type = "critical";
3763 };
3764 };
3765
3766 cooling-maps {
3767 map0 {
3768 trip = <&cpu5_top_alert0>;
3769 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3770 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3771 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3772 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3773 };
3774 map1 {
3775 trip = <&cpu5_top_alert1>;
3776 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3779 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3780 };
3781 };
3782 };
3783
3784 cpu6-top-thermal {
3785 polling-delay-passive = <250>;
3786 polling-delay = <1000>;
3787
3788 thermal-sensors = <&tsens0 9>;
3789
3790 trips {
3791 cpu6_top_alert0: trip-point0 {
3792 temperature = <90000>;
3793 hysteresis = <2000>;
3794 type = "passive";
3795 };
3796
3797 cpu6_top_alert1: trip-point1 {
3798 temperature = <95000>;
3799 hysteresis = <2000>;
3800 type = "passive";
3801 };
3802
1364acc3 3803 cpu6_top_crit: cpu-crit {
20f9d94e
RF		 3804 temperature = <110000>;
3805 hysteresis = <1000>;
3806 type = "critical";
3807 };
3808 };
3809
3810 cooling-maps {
3811 map0 {
3812 trip = <&cpu6_top_alert0>;
3813 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3814 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3815 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3816 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3817 };
3818 map1 {
3819 trip = <&cpu6_top_alert1>;
3820 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3821 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3822 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3823 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3824 };
3825 };
3826 };
3827
3828 cpu7-top-thermal {
3829 polling-delay-passive = <250>;
3830 polling-delay = <1000>;
3831
3832 thermal-sensors = <&tsens0 10>;
3833
3834 trips {
3835 cpu7_top_alert0: trip-point0 {
3836 temperature = <90000>;
3837 hysteresis = <2000>;
3838 type = "passive";
3839 };
3840
3841 cpu7_top_alert1: trip-point1 {
3842 temperature = <95000>;
3843 hysteresis = <2000>;
3844 type = "passive";
3845 };
3846
1364acc3 3847 cpu7_top_crit: cpu-crit {
20f9d94e
RF		 3848 temperature = <110000>;
3849 hysteresis = <1000>;
3850 type = "critical";
3851 };
3852 };
3853
3854 cooling-maps {
3855 map0 {
3856 trip = <&cpu7_top_alert0>;
3857 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3858 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3859 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3860 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3861 };
3862 map1 {
3863 trip = <&cpu7_top_alert1>;
3864 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3865 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3866 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3867 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3868 };
3869 };
3870 };
3871
3872 cpu4-bottom-thermal {
3873 polling-delay-passive = <250>;
3874 polling-delay = <1000>;
3875
3876 thermal-sensors = <&tsens0 11>;
3877
3878 trips {
3879 cpu4_bottom_alert0: trip-point0 {
3880 temperature = <90000>;
3881 hysteresis = <2000>;
3882 type = "passive";
3883 };
3884
3885 cpu4_bottom_alert1: trip-point1 {
3886 temperature = <95000>;
3887 hysteresis = <2000>;
3888 type = "passive";
3889 };
3890
1364acc3 3891 cpu4_bottom_crit: cpu-crit {
20f9d94e
RF		 3892 temperature = <110000>;
3893 hysteresis = <1000>;
3894 type = "critical";
3895 };
3896 };
3897
3898 cooling-maps {
3899 map0 {
3900 trip = <&cpu4_bottom_alert0>;
3901 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3902 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3903 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3904 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3905 };
3906 map1 {
3907 trip = <&cpu4_bottom_alert1>;
3908 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3909 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3910 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3911 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3912 };
3913 };
3914 };
3915
3916 cpu5-bottom-thermal {
3917 polling-delay-passive = <250>;
3918 polling-delay = <1000>;
3919
3920 thermal-sensors = <&tsens0 12>;
3921
3922 trips {
3923 cpu5_bottom_alert0: trip-point0 {
3924 temperature = <90000>;
3925 hysteresis = <2000>;
3926 type = "passive";
3927 };
3928
3929 cpu5_bottom_alert1: trip-point1 {
3930 temperature = <95000>;
3931 hysteresis = <2000>;
3932 type = "passive";
3933 };
3934
1364acc3 3935 cpu5_bottom_crit: cpu-crit {
20f9d94e
RF		 3936 temperature = <110000>;
3937 hysteresis = <1000>;
3938 type = "critical";
3939 };
3940 };
3941
3942 cooling-maps {
3943 map0 {
3944 trip = <&cpu5_bottom_alert0>;
3945 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3946 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3947 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3948 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3949 };
3950 map1 {
3951 trip = <&cpu5_bottom_alert1>;
3952 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3953 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3954 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3955 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3956 };
3957 };
3958 };
3959
3960 cpu6-bottom-thermal {
3961 polling-delay-passive = <250>;
3962 polling-delay = <1000>;
3963
3964 thermal-sensors = <&tsens0 13>;
3965
3966 trips {
3967 cpu6_bottom_alert0: trip-point0 {
3968 temperature = <90000>;
3969 hysteresis = <2000>;
3970 type = "passive";
3971 };
3972
3973 cpu6_bottom_alert1: trip-point1 {
3974 temperature = <95000>;
3975 hysteresis = <2000>;
3976 type = "passive";
3977 };
3978
1364acc3 3979 cpu6_bottom_crit: cpu-crit {
20f9d94e
RF		 3980 temperature = <110000>;
3981 hysteresis = <1000>;
3982 type = "critical";
3983 };
3984 };
3985
3986 cooling-maps {
3987 map0 {
3988 trip = <&cpu6_bottom_alert0>;
3989 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3990 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3991 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3992 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3993 };
3994 map1 {
3995 trip = <&cpu6_bottom_alert1>;
3996 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3997 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3998 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4000 };
4001 };
4002 };
4003
4004 cpu7-bottom-thermal {
4005 polling-delay-passive = <250>;
4006 polling-delay = <1000>;
4007
4008 thermal-sensors = <&tsens0 14>;
4009
4010 trips {
4011 cpu7_bottom_alert0: trip-point0 {
4012 temperature = <90000>;
4013 hysteresis = <2000>;
4014 type = "passive";
4015 };
4016
4017 cpu7_bottom_alert1: trip-point1 {
4018 temperature = <95000>;
4019 hysteresis = <2000>;
4020 type = "passive";
4021 };
4022
1364acc3 4023 cpu7_bottom_crit: cpu-crit {
20f9d94e
RF		 4024 temperature = <110000>;
4025 hysteresis = <1000>;
4026 type = "critical";
4027 };
4028 };
4029
4030 cooling-maps {
4031 map0 {
4032 trip = <&cpu7_bottom_alert0>;
4033 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4034 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4035 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4036 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4037 };
4038 map1 {
4039 trip = <&cpu7_bottom_alert1>;
4040 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4041 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4042 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4043 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4044 };
4045 };
4046 };
4047
4048 aoss0-thermal {
4049 polling-delay-passive = <250>;
4050 polling-delay = <1000>;
4051
4052 thermal-sensors = <&tsens0 0>;
4053
4054 trips {
4055 aoss0_alert0: trip-point0 {
4056 temperature = <90000>;
4057 hysteresis = <2000>;
4058 type = "hot";
4059 };
4060 };
4061 };
4062
4063 cluster0-thermal {
4064 polling-delay-passive = <250>;
4065 polling-delay = <1000>;
4066
4067 thermal-sensors = <&tsens0 5>;
4068
4069 trips {
4070 cluster0_alert0: trip-point0 {
4071 temperature = <90000>;
4072 hysteresis = <2000>;
4073 type = "hot";
4074 };
4075 cluster0_crit: cluster0_crit {
4076 temperature = <110000>;
4077 hysteresis = <2000>;
4078 type = "critical";
4079 };
4080 };
4081 };
4082
4083 cluster1-thermal {
4084 polling-delay-passive = <250>;
4085 polling-delay = <1000>;
4086
4087 thermal-sensors = <&tsens0 6>;
4088
4089 trips {
4090 cluster1_alert0: trip-point0 {
4091 temperature = <90000>;
4092 hysteresis = <2000>;
4093 type = "hot";
4094 };
4095 cluster1_crit: cluster1_crit {
4096 temperature = <110000>;
4097 hysteresis = <2000>;
4098 type = "critical";
4099 };
4100 };
4101 };
4102
4103 aoss1-thermal {
4104 polling-delay-passive = <250>;
4105 polling-delay = <1000>;
4106
4107 thermal-sensors = <&tsens1 0>;
4108
4109 trips {
4110 aoss1_alert0: trip-point0 {
4111 temperature = <90000>;
4112 hysteresis = <2000>;
4113 type = "hot";
4114 };
4115 };
4116 };
4117
7be1c395 4118 gpu-top-thermal {
20f9d94e
RF		 4119 polling-delay-passive = <250>;
4120 polling-delay = <1000>;
4121
4122 thermal-sensors = <&tsens1 1>;
4123
4124 trips {
4125 gpu1_alert0: trip-point0 {
4126 temperature = <90000>;
4127 hysteresis = <1000>;
4128 type = "hot";
4129 };
4130 };
4131 };
4132
7be1c395 4133 gpu-bottom-thermal {
20f9d94e
RF		 4134 polling-delay-passive = <250>;
4135 polling-delay = <1000>;
4136
4137 thermal-sensors = <&tsens1 2>;
4138
4139 trips {
4140 gpu2_alert0: trip-point0 {
4141 temperature = <90000>;
4142 hysteresis = <1000>;
4143 type = "hot";
4144 };
4145 };
4146 };
4147
4148 nspss1-thermal {
4149 polling-delay-passive = <250>;
4150 polling-delay = <1000>;
4151
4152 thermal-sensors = <&tsens1 3>;
4153
4154 trips {
4155 nspss1_alert0: trip-point0 {
4156 temperature = <90000>;
4157 hysteresis = <1000>;
4158 type = "hot";
4159 };
4160 };
4161 };
4162
4163 nspss2-thermal {
4164 polling-delay-passive = <250>;
4165 polling-delay = <1000>;
4166
4167 thermal-sensors = <&tsens1 4>;
4168
4169 trips {
4170 nspss2_alert0: trip-point0 {
4171 temperature = <90000>;
4172 hysteresis = <1000>;
4173 type = "hot";
4174 };
4175 };
4176 };
4177
4178 nspss3-thermal {
4179 polling-delay-passive = <250>;
4180 polling-delay = <1000>;
4181
4182 thermal-sensors = <&tsens1 5>;
4183
4184 trips {
4185 nspss3_alert0: trip-point0 {
4186 temperature = <90000>;
4187 hysteresis = <1000>;
4188 type = "hot";
4189 };
4190 };
4191 };
4192
4193 video-thermal {
4194 polling-delay-passive = <250>;
4195 polling-delay = <1000>;
4196
4197 thermal-sensors = <&tsens1 6>;
4198
4199 trips {
4200 video_alert0: trip-point0 {
4201 temperature = <90000>;
4202 hysteresis = <2000>;
4203 type = "hot";
4204 };
4205 };
4206 };
4207
4208 mem-thermal {
4209 polling-delay-passive = <250>;
4210 polling-delay = <1000>;
4211
4212 thermal-sensors = <&tsens1 7>;
4213
4214 trips {
4215 mem_alert0: trip-point0 {
4216 temperature = <90000>;
4217 hysteresis = <2000>;
4218 type = "hot";
4219 };
4220 };
4221 };
4222
7be1c395 4223 modem1-top-thermal {
20f9d94e
RF		 4224 polling-delay-passive = <250>;
4225 polling-delay = <1000>;
4226
4227 thermal-sensors = <&tsens1 8>;
4228
4229 trips {
4230 modem1_alert0: trip-point0 {
4231 temperature = <90000>;
4232 hysteresis = <2000>;
4233 type = "hot";
4234 };
4235 };
4236 };
4237
7be1c395 4238 modem2-top-thermal {
20f9d94e
RF		 4239 polling-delay-passive = <250>;
4240 polling-delay = <1000>;
4241
4242 thermal-sensors = <&tsens1 9>;
4243
4244 trips {
4245 modem2_alert0: trip-point0 {
4246 temperature = <90000>;
4247 hysteresis = <2000>;
4248 type = "hot";
4249 };
4250 };
4251 };
4252
7be1c395 4253 modem3-top-thermal {
20f9d94e
RF		 4254 polling-delay-passive = <250>;
4255 polling-delay = <1000>;
4256
4257 thermal-sensors = <&tsens1 10>;
4258
4259 trips {
4260 modem3_alert0: trip-point0 {
4261 temperature = <90000>;
4262 hysteresis = <2000>;
4263 type = "hot";
4264 };
4265 };
4266 };
4267
7be1c395 4268 modem4-top-thermal {
20f9d94e
RF		 4269 polling-delay-passive = <250>;
4270 polling-delay = <1000>;
4271
4272 thermal-sensors = <&tsens1 11>;
4273
4274 trips {
4275 modem4_alert0: trip-point0 {
4276 temperature = <90000>;
4277 hysteresis = <2000>;
4278 type = "hot";
4279 };
4280 };
4281 };
4282
7be1c395 4283 camera-top-thermal {
20f9d94e
RF		 4284 polling-delay-passive = <250>;
4285 polling-delay = <1000>;
4286
4287 thermal-sensors = <&tsens1 12>;
4288
4289 trips {
4290 camera1_alert0: trip-point0 {
4291 temperature = <90000>;
4292 hysteresis = <2000>;
4293 type = "hot";
4294 };
4295 };
4296 };
4297
7be1c395 4298 cam-bottom-thermal {
20f9d94e
RF		 4299 polling-delay-passive = <250>;
4300 polling-delay = <1000>;
4301
4302 thermal-sensors = <&tsens1 13>;
4303
4304 trips {
4305 camera2_alert0: trip-point0 {
4306 temperature = <90000>;
4307 hysteresis = <2000>;
4308 type = "hot";
4309 };
4310 };
4311 };
4312 };
4313
b7e8f433
VK		 4314 timer {
4315 compatible = "arm,armv8-timer";
4316 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4317 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4318 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4319 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4320 };
4321};
Linux 6.x block layer and io_uring tree(s)