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arm64: dts: qcom: sm8250: fix number of pins in 'gpio-ranges'
[linux-block.git] / arch / arm64 / boot / dts / qcom / sm8350.dtsi
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b7e8f433
VK		 1// SPDX-License-Identifier: BSD-3-Clause
2/*
4f23d2a5 3 * Copyright (c) 2020, Linaro Limited
b7e8f433
VK		 4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
6d91e201 7#include <dt-bindings/clock/qcom,gcc-sm8350.h>
b7e8f433
VK		 8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/mailbox/qcom-ipcc.h>
10#include <dt-bindings/power/qcom-aoss-qmp.h>
11#include <dt-bindings/power/qcom-rpmpd.h>
12#include <dt-bindings/soc/qcom,rpmh-rsc.h>
13
14/ {
15 interrupt-parent = <&intc>;
16
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 chosen { };
21
22 clocks {
23 xo_board: xo-board {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <38400000>;
27 clock-output-names = "xo_board";
28 };
29
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32000>;
33 #clock-cells = <0>;
34 };
35 };
36
37 cpus {
38 #address-cells = <2>;
39 #size-cells = <0>;
40
41 CPU0: cpu@0 {
42 device_type = "cpu";
43 compatible = "qcom,kryo685";
44 reg = <0x0 0x0>;
45 enable-method = "psci";
46 next-level-cache = <&L2_0>;
ccbb3abb 47 qcom,freq-domain = <&cpufreq_hw 0>;
b7e8f433
VK		 48 L2_0: l2-cache {
49 compatible = "cache";
50 next-level-cache = <&L3_0>;
51 L3_0: l3-cache {
52 compatible = "cache";
53 };
54 };
55 };
56
57 CPU1: cpu@100 {
58 device_type = "cpu";
59 compatible = "qcom,kryo685";
60 reg = <0x0 0x100>;
61 enable-method = "psci";
62 next-level-cache = <&L2_100>;
ccbb3abb 63 qcom,freq-domain = <&cpufreq_hw 0>;
b7e8f433
VK		 64 L2_100: l2-cache {
65 compatible = "cache";
66 next-level-cache = <&L3_0>;
67 };
68 };
69
70 CPU2: cpu@200 {
71 device_type = "cpu";
72 compatible = "qcom,kryo685";
73 reg = <0x0 0x200>;
74 enable-method = "psci";
75 next-level-cache = <&L2_200>;
ccbb3abb 76 qcom,freq-domain = <&cpufreq_hw 0>;
b7e8f433
VK		 77 L2_200: l2-cache {
78 compatible = "cache";
79 next-level-cache = <&L3_0>;
80 };
81 };
82
83 CPU3: cpu@300 {
84 device_type = "cpu";
85 compatible = "qcom,kryo685";
86 reg = <0x0 0x300>;
87 enable-method = "psci";
88 next-level-cache = <&L2_300>;
ccbb3abb 89 qcom,freq-domain = <&cpufreq_hw 0>;
b7e8f433
VK		 90 L2_300: l2-cache {
91 compatible = "cache";
92 next-level-cache = <&L3_0>;
93 };
94 };
95
96 CPU4: cpu@400 {
97 device_type = "cpu";
98 compatible = "qcom,kryo685";
99 reg = <0x0 0x400>;
100 enable-method = "psci";
101 next-level-cache = <&L2_400>;
ccbb3abb 102 qcom,freq-domain = <&cpufreq_hw 1>;
b7e8f433
VK		 103 L2_400: l2-cache {
104 compatible = "cache";
105 next-level-cache = <&L3_0>;
106 };
107 };
108
109 CPU5: cpu@500 {
110 device_type = "cpu";
111 compatible = "qcom,kryo685";
112 reg = <0x0 0x500>;
113 enable-method = "psci";
114 next-level-cache = <&L2_500>;
ccbb3abb 115 qcom,freq-domain = <&cpufreq_hw 1>;
b7e8f433
VK		 116 L2_500: l2-cache {
117 compatible = "cache";
118 next-level-cache = <&L3_0>;
119 };
120
121 };
122
123 CPU6: cpu@600 {
124 device_type = "cpu";
125 compatible = "qcom,kryo685";
126 reg = <0x0 0x600>;
127 enable-method = "psci";
128 next-level-cache = <&L2_600>;
ccbb3abb 129 qcom,freq-domain = <&cpufreq_hw 1>;
b7e8f433
VK		 130 L2_600: l2-cache {
131 compatible = "cache";
132 next-level-cache = <&L3_0>;
133 };
134 };
135
136 CPU7: cpu@700 {
137 device_type = "cpu";
138 compatible = "qcom,kryo685";
139 reg = <0x0 0x700>;
140 enable-method = "psci";
141 next-level-cache = <&L2_700>;
ccbb3abb 142 qcom,freq-domain = <&cpufreq_hw 2>;
b7e8f433
VK		 143 L2_700: l2-cache {
144 compatible = "cache";
145 next-level-cache = <&L3_0>;
146 };
147 };
148 };
149
150 firmware {
151 scm: scm {
152 compatible = "qcom,scm-sm8350", "qcom,scm";
153 #reset-cells = <1>;
154 };
155 };
156
157 memory@80000000 {
158 device_type = "memory";
159 /* We expect the bootloader to fill in the size */
160 reg = <0x0 0x80000000 0x0 0x0>;
161 };
162
163 pmu {
164 compatible = "arm,armv8-pmuv3";
794d3e30 165 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
b7e8f433
VK		 166 };
167
168 psci {
169 compatible = "arm,psci-1.0";
170 method = "smc";
171 };
172
173 reserved_memory: reserved-memory {
174 #address-cells = <2>;
175 #size-cells = <2>;
176 ranges;
177
178 hyp_mem: memory@80000000 {
179 reg = <0x0 0x80000000 0x0 0x600000>;
180 no-map;
181 };
182
183 xbl_aop_mem: memory@80700000 {
184 no-map;
185 reg = <0x0 0x80700000 0x0 0x160000>;
186 };
187
188 cmd_db: memory@80860000 {
189 compatible = "qcom,cmd-db";
190 reg = <0x0 0x80860000 0x0 0x20000>;
191 no-map;
192 };
193
194 reserved_xbl_uefi_log: memory@80880000 {
195 reg = <0x0 0x80880000 0x0 0x14000>;
196 no-map;
197 };
198
199 smem_mem: memory@80900000 {
200 reg = <0x0 0x80900000 0x0 0x200000>;
201 no-map;
202 };
203
204 cpucp_fw_mem: memory@80b00000 {
205 reg = <0x0 0x80b00000 0x0 0x100000>;
206 no-map;
207 };
208
209 cdsp_secure_heap: memory@80c00000 {
210 reg = <0x0 0x80c00000 0x0 0x4600000>;
211 no-map;
212 };
213
214 pil_camera_mem: mmeory@85200000 {
215 reg = <0x0 0x85200000 0x0 0x500000>;
216 no-map;
217 };
218
219 pil_video_mem: memory@85700000 {
220 reg = <0x0 0x85700000 0x0 0x500000>;
221 no-map;
222 };
223
224 pil_cvp_mem: memory@85c00000 {
225 reg = <0x0 0x85c00000 0x0 0x500000>;
226 no-map;
227 };
228
229 pil_adsp_mem: memory@86100000 {
230 reg = <0x0 0x86100000 0x0 0x2100000>;
231 no-map;
232 };
233
234 pil_slpi_mem: memory@88200000 {
235 reg = <0x0 0x88200000 0x0 0x1500000>;
236 no-map;
237 };
238
239 pil_cdsp_mem: memory@89700000 {
240 reg = <0x0 0x89700000 0x0 0x1e00000>;
241 no-map;
242 };
243
244 pil_ipa_fw_mem: memory@8b500000 {
245 reg = <0x0 0x8b500000 0x0 0x10000>;
246 no-map;
247 };
248
249 pil_ipa_gsi_mem: memory@8b510000 {
250 reg = <0x0 0x8b510000 0x0 0xa000>;
251 no-map;
252 };
253
254 pil_gpu_mem: memory@8b51a000 {
255 reg = <0x0 0x8b51a000 0x0 0x2000>;
256 no-map;
257 };
258
259 pil_spss_mem: memory@8b600000 {
260 reg = <0x0 0x8b600000 0x0 0x100000>;
261 no-map;
262 };
263
264 pil_modem_mem: memory@8b800000 {
265 reg = <0x0 0x8b800000 0x0 0x10000000>;
266 no-map;
267 };
268
774890c9
VK		 269 rmtfs_mem: memory@9b800000 {
270 compatible = "qcom,rmtfs-mem";
271 reg = <0x0 0x9b800000 0x0 0x280000>;
272 no-map;
273
274 qcom,client-id = <1>;
275 qcom,vmid = <15>;
276 };
277
b7e8f433
VK		 278 hyp_reserved_mem: memory@d0000000 {
279 reg = <0x0 0xd0000000 0x0 0x800000>;
280 no-map;
281 };
282
283 pil_trustedvm_mem: memory@d0800000 {
284 reg = <0x0 0xd0800000 0x0 0x76f7000>;
285 no-map;
286 };
287
288 qrtr_shbuf: memory@d7ef7000 {
289 reg = <0x0 0xd7ef7000 0x0 0x9000>;
290 no-map;
291 };
292
293 chan0_shbuf: memory@d7f00000 {
294 reg = <0x0 0xd7f00000 0x0 0x80000>;
295 no-map;
296 };
297
298 chan1_shbuf: memory@d7f80000 {
299 reg = <0x0 0xd7f80000 0x0 0x80000>;
300 no-map;
301 };
302
303 removed_mem: memory@d8800000 {
304 reg = <0x0 0xd8800000 0x0 0x6800000>;
305 no-map;
306 };
307 };
308
309 smem: qcom,smem {
310 compatible = "qcom,smem";
311 memory-region = <&smem_mem>;
312 hwlocks = <&tcsr_mutex 3>;
313 };
314
03a41991
VK		 315 smp2p-adsp {
316 compatible = "qcom,smp2p";
317 qcom,smem = <443>, <429>;
318 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
319 IPCC_MPROC_SIGNAL_SMP2P
320 IRQ_TYPE_EDGE_RISING>;
321 mboxes = <&ipcc IPCC_CLIENT_LPASS
322 IPCC_MPROC_SIGNAL_SMP2P>;
323
324 qcom,local-pid = <0>;
325 qcom,remote-pid = <2>;
326
327 smp2p_adsp_out: master-kernel {
328 qcom,entry-name = "master-kernel";
329 #qcom,smem-state-cells = <1>;
330 };
331
332 smp2p_adsp_in: slave-kernel {
333 qcom,entry-name = "slave-kernel";
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 };
337 };
338
339 smp2p-cdsp {
340 compatible = "qcom,smp2p";
341 qcom,smem = <94>, <432>;
342 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
343 IPCC_MPROC_SIGNAL_SMP2P
344 IRQ_TYPE_EDGE_RISING>;
345 mboxes = <&ipcc IPCC_CLIENT_CDSP
346 IPCC_MPROC_SIGNAL_SMP2P>;
347
348 qcom,local-pid = <0>;
349 qcom,remote-pid = <5>;
350
351 smp2p_cdsp_out: master-kernel {
352 qcom,entry-name = "master-kernel";
353 #qcom,smem-state-cells = <1>;
354 };
355
356 smp2p_cdsp_in: slave-kernel {
357 qcom,entry-name = "slave-kernel";
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 };
361 };
362
363 smp2p-modem {
364 compatible = "qcom,smp2p";
365 qcom,smem = <435>, <428>;
366 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
367 IPCC_MPROC_SIGNAL_SMP2P
368 IRQ_TYPE_EDGE_RISING>;
369 mboxes = <&ipcc IPCC_CLIENT_MPSS
370 IPCC_MPROC_SIGNAL_SMP2P>;
371
372 qcom,local-pid = <0>;
373 qcom,remote-pid = <1>;
374
375 smp2p_modem_out: master-kernel {
376 qcom,entry-name = "master-kernel";
377 #qcom,smem-state-cells = <1>;
378 };
379
380 smp2p_modem_in: slave-kernel {
381 qcom,entry-name = "slave-kernel";
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 };
385 };
386
387 smp2p-slpi {
388 compatible = "qcom,smp2p";
389 qcom,smem = <481>, <430>;
390 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
391 IPCC_MPROC_SIGNAL_SMP2P
392 IRQ_TYPE_EDGE_RISING>;
393 mboxes = <&ipcc IPCC_CLIENT_SLPI
394 IPCC_MPROC_SIGNAL_SMP2P>;
395
396 qcom,local-pid = <0>;
397 qcom,remote-pid = <3>;
398
399 smp2p_slpi_out: master-kernel {
400 qcom,entry-name = "master-kernel";
401 #qcom,smem-state-cells = <1>;
402 };
403
404 smp2p_slpi_in: slave-kernel {
405 qcom,entry-name = "slave-kernel";
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 };
409 };
410
b7e8f433
VK		 411 soc: soc@0 {
412 #address-cells = <2>;
413 #size-cells = <2>;
414 ranges = <0 0 0 0 0x10 0>;
415 dma-ranges = <0 0 0 0 0x10 0>;
416 compatible = "simple-bus";
417
418 gcc: clock-controller@100000 {
419 compatible = "qcom,gcc-sm8350";
420 reg = <0x0 0x00100000 0x0 0x1f0000>;
421 #clock-cells = <1>;
422 #reset-cells = <1>;
423 #power-domain-cells = <1>;
424 clock-names = "bi_tcxo", "sleep_clk";
425 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
426 };
427
428 ipcc: mailbox@408000 {
429 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
430 reg = <0 0x00408000 0 0x1000>;
431 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-controller;
433 #interrupt-cells = <3>;
434 #mbox-cells = <2>;
435 };
436
437 qupv3_id_1: geniqup@9c0000 {
438 compatible = "qcom,geni-se-qup";
439 reg = <0x0 0x009c0000 0x0 0x6000>;
440 clock-names = "m-ahb", "s-ahb";
6d91e201
VK		 441 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
442 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
b7e8f433
VK		 443 #address-cells = <2>;
444 #size-cells = <2>;
445 ranges;
446 status = "disabled";
447
448 uart2: serial@98c000 {
449 compatible = "qcom,geni-debug-uart";
450 reg = <0 0x0098c000 0 0x4000>;
451 clock-names = "se";
6d91e201 452 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
b7e8f433
VK		 453 pinctrl-names = "default";
454 pinctrl-0 = <&qup_uart3_default_state>;
455 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 status = "disabled";
459 };
460 };
461
187f65b7
VK		 462 apps_smmu: iommu@15000000 {
463 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
464 reg = <0 0x15000000 0 0x100000>;
465 #iommu-cells = <2>;
466 #global-interrupts = <2>;
467 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
565 };
566
b7e8f433
VK		 567 tcsr_mutex: hwlock@1f40000 {
568 compatible = "qcom,tcsr-mutex";
569 reg = <0x0 0x01f40000 0x0 0x40000>;
570 #hwlock-cells = <1>;
571 };
572
177fcf0a
VK		 573 mpss: remoteproc@4080000 {
574 compatible = "qcom,sm8350-mpss-pas";
575 reg = <0x0 0x04080000 0x0 0x4040>;
576
577 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
578 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
579 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
580 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
581 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
582 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
583 interrupt-names = "wdog", "fatal", "ready", "handover",
584 "stop-ack", "shutdown-ack";
585
586 clocks = <&rpmhcc RPMH_CXO_CLK>;
587 clock-names = "xo";
588
589 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
590 <&rpmhpd 0>,
591 <&rpmhpd 12>;
592 power-domain-names = "load_state", "cx", "mss";
593
594 memory-region = <&pil_modem_mem>;
595
596 qcom,smem-states = <&smp2p_modem_out 0>;
597 qcom,smem-state-names = "stop";
598
599 status = "disabled";
600
601 glink-edge {
602 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
603 IPCC_MPROC_SIGNAL_GLINK_QMP
604 IRQ_TYPE_EDGE_RISING>;
605 mboxes = <&ipcc IPCC_CLIENT_MPSS
606 IPCC_MPROC_SIGNAL_GLINK_QMP>;
607 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
608 label = "modem";
609 qcom,remote-pid = <1>;
610 };
611 };
612
b7e8f433
VK		 613 pdc: interrupt-controller@b220000 {
614 compatible = "qcom,sm8350-pdc", "qcom,pdc";
615 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
616 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
617 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
618 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
619 <156 716 12>;
620 #interrupt-cells = <2>;
621 interrupt-parent = <&intc>;
622 interrupt-controller;
623 };
624
97832fa8 625 aoss_qmp: power-controller@c300000 {
b7e8f433
VK		 626 compatible = "qcom,sm8350-aoss-qmp";
627 reg = <0 0x0c300000 0 0x100000>;
628 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
629 IRQ_TYPE_EDGE_RISING>;
630 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
631
632 #clock-cells = <0>;
633 #power-domain-cells = <1>;
634 };
635
636 tlmm: pinctrl@f100000 {
637 compatible = "qcom,sm8350-tlmm";
638 reg = <0 0x0f100000 0 0x300000>;
639 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
640 gpio-controller;
641 #gpio-cells = <2>;
642 interrupt-controller;
643 #interrupt-cells = <2>;
644 gpio-ranges = <&tlmm 0 0 203>;
645
646 qup_uart3_default_state: qup-uart3-default-state {
647 rx {
648 pins = "gpio18";
649 function = "qup3";
650 };
651 tx {
652 pins = "gpio19";
653 function = "qup3";
654 };
655 };
656 };
657
658 intc: interrupt-controller@17a00000 {
659 compatible = "arm,gic-v3";
660 #interrupt-cells = <3>;
661 interrupt-controller;
662 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
663 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
664 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
665 };
666
667 timer@17c20000 {
668 compatible = "arm,armv7-timer-mem";
669 #address-cells = <2>;
670 #size-cells = <2>;
671 ranges;
672 reg = <0x0 0x17c20000 0x0 0x1000>;
673 clock-frequency = <19200000>;
674
675 frame@17c21000 {
676 frame-number = <0>;
677 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
679 reg = <0x0 0x17c21000 0x0 0x1000>,
680 <0x0 0x17c22000 0x0 0x1000>;
681 };
682
683 frame@17c23000 {
684 frame-number = <1>;
685 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
686 reg = <0x0 0x17c23000 0x0 0x1000>;
687 status = "disabled";
688 };
689
690 frame@17c25000 {
691 frame-number = <2>;
692 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
693 reg = <0x0 0x17c25000 0x0 0x1000>;
694 status = "disabled";
695 };
696
697 frame@17c27000 {
698 frame-number = <3>;
699 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
700 reg = <0x0 0x17c27000 0x0 0x1000>;
701 status = "disabled";
702 };
703
704 frame@17c29000 {
705 frame-number = <4>;
706 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
707 reg = <0x0 0x17c29000 0x0 0x1000>;
708 status = "disabled";
709 };
710
711 frame@17c2b000 {
712 frame-number = <5>;
713 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
714 reg = <0x0 0x17c2b000 0x0 0x1000>;
715 status = "disabled";
716 };
717
718 frame@17c2d000 {
719 frame-number = <6>;
720 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
721 reg = <0x0 0x17c2d000 0x0 0x1000>;
722 status = "disabled";
723 };
724 };
725
726 apps_rsc: rsc@18200000 {
727 label = "apps_rsc";
728 compatible = "qcom,rpmh-rsc";
729 reg = <0x0 0x18200000 0x0 0x10000>,
730 <0x0 0x18210000 0x0 0x10000>,
731 <0x0 0x18220000 0x0 0x10000>;
732 reg-names = "drv-0", "drv-1", "drv-2";
733 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
736 qcom,tcs-offset = <0xd00>;
737 qcom,drv-id = <2>;
738 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
739 <WAKE_TCS 3>, <CONTROL_TCS 1>;
740
741 rpmhcc: clock-controller {
742 compatible = "qcom,sm8350-rpmh-clk";
743 #clock-cells = <1>;
744 clock-names = "xo";
745 clocks = <&xo_board>;
746 };
747
90f57509
VK		 748 rpmhpd: power-controller {
749 compatible = "qcom,sm8350-rpmhpd";
750 #power-domain-cells = <1>;
751 operating-points-v2 = <&rpmhpd_opp_table>;
752
753 rpmhpd_opp_table: opp-table {
754 compatible = "operating-points-v2";
755
756 rpmhpd_opp_ret: opp1 {
757 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
758 };
759
760 rpmhpd_opp_min_svs: opp2 {
761 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
762 };
763
764 rpmhpd_opp_low_svs: opp3 {
765 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
766 };
767
768 rpmhpd_opp_svs: opp4 {
769 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
770 };
771
772 rpmhpd_opp_svs_l1: opp5 {
773 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
774 };
775
776 rpmhpd_opp_nom: opp6 {
777 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
778 };
779
780 rpmhpd_opp_nom_l1: opp7 {
781 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
782 };
783
784 rpmhpd_opp_nom_l2: opp8 {
785 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
786 };
787
788 rpmhpd_opp_turbo: opp9 {
789 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
790 };
791
792 rpmhpd_opp_turbo_l1: opp10 {
793 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
794 };
795 };
796 };
b7e8f433 797 };
e780fb31 798
ccbb3abb
VK		 799 cpufreq_hw: cpufreq@18591000 {
800 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
801 reg = <0 0x18591000 0 0x1000>,
802 <0 0x18592000 0 0x1000>,
803 <0 0x18593000 0 0x1000>;
804 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
805
806 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
807 clock-names = "xo", "alternate";
808
809 #freq-domain-cells = <1>;
810 };
811
59c7cf81
VK		 812 ufs_mem_hc: ufshc@1d84000 {
813 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
814 "jedec,ufs-2.0";
815 reg = <0 0x01d84000 0 0x3000>;
816 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
817 phys = <&ufs_mem_phy_lanes>;
818 phy-names = "ufsphy";
819 lanes-per-direction = <2>;
820 #reset-cells = <1>;
6d91e201 821 resets = <&gcc GCC_UFS_PHY_BCR>;
59c7cf81
VK		 822 reset-names = "rst";
823
6d91e201 824 power-domains = <&gcc UFS_PHY_GDSC>;
59c7cf81
VK		 825
826 iommus = <&apps_smmu 0xe0 0x0>;
827
828 clock-names =
829 "ref_clk",
830 "core_clk",
831 "bus_aggr_clk",
832 "iface_clk",
833 "core_clk_unipro",
834 "ref_clk",
835 "tx_lane0_sync_clk",
836 "rx_lane0_sync_clk",
837 "rx_lane1_sync_clk";
838 clocks =
839 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 840 <&gcc GCC_UFS_PHY_AXI_CLK>,
841 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
842 <&gcc GCC_UFS_PHY_AHB_CLK>,
843 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
59c7cf81 844 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 845 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
846 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
847 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
59c7cf81
VK		 848 freq-table-hz =
849 <75000000 300000000>,
850 <75000000 300000000>,
851 <0 0>,
852 <0 0>,
853 <75000000 300000000>,
854 <0 0>,
855 <0 0>,
856 <75000000 300000000>,
857 <75000000 300000000>;
858 status = "disabled";
859 };
860
861 ufs_mem_phy: phy@1d87000 {
862 compatible = "qcom,sm8350-qmp-ufs-phy";
863 reg = <0 0x01d87000 0 0xe10>;
864 #address-cells = <2>;
865 #size-cells = <2>;
866 #clock-cells = <1>;
867 ranges;
868 clock-names = "ref",
869 "ref_aux";
870 clocks = <&rpmhcc RPMH_CXO_CLK>,
6d91e201 871 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
59c7cf81
VK		 872
873 resets = <&ufs_mem_hc 0>;
874 reset-names = "ufsphy";
875 status = "disabled";
876
877 ufs_mem_phy_lanes: lanes@1d87400 {
878 reg = <0 0x01d87400 0 0x108>,
879 <0 0x01d87600 0 0x1e0>,
880 <0 0x01d87c00 0 0x1dc>,
881 <0 0x01d87800 0 0x108>,
882 <0 0x01d87a00 0 0x1e0>;
883 #phy-cells = <0>;
884 #clock-cells = <0>;
885 };
886 };
887
177fcf0a
VK		 888 slpi: remoteproc@5c00000 {
889 compatible = "qcom,sm8350-slpi-pas";
890 reg = <0 0x05c00000 0 0x4000>;
891
892 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
893 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
894 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
895 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
896 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
897 interrupt-names = "wdog", "fatal", "ready",
898 "handover", "stop-ack";
899
900 clocks = <&rpmhcc RPMH_CXO_CLK>;
901 clock-names = "xo";
902
903 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
904 <&rpmhpd 4>,
905 <&rpmhpd 5>;
906 power-domain-names = "load_state", "lcx", "lmx";
907
908 memory-region = <&pil_slpi_mem>;
909
910 qcom,smem-states = <&smp2p_slpi_out 0>;
911 qcom,smem-state-names = "stop";
912
913 status = "disabled";
914
915 glink-edge {
916 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
917 IPCC_MPROC_SIGNAL_GLINK_QMP
918 IRQ_TYPE_EDGE_RISING>;
919 mboxes = <&ipcc IPCC_CLIENT_SLPI
920 IPCC_MPROC_SIGNAL_GLINK_QMP>;
921
922 label = "slpi";
923 qcom,remote-pid = <3>;
924
925 };
926 };
927
928 cdsp: remoteproc@98900000 {
929 compatible = "qcom,sm8350-cdsp-pas";
930 reg = <0 0x098900000 0 0x1400000>;
931
932 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
933 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
934 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
935 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
936 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
937 interrupt-names = "wdog", "fatal", "ready",
938 "handover", "stop-ack";
939
940 clocks = <&rpmhcc RPMH_CXO_CLK>;
941 clock-names = "xo";
942
943 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
944 <&rpmhpd 0>,
945 <&rpmhpd 10>;
946 power-domain-names = "load_state", "cx", "mxc";
947
948 memory-region = <&pil_cdsp_mem>;
949
950 qcom,smem-states = <&smp2p_cdsp_out 0>;
951 qcom,smem-state-names = "stop";
952
953 status = "disabled";
954
955 glink-edge {
956 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
957 IPCC_MPROC_SIGNAL_GLINK_QMP
958 IRQ_TYPE_EDGE_RISING>;
959 mboxes = <&ipcc IPCC_CLIENT_CDSP
960 IPCC_MPROC_SIGNAL_GLINK_QMP>;
961
962 label = "cdsp";
963 qcom,remote-pid = <5>;
964 };
965 };
966
e780fb31
JP		 967 usb_1_hsphy: phy@88e3000 {
968 compatible = "qcom,sm8350-usb-hs-phy",
969 "qcom,usb-snps-hs-7nm-phy";
970 reg = <0 0x088e3000 0 0x400>;
971 status = "disabled";
972 #phy-cells = <0>;
973
974 clocks = <&rpmhcc RPMH_CXO_CLK>;
975 clock-names = "ref";
976
6d91e201 977 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
e780fb31
JP		 978 };
979
980 usb_2_hsphy: phy@88e4000 {
981 compatible = "qcom,sm8250-usb-hs-phy",
982 "qcom,usb-snps-hs-7nm-phy";
983 reg = <0 0x088e4000 0 0x400>;
984 status = "disabled";
985 #phy-cells = <0>;
986
987 clocks = <&rpmhcc RPMH_CXO_CLK>;
988 clock-names = "ref";
989
6d91e201 990 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
e780fb31
JP		 991 };
992
993 usb_1_qmpphy: phy-wrapper@88e9000 {
994 compatible = "qcom,sm8350-qmp-usb3-phy";
995 reg = <0 0x088e9000 0 0x200>,
996 <0 0x088e8000 0 0x20>;
997 reg-names = "reg-base", "dp_com";
998 status = "disabled";
999 #clock-cells = <1>;
1000 #address-cells = <2>;
1001 #size-cells = <2>;
1002 ranges;
1003
6d91e201 1004 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
e780fb31 1005 <&rpmhcc RPMH_CXO_CLK>,
6d91e201 1006 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
e780fb31
JP		 1007 clock-names = "aux", "ref_clk_src", "com_aux";
1008
6d91e201
VK		 1009 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1010 <&gcc GCC_USB3_PHY_PRIM_BCR>;
e780fb31
JP		 1011 reset-names = "phy", "common";
1012
1013 usb_1_ssphy: phy@88e9200 {
1014 reg = <0 0x088e9200 0 0x200>,
1015 <0 0x088e9400 0 0x200>,
1016 <0 0x088e9c00 0 0x400>,
1017 <0 0x088e9600 0 0x200>,
1018 <0 0x088e9800 0 0x200>,
1019 <0 0x088e9a00 0 0x100>;
1020 #phy-cells = <0>;
1021 #clock-cells = <1>;
6d91e201 1022 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
e780fb31
JP		 1023 clock-names = "pipe0";
1024 clock-output-names = "usb3_phy_pipe_clk_src";
1025 };
1026 };
1027
1028 usb_2_qmpphy: phy-wrapper@88eb000 {
1029 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
1030 reg = <0 0x088eb000 0 0x200>;
1031 status = "disabled";
1032 #clock-cells = <1>;
1033 #address-cells = <2>;
1034 #size-cells = <2>;
1035 ranges;
1036
6d91e201 1037 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
e780fb31 1038 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 1039 <&gcc GCC_USB3_SEC_CLKREF_EN>,
1040 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
e780fb31
JP		 1041 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1042
6d91e201
VK		 1043 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1044 <&gcc GCC_USB3_PHY_SEC_BCR>;
e780fb31
JP		 1045 reset-names = "phy", "common";
1046
1047 usb_2_ssphy: phy@88ebe00 {
1048 reg = <0 0x088ebe00 0 0x200>,
1049 <0 0x088ec000 0 0x200>,
1050 <0 0x088eb200 0 0x1100>;
1051 #phy-cells = <0>;
1052 #clock-cells = <1>;
6d91e201 1053 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
e780fb31
JP		 1054 clock-names = "pipe0";
1055 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1056 };
1057 };
1058
1059 usb_1: usb@a6f8800 {
1060 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1061 reg = <0 0x0a6f8800 0 0x400>;
1062 status = "disabled";
1063 #address-cells = <2>;
1064 #size-cells = <2>;
1065 ranges;
1066
6d91e201
VK		 1067 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1068 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1069 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1070 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1071 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
e780fb31
JP		 1072 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1073 "sleep";
1074
6d91e201
VK		 1075 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1076 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
e780fb31
JP		 1077 assigned-clock-rates = <19200000>, <200000000>;
1078
1079 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1080 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1081 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1082 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1083 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1084 "dm_hs_phy_irq", "ss_phy_irq";
1085
6d91e201 1086 power-domains = <&gcc USB30_PRIM_GDSC>;
e780fb31 1087
6d91e201 1088 resets = <&gcc GCC_USB30_PRIM_BCR>;
e780fb31
JP		 1089
1090 usb_1_dwc3: dwc3@a600000 {
1091 compatible = "snps,dwc3";
1092 reg = <0 0x0a600000 0 0xcd00>;
1093 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1094 iommus = <&apps_smmu 0x0 0x0>;
1095 snps,dis_u2_susphy_quirk;
1096 snps,dis_enblslpm_quirk;
1097 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1098 phy-names = "usb2-phy", "usb3-phy";
1099 };
1100 };
1101
1102 usb_2: usb@a8f8800 {
1103 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1104 reg = <0 0x0a8f8800 0 0x400>;
1105 status = "disabled";
1106 #address-cells = <2>;
1107 #size-cells = <2>;
1108 ranges;
1109
6d91e201
VK		 1110 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1111 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1112 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1113 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1114 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1115 <&gcc GCC_USB3_SEC_CLKREF_EN>;
e780fb31
JP		 1116 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1117 "sleep", "xo";
1118
6d91e201
VK		 1119 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1120 <&gcc GCC_USB30_SEC_MASTER_CLK>;
e780fb31
JP		 1121 assigned-clock-rates = <19200000>, <200000000>;
1122
1123 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1124 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1125 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1126 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1127 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1128 "dm_hs_phy_irq", "ss_phy_irq";
1129
6d91e201 1130 power-domains = <&gcc USB30_SEC_GDSC>;
e780fb31 1131
6d91e201 1132 resets = <&gcc GCC_USB30_SEC_BCR>;
e780fb31
JP		 1133
1134 usb_2_dwc3: dwc3@a800000 {
1135 compatible = "snps,dwc3";
1136 reg = <0 0x0a800000 0 0xcd00>;
1137 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1138 iommus = <&apps_smmu 0x20 0x0>;
1139 snps,dis_u2_susphy_quirk;
1140 snps,dis_enblslpm_quirk;
1141 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1142 phy-names = "usb2-phy", "usb3-phy";
1143 };
1144 };
177fcf0a
VK		 1145
1146 adsp: remoteproc@17300000 {
1147 compatible = "qcom,sm8350-adsp-pas";
1148 reg = <0 0x17300000 0 0x100>;
1149
1150 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1151 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1152 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1153 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1154 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1155 interrupt-names = "wdog", "fatal", "ready",
1156 "handover", "stop-ack";
1157
1158 clocks = <&rpmhcc RPMH_CXO_CLK>;
1159 clock-names = "xo";
1160
1161 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
1162 <&rpmhpd 4>,
1163 <&rpmhpd 5>;
1164 power-domain-names = "load_state", "lcx", "lmx";
1165
1166 memory-region = <&pil_adsp_mem>;
1167
1168 qcom,smem-states = <&smp2p_adsp_out 0>;
1169 qcom,smem-state-names = "stop";
1170
1171 status = "disabled";
1172
1173 glink-edge {
1174 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1175 IPCC_MPROC_SIGNAL_GLINK_QMP
1176 IRQ_TYPE_EDGE_RISING>;
1177 mboxes = <&ipcc IPCC_CLIENT_LPASS
1178 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1179
1180 label = "lpass";
1181 qcom,remote-pid = <2>;
1182 };
1183 };
b7e8f433
VK		 1184 };
1185
1186 timer {
1187 compatible = "arm,armv8-timer";
1188 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1189 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1190 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1191 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1192 };
1193};
Linux 6.x block layer and io_uring tree(s)