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arm64: dts: qcom: sm8250: Add Crypto Engine support
[linux-block.git] / arch / arm64 / boot / dts / qcom / sm8350.dtsi
CommitLineData
b7e8f433
VK		 1// SPDX-License-Identifier: BSD-3-Clause
2/*
4f23d2a5 3 * Copyright (c) 2020, Linaro Limited
b7e8f433
VK		 4 */
5
d4a44105 6#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433 7#include <dt-bindings/interrupt-controller/arm-gic.h>
9fd4887c 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
6d91e201 9#include <dt-bindings/clock/qcom,gcc-sm8350.h>
54af0ceb 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
b7e8f433 11#include <dt-bindings/clock/qcom,rpmh.h>
bc08fbf4 12#include <dt-bindings/dma/qcom-gpi.h>
f0360a7c 13#include <dt-bindings/gpio/gpio.h>
84c856d0 14#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433 15#include <dt-bindings/mailbox/qcom-ipcc.h>
2458a305 16#include <dt-bindings/phy/phy-qcom-qmp.h>
b7e8f433
VK		 17#include <dt-bindings/power/qcom-rpmpd.h>
18#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20f9d94e 19#include <dt-bindings/thermal/thermal.h>
f11d3e7d 20#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433
VK		 21
22/ {
23 interrupt-parent = <&intc>;
24
25 #address-cells = <2>;
26 #size-cells = <2>;
27
28 chosen { };
29
30 clocks {
31 xo_board: xo-board {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <38400000>;
35 clock-output-names = "xo_board";
36 };
37
38 sleep_clk: sleep-clk {
39 compatible = "fixed-clock";
40 clock-frequency = <32000>;
41 #clock-cells = <0>;
42 };
43 };
44
45 cpus {
46 #address-cells = <2>;
47 #size-cells = <0>;
48
49 CPU0: cpu@0 {
50 device_type = "cpu";
51 compatible = "qcom,kryo685";
52 reg = <0x0 0x0>;
c2a18730 53 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 54 enable-method = "psci";
55 next-level-cache = <&L2_0>;
ccbb3abb 56 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 57 power-domains = <&CPU_PD0>;
58 power-domain-names = "psci";
20f9d94e 59 #cooling-cells = <2>;
b7e8f433
VK		 60 L2_0: l2-cache {
61 compatible = "cache";
9435294c 62 cache-level = <2>;
b7e8f433
VK		 63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
65 compatible = "cache";
9435294c 66 cache-level = <3>;
b7e8f433
VK		 67 };
68 };
69 };
70
71 CPU1: cpu@100 {
72 device_type = "cpu";
73 compatible = "qcom,kryo685";
74 reg = <0x0 0x100>;
c2a18730 75 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 76 enable-method = "psci";
77 next-level-cache = <&L2_100>;
ccbb3abb 78 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 79 power-domains = <&CPU_PD1>;
80 power-domain-names = "psci";
20f9d94e 81 #cooling-cells = <2>;
b7e8f433
VK		 82 L2_100: l2-cache {
83 compatible = "cache";
9435294c 84 cache-level = <2>;
b7e8f433
VK		 85 next-level-cache = <&L3_0>;
86 };
87 };
88
89 CPU2: cpu@200 {
90 device_type = "cpu";
91 compatible = "qcom,kryo685";
92 reg = <0x0 0x200>;
c2a18730 93 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 94 enable-method = "psci";
95 next-level-cache = <&L2_200>;
ccbb3abb 96 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 97 power-domains = <&CPU_PD2>;
98 power-domain-names = "psci";
20f9d94e 99 #cooling-cells = <2>;
b7e8f433
VK		 100 L2_200: l2-cache {
101 compatible = "cache";
9435294c 102 cache-level = <2>;
b7e8f433
VK		 103 next-level-cache = <&L3_0>;
104 };
105 };
106
107 CPU3: cpu@300 {
108 device_type = "cpu";
109 compatible = "qcom,kryo685";
110 reg = <0x0 0x300>;
c2a18730 111 clocks = <&cpufreq_hw 0>;
b7e8f433
VK		 112 enable-method = "psci";
113 next-level-cache = <&L2_300>;
ccbb3abb 114 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 115 power-domains = <&CPU_PD3>;
116 power-domain-names = "psci";
20f9d94e 117 #cooling-cells = <2>;
b7e8f433
VK		 118 L2_300: l2-cache {
119 compatible = "cache";
9435294c 120 cache-level = <2>;
b7e8f433
VK		 121 next-level-cache = <&L3_0>;
122 };
123 };
124
125 CPU4: cpu@400 {
126 device_type = "cpu";
127 compatible = "qcom,kryo685";
128 reg = <0x0 0x400>;
c2a18730 129 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 130 enable-method = "psci";
131 next-level-cache = <&L2_400>;
ccbb3abb 132 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 133 power-domains = <&CPU_PD4>;
134 power-domain-names = "psci";
20f9d94e 135 #cooling-cells = <2>;
b7e8f433
VK		 136 L2_400: l2-cache {
137 compatible = "cache";
9435294c 138 cache-level = <2>;
b7e8f433
VK		 139 next-level-cache = <&L3_0>;
140 };
141 };
142
143 CPU5: cpu@500 {
144 device_type = "cpu";
145 compatible = "qcom,kryo685";
146 reg = <0x0 0x500>;
c2a18730 147 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 148 enable-method = "psci";
149 next-level-cache = <&L2_500>;
ccbb3abb 150 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 151 power-domains = <&CPU_PD5>;
152 power-domain-names = "psci";
20f9d94e 153 #cooling-cells = <2>;
b7e8f433
VK		 154 L2_500: l2-cache {
155 compatible = "cache";
9435294c 156 cache-level = <2>;
b7e8f433
VK		 157 next-level-cache = <&L3_0>;
158 };
b7e8f433
VK		 159 };
160
161 CPU6: cpu@600 {
162 device_type = "cpu";
163 compatible = "qcom,kryo685";
164 reg = <0x0 0x600>;
c2a18730 165 clocks = <&cpufreq_hw 1>;
b7e8f433
VK		 166 enable-method = "psci";
167 next-level-cache = <&L2_600>;
ccbb3abb 168 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 169 power-domains = <&CPU_PD6>;
170 power-domain-names = "psci";
20f9d94e 171 #cooling-cells = <2>;
b7e8f433
VK		 172 L2_600: l2-cache {
173 compatible = "cache";
9435294c 174 cache-level = <2>;
b7e8f433
VK		 175 next-level-cache = <&L3_0>;
176 };
177 };
178
179 CPU7: cpu@700 {
180 device_type = "cpu";
181 compatible = "qcom,kryo685";
182 reg = <0x0 0x700>;
c2a18730 183 clocks = <&cpufreq_hw 2>;
b7e8f433
VK		 184 enable-method = "psci";
185 next-level-cache = <&L2_700>;
ccbb3abb 186 qcom,freq-domain = <&cpufreq_hw 2>;
07ddb302
BA		 187 power-domains = <&CPU_PD7>;
188 power-domain-names = "psci";
20f9d94e 189 #cooling-cells = <2>;
b7e8f433
VK		 190 L2_700: l2-cache {
191 compatible = "cache";
9435294c 192 cache-level = <2>;
b7e8f433
VK		 193 next-level-cache = <&L3_0>;
194 };
195 };
07ddb302
BA		 196
197 cpu-map {
198 cluster0 {
199 core0 {
200 cpu = <&CPU0>;
201 };
202
203 core1 {
204 cpu = <&CPU1>;
205 };
206
207 core2 {
208 cpu = <&CPU2>;
209 };
210
211 core3 {
212 cpu = <&CPU3>;
213 };
214
215 core4 {
216 cpu = <&CPU4>;
217 };
218
219 core5 {
220 cpu = <&CPU5>;
221 };
222
223 core6 {
224 cpu = <&CPU6>;
225 };
226
227 core7 {
228 cpu = <&CPU7>;
229 };
230 };
231 };
232
233 idle-states {
234 entry-method = "psci";
235
236 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
237 compatible = "arm,idle-state";
238 idle-state-name = "silver-rail-power-collapse";
239 arm,psci-suspend-param = <0x40000004>;
240 entry-latency-us = <355>;
241 exit-latency-us = <909>;
242 min-residency-us = <3934>;
243 local-timer-stop;
244 };
245
246 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
247 compatible = "arm,idle-state";
248 idle-state-name = "gold-rail-power-collapse";
249 arm,psci-suspend-param = <0x40000004>;
250 entry-latency-us = <241>;
251 exit-latency-us = <1461>;
252 min-residency-us = <4488>;
253 local-timer-stop;
254 };
255 };
256
257 domain-idle-states {
258 CLUSTER_SLEEP_0: cluster-sleep-0 {
259 compatible = "domain-idle-state";
07ddb302
BA		 260 arm,psci-suspend-param = <0x4100c344>;
261 entry-latency-us = <3263>;
262 exit-latency-us = <6562>;
263 min-residency-us = <9987>;
07ddb302
BA		 264 };
265 };
b7e8f433
VK		 266 };
267
268 firmware {
269 scm: scm {
270 compatible = "qcom,scm-sm8350", "qcom,scm";
271 #reset-cells = <1>;
272 };
273 };
274
275 memory@80000000 {
276 device_type = "memory";
277 /* We expect the bootloader to fill in the size */
278 reg = <0x0 0x80000000 0x0 0x0>;
279 };
280
281 pmu {
282 compatible = "arm,armv8-pmuv3";
794d3e30 283 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
b7e8f433
VK		 284 };
285
286 psci {
287 compatible = "arm,psci-1.0";
288 method = "smc";
07ddb302 289
a9371962 290 CPU_PD0: power-domain-cpu0 {
07ddb302
BA		 291 #power-domain-cells = <0>;
292 power-domains = <&CLUSTER_PD>;
293 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
294 };
295
a9371962 296 CPU_PD1: power-domain-cpu1 {
07ddb302
BA		 297 #power-domain-cells = <0>;
298 power-domains = <&CLUSTER_PD>;
299 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
300 };
301
a9371962 302 CPU_PD2: power-domain-cpu2 {
07ddb302
BA		 303 #power-domain-cells = <0>;
304 power-domains = <&CLUSTER_PD>;
305 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
306 };
307
a9371962 308 CPU_PD3: power-domain-cpu3 {
07ddb302
BA		 309 #power-domain-cells = <0>;
310 power-domains = <&CLUSTER_PD>;
311 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
312 };
313
a9371962 314 CPU_PD4: power-domain-cpu4 {
07ddb302
BA		 315 #power-domain-cells = <0>;
316 power-domains = <&CLUSTER_PD>;
317 domain-idle-states = <&BIG_CPU_SLEEP_0>;
318 };
319
a9371962 320 CPU_PD5: power-domain-cpu5 {
07ddb302
BA		 321 #power-domain-cells = <0>;
322 power-domains = <&CLUSTER_PD>;
323 domain-idle-states = <&BIG_CPU_SLEEP_0>;
324 };
325
a9371962 326 CPU_PD6: power-domain-cpu6 {
07ddb302
BA		 327 #power-domain-cells = <0>;
328 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = <&BIG_CPU_SLEEP_0>;
330 };
331
a9371962 332 CPU_PD7: power-domain-cpu7 {
07ddb302
BA		 333 #power-domain-cells = <0>;
334 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = <&BIG_CPU_SLEEP_0>;
336 };
337
a9371962 338 CLUSTER_PD: power-domain-cpu-cluster0 {
07ddb302
BA		 339 #power-domain-cells = <0>;
340 domain-idle-states = <&CLUSTER_SLEEP_0>;
341 };
b7e8f433
VK		 342 };
343
e2eedde4
VK		 344 qup_opp_table_100mhz: opp-table-qup100mhz {
345 compatible = "operating-points-v2";
346
347 opp-50000000 {
348 opp-hz = /bits/ 64 <50000000>;
349 required-opps = <&rpmhpd_opp_min_svs>;
350 };
351
352 opp-75000000 {
353 opp-hz = /bits/ 64 <75000000>;
354 required-opps = <&rpmhpd_opp_low_svs>;
355 };
356
357 opp-100000000 {
358 opp-hz = /bits/ 64 <100000000>;
359 required-opps = <&rpmhpd_opp_svs>;
360 };
361 };
362
363 qup_opp_table_120mhz: opp-table-qup120mhz {
364 compatible = "operating-points-v2";
365
366 opp-50000000 {
367 opp-hz = /bits/ 64 <50000000>;
368 required-opps = <&rpmhpd_opp_min_svs>;
369 };
370
371 opp-75000000 {
372 opp-hz = /bits/ 64 <75000000>;
373 required-opps = <&rpmhpd_opp_low_svs>;
374 };
375
376 opp-120000000 {
377 opp-hz = /bits/ 64 <120000000>;
378 required-opps = <&rpmhpd_opp_svs>;
379 };
380 };
381
b7e8f433
VK		 382 reserved_memory: reserved-memory {
383 #address-cells = <2>;
384 #size-cells = <2>;
385 ranges;
386
387 hyp_mem: memory@80000000 {
388 reg = <0x0 0x80000000 0x0 0x600000>;
389 no-map;
390 };
391
392 xbl_aop_mem: memory@80700000 {
393 no-map;
394 reg = <0x0 0x80700000 0x0 0x160000>;
395 };
396
397 cmd_db: memory@80860000 {
398 compatible = "qcom,cmd-db";
399 reg = <0x0 0x80860000 0x0 0x20000>;
400 no-map;
401 };
402
403 reserved_xbl_uefi_log: memory@80880000 {
404 reg = <0x0 0x80880000 0x0 0x14000>;
405 no-map;
406 };
407
8503babc
KD		 408 smem@80900000 {
409 compatible = "qcom,smem";
b7e8f433 410 reg = <0x0 0x80900000 0x0 0x200000>;
8503babc 411 hwlocks = <&tcsr_mutex 3>;
b7e8f433
VK		 412 no-map;
413 };
414
415 cpucp_fw_mem: memory@80b00000 {
416 reg = <0x0 0x80b00000 0x0 0x100000>;
417 no-map;
418 };
419
420 cdsp_secure_heap: memory@80c00000 {
421 reg = <0x0 0x80c00000 0x0 0x4600000>;
422 no-map;
423 };
424
425 pil_camera_mem: mmeory@85200000 {
426 reg = <0x0 0x85200000 0x0 0x500000>;
427 no-map;
428 };
429
430 pil_video_mem: memory@85700000 {
431 reg = <0x0 0x85700000 0x0 0x500000>;
432 no-map;
433 };
434
435 pil_cvp_mem: memory@85c00000 {
436 reg = <0x0 0x85c00000 0x0 0x500000>;
437 no-map;
438 };
439
440 pil_adsp_mem: memory@86100000 {
441 reg = <0x0 0x86100000 0x0 0x2100000>;
442 no-map;
443 };
444
445 pil_slpi_mem: memory@88200000 {
446 reg = <0x0 0x88200000 0x0 0x1500000>;
447 no-map;
448 };
449
450 pil_cdsp_mem: memory@89700000 {
451 reg = <0x0 0x89700000 0x0 0x1e00000>;
452 no-map;
453 };
454
455 pil_ipa_fw_mem: memory@8b500000 {
456 reg = <0x0 0x8b500000 0x0 0x10000>;
457 no-map;
458 };
459
460 pil_ipa_gsi_mem: memory@8b510000 {
461 reg = <0x0 0x8b510000 0x0 0xa000>;
462 no-map;
463 };
464
465 pil_gpu_mem: memory@8b51a000 {
466 reg = <0x0 0x8b51a000 0x0 0x2000>;
467 no-map;
468 };
469
470 pil_spss_mem: memory@8b600000 {
471 reg = <0x0 0x8b600000 0x0 0x100000>;
472 no-map;
473 };
474
475 pil_modem_mem: memory@8b800000 {
476 reg = <0x0 0x8b800000 0x0 0x10000000>;
477 no-map;
478 };
479
774890c9
VK		 480 rmtfs_mem: memory@9b800000 {
481 compatible = "qcom,rmtfs-mem";
482 reg = <0x0 0x9b800000 0x0 0x280000>;
483 no-map;
484
485 qcom,client-id = <1>;
486 qcom,vmid = <15>;
487 };
488
b7e8f433
VK		 489 hyp_reserved_mem: memory@d0000000 {
490 reg = <0x0 0xd0000000 0x0 0x800000>;
491 no-map;
492 };
493
494 pil_trustedvm_mem: memory@d0800000 {
495 reg = <0x0 0xd0800000 0x0 0x76f7000>;
496 no-map;
497 };
498
499 qrtr_shbuf: memory@d7ef7000 {
500 reg = <0x0 0xd7ef7000 0x0 0x9000>;
501 no-map;
502 };
503
504 chan0_shbuf: memory@d7f00000 {
505 reg = <0x0 0xd7f00000 0x0 0x80000>;
506 no-map;
507 };
508
509 chan1_shbuf: memory@d7f80000 {
510 reg = <0x0 0xd7f80000 0x0 0x80000>;
511 no-map;
512 };
513
514 removed_mem: memory@d8800000 {
515 reg = <0x0 0xd8800000 0x0 0x6800000>;
516 no-map;
517 };
518 };
519
03a41991
VK		 520 smp2p-adsp {
521 compatible = "qcom,smp2p";
522 qcom,smem = <443>, <429>;
523 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
524 IPCC_MPROC_SIGNAL_SMP2P
525 IRQ_TYPE_EDGE_RISING>;
526 mboxes = <&ipcc IPCC_CLIENT_LPASS
527 IPCC_MPROC_SIGNAL_SMP2P>;
528
529 qcom,local-pid = <0>;
530 qcom,remote-pid = <2>;
531
532 smp2p_adsp_out: master-kernel {
533 qcom,entry-name = "master-kernel";
534 #qcom,smem-state-cells = <1>;
535 };
536
537 smp2p_adsp_in: slave-kernel {
538 qcom,entry-name = "slave-kernel";
539 interrupt-controller;
540 #interrupt-cells = <2>;
541 };
542 };
543
544 smp2p-cdsp {
545 compatible = "qcom,smp2p";
546 qcom,smem = <94>, <432>;
547 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
548 IPCC_MPROC_SIGNAL_SMP2P
549 IRQ_TYPE_EDGE_RISING>;
550 mboxes = <&ipcc IPCC_CLIENT_CDSP
551 IPCC_MPROC_SIGNAL_SMP2P>;
552
553 qcom,local-pid = <0>;
554 qcom,remote-pid = <5>;
555
556 smp2p_cdsp_out: master-kernel {
557 qcom,entry-name = "master-kernel";
558 #qcom,smem-state-cells = <1>;
559 };
560
561 smp2p_cdsp_in: slave-kernel {
562 qcom,entry-name = "slave-kernel";
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 };
566 };
567
568 smp2p-modem {
569 compatible = "qcom,smp2p";
570 qcom,smem = <435>, <428>;
571 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
572 IPCC_MPROC_SIGNAL_SMP2P
573 IRQ_TYPE_EDGE_RISING>;
574 mboxes = <&ipcc IPCC_CLIENT_MPSS
575 IPCC_MPROC_SIGNAL_SMP2P>;
576
577 qcom,local-pid = <0>;
578 qcom,remote-pid = <1>;
579
580 smp2p_modem_out: master-kernel {
581 qcom,entry-name = "master-kernel";
582 #qcom,smem-state-cells = <1>;
583 };
584
585 smp2p_modem_in: slave-kernel {
586 qcom,entry-name = "slave-kernel";
587 interrupt-controller;
588 #interrupt-cells = <2>;
589 };
f11d3e7d
AE		 590
591 ipa_smp2p_out: ipa-ap-to-modem {
592 qcom,entry-name = "ipa";
593 #qcom,smem-state-cells = <1>;
594 };
595
596 ipa_smp2p_in: ipa-modem-to-ap {
597 qcom,entry-name = "ipa";
598 interrupt-controller;
599 #interrupt-cells = <2>;
600 };
03a41991
VK		 601 };
602
603 smp2p-slpi {
604 compatible = "qcom,smp2p";
605 qcom,smem = <481>, <430>;
606 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
607 IPCC_MPROC_SIGNAL_SMP2P
608 IRQ_TYPE_EDGE_RISING>;
609 mboxes = <&ipcc IPCC_CLIENT_SLPI
610 IPCC_MPROC_SIGNAL_SMP2P>;
611
612 qcom,local-pid = <0>;
613 qcom,remote-pid = <3>;
614
615 smp2p_slpi_out: master-kernel {
616 qcom,entry-name = "master-kernel";
617 #qcom,smem-state-cells = <1>;
618 };
619
620 smp2p_slpi_in: slave-kernel {
621 qcom,entry-name = "slave-kernel";
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 };
625 };
626
b7e8f433
VK		 627 soc: soc@0 {
628 #address-cells = <2>;
629 #size-cells = <2>;
630 ranges = <0 0 0 0 0x10 0>;
631 dma-ranges = <0 0 0 0 0x10 0>;
632 compatible = "simple-bus";
633
634 gcc: clock-controller@100000 {
635 compatible = "qcom,gcc-sm8350";
636 reg = <0x0 0x00100000 0x0 0x1f0000>;
637 #clock-cells = <1>;
638 #reset-cells = <1>;
639 #power-domain-cells = <1>;
9ea9eb36
KD		 640 clock-names = "bi_tcxo",
641 "sleep_clk",
642 "pcie_0_pipe_clk",
643 "pcie_1_pipe_clk",
644 "ufs_card_rx_symbol_0_clk",
645 "ufs_card_rx_symbol_1_clk",
646 "ufs_card_tx_symbol_0_clk",
647 "ufs_phy_rx_symbol_0_clk",
648 "ufs_phy_rx_symbol_1_clk",
649 "ufs_phy_tx_symbol_0_clk",
650 "usb3_phy_wrapper_gcc_usb30_pipe_clk",
651 "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
652 clocks = <&rpmhcc RPMH_CXO_CLK>,
653 <&sleep_clk>,
6daee406
DB		 654 <&pcie0_phy>,
655 <&pcie1_phy>,
9ea9eb36
KD		 656 <0>,
657 <0>,
658 <0>,
86543bc6
DB		 659 <&ufs_mem_phy_lanes 0>,
660 <&ufs_mem_phy_lanes 1>,
661 <&ufs_mem_phy_lanes 2>,
2458a305 662 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
9ea9eb36 663 <0>;
b7e8f433
VK		 664 };
665
666 ipcc: mailbox@408000 {
667 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
668 reg = <0 0x00408000 0 0x1000>;
669 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
670 interrupt-controller;
671 #interrupt-cells = <3>;
672 #mbox-cells = <2>;
673 };
674
bc08fbf4 675 gpi_dma2: dma-controller@800000 {
b561e225 676 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 677 reg = <0 0x00800000 0 0x60000>;
678 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
690 dma-channels = <12>;
691 dma-channel-mask = <0xff>;
692 iommus = <&apps_smmu 0x5f6 0x0>;
693 #dma-cells = <3>;
694 status = "disabled";
695 };
696
e84d04a2
KD		 697 qupv3_id_2: geniqup@8c0000 {
698 compatible = "qcom,geni-se-qup";
699 reg = <0x0 0x008c0000 0x0 0x6000>;
700 clock-names = "m-ahb", "s-ahb";
701 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
702 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
9bc2c8fe 703 iommus = <&apps_smmu 0x5e3 0x0>;
e84d04a2
KD		 704 #address-cells = <2>;
705 #size-cells = <2>;
706 ranges;
707 status = "disabled";
98374e69
KD		 708
709 i2c14: i2c@880000 {
710 compatible = "qcom,geni-i2c";
711 reg = <0 0x00880000 0 0x4000>;
712 clock-names = "se";
713 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&qup_i2c14_default>;
716 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 717 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
718 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
719 dma-names = "tx", "rx";
98374e69
KD		 720 #address-cells = <1>;
721 #size-cells = <0>;
722 status = "disabled";
723 };
724
725 spi14: spi@880000 {
726 compatible = "qcom,geni-spi";
727 reg = <0 0x00880000 0 0x4000>;
728 clock-names = "se";
729 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
730 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
731 power-domains = <&rpmhpd SM8350_CX>;
732 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 733 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
734 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
735 dma-names = "tx", "rx";
98374e69
KD		 736 #address-cells = <1>;
737 #size-cells = <0>;
738 status = "disabled";
739 };
740
741 i2c15: i2c@884000 {
742 compatible = "qcom,geni-i2c";
743 reg = <0 0x00884000 0 0x4000>;
744 clock-names = "se";
745 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
746 pinctrl-names = "default";
747 pinctrl-0 = <&qup_i2c15_default>;
748 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 749 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
750 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
751 dma-names = "tx", "rx";
98374e69
KD		 752 #address-cells = <1>;
753 #size-cells = <0>;
754 status = "disabled";
755 };
756
757 spi15: spi@884000 {
758 compatible = "qcom,geni-spi";
759 reg = <0 0x00884000 0 0x4000>;
760 clock-names = "se";
761 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
762 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
763 power-domains = <&rpmhpd SM8350_CX>;
764 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 765 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
766 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
767 dma-names = "tx", "rx";
98374e69
KD		 768 #address-cells = <1>;
769 #size-cells = <0>;
770 status = "disabled";
771 };
772
773 i2c16: i2c@888000 {
774 compatible = "qcom,geni-i2c";
775 reg = <0 0x00888000 0 0x4000>;
776 clock-names = "se";
777 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
778 pinctrl-names = "default";
779 pinctrl-0 = <&qup_i2c16_default>;
780 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 781 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
782 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
783 dma-names = "tx", "rx";
98374e69
KD		 784 #address-cells = <1>;
785 #size-cells = <0>;
786 status = "disabled";
787 };
788
789 spi16: spi@888000 {
790 compatible = "qcom,geni-spi";
791 reg = <0 0x00888000 0 0x4000>;
792 clock-names = "se";
793 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
794 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
795 power-domains = <&rpmhpd SM8350_CX>;
796 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 797 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
798 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
799 dma-names = "tx", "rx";
98374e69
KD		 800 #address-cells = <1>;
801 #size-cells = <0>;
802 status = "disabled";
803 };
804
805 i2c17: i2c@88c000 {
806 compatible = "qcom,geni-i2c";
807 reg = <0 0x0088c000 0 0x4000>;
808 clock-names = "se";
809 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&qup_i2c17_default>;
812 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 813 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
814 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
815 dma-names = "tx", "rx";
98374e69
KD		 816 #address-cells = <1>;
817 #size-cells = <0>;
818 status = "disabled";
819 };
820
821 spi17: spi@88c000 {
822 compatible = "qcom,geni-spi";
823 reg = <0 0x0088c000 0 0x4000>;
824 clock-names = "se";
825 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
826 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
827 power-domains = <&rpmhpd SM8350_CX>;
828 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 829 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
830 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
831 dma-names = "tx", "rx";
98374e69
KD		 832 #address-cells = <1>;
833 #size-cells = <0>;
834 status = "disabled";
835 };
836
837 /* QUP no. 18 seems to be strictly SPI/UART-only */
838
839 spi18: spi@890000 {
840 compatible = "qcom,geni-spi";
841 reg = <0 0x00890000 0 0x4000>;
842 clock-names = "se";
843 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
844 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
845 power-domains = <&rpmhpd SM8350_CX>;
846 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 847 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
848 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
849 dma-names = "tx", "rx";
98374e69
KD		 850 #address-cells = <1>;
851 #size-cells = <0>;
852 status = "disabled";
853 };
854
855 uart18: serial@890000 {
856 compatible = "qcom,geni-uart";
857 reg = <0 0x00890000 0 0x4000>;
858 clock-names = "se";
859 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
860 pinctrl-names = "default";
861 pinctrl-0 = <&qup_uart18_default>;
862 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
863 power-domains = <&rpmhpd SM8350_CX>;
864 operating-points-v2 = <&qup_opp_table_100mhz>;
865 status = "disabled";
866 };
867
868 i2c19: i2c@894000 {
869 compatible = "qcom,geni-i2c";
870 reg = <0 0x00894000 0 0x4000>;
871 clock-names = "se";
872 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
873 pinctrl-names = "default";
874 pinctrl-0 = <&qup_i2c19_default>;
875 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 876 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
877 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
878 dma-names = "tx", "rx";
98374e69
KD		 879 #address-cells = <1>;
880 #size-cells = <0>;
881 status = "disabled";
882 };
883
884 spi19: spi@894000 {
885 compatible = "qcom,geni-spi";
886 reg = <0 0x00894000 0 0x4000>;
887 clock-names = "se";
888 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
889 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
890 power-domains = <&rpmhpd SM8350_CX>;
891 operating-points-v2 = <&qup_opp_table_100mhz>;
bc08fbf4
BA		 892 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
893 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
894 dma-names = "tx", "rx";
98374e69
KD		 895 #address-cells = <1>;
896 #size-cells = <0>;
897 status = "disabled";
898 };
e84d04a2
KD		 899 };
900
41d6bca7 901 gpi_dma0: dma-controller@9800000 {
b561e225 902 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 903 reg = <0 0x09800000 0 0x60000>;
904 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
916 dma-channels = <12>;
917 dma-channel-mask = <0x7e>;
918 iommus = <&apps_smmu 0x5b6 0x0>;
919 #dma-cells = <3>;
920 status = "disabled";
921 };
922
87f0b434 923 qupv3_id_0: geniqup@9c0000 {
b7e8f433
VK		 924 compatible = "qcom,geni-se-qup";
925 reg = <0x0 0x009c0000 0x0 0x6000>;
926 clock-names = "m-ahb", "s-ahb";
6d91e201
VK		 927 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
928 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
9bc2c8fe 929 iommus = <&apps_smmu 0x5a3 0>;
b7e8f433
VK		 930 #address-cells = <2>;
931 #size-cells = <2>;
932 ranges;
933 status = "disabled";
934
cf03cd7e
KD		 935 i2c0: i2c@980000 {
936 compatible = "qcom,geni-i2c";
937 reg = <0 0x00980000 0 0x4000>;
938 clock-names = "se";
939 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
940 pinctrl-names = "default";
941 pinctrl-0 = <&qup_i2c0_default>;
942 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 943 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
944 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
945 dma-names = "tx", "rx";
cf03cd7e
KD		 946 #address-cells = <1>;
947 #size-cells = <0>;
948 status = "disabled";
949 };
950
951 spi0: spi@980000 {
952 compatible = "qcom,geni-spi";
953 reg = <0 0x00980000 0 0x4000>;
954 clock-names = "se";
955 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
956 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
957 power-domains = <&rpmhpd SM8350_CX>;
958 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 959 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
960 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
961 dma-names = "tx", "rx";
cf03cd7e
KD		 962 #address-cells = <1>;
963 #size-cells = <0>;
964 status = "disabled";
965 };
966
967 i2c1: i2c@984000 {
968 compatible = "qcom,geni-i2c";
969 reg = <0 0x00984000 0 0x4000>;
970 clock-names = "se";
971 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
972 pinctrl-names = "default";
973 pinctrl-0 = <&qup_i2c1_default>;
974 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 975 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
976 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
977 dma-names = "tx", "rx";
cf03cd7e
KD		 978 #address-cells = <1>;
979 #size-cells = <0>;
980 status = "disabled";
981 };
982
983 spi1: spi@984000 {
984 compatible = "qcom,geni-spi";
985 reg = <0 0x00984000 0 0x4000>;
986 clock-names = "se";
987 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
988 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains = <&rpmhpd SM8350_CX>;
990 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 991 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
992 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
993 dma-names = "tx", "rx";
cf03cd7e
KD		 994 #address-cells = <1>;
995 #size-cells = <0>;
996 status = "disabled";
997 };
998
999 i2c2: i2c@988000 {
1000 compatible = "qcom,geni-i2c";
1001 reg = <0 0x00988000 0 0x4000>;
1002 clock-names = "se";
1003 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1004 pinctrl-names = "default";
1005 pinctrl-0 = <&qup_i2c2_default>;
1006 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1007 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1008 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1009 dma-names = "tx", "rx";
cf03cd7e
KD		 1010 #address-cells = <1>;
1011 #size-cells = <0>;
1012 status = "disabled";
1013 };
1014
1015 spi2: spi@988000 {
1016 compatible = "qcom,geni-spi";
1017 reg = <0 0x00988000 0 0x4000>;
1018 clock-names = "se";
1019 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1020 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1021 power-domains = <&rpmhpd SM8350_CX>;
1022 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1023 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1024 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1025 dma-names = "tx", "rx";
cf03cd7e
KD		 1026 #address-cells = <1>;
1027 #size-cells = <0>;
1028 status = "disabled";
1029 };
1030
b7e8f433
VK		 1031 uart2: serial@98c000 {
1032 compatible = "qcom,geni-debug-uart";
1033 reg = <0 0x0098c000 0 0x4000>;
1034 clock-names = "se";
6d91e201 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
b7e8f433
VK		 1036 pinctrl-names = "default";
1037 pinctrl-0 = <&qup_uart3_default_state>;
1038 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
cf03cd7e
KD		 1039 power-domains = <&rpmhpd SM8350_CX>;
1040 operating-points-v2 = <&qup_opp_table_100mhz>;
cf03cd7e
KD		 1041 status = "disabled";
1042 };
1043
1044 /* QUP no. 3 seems to be strictly SPI-only */
1045
1046 spi3: spi@98c000 {
1047 compatible = "qcom,geni-spi";
1048 reg = <0 0x0098c000 0 0x4000>;
1049 clock-names = "se";
1050 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1051 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1052 power-domains = <&rpmhpd SM8350_CX>;
1053 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1054 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1055 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1056 dma-names = "tx", "rx";
cf03cd7e
KD		 1057 #address-cells = <1>;
1058 #size-cells = <0>;
1059 status = "disabled";
1060 };
1061
1062 i2c4: i2c@990000 {
1063 compatible = "qcom,geni-i2c";
1064 reg = <0 0x00990000 0 0x4000>;
1065 clock-names = "se";
1066 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&qup_i2c4_default>;
1069 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1070 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1071 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1072 dma-names = "tx", "rx";
cf03cd7e
KD		 1073 #address-cells = <1>;
1074 #size-cells = <0>;
1075 status = "disabled";
1076 };
1077
1078 spi4: spi@990000 {
1079 compatible = "qcom,geni-spi";
1080 reg = <0 0x00990000 0 0x4000>;
1081 clock-names = "se";
1082 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1083 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1084 power-domains = <&rpmhpd SM8350_CX>;
1085 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1086 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1087 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1088 dma-names = "tx", "rx";
cf03cd7e
KD		 1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 status = "disabled";
1092 };
1093
1094 i2c5: i2c@994000 {
1095 compatible = "qcom,geni-i2c";
1096 reg = <0 0x00994000 0 0x4000>;
1097 clock-names = "se";
1098 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&qup_i2c5_default>;
1101 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1102 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1103 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1104 dma-names = "tx", "rx";
cf03cd7e
KD		 1105 #address-cells = <1>;
1106 #size-cells = <0>;
1107 status = "disabled";
1108 };
1109
1110 spi5: spi@994000 {
1111 compatible = "qcom,geni-spi";
1112 reg = <0 0x00994000 0 0x4000>;
1113 clock-names = "se";
1114 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1115 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1116 power-domains = <&rpmhpd SM8350_CX>;
1117 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1118 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1119 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1120 dma-names = "tx", "rx";
cf03cd7e
KD		 1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 status = "disabled";
1124 };
1125
1126 i2c6: i2c@998000 {
1127 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00998000 0 0x4000>;
1129 clock-names = "se";
1130 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&qup_i2c6_default>;
1133 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1134 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1135 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1136 dma-names = "tx", "rx";
cf03cd7e
KD		 1137 #address-cells = <1>;
1138 #size-cells = <0>;
1139 status = "disabled";
1140 };
1141
1142 spi6: spi@998000 {
1143 compatible = "qcom,geni-spi";
1144 reg = <0 0x00998000 0 0x4000>;
1145 clock-names = "se";
1146 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1147 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1148 power-domains = <&rpmhpd SM8350_CX>;
1149 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1150 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1151 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1152 dma-names = "tx", "rx";
cf03cd7e
KD		 1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 status = "disabled";
1156 };
1157
1158 uart6: serial@998000 {
1159 compatible = "qcom,geni-uart";
1160 reg = <0 0x00998000 0 0x4000>;
1161 clock-names = "se";
1162 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_uart6_default>;
1165 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1166 power-domains = <&rpmhpd SM8350_CX>;
1167 operating-points-v2 = <&qup_opp_table_100mhz>;
1168 status = "disabled";
1169 };
1170
1171 i2c7: i2c@99c000 {
1172 compatible = "qcom,geni-i2c";
1173 reg = <0 0x0099c000 0 0x4000>;
1174 clock-names = "se";
1175 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&qup_i2c7_default>;
1178 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1179 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1180 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1181 dma-names = "tx", "rx";
cf03cd7e
KD		 1182 #address-cells = <1>;
1183 #size-cells = <0>;
1184 status = "disabled";
1185 };
1186
1187 spi7: spi@99c000 {
1188 compatible = "qcom,geni-spi";
1189 reg = <0 0x0099c000 0 0x4000>;
1190 clock-names = "se";
1191 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1192 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1193 power-domains = <&rpmhpd SM8350_CX>;
1194 operating-points-v2 = <&qup_opp_table_100mhz>;
bc08fbf4
BA		 1195 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1196 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1197 dma-names = "tx", "rx";
b7e8f433
VK		 1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 status = "disabled";
1201 };
1202 };
1203
bc08fbf4 1204 gpi_dma1: dma-controller@a00000 {
b561e225 1205 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 1206 reg = <0 0x00a00000 0 0x60000>;
1207 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1219 dma-channels = <12>;
1220 dma-channel-mask = <0xff>;
1221 iommus = <&apps_smmu 0x56 0x0>;
1222 #dma-cells = <3>;
1223 status = "disabled";
1224 };
1225
06bf656e
JM		 1226 qupv3_id_1: geniqup@ac0000 {
1227 compatible = "qcom,geni-se-qup";
1228 reg = <0x0 0x00ac0000 0x0 0x6000>;
1229 clock-names = "m-ahb", "s-ahb";
1230 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1231 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
9bc2c8fe 1232 iommus = <&apps_smmu 0x43 0>;
06bf656e
JM		 1233 #address-cells = <2>;
1234 #size-cells = <2>;
1235 ranges;
1236 status = "disabled";
1237
89345355
KD		 1238 i2c8: i2c@a80000 {
1239 compatible = "qcom,geni-i2c";
1240 reg = <0 0x00a80000 0 0x4000>;
1241 clock-names = "se";
1242 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&qup_i2c8_default>;
1245 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1246 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1247 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1248 dma-names = "tx", "rx";
89345355
KD		 1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251 status = "disabled";
1252 };
1253
1254 spi8: spi@a80000 {
1255 compatible = "qcom,geni-spi";
1256 reg = <0 0x00a80000 0 0x4000>;
1257 clock-names = "se";
1258 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1259 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1260 power-domains = <&rpmhpd SM8350_CX>;
1261 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 1262 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1263 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1264 dma-names = "tx", "rx";
89345355
KD		 1265 #address-cells = <1>;
1266 #size-cells = <0>;
1267 status = "disabled";
1268 };
1269
1270 i2c9: i2c@a84000 {
1271 compatible = "qcom,geni-i2c";
1272 reg = <0 0x00a84000 0 0x4000>;
1273 clock-names = "se";
1274 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1275 pinctrl-names = "default";
1276 pinctrl-0 = <&qup_i2c9_default>;
1277 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1278 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1279 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1280 dma-names = "tx", "rx";
89345355
KD		 1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283 status = "disabled";
1284 };
1285
1286 spi9: spi@a84000 {
1287 compatible = "qcom,geni-spi";
1288 reg = <0 0x00a84000 0 0x4000>;
1289 clock-names = "se";
1290 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1291 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1292 power-domains = <&rpmhpd SM8350_CX>;
1293 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1294 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1295 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1296 dma-names = "tx", "rx";
89345355
KD		 1297 #address-cells = <1>;
1298 #size-cells = <0>;
1299 status = "disabled";
1300 };
1301
1302 i2c10: i2c@a88000 {
1303 compatible = "qcom,geni-i2c";
1304 reg = <0 0x00a88000 0 0x4000>;
1305 clock-names = "se";
1306 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1307 pinctrl-names = "default";
1308 pinctrl-0 = <&qup_i2c10_default>;
1309 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1310 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1311 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1312 dma-names = "tx", "rx";
89345355
KD		 1313 #address-cells = <1>;
1314 #size-cells = <0>;
1315 status = "disabled";
1316 };
1317
1318 spi10: spi@a88000 {
1319 compatible = "qcom,geni-spi";
1320 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = "se";
1322 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1324 power-domains = <&rpmhpd SM8350_CX>;
1325 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1326 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1327 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1328 dma-names = "tx", "rx";
89345355
KD		 1329 #address-cells = <1>;
1330 #size-cells = <0>;
1331 status = "disabled";
1332 };
1333
1334 i2c11: i2c@a8c000 {
1335 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = "se";
1338 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_i2c11_default>;
1341 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1342 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1343 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1344 dma-names = "tx", "rx";
89345355
KD		 1345 #address-cells = <1>;
1346 #size-cells = <0>;
1347 status = "disabled";
1348 };
1349
1350 spi11: spi@a8c000 {
1351 compatible = "qcom,geni-spi";
1352 reg = <0 0x00a8c000 0 0x4000>;
1353 clock-names = "se";
1354 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1355 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1356 power-domains = <&rpmhpd SM8350_CX>;
1357 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1358 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1359 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1360 dma-names = "tx", "rx";
89345355
KD		 1361 #address-cells = <1>;
1362 #size-cells = <0>;
1363 status = "disabled";
1364 };
1365
1366 i2c12: i2c@a90000 {
1367 compatible = "qcom,geni-i2c";
1368 reg = <0 0x00a90000 0 0x4000>;
1369 clock-names = "se";
1370 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1371 pinctrl-names = "default";
1372 pinctrl-0 = <&qup_i2c12_default>;
1373 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1374 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1375 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1376 dma-names = "tx", "rx";
89345355
KD		 1377 #address-cells = <1>;
1378 #size-cells = <0>;
1379 status = "disabled";
1380 };
1381
1382 spi12: spi@a90000 {
1383 compatible = "qcom,geni-spi";
1384 reg = <0 0x00a90000 0 0x4000>;
1385 clock-names = "se";
1386 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1387 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1388 power-domains = <&rpmhpd SM8350_CX>;
1389 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1390 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1391 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1392 dma-names = "tx", "rx";
89345355
KD		 1393 #address-cells = <1>;
1394 #size-cells = <0>;
1395 status = "disabled";
1396 };
1397
06bf656e
JM		 1398 i2c13: i2c@a94000 {
1399 compatible = "qcom,geni-i2c";
1400 reg = <0 0x00a94000 0 0x4000>;
1401 clock-names = "se";
1402 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1403 pinctrl-names = "default";
89345355 1404 pinctrl-0 = <&qup_i2c13_default>;
06bf656e 1405 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1406 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1407 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1408 dma-names = "tx", "rx";
06bf656e
JM		 1409 #address-cells = <1>;
1410 #size-cells = <0>;
1411 status = "disabled";
1412 };
89345355
KD		 1413
1414 spi13: spi@a94000 {
1415 compatible = "qcom,geni-spi";
1416 reg = <0 0x00a94000 0 0x4000>;
1417 clock-names = "se";
1418 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1419 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1420 power-domains = <&rpmhpd SM8350_CX>;
1421 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1422 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1423 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1424 dma-names = "tx", "rx";
89345355
KD		 1425 #address-cells = <1>;
1426 #size-cells = <0>;
1427 status = "disabled";
1428 };
06bf656e
JM		 1429 };
1430
1417372f
DB		 1431 rng: rng@10d3000 {
1432 compatible = "qcom,prng-ee";
1433 reg = <0 0x010d3000 0 0x1000>;
1434 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1435 clock-names = "core";
1436 };
1437
da6b2482
VK		 1438 config_noc: interconnect@1500000 {
1439 compatible = "qcom,sm8350-config-noc";
1440 reg = <0 0x01500000 0 0xa580>;
4f287e31 1441 #interconnect-cells = <2>;
da6b2482
VK		 1442 qcom,bcm-voters = <&apps_bcm_voter>;
1443 };
1444
1445 mc_virt: interconnect@1580000 {
1446 compatible = "qcom,sm8350-mc-virt";
1447 reg = <0 0x01580000 0 0x1000>;
4f287e31 1448 #interconnect-cells = <2>;
da6b2482
VK		 1449 qcom,bcm-voters = <&apps_bcm_voter>;
1450 };
1451
1452 system_noc: interconnect@1680000 {
1453 compatible = "qcom,sm8350-system-noc";
1454 reg = <0 0x01680000 0 0x1c200>;
4f287e31 1455 #interconnect-cells = <2>;
da6b2482
VK		 1456 qcom,bcm-voters = <&apps_bcm_voter>;
1457 };
1458
1459 aggre1_noc: interconnect@16e0000 {
1460 compatible = "qcom,sm8350-aggre1-noc";
1461 reg = <0 0x016e0000 0 0x1f180>;
4f287e31 1462 #interconnect-cells = <2>;
da6b2482
VK		 1463 qcom,bcm-voters = <&apps_bcm_voter>;
1464 };
1465
1466 aggre2_noc: interconnect@1700000 {
1467 compatible = "qcom,sm8350-aggre2-noc";
1468 reg = <0 0x01700000 0 0x33000>;
4f287e31 1469 #interconnect-cells = <2>;
da6b2482
VK		 1470 qcom,bcm-voters = <&apps_bcm_voter>;
1471 };
1472
1473 mmss_noc: interconnect@1740000 {
1474 compatible = "qcom,sm8350-mmss-noc";
1475 reg = <0 0x01740000 0 0x1f080>;
4f287e31 1476 #interconnect-cells = <2>;
da6b2482
VK		 1477 qcom,bcm-voters = <&apps_bcm_voter>;
1478 };
1479
6daee406
DB		 1480 pcie0: pci@1c00000 {
1481 compatible = "qcom,pcie-sm8350";
1482 reg = <0 0x01c00000 0 0x3000>,
1483 <0 0x60000000 0 0xf1d>,
1484 <0 0x60000f20 0 0xa8>,
1485 <0 0x60001000 0 0x1000>,
1486 <0 0x60100000 0 0x100000>;
1487 reg-names = "parf", "dbi", "elbi", "atu", "config";
1488 device_type = "pci";
1489 linux,pci-domain = <0>;
1490 bus-range = <0x00 0xff>;
1491 num-lanes = <1>;
1492
1493 #address-cells = <3>;
1494 #size-cells = <2>;
1495
cf4e716e
MS		 1496 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1497 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
6daee406
DB		 1498
1499 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1500 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1501 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1507 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1508 "msi4", "msi5", "msi6", "msi7";
1509 #interrupt-cells = <1>;
1510 interrupt-map-mask = <0 0 0 0x7>;
1511 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1512 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1513 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1514 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1515
1516 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1517 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1518 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1519 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1520 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1521 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1522 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1523 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1524 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
1525 clock-names = "aux",
1526 "cfg",
1527 "bus_master",
1528 "bus_slave",
1529 "slave_q2a",
1530 "tbu",
1531 "ddrss_sf_tbu",
1532 "aggre1",
1533 "aggre0";
1534
6daee406
DB		 1535 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1536 <0x100 &apps_smmu 0x1c01 0x1>;
1537
1538 resets = <&gcc GCC_PCIE_0_BCR>;
1539 reset-names = "pci";
1540
1541 power-domains = <&gcc PCIE_0_GDSC>;
1542
1543 phys = <&pcie0_phy>;
1544 phy-names = "pciephy";
1545
1546 status = "disabled";
1547 };
1548
1549 pcie0_phy: phy@1c06000 {
1550 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1551 reg = <0 0x01c06000 0 0x2000>;
1552 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1553 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1554 <&gcc GCC_PCIE_0_CLKREF_EN>,
1555 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
1556 <&gcc GCC_PCIE_0_PIPE_CLK>;
1557 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1558
1559 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1560 reset-names = "phy";
1561
1562 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1563 assigned-clock-rates = <100000000>;
1564
1565 #clock-cells = <0>;
1566 clock-output-names = "pcie_0_pipe_clk";
1567
1568 #phy-cells = <0>;
1569
1570 status = "disabled";
1571 };
1572
1573 pcie1: pci@1c08000 {
1574 compatible = "qcom,pcie-sm8350";
1575 reg = <0 0x01c08000 0 0x3000>,
1576 <0 0x40000000 0 0xf1d>,
1577 <0 0x40000f20 0 0xa8>,
1578 <0 0x40001000 0 0x1000>,
1579 <0 0x40100000 0 0x100000>;
1580 reg-names = "parf", "dbi", "elbi", "atu", "config";
1581 device_type = "pci";
1582 linux,pci-domain = <1>;
1583 bus-range = <0x00 0xff>;
1584 num-lanes = <2>;
1585
1586 #address-cells = <3>;
1587 #size-cells = <2>;
1588
cf4e716e
MS		 1589 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1590 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
6daee406
DB		 1591
1592 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1593 interrupt-names = "msi";
1594 #interrupt-cells = <1>;
1595 interrupt-map-mask = <0 0 0 0x7>;
1596 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1597 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1598 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1599 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1600
1601 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1602 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1603 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1604 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1605 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1606 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1607 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1608 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1609 clock-names = "aux",
1610 "cfg",
1611 "bus_master",
1612 "bus_slave",
1613 "slave_q2a",
1614 "tbu",
1615 "ddrss_sf_tbu",
1616 "aggre1";
1617
6daee406
DB		 1618 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1619 <0x100 &apps_smmu 0x1c81 0x1>;
1620
1621 resets = <&gcc GCC_PCIE_1_BCR>;
1622 reset-names = "pci";
1623
1624 power-domains = <&gcc PCIE_1_GDSC>;
1625
1626 phys = <&pcie1_phy>;
1627 phy-names = "pciephy";
1628
1629 status = "disabled";
1630 };
1631
ab98c21b 1632 pcie1_phy: phy@1c0e000 {
6daee406
DB		 1633 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1634 reg = <0 0x01c0e000 0 0x2000>;
1635 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1636 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1637 <&gcc GCC_PCIE_1_CLKREF_EN>,
1638 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
1639 <&gcc GCC_PCIE_1_PIPE_CLK>;
1640 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1641
1642 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1643 reset-names = "phy";
1644
1645 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1646 assigned-clock-rates = <100000000>;
1647
1648 #clock-cells = <0>;
1649 clock-output-names = "pcie_1_pipe_clk";
1650
1651 #phy-cells = <0>;
1652
1653 status = "disabled";
1654 };
1655
1417372f
DB		 1656 ufs_mem_hc: ufshc@1d84000 {
1657 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1658 "jedec,ufs-2.0";
1659 reg = <0 0x01d84000 0 0x3000>;
1660 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1661 phys = <&ufs_mem_phy_lanes>;
1662 phy-names = "ufsphy";
1663 lanes-per-direction = <2>;
1664 #reset-cells = <1>;
1665 resets = <&gcc GCC_UFS_PHY_BCR>;
1666 reset-names = "rst";
1667
1668 power-domains = <&gcc UFS_PHY_GDSC>;
1669
1670 iommus = <&apps_smmu 0xe0 0x0>;
e607b3c1 1671 dma-coherent;
1417372f
DB		 1672
1673 clock-names =
1674 "core_clk",
1675 "bus_aggr_clk",
1676 "iface_clk",
1677 "core_clk_unipro",
1678 "ref_clk",
1679 "tx_lane0_sync_clk",
1680 "rx_lane0_sync_clk",
1681 "rx_lane1_sync_clk";
1682 clocks =
1683 <&gcc GCC_UFS_PHY_AXI_CLK>,
1684 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1685 <&gcc GCC_UFS_PHY_AHB_CLK>,
1686 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1687 <&rpmhcc RPMH_CXO_CLK>,
1688 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1689 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1690 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1691 freq-table-hz =
1692 <75000000 300000000>,
1693 <0 0>,
1694 <0 0>,
1695 <75000000 300000000>,
1696 <0 0>,
1697 <0 0>,
1698 <0 0>,
1699 <0 0>;
1700 status = "disabled";
da6b2482
VK		 1701 };
1702
1417372f
DB		 1703 ufs_mem_phy: phy@1d87000 {
1704 compatible = "qcom,sm8350-qmp-ufs-phy";
1705 reg = <0 0x01d87000 0 0x1c4>;
1706 #address-cells = <2>;
1707 #size-cells = <2>;
1708 ranges;
1709 clock-names = "ref",
1710 "ref_aux";
1711 clocks = <&rpmhcc RPMH_CXO_CLK>,
1712 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1713
1714 resets = <&ufs_mem_hc 0>;
1715 reset-names = "ufsphy";
1716 status = "disabled";
1717
1718 ufs_mem_phy_lanes: phy@1d87400 {
1719 reg = <0 0x01d87400 0 0x188>,
1720 <0 0x01d87600 0 0x200>,
1721 <0 0x01d87c00 0 0x200>,
1722 <0 0x01d87800 0 0x188>,
1723 <0 0x01d87a00 0 0x200>;
1724 #clock-cells = <1>;
1725 #phy-cells = <0>;
1726 };
da6b2482
VK		 1727 };
1728
f11d3e7d
AE		 1729 ipa: ipa@1e40000 {
1730 compatible = "qcom,sm8350-ipa";
1731
1732 iommus = <&apps_smmu 0x5c0 0x0>,
1733 <&apps_smmu 0x5c2 0x0>;
f3c08ae6
KD		 1734 reg = <0 0x01e40000 0 0x8000>,
1735 <0 0x01e50000 0 0x4b20>,
1736 <0 0x01e04000 0 0x23000>;
f11d3e7d
AE		 1737 reg-names = "ipa-reg",
1738 "ipa-shared",
1739 "gsi";
1740
1741 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1742 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1743 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1744 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1745 interrupt-names = "ipa",
1746 "gsi",
1747 "ipa-clock-query",
1748 "ipa-setup-ready";
1749
1750 clocks = <&rpmhcc RPMH_IPA_CLK>;
1751 clock-names = "core";
1752
4f287e31
RF		 1753 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1754 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
84173ca3
AE		 1755 interconnect-names = "memory",
1756 "config";
f11d3e7d 1757
73419e4d
AE		 1758 qcom,qmp = <&aoss_qmp>;
1759
f11d3e7d
AE		 1760 qcom,smem-states = <&ipa_smp2p_out 0>,
1761 <&ipa_smp2p_out 1>;
1762 qcom,smem-state-names = "ipa-clock-enabled-valid",
1763 "ipa-clock-enabled";
1764
1765 status = "disabled";
1766 };
1767
b7e8f433
VK		 1768 tcsr_mutex: hwlock@1f40000 {
1769 compatible = "qcom,tcsr-mutex";
1770 reg = <0x0 0x01f40000 0x0 0x40000>;
1771 #hwlock-cells = <1>;
1772 };
1773
54af0ceb
DB		 1774 gpu: gpu@3d00000 {
1775 compatible = "qcom,adreno-660.1", "qcom,adreno";
1776
1777 reg = <0 0x03d00000 0 0x40000>,
1778 <0 0x03d9e000 0 0x1000>,
1779 <0 0x03d61000 0 0x800>;
1780 reg-names = "kgsl_3d0_reg_memory",
1781 "cx_mem",
1782 "cx_dbgc";
1783
1784 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1785
1786 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1787
1788 operating-points-v2 = <&gpu_opp_table>;
1789
1790 qcom,gmu = <&gmu>;
1791
1792 status = "disabled";
1793
1794 zap-shader {
1795 memory-region = <&pil_gpu_mem>;
1796 };
1797
1798 /* note: downstream checks gpu binning for 670 Mhz */
1799 gpu_opp_table: opp-table {
1800 compatible = "operating-points-v2";
1801
1802 opp-840000000 {
1803 opp-hz = /bits/ 64 <840000000>;
1804 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1805 };
1806
1807 opp-778000000 {
1808 opp-hz = /bits/ 64 <778000000>;
1809 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1810 };
1811
1812 opp-738000000 {
1813 opp-hz = /bits/ 64 <738000000>;
1814 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1815 };
1816
1817 opp-676000000 {
1818 opp-hz = /bits/ 64 <676000000>;
1819 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1820 };
1821
1822 opp-608000000 {
1823 opp-hz = /bits/ 64 <608000000>;
1824 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1825 };
1826
1827 opp-540000000 {
1828 opp-hz = /bits/ 64 <540000000>;
1829 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1830 };
1831
1832 opp-491000000 {
1833 opp-hz = /bits/ 64 <491000000>;
1834 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1835 };
1836
1837 opp-443000000 {
1838 opp-hz = /bits/ 64 <443000000>;
1839 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1840 };
1841
1842 opp-379000000 {
1843 opp-hz = /bits/ 64 <379000000>;
1844 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1845 };
1846
1847 opp-315000000 {
1848 opp-hz = /bits/ 64 <315000000>;
1849 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1850 };
1851 };
1852 };
1853
1854 gmu: gmu@3d6a000 {
1855 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1856
1857 reg = <0 0x03d6a000 0 0x34000>,
1858 <0 0x03de0000 0 0x10000>,
1859 <0 0x0b290000 0 0x10000>;
1860 reg-names = "gmu", "rscc", "gmu_pdc";
1861
1862 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1863 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1864 interrupt-names = "hfi", "gmu";
1865
1866 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1867 <&gpucc GPU_CC_CXO_CLK>,
1868 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1869 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1870 <&gpucc GPU_CC_AHB_CLK>,
1871 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1872 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
1873 clock-names = "gmu",
1874 "cxo",
1875 "axi",
1876 "memnoc",
1877 "ahb",
1878 "hub",
1879 "smmu_vote";
1880
1881 power-domains = <&gpucc GPU_CX_GDSC>,
1882 <&gpucc GPU_GX_GDSC>;
1883 power-domain-names = "cx",
1884 "gx";
1885
1886 iommus = <&adreno_smmu 5 0x400>;
1887
1888 operating-points-v2 = <&gmu_opp_table>;
1889
1890 gmu_opp_table: opp-table {
1891 compatible = "operating-points-v2";
1892
1893 opp-200000000 {
1894 opp-hz = /bits/ 64 <200000000>;
1895 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1896 };
1897 };
1898 };
1899
1900 gpucc: clock-controller@3d90000 {
1901 compatible = "qcom,sm8350-gpucc";
1902 reg = <0 0x03d90000 0 0x9000>;
1903 clocks = <&rpmhcc RPMH_CXO_CLK>,
1904 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1905 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1906 clock-names = "bi_tcxo",
1907 "gcc_gpu_gpll0_clk_src",
1908 "gcc_gpu_gpll0_div_clk_src";
1909 #clock-cells = <1>;
1910 #reset-cells = <1>;
1911 #power-domain-cells = <1>;
1912 };
1913
1914 adreno_smmu: iommu@3da0000 {
78c61b6b
KD		 1915 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
1916 "qcom,smmu-500", "arm,mmu-500";
54af0ceb
DB		 1917 reg = <0 0x03da0000 0 0x20000>;
1918 #iommu-cells = <2>;
1919 #global-interrupts = <2>;
1920 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1921 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1923 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1930 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1932
1933 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1934 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1935 <&gpucc GPU_CC_AHB_CLK>,
1936 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1937 <&gpucc GPU_CC_CX_GMU_CLK>,
1938 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1939 <&gpucc GPU_CC_HUB_AON_CLK>;
1940 clock-names = "bus",
1941 "iface",
1942 "ahb",
1943 "hlos1_vote_gpu_smmu",
1944 "cx_gmu",
1945 "hub_cx_int",
1946 "hub_aon";
1947
1948 power-domains = <&gpucc GPU_CX_GDSC>;
1949 dma-coherent;
1950 };
1951
1417372f
DB		 1952 lpass_ag_noc: interconnect@3c40000 {
1953 compatible = "qcom,sm8350-lpass-ag-noc";
1954 reg = <0 0x03c40000 0 0xf080>;
1955 #interconnect-cells = <2>;
1956 qcom,bcm-voters = <&apps_bcm_voter>;
1957 };
1958
177fcf0a
VK		 1959 mpss: remoteproc@4080000 {
1960 compatible = "qcom,sm8350-mpss-pas";
1961 reg = <0x0 0x04080000 0x0 0x4040>;
1962
1963 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1964 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1965 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1966 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1967 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1968 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1969 interrupt-names = "wdog", "fatal", "ready", "handover",
1970 "stop-ack", "shutdown-ack";
1971
1972 clocks = <&rpmhcc RPMH_CXO_CLK>;
1973 clock-names = "xo";
1974
d0e285c3
RF		 1975 power-domains = <&rpmhpd SM8350_CX>,
1976 <&rpmhpd SM8350_MSS>;
6b7cb2d2 1977 power-domain-names = "cx", "mss";
177fcf0a 1978
4f287e31 1979 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
da6b2482 1980
177fcf0a
VK		 1981 memory-region = <&pil_modem_mem>;
1982
6b7cb2d2
SS		 1983 qcom,qmp = <&aoss_qmp>;
1984
177fcf0a
VK		 1985 qcom,smem-states = <&smp2p_modem_out 0>;
1986 qcom,smem-state-names = "stop";
1987
1988 status = "disabled";
1989
1990 glink-edge {
1991 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1992 IPCC_MPROC_SIGNAL_GLINK_QMP
1993 IRQ_TYPE_EDGE_RISING>;
1994 mboxes = <&ipcc IPCC_CLIENT_MPSS
1995 IPCC_MPROC_SIGNAL_GLINK_QMP>;
177fcf0a
VK		 1996 label = "modem";
1997 qcom,remote-pid = <1>;
1998 };
1999 };
2000
1417372f
DB		 2001 slpi: remoteproc@5c00000 {
2002 compatible = "qcom,sm8350-slpi-pas";
2003 reg = <0 0x05c00000 0 0x4000>;
2004
2005 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2006 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2007 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2008 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2009 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2010 interrupt-names = "wdog", "fatal", "ready",
2011 "handover", "stop-ack";
2012
2013 clocks = <&rpmhcc RPMH_CXO_CLK>;
2014 clock-names = "xo";
2015
2016 power-domains = <&rpmhpd SM8350_LCX>,
2017 <&rpmhpd SM8350_LMX>;
2018 power-domain-names = "lcx", "lmx";
2019
2020 memory-region = <&pil_slpi_mem>;
2021
2022 qcom,qmp = <&aoss_qmp>;
2023
2024 qcom,smem-states = <&smp2p_slpi_out 0>;
2025 qcom,smem-state-names = "stop";
2026
2027 status = "disabled";
2028
2029 glink-edge {
2030 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2031 IPCC_MPROC_SIGNAL_GLINK_QMP
2032 IRQ_TYPE_EDGE_RISING>;
2033 mboxes = <&ipcc IPCC_CLIENT_SLPI
2034 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2035
2036 label = "slpi";
2037 qcom,remote-pid = <3>;
2038
2039 fastrpc {
2040 compatible = "qcom,fastrpc";
2041 qcom,glink-channels = "fastrpcglink-apps-dsp";
2042 label = "sdsp";
2043 qcom,non-secure-domain;
2044 #address-cells = <1>;
2045 #size-cells = <0>;
2046
2047 compute-cb@1 {
2048 compatible = "qcom,fastrpc-compute-cb";
2049 reg = <1>;
2050 iommus = <&apps_smmu 0x0541 0x0>;
2051 };
2052
2053 compute-cb@2 {
2054 compatible = "qcom,fastrpc-compute-cb";
2055 reg = <2>;
2056 iommus = <&apps_smmu 0x0542 0x0>;
2057 };
2058
2059 compute-cb@3 {
2060 compatible = "qcom,fastrpc-compute-cb";
2061 reg = <3>;
2062 iommus = <&apps_smmu 0x0543 0x0>;
2063 /* note: shared-cb = <4> in downstream */
2064 };
2065 };
2066 };
2067 };
2068
f5f6bd58
DB		 2069 sdhc_2: mmc@8804000 {
2070 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2071 reg = <0 0x08804000 0 0x1000>;
177fcf0a 2072
f5f6bd58
DB		 2073 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2074 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2075 interrupt-names = "hc_irq", "pwr_irq";
177fcf0a 2076
f5f6bd58
DB		 2077 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2078 <&gcc GCC_SDCC2_APPS_CLK>,
2079 <&rpmhcc RPMH_CXO_CLK>;
2080 clock-names = "iface", "core", "xo";
2081 resets = <&gcc GCC_SDCC2_BCR>;
2082 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2083 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2084 interconnect-names = "sdhc-ddr","cpu-sdhc";
2085 iommus = <&apps_smmu 0x4a0 0x0>;
2086 power-domains = <&rpmhpd SM8350_CX>;
2087 operating-points-v2 = <&sdhc2_opp_table>;
2088 bus-width = <4>;
2089 dma-coherent;
177fcf0a 2090
f5f6bd58 2091 status = "disabled";
da6b2482 2092
f5f6bd58
DB		 2093 sdhc2_opp_table: opp-table {
2094 compatible = "operating-points-v2";
177fcf0a 2095
f5f6bd58
DB		 2096 opp-100000000 {
2097 opp-hz = /bits/ 64 <100000000>;
2098 required-opps = <&rpmhpd_opp_low_svs>;
2099 };
6b7cb2d2 2100
f5f6bd58
DB		 2101 opp-202000000 {
2102 opp-hz = /bits/ 64 <202000000>;
2103 required-opps = <&rpmhpd_opp_svs_l1>;
2104 };
2105 };
2106 };
177fcf0a 2107
f5f6bd58
DB		 2108 usb_1_hsphy: phy@88e3000 {
2109 compatible = "qcom,sm8350-usb-hs-phy",
2110 "qcom,usb-snps-hs-7nm-phy";
2111 reg = <0 0x088e3000 0 0x400>;
177fcf0a 2112 status = "disabled";
f5f6bd58 2113 #phy-cells = <0>;
177fcf0a 2114
f5f6bd58
DB		 2115 clocks = <&rpmhcc RPMH_CXO_CLK>;
2116 clock-names = "ref";
177fcf0a 2117
f5f6bd58
DB		 2118 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2119 };
178056a4 2120
f5f6bd58
DB		 2121 usb_2_hsphy: phy@88e4000 {
2122 compatible = "qcom,sm8250-usb-hs-phy",
2123 "qcom,usb-snps-hs-7nm-phy";
2124 reg = <0 0x088e4000 0 0x400>;
2125 status = "disabled";
2126 #phy-cells = <0>;
178056a4 2127
f5f6bd58
DB		 2128 clocks = <&rpmhcc RPMH_CXO_CLK>;
2129 clock-names = "ref";
e780fb31 2130
6d91e201 2131 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
e780fb31
JP		 2132 };
2133
a560ab70 2134 usb_1_qmpphy: phy@88e8000 {
2458a305
NA		 2135 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2136 reg = <0 0x088e8000 0 0x3000>;
e780fb31 2137
6d91e201 2138 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
e780fb31 2139 <&rpmhcc RPMH_CXO_CLK>,
2458a305
NA		 2140 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2141 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2142 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
e780fb31 2143
6d91e201
VK		 2144 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2145 <&gcc GCC_USB3_PHY_PRIM_BCR>;
e780fb31
JP		 2146 reset-names = "phy", "common";
2147
2458a305
NA		 2148 #clock-cells = <1>;
2149 #phy-cells = <1>;
2150
2151 status = "disabled";
d8313125
NA		 2152
2153 ports {
2154 #address-cells = <1>;
2155 #size-cells = <0>;
2156
2157 port@0 {
2158 reg = <0>;
2159
2160 usb_1_qmpphy_out: endpoint {
2161 };
2162 };
2163
2164 port@1 {
2165 reg = <1>;
2166
2167 usb_1_qmpphy_usb_ss_in: endpoint {
2168 };
2169 };
2170
2171 port@2 {
2172 reg = <2>;
2173
2174 usb_1_qmpphy_dp_in: endpoint {
2175 };
2176 };
2177 };
e780fb31
JP		 2178 };
2179
2180 usb_2_qmpphy: phy-wrapper@88eb000 {
2181 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2182 reg = <0 0x088eb000 0 0x200>;
2183 status = "disabled";
e780fb31
JP		 2184 #address-cells = <2>;
2185 #size-cells = <2>;
2186 ranges;
2187
6d91e201 2188 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
e780fb31 2189 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 2190 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2191 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
e780fb31
JP		 2192 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2193
6d91e201
VK		 2194 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2195 <&gcc GCC_USB3_PHY_SEC_BCR>;
e780fb31
JP		 2196 reset-names = "phy", "common";
2197
2198 usb_2_ssphy: phy@88ebe00 {
2199 reg = <0 0x088ebe00 0 0x200>,
2200 <0 0x088ec000 0 0x200>,
2201 <0 0x088eb200 0 0x1100>;
2202 #phy-cells = <0>;
af551554 2203 #clock-cells = <0>;
6d91e201 2204 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
e780fb31
JP		 2205 clock-names = "pipe0";
2206 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2207 };
2208 };
2209
1dee9e3b 2210 dc_noc: interconnect@90c0000 {
da6b2482
VK		 2211 compatible = "qcom,sm8350-dc-noc";
2212 reg = <0 0x090c0000 0 0x4200>;
4f287e31 2213 #interconnect-cells = <2>;
da6b2482
VK		 2214 qcom,bcm-voters = <&apps_bcm_voter>;
2215 };
2216
2217 gem_noc: interconnect@9100000 {
2218 compatible = "qcom,sm8350-gem-noc";
2219 reg = <0 0x09100000 0 0xb4000>;
4f287e31 2220 #interconnect-cells = <2>;
da6b2482
VK		 2221 qcom,bcm-voters = <&apps_bcm_voter>;
2222 };
2223
9ac8999e
KD		 2224 system-cache-controller@9200000 {
2225 compatible = "qcom,sm8350-llcc";
7ae317cb
MS		 2226 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2227 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2228 <0 0x09600000 0 0x58000>;
2229 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2230 "llcc3_base", "llcc_broadcast_base";
9ac8999e
KD		 2231 };
2232
1417372f
DB		 2233 compute_noc: interconnect@a0c0000 {
2234 compatible = "qcom,sm8350-compute-noc";
2235 reg = <0 0x0a0c0000 0 0xa180>;
2236 #interconnect-cells = <2>;
2237 qcom,bcm-voters = <&apps_bcm_voter>;
2238 };
2239
e780fb31
JP		 2240 usb_1: usb@a6f8800 {
2241 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2242 reg = <0 0x0a6f8800 0 0x400>;
2243 status = "disabled";
2244 #address-cells = <2>;
2245 #size-cells = <2>;
2246 ranges;
2247
6d91e201
VK		 2248 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2249 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2250 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
8d5fd4e4
KK		 2251 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2252 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2253 clock-names = "cfg_noc",
2254 "core",
2255 "iface",
2256 "sleep",
2257 "mock_utmi";
e780fb31 2258
6d91e201
VK		 2259 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2260 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
e780fb31
JP		 2261 assigned-clock-rates = <19200000>, <200000000>;
2262
2263 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
5b7e3499 2264 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
e780fb31 2265 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
5b7e3499
JH		 2266 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2267 interrupt-names = "hs_phy_irq",
2268 "ss_phy_irq",
2269 "dm_hs_phy_irq",
2270 "dp_hs_phy_irq";
e780fb31 2271
6d91e201 2272 power-domains = <&gcc USB30_PRIM_GDSC>;
e780fb31 2273
6d91e201 2274 resets = <&gcc GCC_USB30_PRIM_BCR>;
e780fb31 2275
2aa2b50d 2276 usb_1_dwc3: usb@a600000 {
e780fb31
JP		 2277 compatible = "snps,dwc3";
2278 reg = <0 0x0a600000 0 0xcd00>;
2279 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2280 iommus = <&apps_smmu 0x0 0x0>;
2281 snps,dis_u2_susphy_quirk;
2282 snps,dis_enblslpm_quirk;
2458a305 2283 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
e780fb31 2284 phy-names = "usb2-phy", "usb3-phy";
75b81e5a
NA		 2285
2286 ports {
2287 #address-cells = <1>;
2288 #size-cells = <0>;
2289
2290 port@0 {
2291 reg = <0>;
2292
2293 usb_1_dwc3_hs: endpoint {
2294 };
2295 };
2296
2297 port@1 {
2298 reg = <1>;
2299
2300 usb_1_dwc3_ss: endpoint {
2301 };
2302 };
2303 };
e780fb31
JP		 2304 };
2305 };
2306
2307 usb_2: usb@a8f8800 {
2308 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2309 reg = <0 0x0a8f8800 0 0x400>;
2310 status = "disabled";
2311 #address-cells = <2>;
2312 #size-cells = <2>;
2313 ranges;
2314
6d91e201
VK		 2315 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2316 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2317 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
6d91e201 2318 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
8d5fd4e4 2319 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
6d91e201 2320 <&gcc GCC_USB3_SEC_CLKREF_EN>;
8d5fd4e4
KK		 2321 clock-names = "cfg_noc",
2322 "core",
2323 "iface",
2324 "sleep",
2325 "mock_utmi",
2326 "xo";
e780fb31 2327
6d91e201
VK		 2328 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2329 <&gcc GCC_USB30_SEC_MASTER_CLK>;
e780fb31
JP		 2330 assigned-clock-rates = <19200000>, <200000000>;
2331
2332 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
5b7e3499 2333 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
e780fb31 2334 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
5b7e3499
JH		 2335 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2336 interrupt-names = "hs_phy_irq",
2337 "ss_phy_irq",
2338 "dm_hs_phy_irq",
2339 "dp_hs_phy_irq";
e780fb31 2340
6d91e201 2341 power-domains = <&gcc USB30_SEC_GDSC>;
e780fb31 2342
6d91e201 2343 resets = <&gcc GCC_USB30_SEC_BCR>;
e780fb31 2344
2aa2b50d 2345 usb_2_dwc3: usb@a800000 {
e780fb31
JP		 2346 compatible = "snps,dwc3";
2347 reg = <0 0x0a800000 0 0xcd00>;
2348 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2349 iommus = <&apps_smmu 0x20 0x0>;
2350 snps,dis_u2_susphy_quirk;
2351 snps,dis_enblslpm_quirk;
2352 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2353 phy-names = "usb2-phy", "usb3-phy";
2354 };
2355 };
177fcf0a 2356
d4a44105
RF		 2357 mdss: display-subsystem@ae00000 {
2358 compatible = "qcom,sm8350-mdss";
2359 reg = <0 0x0ae00000 0 0x1000>;
2360 reg-names = "mdss";
2361
2362 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2363 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2364 interconnect-names = "mdp0-mem", "mdp1-mem";
2365
2366 power-domains = <&dispcc MDSS_GDSC>;
2367 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2368
2369 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2370 <&gcc GCC_DISP_HF_AXI_CLK>,
2371 <&gcc GCC_DISP_SF_AXI_CLK>,
2372 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2373 clock-names = "iface", "bus", "nrt_bus", "core";
2374
2375 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2376 interrupt-controller;
2377 #interrupt-cells = <1>;
2378
2379 iommus = <&apps_smmu 0x820 0x402>;
2380
2381 status = "disabled";
2382
2383 #address-cells = <2>;
2384 #size-cells = <2>;
2385 ranges;
2386
2387 dpu_opp_table: opp-table {
2388 compatible = "operating-points-v2";
2389
2390 /* TODO: opp-200000000 should work with
2391 * &rpmhpd_opp_low_svs, but one some of
2392 * sm8350_hdk boards reboot using this
2393 * opp.
2394 */
2395 opp-200000000 {
2396 opp-hz = /bits/ 64 <200000000>;
2397 required-opps = <&rpmhpd_opp_svs>;
2398 };
2399
2400 opp-300000000 {
2401 opp-hz = /bits/ 64 <300000000>;
2402 required-opps = <&rpmhpd_opp_svs>;
2403 };
2404
2405 opp-345000000 {
2406 opp-hz = /bits/ 64 <345000000>;
2407 required-opps = <&rpmhpd_opp_svs_l1>;
2408 };
2409
2410 opp-460000000 {
2411 opp-hz = /bits/ 64 <460000000>;
2412 required-opps = <&rpmhpd_opp_nom>;
2413 };
2414 };
2415
2416 mdss_mdp: display-controller@ae01000 {
2417 compatible = "qcom,sm8350-dpu";
2418 reg = <0 0x0ae01000 0 0x8f000>,
2419 <0 0x0aeb0000 0 0x2008>;
2420 reg-names = "mdp", "vbif";
2421
2422 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2423 <&gcc GCC_DISP_SF_AXI_CLK>,
2424 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2425 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2426 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2427 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2428 clock-names = "bus",
2429 "nrt_bus",
2430 "iface",
2431 "lut",
2432 "core",
2433 "vsync";
2434
2435 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2436 assigned-clock-rates = <19200000>;
2437
2438 operating-points-v2 = <&dpu_opp_table>;
2439 power-domains = <&rpmhpd SM8350_MMCX>;
2440
2441 interrupt-parent = <&mdss>;
2442 interrupts = <0>;
2443
2444 ports {
2445 #address-cells = <1>;
2446 #size-cells = <0>;
2447
2448 port@0 {
2449 reg = <0>;
2450 dpu_intf1_out: endpoint {
2a07efb8 2451 remote-endpoint = <&mdss_dsi0_in>;
d4a44105
RF		 2452 };
2453 };
b904227a
KD		 2454
2455 port@1 {
2456 reg = <1>;
2457 dpu_intf2_out: endpoint {
2458 remote-endpoint = <&mdss_dsi1_in>;
2459 };
2460 };
a2802008
NA		 2461
2462 port@2 {
2463 reg = <2>;
2464 dpu_intf0_out: endpoint {
2465 remote-endpoint = <&mdss_dp_in>;
2466 };
2467 };
2468 };
2469 };
2470
2471 mdss_dp: displayport-controller@ae90000 {
2472 compatible = "qcom,sm8350-dp";
2473 reg = <0 0xae90000 0 0x200>,
2474 <0 0xae90200 0 0x200>,
2475 <0 0xae90400 0 0x600>,
2476 <0 0xae91000 0 0x400>,
2477 <0 0xae91400 0 0x400>;
2478 interrupt-parent = <&mdss>;
2479 interrupts = <12>;
2480 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2481 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2482 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2483 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
2484 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
2485 clock-names = "core_iface",
2486 "core_aux",
2487 "ctrl_link",
2488 "ctrl_link_iface",
2489 "stream_pixel";
2490
2491 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2492 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
2493 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2494 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2495
2496 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2497 phy-names = "dp";
2498
2499 #sound-dai-cells = <0>;
2500
2501 operating-points-v2 = <&dp_opp_table>;
2502 power-domains = <&rpmhpd SM8350_MMCX>;
2503
2504 status = "disabled";
2505
2506 ports {
2507 #address-cells = <1>;
2508 #size-cells = <0>;
2509
2510 port@0 {
2511 reg = <0>;
2512 mdss_dp_in: endpoint {
2513 remote-endpoint = <&dpu_intf0_out>;
2514 };
2515 };
2516 };
2517
2518 dp_opp_table: opp-table {
2519 compatible = "operating-points-v2";
2520
2521 opp-160000000 {
2522 opp-hz = /bits/ 64 <160000000>;
2523 required-opps = <&rpmhpd_opp_low_svs>;
2524 };
2525
2526 opp-270000000 {
2527 opp-hz = /bits/ 64 <270000000>;
2528 required-opps = <&rpmhpd_opp_svs>;
2529 };
2530
2531 opp-540000000 {
2532 opp-hz = /bits/ 64 <540000000>;
2533 required-opps = <&rpmhpd_opp_svs_l1>;
2534 };
2535
2536 opp-810000000 {
2537 opp-hz = /bits/ 64 <810000000>;
2538 required-opps = <&rpmhpd_opp_nom>;
2539 };
d4a44105
RF		 2540 };
2541 };
2542
2543 mdss_dsi0: dsi@ae94000 {
d7133d6d 2544 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
d4a44105
RF		 2545 reg = <0 0x0ae94000 0 0x400>;
2546 reg-names = "dsi_ctrl";
2547
2548 interrupt-parent = <&mdss>;
2549 interrupts = <4>;
2550
2551 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2552 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2553 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2554 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2555 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2556 <&gcc GCC_DISP_HF_AXI_CLK>;
2557 clock-names = "byte",
2558 "byte_intf",
2559 "pixel",
2560 "core",
2561 "iface",
2562 "bus";
2563
2564 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2565 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2566 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2567 <&mdss_dsi0_phy 1>;
2568
2569 operating-points-v2 = <&dsi0_opp_table>;
2570 power-domains = <&rpmhpd SM8350_MMCX>;
2571
2572 phys = <&mdss_dsi0_phy>;
2573
6636818e
KD		 2574 #address-cells = <1>;
2575 #size-cells = <0>;
2576
d4a44105
RF		 2577 status = "disabled";
2578
2579 dsi0_opp_table: opp-table {
2580 compatible = "operating-points-v2";
2581
2582 /* TODO: opp-187500000 should work with
2583 * &rpmhpd_opp_low_svs, but one some of
2584 * sm8350_hdk boards reboot using this
2585 * opp.
2586 */
2587 opp-187500000 {
2588 opp-hz = /bits/ 64 <187500000>;
2589 required-opps = <&rpmhpd_opp_svs>;
2590 };
2591
2592 opp-300000000 {
2593 opp-hz = /bits/ 64 <300000000>;
2594 required-opps = <&rpmhpd_opp_svs>;
2595 };
2596
2597 opp-358000000 {
2598 opp-hz = /bits/ 64 <358000000>;
2599 required-opps = <&rpmhpd_opp_svs_l1>;
2600 };
2601 };
2602
2603 ports {
2604 #address-cells = <1>;
2605 #size-cells = <0>;
2606
2607 port@0 {
2608 reg = <0>;
2a07efb8 2609 mdss_dsi0_in: endpoint {
d4a44105
RF		 2610 remote-endpoint = <&dpu_intf1_out>;
2611 };
2612 };
2613
2614 port@1 {
2615 reg = <1>;
2a07efb8 2616 mdss_dsi0_out: endpoint {
d4a44105
RF		 2617 };
2618 };
2619 };
2620 };
2621
51f83fbb
DB		 2622 mdss_dsi0_phy: phy@ae94400 {
2623 compatible = "qcom,sm8350-dsi-phy-5nm";
2624 reg = <0 0x0ae94400 0 0x200>,
2625 <0 0x0ae94600 0 0x280>,
2626 <0 0x0ae94900 0 0x27c>;
2627 reg-names = "dsi_phy",
2628 "dsi_phy_lane",
2629 "dsi_pll";
2630
2631 #clock-cells = <1>;
2632 #phy-cells = <0>;
2633
2634 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2635 <&rpmhcc RPMH_CXO_CLK>;
2636 clock-names = "iface", "ref";
2637
2638 status = "disabled";
2639 };
2640
2641 mdss_dsi1: dsi@ae96000 {
2642 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2643 reg = <0 0x0ae96000 0 0x400>;
2644 reg-names = "dsi_ctrl";
2645
2646 interrupt-parent = <&mdss>;
2647 interrupts = <5>;
2648
2649 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2650 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2651 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2652 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2653 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2654 <&gcc GCC_DISP_HF_AXI_CLK>;
2655 clock-names = "byte",
2656 "byte_intf",
2657 "pixel",
2658 "core",
2659 "iface",
2660 "bus";
2661
2662 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2663 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2664 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2665 <&mdss_dsi1_phy 1>;
2666
2667 operating-points-v2 = <&dsi1_opp_table>;
2668 power-domains = <&rpmhpd SM8350_MMCX>;
2669
2670 phys = <&mdss_dsi1_phy>;
2671
2672 #address-cells = <1>;
2673 #size-cells = <0>;
2674
2675 status = "disabled";
2676
2677 dsi1_opp_table: opp-table {
2678 compatible = "operating-points-v2";
2679
2680 /* TODO: opp-187500000 should work with
2681 * &rpmhpd_opp_low_svs, but one some of
2682 * sm8350_hdk boards reboot using this
2683 * opp.
2684 */
2685 opp-187500000 {
2686 opp-hz = /bits/ 64 <187500000>;
2687 required-opps = <&rpmhpd_opp_svs>;
2688 };
2689
2690 opp-300000000 {
2691 opp-hz = /bits/ 64 <300000000>;
2692 required-opps = <&rpmhpd_opp_svs>;
2693 };
2694
2695 opp-358000000 {
2696 opp-hz = /bits/ 64 <358000000>;
2697 required-opps = <&rpmhpd_opp_svs_l1>;
2698 };
2699 };
2700
2701 ports {
2702 #address-cells = <1>;
2703 #size-cells = <0>;
2704
2705 port@0 {
2706 reg = <0>;
2707 mdss_dsi1_in: endpoint {
2708 remote-endpoint = <&dpu_intf2_out>;
2709 };
2710 };
2711
2712 port@1 {
2713 reg = <1>;
2714 mdss_dsi1_out: endpoint {
2715 };
2716 };
2717 };
2718 };
2719
2720 mdss_dsi1_phy: phy@ae96400 {
2721 compatible = "qcom,sm8350-dsi-phy-5nm";
2722 reg = <0 0x0ae96400 0 0x200>,
2723 <0 0x0ae96600 0 0x280>,
2724 <0 0x0ae96900 0 0x27c>;
2725 reg-names = "dsi_phy",
2726 "dsi_phy_lane",
2727 "dsi_pll";
2728
2729 #clock-cells = <1>;
2730 #phy-cells = <0>;
2731
2732 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2733 <&rpmhcc RPMH_CXO_CLK>;
2734 clock-names = "iface", "ref";
2735
2736 status = "disabled";
2737 };
2738 };
2739
2740 dispcc: clock-controller@af00000 {
2741 compatible = "qcom,sm8350-dispcc";
2742 reg = <0 0x0af00000 0 0x10000>;
2743 clocks = <&rpmhcc RPMH_CXO_CLK>,
2744 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2745 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2458a305
NA		 2746 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2747 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
51f83fbb
DB		 2748 clock-names = "bi_tcxo",
2749 "dsi0_phy_pll_out_byteclk",
2750 "dsi0_phy_pll_out_dsiclk",
2751 "dsi1_phy_pll_out_byteclk",
2752 "dsi1_phy_pll_out_dsiclk",
2753 "dp_phy_pll_link_clk",
2754 "dp_phy_pll_vco_div_clk";
2755 #clock-cells = <1>;
2756 #reset-cells = <1>;
2757 #power-domain-cells = <1>;
2758
2759 power-domains = <&rpmhpd SM8350_MMCX>;
2760 };
2761
2762 pdc: interrupt-controller@b220000 {
2763 compatible = "qcom,sm8350-pdc", "qcom,pdc";
2764 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2765 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2766 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
2767 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
2768 <156 716 12>;
2769 #interrupt-cells = <2>;
2770 interrupt-parent = <&intc>;
2771 interrupt-controller;
2772 };
2773
2774 tsens0: thermal-sensor@c263000 {
2775 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2776 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2777 <0 0x0c222000 0 0x8>; /* SROT */
2778 #qcom,sensors = <15>;
2779 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2780 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2781 interrupt-names = "uplow", "critical";
2782 #thermal-sensor-cells = <1>;
2783 };
2784
2785 tsens1: thermal-sensor@c265000 {
2786 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2787 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2788 <0 0x0c223000 0 0x8>; /* SROT */
2789 #qcom,sensors = <14>;
2790 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2791 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2792 interrupt-names = "uplow", "critical";
2793 #thermal-sensor-cells = <1>;
2794 };
2795
2796 aoss_qmp: power-management@c300000 {
2797 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2798 reg = <0 0x0c300000 0 0x400>;
2799 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2800 IRQ_TYPE_EDGE_RISING>;
2801 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2802
2803 #clock-cells = <0>;
2804 };
2805
2806 sram@c3f0000 {
2807 compatible = "qcom,rpmh-stats";
2808 reg = <0 0x0c3f0000 0 0x400>;
2809 };
2810
2811 spmi_bus: spmi@c440000 {
2812 compatible = "qcom,spmi-pmic-arb";
2813 reg = <0x0 0x0c440000 0x0 0x1100>,
2814 <0x0 0x0c600000 0x0 0x2000000>,
2815 <0x0 0x0e600000 0x0 0x100000>,
2816 <0x0 0x0e700000 0x0 0xa0000>,
2817 <0x0 0x0c40a000 0x0 0x26000>;
2818 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2819 interrupt-names = "periph_irq";
2820 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2821 qcom,ee = <0>;
2822 qcom,channel = <0>;
2823 #address-cells = <2>;
2824 #size-cells = <0>;
2825 interrupt-controller;
2826 #interrupt-cells = <4>;
2827 };
2828
2829 tlmm: pinctrl@f100000 {
2830 compatible = "qcom,sm8350-tlmm";
2831 reg = <0 0x0f100000 0 0x300000>;
2832 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2833 gpio-controller;
2834 #gpio-cells = <2>;
2835 interrupt-controller;
2836 #interrupt-cells = <2>;
2837 gpio-ranges = <&tlmm 0 0 204>;
2838 wakeup-parent = <&pdc>;
2839
2840 sdc2_default_state: sdc2-default-state {
2841 clk-pins {
2842 pins = "sdc2_clk";
2843 drive-strength = <16>;
2844 bias-disable;
2845 };
2846
2847 cmd-pins {
2848 pins = "sdc2_cmd";
2849 drive-strength = <16>;
2850 bias-pull-up;
2851 };
2852
2853 data-pins {
2854 pins = "sdc2_data";
2855 drive-strength = <16>;
2856 bias-pull-up;
2857 };
2858 };
2859
2860 sdc2_sleep_state: sdc2-sleep-state {
2861 clk-pins {
2862 pins = "sdc2_clk";
2863 drive-strength = <2>;
2864 bias-disable;
2865 };
d4a44105 2866
51f83fbb
DB		 2867 cmd-pins {
2868 pins = "sdc2_cmd";
2869 drive-strength = <2>;
2870 bias-pull-up;
2871 };
d4a44105 2872
51f83fbb
DB		 2873 data-pins {
2874 pins = "sdc2_data";
2875 drive-strength = <2>;
2876 bias-pull-up;
2877 };
d4a44105
RF		 2878 };
2879
51f83fbb
DB		 2880 qup_uart3_default_state: qup-uart3-default-state {
2881 rx-pins {
2882 pins = "gpio18";
2883 function = "qup3";
2884 };
2885 tx-pins {
2886 pins = "gpio19";
2887 function = "qup3";
2888 };
2889 };
f5f6bd58 2890
51f83fbb
DB		 2891 qup_uart6_default: qup-uart6-default-state {
2892 pins = "gpio30", "gpio31";
2893 function = "qup6";
2894 drive-strength = <2>;
2895 bias-disable;
2896 };
f5f6bd58 2897
51f83fbb
DB		 2898 qup_uart18_default: qup-uart18-default-state {
2899 pins = "gpio58", "gpio59";
2900 function = "qup18";
2901 drive-strength = <2>;
2902 bias-disable;
2903 };
f5f6bd58 2904
51f83fbb
DB		 2905 qup_i2c0_default: qup-i2c0-default-state {
2906 pins = "gpio4", "gpio5";
2907 function = "qup0";
2908 drive-strength = <2>;
2909 bias-pull-up;
2910 };
f5f6bd58 2911
51f83fbb
DB		 2912 qup_i2c1_default: qup-i2c1-default-state {
2913 pins = "gpio8", "gpio9";
2914 function = "qup1";
2915 drive-strength = <2>;
2916 bias-pull-up;
2917 };
f5f6bd58 2918
51f83fbb
DB		 2919 qup_i2c2_default: qup-i2c2-default-state {
2920 pins = "gpio12", "gpio13";
2921 function = "qup2";
2922 drive-strength = <2>;
2923 bias-pull-up;
2924 };
f5f6bd58 2925
51f83fbb
DB		 2926 qup_i2c4_default: qup-i2c4-default-state {
2927 pins = "gpio20", "gpio21";
2928 function = "qup4";
2929 drive-strength = <2>;
2930 bias-pull-up;
2931 };
f5f6bd58 2932
51f83fbb
DB		 2933 qup_i2c5_default: qup-i2c5-default-state {
2934 pins = "gpio24", "gpio25";
2935 function = "qup5";
2936 drive-strength = <2>;
2937 bias-pull-up;
2938 };
f5f6bd58 2939
51f83fbb
DB		 2940 qup_i2c6_default: qup-i2c6-default-state {
2941 pins = "gpio28", "gpio29";
2942 function = "qup6";
2943 drive-strength = <2>;
2944 bias-pull-up;
2945 };
f5f6bd58 2946
51f83fbb
DB		 2947 qup_i2c7_default: qup-i2c7-default-state {
2948 pins = "gpio32", "gpio33";
2949 function = "qup7";
2950 drive-strength = <2>;
2951 bias-disable;
2952 };
f5f6bd58 2953
51f83fbb
DB		 2954 qup_i2c8_default: qup-i2c8-default-state {
2955 pins = "gpio36", "gpio37";
2956 function = "qup8";
2957 drive-strength = <2>;
2958 bias-pull-up;
2959 };
f5f6bd58 2960
51f83fbb
DB		 2961 qup_i2c9_default: qup-i2c9-default-state {
2962 pins = "gpio40", "gpio41";
2963 function = "qup9";
2964 drive-strength = <2>;
2965 bias-pull-up;
2966 };
f5f6bd58 2967
51f83fbb
DB		 2968 qup_i2c10_default: qup-i2c10-default-state {
2969 pins = "gpio44", "gpio45";
2970 function = "qup10";
2971 drive-strength = <2>;
2972 bias-pull-up;
2973 };
f5f6bd58 2974
51f83fbb
DB		 2975 qup_i2c11_default: qup-i2c11-default-state {
2976 pins = "gpio48", "gpio49";
2977 function = "qup11";
2978 drive-strength = <2>;
2979 bias-pull-up;
2980 };
f5f6bd58 2981
51f83fbb
DB		 2982 qup_i2c12_default: qup-i2c12-default-state {
2983 pins = "gpio52", "gpio53";
2984 function = "qup12";
2985 drive-strength = <2>;
2986 bias-pull-up;
f5f6bd58
DB		 2987 };
2988
51f83fbb
DB		 2989 qup_i2c13_default: qup-i2c13-default-state {
2990 pins = "gpio0", "gpio1";
2991 function = "qup13";
2992 drive-strength = <2>;
2993 bias-pull-up;
2994 };
f5f6bd58 2995
51f83fbb
DB		 2996 qup_i2c14_default: qup-i2c14-default-state {
2997 pins = "gpio56", "gpio57";
2998 function = "qup14";
2999 drive-strength = <2>;
3000 bias-disable;
3001 };
f5f6bd58 3002
51f83fbb
DB		 3003 qup_i2c15_default: qup-i2c15-default-state {
3004 pins = "gpio60", "gpio61";
3005 function = "qup15";
3006 drive-strength = <2>;
3007 bias-disable;
3008 };
f5f6bd58 3009
51f83fbb
DB		 3010 qup_i2c16_default: qup-i2c16-default-state {
3011 pins = "gpio64", "gpio65";
3012 function = "qup16";
3013 drive-strength = <2>;
3014 bias-disable;
f5f6bd58 3015 };
f5f6bd58 3016
51f83fbb
DB		 3017 qup_i2c17_default: qup-i2c17-default-state {
3018 pins = "gpio72", "gpio73";
3019 function = "qup17";
3020 drive-strength = <2>;
3021 bias-disable;
3022 };
f5f6bd58 3023
51f83fbb
DB		 3024 qup_i2c19_default: qup-i2c19-default-state {
3025 pins = "gpio76", "gpio77";
3026 function = "qup19";
3027 drive-strength = <2>;
3028 bias-disable;
3029 };
f5f6bd58
DB		 3030 };
3031
3032 apps_smmu: iommu@15000000 {
3033 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3034 reg = <0 0x15000000 0 0x100000>;
3035 #iommu-cells = <2>;
3036 #global-interrupts = <2>;
3037 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3038 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3039 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3040 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3041 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3042 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3043 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3044 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3045 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3046 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3047 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3048 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3049 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3050 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3051 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3061 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3062 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3063 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3064 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3065 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3066 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3067 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3068 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3070 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3071 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3072 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3073 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3074 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3075 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3076 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3077 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3078 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3079 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3080 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3081 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3082 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3083 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3084 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3085 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3086 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3087 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3088 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3089 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3090 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3091 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3092 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3093 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3100 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3101 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3102 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3103 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3104 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3105 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3106 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3107 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3108 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3109 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3110 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3113 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3114 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3115 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3116 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3117 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3118 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3119 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3120 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3121 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3122 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3123 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3124 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3125 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3126 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3127 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3128 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3129 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3130 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3131 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3132 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3133 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3134 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3135 };
3136
3137 adsp: remoteproc@17300000 {
3138 compatible = "qcom,sm8350-adsp-pas";
3139 reg = <0 0x17300000 0 0x100>;
3140
3141 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3142 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3143 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3144 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3145 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3146 interrupt-names = "wdog", "fatal", "ready",
3147 "handover", "stop-ack";
3148
3149 clocks = <&rpmhcc RPMH_CXO_CLK>;
3150 clock-names = "xo";
3151
3152 power-domains = <&rpmhpd SM8350_LCX>,
3153 <&rpmhpd SM8350_LMX>;
3154 power-domain-names = "lcx", "lmx";
3155
3156 memory-region = <&pil_adsp_mem>;
3157
3158 qcom,qmp = <&aoss_qmp>;
3159
3160 qcom,smem-states = <&smp2p_adsp_out 0>;
3161 qcom,smem-state-names = "stop";
3162
3163 status = "disabled";
3164
3165 glink-edge {
3166 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3167 IPCC_MPROC_SIGNAL_GLINK_QMP
3168 IRQ_TYPE_EDGE_RISING>;
3169 mboxes = <&ipcc IPCC_CLIENT_LPASS
3170 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3171
3172 label = "lpass";
3173 qcom,remote-pid = <2>;
3174
3175 fastrpc {
3176 compatible = "qcom,fastrpc";
3177 qcom,glink-channels = "fastrpcglink-apps-dsp";
3178 label = "adsp";
3179 qcom,non-secure-domain;
3180 #address-cells = <1>;
3181 #size-cells = <0>;
3182
3183 compute-cb@3 {
3184 compatible = "qcom,fastrpc-compute-cb";
3185 reg = <3>;
3186 iommus = <&apps_smmu 0x1803 0x0>;
3187 };
3188
3189 compute-cb@4 {
3190 compatible = "qcom,fastrpc-compute-cb";
3191 reg = <4>;
3192 iommus = <&apps_smmu 0x1804 0x0>;
3193 };
3194
3195 compute-cb@5 {
3196 compatible = "qcom,fastrpc-compute-cb";
3197 reg = <5>;
3198 iommus = <&apps_smmu 0x1805 0x0>;
3199 };
3200 };
3201 };
3202 };
3203
3204 intc: interrupt-controller@17a00000 {
3205 compatible = "arm,gic-v3";
3206 #interrupt-cells = <3>;
3207 interrupt-controller;
3208 #redistributor-regions = <1>;
3209 redistributor-stride = <0 0x20000>;
3210 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3211 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3212 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3213 };
3214
3215 timer@17c20000 {
3216 compatible = "arm,armv7-timer-mem";
3217 #address-cells = <1>;
3218 #size-cells = <1>;
3219 ranges = <0 0 0 0x20000000>;
3220 reg = <0x0 0x17c20000 0x0 0x1000>;
3221 clock-frequency = <19200000>;
3222
3223 frame@17c21000 {
3224 frame-number = <0>;
3225 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3226 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3227 reg = <0x17c21000 0x1000>,
3228 <0x17c22000 0x1000>;
3229 };
3230
3231 frame@17c23000 {
3232 frame-number = <1>;
3233 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3234 reg = <0x17c23000 0x1000>;
3235 status = "disabled";
3236 };
3237
3238 frame@17c25000 {
3239 frame-number = <2>;
3240 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3241 reg = <0x17c25000 0x1000>;
3242 status = "disabled";
3243 };
3244
3245 frame@17c27000 {
3246 frame-number = <3>;
3247 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3248 reg = <0x17c27000 0x1000>;
3249 status = "disabled";
3250 };
3251
3252 frame@17c29000 {
3253 frame-number = <4>;
3254 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3255 reg = <0x17c29000 0x1000>;
3256 status = "disabled";
3257 };
3258
3259 frame@17c2b000 {
3260 frame-number = <5>;
3261 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3262 reg = <0x17c2b000 0x1000>;
3263 status = "disabled";
3264 };
3265
3266 frame@17c2d000 {
3267 frame-number = <6>;
3268 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3269 reg = <0x17c2d000 0x1000>;
3270 status = "disabled";
3271 };
3272 };
d4a44105 3273
f5f6bd58
DB		 3274 apps_rsc: rsc@18200000 {
3275 label = "apps_rsc";
3276 compatible = "qcom,rpmh-rsc";
3277 reg = <0x0 0x18200000 0x0 0x10000>,
3278 <0x0 0x18210000 0x0 0x10000>,
3279 <0x0 0x18220000 0x0 0x10000>;
3280 reg-names = "drv-0", "drv-1", "drv-2";
3281 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3282 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3283 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3284 qcom,tcs-offset = <0xd00>;
3285 qcom,drv-id = <2>;
3286 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3287 <WAKE_TCS 3>, <CONTROL_TCS 0>;
3288 power-domains = <&CLUSTER_PD>;
d4a44105 3289
f5f6bd58
DB		 3290 rpmhcc: clock-controller {
3291 compatible = "qcom,sm8350-rpmh-clk";
3292 #clock-cells = <1>;
3293 clock-names = "xo";
3294 clocks = <&xo_board>;
3295 };
d4a44105 3296
f5f6bd58
DB		 3297 rpmhpd: power-controller {
3298 compatible = "qcom,sm8350-rpmhpd";
3299 #power-domain-cells = <1>;
3300 operating-points-v2 = <&rpmhpd_opp_table>;
d4a44105 3301
f5f6bd58
DB		 3302 rpmhpd_opp_table: opp-table {
3303 compatible = "operating-points-v2";
d4a44105 3304
f5f6bd58
DB		 3305 rpmhpd_opp_ret: opp1 {
3306 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3307 };
d4a44105 3308
f5f6bd58
DB		 3309 rpmhpd_opp_min_svs: opp2 {
3310 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3311 };
6636818e 3312
f5f6bd58
DB		 3313 rpmhpd_opp_low_svs: opp3 {
3314 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3315 };
d4a44105 3316
f5f6bd58
DB		 3317 rpmhpd_opp_svs: opp4 {
3318 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3319 };
d4a44105 3320
f5f6bd58
DB		 3321 rpmhpd_opp_svs_l1: opp5 {
3322 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
d4a44105
RF		 3323 };
3324
f5f6bd58
DB		 3325 rpmhpd_opp_nom: opp6 {
3326 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
d4a44105
RF		 3327 };
3328
f5f6bd58
DB		 3329 rpmhpd_opp_nom_l1: opp7 {
3330 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
d4a44105 3331 };
d4a44105 3332
f5f6bd58
DB		 3333 rpmhpd_opp_nom_l2: opp8 {
3334 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3335 };
d4a44105 3336
f5f6bd58
DB		 3337 rpmhpd_opp_turbo: opp9 {
3338 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
d4a44105
RF		 3339 };
3340
f5f6bd58
DB		 3341 rpmhpd_opp_turbo_l1: opp10 {
3342 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
d4a44105
RF		 3343 };
3344 };
3345 };
3346
f5f6bd58
DB		 3347 apps_bcm_voter: bcm-voter {
3348 compatible = "qcom,bcm-voter";
d4a44105
RF		 3349 };
3350 };
3351
f5f6bd58
DB		 3352 cpufreq_hw: cpufreq@18591000 {
3353 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3354 reg = <0 0x18591000 0 0x1000>,
3355 <0 0x18592000 0 0x1000>,
3356 <0 0x18593000 0 0x1000>;
3357 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
9fd4887c 3358
f5f6bd58
DB		 3359 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3360 clock-names = "xo", "alternate";
3361
3362 #freq-domain-cells = <1>;
c2a18730 3363 #clock-cells = <1>;
9fd4887c
RF		 3364 };
3365
f5f6bd58
DB		 3366 cdsp: remoteproc@98900000 {
3367 compatible = "qcom,sm8350-cdsp-pas";
3368 reg = <0 0x98900000 0 0x1400000>;
177fcf0a 3369
f5f6bd58
DB		 3370 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3371 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3372 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3373 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3374 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
177fcf0a
VK		 3375 interrupt-names = "wdog", "fatal", "ready",
3376 "handover", "stop-ack";
3377
3378 clocks = <&rpmhcc RPMH_CXO_CLK>;
3379 clock-names = "xo";
3380
f5f6bd58
DB		 3381 power-domains = <&rpmhpd SM8350_CX>,
3382 <&rpmhpd SM8350_MXC>;
3383 power-domain-names = "cx", "mxc";
177fcf0a 3384
f5f6bd58
DB		 3385 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3386
3387 memory-region = <&pil_cdsp_mem>;
177fcf0a 3388
6b7cb2d2
SS		 3389 qcom,qmp = <&aoss_qmp>;
3390
f5f6bd58 3391 qcom,smem-states = <&smp2p_cdsp_out 0>;
177fcf0a
VK		 3392 qcom,smem-state-names = "stop";
3393
3394 status = "disabled";
3395
3396 glink-edge {
f5f6bd58 3397 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
177fcf0a
VK		 3398 IPCC_MPROC_SIGNAL_GLINK_QMP
3399 IRQ_TYPE_EDGE_RISING>;
f5f6bd58 3400 mboxes = <&ipcc IPCC_CLIENT_CDSP
177fcf0a
VK		 3401 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3402
f5f6bd58
DB		 3403 label = "cdsp";
3404 qcom,remote-pid = <5>;
178056a4
OJ		 3405
3406 fastrpc {
3407 compatible = "qcom,fastrpc";
3408 qcom,glink-channels = "fastrpcglink-apps-dsp";
f5f6bd58 3409 label = "cdsp";
8c8ce95b 3410 qcom,non-secure-domain;
178056a4
OJ		 3411 #address-cells = <1>;
3412 #size-cells = <0>;
3413
f5f6bd58
DB		 3414 compute-cb@1 {
3415 compatible = "qcom,fastrpc-compute-cb";
3416 reg = <1>;
3417 iommus = <&apps_smmu 0x2161 0x0400>,
3418 <&apps_smmu 0x1181 0x0420>;
3419 };
3420
3421 compute-cb@2 {
3422 compatible = "qcom,fastrpc-compute-cb";
3423 reg = <2>;
3424 iommus = <&apps_smmu 0x2162 0x0400>,
3425 <&apps_smmu 0x1182 0x0420>;
3426 };
3427
178056a4
OJ		 3428 compute-cb@3 {
3429 compatible = "qcom,fastrpc-compute-cb";
3430 reg = <3>;
f5f6bd58
DB		 3431 iommus = <&apps_smmu 0x2163 0x0400>,
3432 <&apps_smmu 0x1183 0x0420>;
178056a4
OJ		 3433 };
3434
3435 compute-cb@4 {
3436 compatible = "qcom,fastrpc-compute-cb";
3437 reg = <4>;
f5f6bd58
DB		 3438 iommus = <&apps_smmu 0x2164 0x0400>,
3439 <&apps_smmu 0x1184 0x0420>;
178056a4
OJ		 3440 };
3441
3442 compute-cb@5 {
3443 compatible = "qcom,fastrpc-compute-cb";
3444 reg = <5>;
f5f6bd58
DB		 3445 iommus = <&apps_smmu 0x2165 0x0400>,
3446 <&apps_smmu 0x1185 0x0420>;
3447 };
3448
3449 compute-cb@6 {
3450 compatible = "qcom,fastrpc-compute-cb";
3451 reg = <6>;
3452 iommus = <&apps_smmu 0x2166 0x0400>,
3453 <&apps_smmu 0x1186 0x0420>;
178056a4 3454 };
f5f6bd58
DB		 3455
3456 compute-cb@7 {
3457 compatible = "qcom,fastrpc-compute-cb";
3458 reg = <7>;
3459 iommus = <&apps_smmu 0x2167 0x0400>,
3460 <&apps_smmu 0x1187 0x0420>;
3461 };
3462
3463 compute-cb@8 {
3464 compatible = "qcom,fastrpc-compute-cb";
3465 reg = <8>;
3466 iommus = <&apps_smmu 0x2168 0x0400>,
3467 <&apps_smmu 0x1188 0x0420>;
3468 };
3469
3470 /* note: secure cb9 in downstream */
178056a4 3471 };
177fcf0a
VK		 3472 };
3473 };
b7e8f433
VK		 3474 };
3475
4dcaa68e 3476 thermal_zones: thermal-zones {
20f9d94e
RF		 3477 cpu0-thermal {
3478 polling-delay-passive = <250>;
3479 polling-delay = <1000>;
3480
3481 thermal-sensors = <&tsens0 1>;
3482
3483 trips {
3484 cpu0_alert0: trip-point0 {
3485 temperature = <90000>;
3486 hysteresis = <2000>;
3487 type = "passive";
3488 };
3489
3490 cpu0_alert1: trip-point1 {
3491 temperature = <95000>;
3492 hysteresis = <2000>;
3493 type = "passive";
3494 };
3495
1364acc3 3496 cpu0_crit: cpu-crit {
20f9d94e
RF		 3497 temperature = <110000>;
3498 hysteresis = <1000>;
3499 type = "critical";
3500 };
3501 };
3502
3503 cooling-maps {
3504 map0 {
3505 trip = <&cpu0_alert0>;
3506 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3507 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3508 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3509 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3510 };
3511 map1 {
3512 trip = <&cpu0_alert1>;
3513 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3514 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3515 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3516 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3517 };
3518 };
3519 };
3520
3521 cpu1-thermal {
3522 polling-delay-passive = <250>;
3523 polling-delay = <1000>;
3524
3525 thermal-sensors = <&tsens0 2>;
3526
3527 trips {
3528 cpu1_alert0: trip-point0 {
3529 temperature = <90000>;
3530 hysteresis = <2000>;
3531 type = "passive";
3532 };
3533
3534 cpu1_alert1: trip-point1 {
3535 temperature = <95000>;
3536 hysteresis = <2000>;
3537 type = "passive";
3538 };
3539
1364acc3 3540 cpu1_crit: cpu-crit {
20f9d94e
RF		 3541 temperature = <110000>;
3542 hysteresis = <1000>;
3543 type = "critical";
3544 };
3545 };
3546
3547 cooling-maps {
3548 map0 {
3549 trip = <&cpu1_alert0>;
3550 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3551 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3552 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3553 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3554 };
3555 map1 {
3556 trip = <&cpu1_alert1>;
3557 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3558 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3559 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3560 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3561 };
3562 };
3563 };
3564
3565 cpu2-thermal {
3566 polling-delay-passive = <250>;
3567 polling-delay = <1000>;
3568
3569 thermal-sensors = <&tsens0 3>;
3570
3571 trips {
3572 cpu2_alert0: trip-point0 {
3573 temperature = <90000>;
3574 hysteresis = <2000>;
3575 type = "passive";
3576 };
3577
3578 cpu2_alert1: trip-point1 {
3579 temperature = <95000>;
3580 hysteresis = <2000>;
3581 type = "passive";
3582 };
3583
1364acc3 3584 cpu2_crit: cpu-crit {
20f9d94e
RF		 3585 temperature = <110000>;
3586 hysteresis = <1000>;
3587 type = "critical";
3588 };
3589 };
3590
3591 cooling-maps {
3592 map0 {
3593 trip = <&cpu2_alert0>;
3594 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3595 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3596 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3597 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3598 };
3599 map1 {
3600 trip = <&cpu2_alert1>;
3601 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3602 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3603 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3604 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3605 };
3606 };
3607 };
3608
3609 cpu3-thermal {
3610 polling-delay-passive = <250>;
3611 polling-delay = <1000>;
3612
3613 thermal-sensors = <&tsens0 4>;
3614
3615 trips {
3616 cpu3_alert0: trip-point0 {
3617 temperature = <90000>;
3618 hysteresis = <2000>;
3619 type = "passive";
3620 };
3621
3622 cpu3_alert1: trip-point1 {
3623 temperature = <95000>;
3624 hysteresis = <2000>;
3625 type = "passive";
3626 };
3627
1364acc3 3628 cpu3_crit: cpu-crit {
20f9d94e
RF		 3629 temperature = <110000>;
3630 hysteresis = <1000>;
3631 type = "critical";
3632 };
3633 };
3634
3635 cooling-maps {
3636 map0 {
3637 trip = <&cpu3_alert0>;
3638 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3639 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3640 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3641 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3642 };
3643 map1 {
3644 trip = <&cpu3_alert1>;
3645 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3646 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3647 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3648 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3649 };
3650 };
3651 };
3652
3653 cpu4-top-thermal {
3654 polling-delay-passive = <250>;
3655 polling-delay = <1000>;
3656
3657 thermal-sensors = <&tsens0 7>;
3658
3659 trips {
3660 cpu4_top_alert0: trip-point0 {
3661 temperature = <90000>;
3662 hysteresis = <2000>;
3663 type = "passive";
3664 };
3665
3666 cpu4_top_alert1: trip-point1 {
3667 temperature = <95000>;
3668 hysteresis = <2000>;
3669 type = "passive";
3670 };
3671
1364acc3 3672 cpu4_top_crit: cpu-crit {
20f9d94e
RF		 3673 temperature = <110000>;
3674 hysteresis = <1000>;
3675 type = "critical";
3676 };
3677 };
3678
3679 cooling-maps {
3680 map0 {
3681 trip = <&cpu4_top_alert0>;
3682 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3683 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3684 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3685 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3686 };
3687 map1 {
3688 trip = <&cpu4_top_alert1>;
3689 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3690 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3691 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3692 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3693 };
3694 };
3695 };
3696
3697 cpu5-top-thermal {
3698 polling-delay-passive = <250>;
3699 polling-delay = <1000>;
3700
3701 thermal-sensors = <&tsens0 8>;
3702
3703 trips {
3704 cpu5_top_alert0: trip-point0 {
3705 temperature = <90000>;
3706 hysteresis = <2000>;
3707 type = "passive";
3708 };
3709
3710 cpu5_top_alert1: trip-point1 {
3711 temperature = <95000>;
3712 hysteresis = <2000>;
3713 type = "passive";
3714 };
3715
1364acc3 3716 cpu5_top_crit: cpu-crit {
20f9d94e
RF		 3717 temperature = <110000>;
3718 hysteresis = <1000>;
3719 type = "critical";
3720 };
3721 };
3722
3723 cooling-maps {
3724 map0 {
3725 trip = <&cpu5_top_alert0>;
3726 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3727 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3728 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3729 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3730 };
3731 map1 {
3732 trip = <&cpu5_top_alert1>;
3733 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3734 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3735 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3736 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3737 };
3738 };
3739 };
3740
3741 cpu6-top-thermal {
3742 polling-delay-passive = <250>;
3743 polling-delay = <1000>;
3744
3745 thermal-sensors = <&tsens0 9>;
3746
3747 trips {
3748 cpu6_top_alert0: trip-point0 {
3749 temperature = <90000>;
3750 hysteresis = <2000>;
3751 type = "passive";
3752 };
3753
3754 cpu6_top_alert1: trip-point1 {
3755 temperature = <95000>;
3756 hysteresis = <2000>;
3757 type = "passive";
3758 };
3759
1364acc3 3760 cpu6_top_crit: cpu-crit {
20f9d94e
RF		 3761 temperature = <110000>;
3762 hysteresis = <1000>;
3763 type = "critical";
3764 };
3765 };
3766
3767 cooling-maps {
3768 map0 {
3769 trip = <&cpu6_top_alert0>;
3770 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3771 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3772 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3773 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3774 };
3775 map1 {
3776 trip = <&cpu6_top_alert1>;
3777 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3779 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3780 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3781 };
3782 };
3783 };
3784
3785 cpu7-top-thermal {
3786 polling-delay-passive = <250>;
3787 polling-delay = <1000>;
3788
3789 thermal-sensors = <&tsens0 10>;
3790
3791 trips {
3792 cpu7_top_alert0: trip-point0 {
3793 temperature = <90000>;
3794 hysteresis = <2000>;
3795 type = "passive";
3796 };
3797
3798 cpu7_top_alert1: trip-point1 {
3799 temperature = <95000>;
3800 hysteresis = <2000>;
3801 type = "passive";
3802 };
3803
1364acc3 3804 cpu7_top_crit: cpu-crit {
20f9d94e
RF		 3805 temperature = <110000>;
3806 hysteresis = <1000>;
3807 type = "critical";
3808 };
3809 };
3810
3811 cooling-maps {
3812 map0 {
3813 trip = <&cpu7_top_alert0>;
3814 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3815 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3816 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3817 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3818 };
3819 map1 {
3820 trip = <&cpu7_top_alert1>;
3821 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3822 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3823 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3824 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3825 };
3826 };
3827 };
3828
3829 cpu4-bottom-thermal {
3830 polling-delay-passive = <250>;
3831 polling-delay = <1000>;
3832
3833 thermal-sensors = <&tsens0 11>;
3834
3835 trips {
3836 cpu4_bottom_alert0: trip-point0 {
3837 temperature = <90000>;
3838 hysteresis = <2000>;
3839 type = "passive";
3840 };
3841
3842 cpu4_bottom_alert1: trip-point1 {
3843 temperature = <95000>;
3844 hysteresis = <2000>;
3845 type = "passive";
3846 };
3847
1364acc3 3848 cpu4_bottom_crit: cpu-crit {
20f9d94e
RF		 3849 temperature = <110000>;
3850 hysteresis = <1000>;
3851 type = "critical";
3852 };
3853 };
3854
3855 cooling-maps {
3856 map0 {
3857 trip = <&cpu4_bottom_alert0>;
3858 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3859 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3860 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3861 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3862 };
3863 map1 {
3864 trip = <&cpu4_bottom_alert1>;
3865 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3866 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3867 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3868 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3869 };
3870 };
3871 };
3872
3873 cpu5-bottom-thermal {
3874 polling-delay-passive = <250>;
3875 polling-delay = <1000>;
3876
3877 thermal-sensors = <&tsens0 12>;
3878
3879 trips {
3880 cpu5_bottom_alert0: trip-point0 {
3881 temperature = <90000>;
3882 hysteresis = <2000>;
3883 type = "passive";
3884 };
3885
3886 cpu5_bottom_alert1: trip-point1 {
3887 temperature = <95000>;
3888 hysteresis = <2000>;
3889 type = "passive";
3890 };
3891
1364acc3 3892 cpu5_bottom_crit: cpu-crit {
20f9d94e
RF		 3893 temperature = <110000>;
3894 hysteresis = <1000>;
3895 type = "critical";
3896 };
3897 };
3898
3899 cooling-maps {
3900 map0 {
3901 trip = <&cpu5_bottom_alert0>;
3902 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3903 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3904 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3905 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3906 };
3907 map1 {
3908 trip = <&cpu5_bottom_alert1>;
3909 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3910 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3911 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3912 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3913 };
3914 };
3915 };
3916
3917 cpu6-bottom-thermal {
3918 polling-delay-passive = <250>;
3919 polling-delay = <1000>;
3920
3921 thermal-sensors = <&tsens0 13>;
3922
3923 trips {
3924 cpu6_bottom_alert0: trip-point0 {
3925 temperature = <90000>;
3926 hysteresis = <2000>;
3927 type = "passive";
3928 };
3929
3930 cpu6_bottom_alert1: trip-point1 {
3931 temperature = <95000>;
3932 hysteresis = <2000>;
3933 type = "passive";
3934 };
3935
1364acc3 3936 cpu6_bottom_crit: cpu-crit {
20f9d94e
RF		 3937 temperature = <110000>;
3938 hysteresis = <1000>;
3939 type = "critical";
3940 };
3941 };
3942
3943 cooling-maps {
3944 map0 {
3945 trip = <&cpu6_bottom_alert0>;
3946 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3947 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3948 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3949 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3950 };
3951 map1 {
3952 trip = <&cpu6_bottom_alert1>;
3953 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3954 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3955 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3956 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3957 };
3958 };
3959 };
3960
3961 cpu7-bottom-thermal {
3962 polling-delay-passive = <250>;
3963 polling-delay = <1000>;
3964
3965 thermal-sensors = <&tsens0 14>;
3966
3967 trips {
3968 cpu7_bottom_alert0: trip-point0 {
3969 temperature = <90000>;
3970 hysteresis = <2000>;
3971 type = "passive";
3972 };
3973
3974 cpu7_bottom_alert1: trip-point1 {
3975 temperature = <95000>;
3976 hysteresis = <2000>;
3977 type = "passive";
3978 };
3979
1364acc3 3980 cpu7_bottom_crit: cpu-crit {
20f9d94e
RF		 3981 temperature = <110000>;
3982 hysteresis = <1000>;
3983 type = "critical";
3984 };
3985 };
3986
3987 cooling-maps {
3988 map0 {
3989 trip = <&cpu7_bottom_alert0>;
3990 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3991 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3992 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3993 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3994 };
3995 map1 {
3996 trip = <&cpu7_bottom_alert1>;
3997 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3998 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3999 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4000 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4001 };
4002 };
4003 };
4004
4005 aoss0-thermal {
4006 polling-delay-passive = <250>;
4007 polling-delay = <1000>;
4008
4009 thermal-sensors = <&tsens0 0>;
4010
4011 trips {
4012 aoss0_alert0: trip-point0 {
4013 temperature = <90000>;
4014 hysteresis = <2000>;
4015 type = "hot";
4016 };
4017 };
4018 };
4019
4020 cluster0-thermal {
4021 polling-delay-passive = <250>;
4022 polling-delay = <1000>;
4023
4024 thermal-sensors = <&tsens0 5>;
4025
4026 trips {
4027 cluster0_alert0: trip-point0 {
4028 temperature = <90000>;
4029 hysteresis = <2000>;
4030 type = "hot";
4031 };
4032 cluster0_crit: cluster0_crit {
4033 temperature = <110000>;
4034 hysteresis = <2000>;
4035 type = "critical";
4036 };
4037 };
4038 };
4039
4040 cluster1-thermal {
4041 polling-delay-passive = <250>;
4042 polling-delay = <1000>;
4043
4044 thermal-sensors = <&tsens0 6>;
4045
4046 trips {
4047 cluster1_alert0: trip-point0 {
4048 temperature = <90000>;
4049 hysteresis = <2000>;
4050 type = "hot";
4051 };
4052 cluster1_crit: cluster1_crit {
4053 temperature = <110000>;
4054 hysteresis = <2000>;
4055 type = "critical";
4056 };
4057 };
4058 };
4059
4060 aoss1-thermal {
4061 polling-delay-passive = <250>;
4062 polling-delay = <1000>;
4063
4064 thermal-sensors = <&tsens1 0>;
4065
4066 trips {
4067 aoss1_alert0: trip-point0 {
4068 temperature = <90000>;
4069 hysteresis = <2000>;
4070 type = "hot";
4071 };
4072 };
4073 };
4074
7be1c395 4075 gpu-top-thermal {
20f9d94e
RF		 4076 polling-delay-passive = <250>;
4077 polling-delay = <1000>;
4078
4079 thermal-sensors = <&tsens1 1>;
4080
4081 trips {
4082 gpu1_alert0: trip-point0 {
4083 temperature = <90000>;
4084 hysteresis = <1000>;
4085 type = "hot";
4086 };
4087 };
4088 };
4089
7be1c395 4090 gpu-bottom-thermal {
20f9d94e
RF		 4091 polling-delay-passive = <250>;
4092 polling-delay = <1000>;
4093
4094 thermal-sensors = <&tsens1 2>;
4095
4096 trips {
4097 gpu2_alert0: trip-point0 {
4098 temperature = <90000>;
4099 hysteresis = <1000>;
4100 type = "hot";
4101 };
4102 };
4103 };
4104
4105 nspss1-thermal {
4106 polling-delay-passive = <250>;
4107 polling-delay = <1000>;
4108
4109 thermal-sensors = <&tsens1 3>;
4110
4111 trips {
4112 nspss1_alert0: trip-point0 {
4113 temperature = <90000>;
4114 hysteresis = <1000>;
4115 type = "hot";
4116 };
4117 };
4118 };
4119
4120 nspss2-thermal {
4121 polling-delay-passive = <250>;
4122 polling-delay = <1000>;
4123
4124 thermal-sensors = <&tsens1 4>;
4125
4126 trips {
4127 nspss2_alert0: trip-point0 {
4128 temperature = <90000>;
4129 hysteresis = <1000>;
4130 type = "hot";
4131 };
4132 };
4133 };
4134
4135 nspss3-thermal {
4136 polling-delay-passive = <250>;
4137 polling-delay = <1000>;
4138
4139 thermal-sensors = <&tsens1 5>;
4140
4141 trips {
4142 nspss3_alert0: trip-point0 {
4143 temperature = <90000>;
4144 hysteresis = <1000>;
4145 type = "hot";
4146 };
4147 };
4148 };
4149
4150 video-thermal {
4151 polling-delay-passive = <250>;
4152 polling-delay = <1000>;
4153
4154 thermal-sensors = <&tsens1 6>;
4155
4156 trips {
4157 video_alert0: trip-point0 {
4158 temperature = <90000>;
4159 hysteresis = <2000>;
4160 type = "hot";
4161 };
4162 };
4163 };
4164
4165 mem-thermal {
4166 polling-delay-passive = <250>;
4167 polling-delay = <1000>;
4168
4169 thermal-sensors = <&tsens1 7>;
4170
4171 trips {
4172 mem_alert0: trip-point0 {
4173 temperature = <90000>;
4174 hysteresis = <2000>;
4175 type = "hot";
4176 };
4177 };
4178 };
4179
7be1c395 4180 modem1-top-thermal {
20f9d94e
RF		 4181 polling-delay-passive = <250>;
4182 polling-delay = <1000>;
4183
4184 thermal-sensors = <&tsens1 8>;
4185
4186 trips {
4187 modem1_alert0: trip-point0 {
4188 temperature = <90000>;
4189 hysteresis = <2000>;
4190 type = "hot";
4191 };
4192 };
4193 };
4194
7be1c395 4195 modem2-top-thermal {
20f9d94e
RF		 4196 polling-delay-passive = <250>;
4197 polling-delay = <1000>;
4198
4199 thermal-sensors = <&tsens1 9>;
4200
4201 trips {
4202 modem2_alert0: trip-point0 {
4203 temperature = <90000>;
4204 hysteresis = <2000>;
4205 type = "hot";
4206 };
4207 };
4208 };
4209
7be1c395 4210 modem3-top-thermal {
20f9d94e
RF		 4211 polling-delay-passive = <250>;
4212 polling-delay = <1000>;
4213
4214 thermal-sensors = <&tsens1 10>;
4215
4216 trips {
4217 modem3_alert0: trip-point0 {
4218 temperature = <90000>;
4219 hysteresis = <2000>;
4220 type = "hot";
4221 };
4222 };
4223 };
4224
7be1c395 4225 modem4-top-thermal {
20f9d94e
RF		 4226 polling-delay-passive = <250>;
4227 polling-delay = <1000>;
4228
4229 thermal-sensors = <&tsens1 11>;
4230
4231 trips {
4232 modem4_alert0: trip-point0 {
4233 temperature = <90000>;
4234 hysteresis = <2000>;
4235 type = "hot";
4236 };
4237 };
4238 };
4239
7be1c395 4240 camera-top-thermal {
20f9d94e
RF		 4241 polling-delay-passive = <250>;
4242 polling-delay = <1000>;
4243
4244 thermal-sensors = <&tsens1 12>;
4245
4246 trips {
4247 camera1_alert0: trip-point0 {
4248 temperature = <90000>;
4249 hysteresis = <2000>;
4250 type = "hot";
4251 };
4252 };
4253 };
4254
7be1c395 4255 cam-bottom-thermal {
20f9d94e
RF		 4256 polling-delay-passive = <250>;
4257 polling-delay = <1000>;
4258
4259 thermal-sensors = <&tsens1 13>;
4260
4261 trips {
4262 camera2_alert0: trip-point0 {
4263 temperature = <90000>;
4264 hysteresis = <2000>;
4265 type = "hot";
4266 };
4267 };
4268 };
4269 };
4270
b7e8f433
VK		 4271 timer {
4272 compatible = "arm,armv8-timer";
4273 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4274 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4275 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4276 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4277 };
4278};
Linux 6.x block layer and io_uring tree(s)