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Linux 5.13-rc1
[linux-block.git] / arch / arm64 / boot / dts / qcom / sm8350.dtsi
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b7e8f433
VK		 1// SPDX-License-Identifier: BSD-3-Clause
2/*
4f23d2a5 3 * Copyright (c) 2020, Linaro Limited
b7e8f433
VK		 4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
6d91e201 7#include <dt-bindings/clock/qcom,gcc-sm8350.h>
b7e8f433
VK		 8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/mailbox/qcom-ipcc.h>
10#include <dt-bindings/power/qcom-aoss-qmp.h>
11#include <dt-bindings/power/qcom-rpmpd.h>
12#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20f9d94e 13#include <dt-bindings/thermal/thermal.h>
b7e8f433
VK		 14
15/ {
16 interrupt-parent = <&intc>;
17
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 clocks {
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <38400000>;
28 clock-output-names = "xo_board";
29 };
30
31 sleep_clk: sleep-clk {
32 compatible = "fixed-clock";
33 clock-frequency = <32000>;
34 #clock-cells = <0>;
35 };
36 };
37
38 cpus {
39 #address-cells = <2>;
40 #size-cells = <0>;
41
42 CPU0: cpu@0 {
43 device_type = "cpu";
44 compatible = "qcom,kryo685";
45 reg = <0x0 0x0>;
46 enable-method = "psci";
47 next-level-cache = <&L2_0>;
ccbb3abb 48 qcom,freq-domain = <&cpufreq_hw 0>;
20f9d94e 49 #cooling-cells = <2>;
b7e8f433
VK		 50 L2_0: l2-cache {
51 compatible = "cache";
52 next-level-cache = <&L3_0>;
53 L3_0: l3-cache {
54 compatible = "cache";
55 };
56 };
57 };
58
59 CPU1: cpu@100 {
60 device_type = "cpu";
61 compatible = "qcom,kryo685";
62 reg = <0x0 0x100>;
63 enable-method = "psci";
64 next-level-cache = <&L2_100>;
ccbb3abb 65 qcom,freq-domain = <&cpufreq_hw 0>;
20f9d94e 66 #cooling-cells = <2>;
b7e8f433
VK		 67 L2_100: l2-cache {
68 compatible = "cache";
69 next-level-cache = <&L3_0>;
70 };
71 };
72
73 CPU2: cpu@200 {
74 device_type = "cpu";
75 compatible = "qcom,kryo685";
76 reg = <0x0 0x200>;
77 enable-method = "psci";
78 next-level-cache = <&L2_200>;
ccbb3abb 79 qcom,freq-domain = <&cpufreq_hw 0>;
20f9d94e 80 #cooling-cells = <2>;
b7e8f433
VK		 81 L2_200: l2-cache {
82 compatible = "cache";
83 next-level-cache = <&L3_0>;
84 };
85 };
86
87 CPU3: cpu@300 {
88 device_type = "cpu";
89 compatible = "qcom,kryo685";
90 reg = <0x0 0x300>;
91 enable-method = "psci";
92 next-level-cache = <&L2_300>;
ccbb3abb 93 qcom,freq-domain = <&cpufreq_hw 0>;
20f9d94e 94 #cooling-cells = <2>;
b7e8f433
VK		 95 L2_300: l2-cache {
96 compatible = "cache";
97 next-level-cache = <&L3_0>;
98 };
99 };
100
101 CPU4: cpu@400 {
102 device_type = "cpu";
103 compatible = "qcom,kryo685";
104 reg = <0x0 0x400>;
105 enable-method = "psci";
106 next-level-cache = <&L2_400>;
ccbb3abb 107 qcom,freq-domain = <&cpufreq_hw 1>;
20f9d94e 108 #cooling-cells = <2>;
b7e8f433
VK		 109 L2_400: l2-cache {
110 compatible = "cache";
111 next-level-cache = <&L3_0>;
112 };
113 };
114
115 CPU5: cpu@500 {
116 device_type = "cpu";
117 compatible = "qcom,kryo685";
118 reg = <0x0 0x500>;
119 enable-method = "psci";
120 next-level-cache = <&L2_500>;
ccbb3abb 121 qcom,freq-domain = <&cpufreq_hw 1>;
20f9d94e 122 #cooling-cells = <2>;
b7e8f433
VK		 123 L2_500: l2-cache {
124 compatible = "cache";
125 next-level-cache = <&L3_0>;
126 };
127
128 };
129
130 CPU6: cpu@600 {
131 device_type = "cpu";
132 compatible = "qcom,kryo685";
133 reg = <0x0 0x600>;
134 enable-method = "psci";
135 next-level-cache = <&L2_600>;
ccbb3abb 136 qcom,freq-domain = <&cpufreq_hw 1>;
20f9d94e 137 #cooling-cells = <2>;
b7e8f433
VK		 138 L2_600: l2-cache {
139 compatible = "cache";
140 next-level-cache = <&L3_0>;
141 };
142 };
143
144 CPU7: cpu@700 {
145 device_type = "cpu";
146 compatible = "qcom,kryo685";
147 reg = <0x0 0x700>;
148 enable-method = "psci";
149 next-level-cache = <&L2_700>;
ccbb3abb 150 qcom,freq-domain = <&cpufreq_hw 2>;
20f9d94e 151 #cooling-cells = <2>;
b7e8f433
VK		 152 L2_700: l2-cache {
153 compatible = "cache";
154 next-level-cache = <&L3_0>;
155 };
156 };
157 };
158
159 firmware {
160 scm: scm {
161 compatible = "qcom,scm-sm8350", "qcom,scm";
162 #reset-cells = <1>;
163 };
164 };
165
166 memory@80000000 {
167 device_type = "memory";
168 /* We expect the bootloader to fill in the size */
169 reg = <0x0 0x80000000 0x0 0x0>;
170 };
171
172 pmu {
173 compatible = "arm,armv8-pmuv3";
794d3e30 174 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
b7e8f433
VK		 175 };
176
177 psci {
178 compatible = "arm,psci-1.0";
179 method = "smc";
180 };
181
182 reserved_memory: reserved-memory {
183 #address-cells = <2>;
184 #size-cells = <2>;
185 ranges;
186
187 hyp_mem: memory@80000000 {
188 reg = <0x0 0x80000000 0x0 0x600000>;
189 no-map;
190 };
191
192 xbl_aop_mem: memory@80700000 {
193 no-map;
194 reg = <0x0 0x80700000 0x0 0x160000>;
195 };
196
197 cmd_db: memory@80860000 {
198 compatible = "qcom,cmd-db";
199 reg = <0x0 0x80860000 0x0 0x20000>;
200 no-map;
201 };
202
203 reserved_xbl_uefi_log: memory@80880000 {
204 reg = <0x0 0x80880000 0x0 0x14000>;
205 no-map;
206 };
207
208 smem_mem: memory@80900000 {
209 reg = <0x0 0x80900000 0x0 0x200000>;
210 no-map;
211 };
212
213 cpucp_fw_mem: memory@80b00000 {
214 reg = <0x0 0x80b00000 0x0 0x100000>;
215 no-map;
216 };
217
218 cdsp_secure_heap: memory@80c00000 {
219 reg = <0x0 0x80c00000 0x0 0x4600000>;
220 no-map;
221 };
222
223 pil_camera_mem: mmeory@85200000 {
224 reg = <0x0 0x85200000 0x0 0x500000>;
225 no-map;
226 };
227
228 pil_video_mem: memory@85700000 {
229 reg = <0x0 0x85700000 0x0 0x500000>;
230 no-map;
231 };
232
233 pil_cvp_mem: memory@85c00000 {
234 reg = <0x0 0x85c00000 0x0 0x500000>;
235 no-map;
236 };
237
238 pil_adsp_mem: memory@86100000 {
239 reg = <0x0 0x86100000 0x0 0x2100000>;
240 no-map;
241 };
242
243 pil_slpi_mem: memory@88200000 {
244 reg = <0x0 0x88200000 0x0 0x1500000>;
245 no-map;
246 };
247
248 pil_cdsp_mem: memory@89700000 {
249 reg = <0x0 0x89700000 0x0 0x1e00000>;
250 no-map;
251 };
252
253 pil_ipa_fw_mem: memory@8b500000 {
254 reg = <0x0 0x8b500000 0x0 0x10000>;
255 no-map;
256 };
257
258 pil_ipa_gsi_mem: memory@8b510000 {
259 reg = <0x0 0x8b510000 0x0 0xa000>;
260 no-map;
261 };
262
263 pil_gpu_mem: memory@8b51a000 {
264 reg = <0x0 0x8b51a000 0x0 0x2000>;
265 no-map;
266 };
267
268 pil_spss_mem: memory@8b600000 {
269 reg = <0x0 0x8b600000 0x0 0x100000>;
270 no-map;
271 };
272
273 pil_modem_mem: memory@8b800000 {
274 reg = <0x0 0x8b800000 0x0 0x10000000>;
275 no-map;
276 };
277
774890c9
VK		 278 rmtfs_mem: memory@9b800000 {
279 compatible = "qcom,rmtfs-mem";
280 reg = <0x0 0x9b800000 0x0 0x280000>;
281 no-map;
282
283 qcom,client-id = <1>;
284 qcom,vmid = <15>;
285 };
286
b7e8f433
VK		 287 hyp_reserved_mem: memory@d0000000 {
288 reg = <0x0 0xd0000000 0x0 0x800000>;
289 no-map;
290 };
291
292 pil_trustedvm_mem: memory@d0800000 {
293 reg = <0x0 0xd0800000 0x0 0x76f7000>;
294 no-map;
295 };
296
297 qrtr_shbuf: memory@d7ef7000 {
298 reg = <0x0 0xd7ef7000 0x0 0x9000>;
299 no-map;
300 };
301
302 chan0_shbuf: memory@d7f00000 {
303 reg = <0x0 0xd7f00000 0x0 0x80000>;
304 no-map;
305 };
306
307 chan1_shbuf: memory@d7f80000 {
308 reg = <0x0 0xd7f80000 0x0 0x80000>;
309 no-map;
310 };
311
312 removed_mem: memory@d8800000 {
313 reg = <0x0 0xd8800000 0x0 0x6800000>;
314 no-map;
315 };
316 };
317
318 smem: qcom,smem {
319 compatible = "qcom,smem";
320 memory-region = <&smem_mem>;
321 hwlocks = <&tcsr_mutex 3>;
322 };
323
03a41991
VK		 324 smp2p-adsp {
325 compatible = "qcom,smp2p";
326 qcom,smem = <443>, <429>;
327 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
328 IPCC_MPROC_SIGNAL_SMP2P
329 IRQ_TYPE_EDGE_RISING>;
330 mboxes = <&ipcc IPCC_CLIENT_LPASS
331 IPCC_MPROC_SIGNAL_SMP2P>;
332
333 qcom,local-pid = <0>;
334 qcom,remote-pid = <2>;
335
336 smp2p_adsp_out: master-kernel {
337 qcom,entry-name = "master-kernel";
338 #qcom,smem-state-cells = <1>;
339 };
340
341 smp2p_adsp_in: slave-kernel {
342 qcom,entry-name = "slave-kernel";
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 };
346 };
347
348 smp2p-cdsp {
349 compatible = "qcom,smp2p";
350 qcom,smem = <94>, <432>;
351 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
352 IPCC_MPROC_SIGNAL_SMP2P
353 IRQ_TYPE_EDGE_RISING>;
354 mboxes = <&ipcc IPCC_CLIENT_CDSP
355 IPCC_MPROC_SIGNAL_SMP2P>;
356
357 qcom,local-pid = <0>;
358 qcom,remote-pid = <5>;
359
360 smp2p_cdsp_out: master-kernel {
361 qcom,entry-name = "master-kernel";
362 #qcom,smem-state-cells = <1>;
363 };
364
365 smp2p_cdsp_in: slave-kernel {
366 qcom,entry-name = "slave-kernel";
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 };
370 };
371
372 smp2p-modem {
373 compatible = "qcom,smp2p";
374 qcom,smem = <435>, <428>;
375 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
376 IPCC_MPROC_SIGNAL_SMP2P
377 IRQ_TYPE_EDGE_RISING>;
378 mboxes = <&ipcc IPCC_CLIENT_MPSS
379 IPCC_MPROC_SIGNAL_SMP2P>;
380
381 qcom,local-pid = <0>;
382 qcom,remote-pid = <1>;
383
384 smp2p_modem_out: master-kernel {
385 qcom,entry-name = "master-kernel";
386 #qcom,smem-state-cells = <1>;
387 };
388
389 smp2p_modem_in: slave-kernel {
390 qcom,entry-name = "slave-kernel";
391 interrupt-controller;
392 #interrupt-cells = <2>;
393 };
394 };
395
396 smp2p-slpi {
397 compatible = "qcom,smp2p";
398 qcom,smem = <481>, <430>;
399 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
400 IPCC_MPROC_SIGNAL_SMP2P
401 IRQ_TYPE_EDGE_RISING>;
402 mboxes = <&ipcc IPCC_CLIENT_SLPI
403 IPCC_MPROC_SIGNAL_SMP2P>;
404
405 qcom,local-pid = <0>;
406 qcom,remote-pid = <3>;
407
408 smp2p_slpi_out: master-kernel {
409 qcom,entry-name = "master-kernel";
410 #qcom,smem-state-cells = <1>;
411 };
412
413 smp2p_slpi_in: slave-kernel {
414 qcom,entry-name = "slave-kernel";
415 interrupt-controller;
416 #interrupt-cells = <2>;
417 };
418 };
419
b7e8f433
VK		 420 soc: soc@0 {
421 #address-cells = <2>;
422 #size-cells = <2>;
423 ranges = <0 0 0 0 0x10 0>;
424 dma-ranges = <0 0 0 0 0x10 0>;
425 compatible = "simple-bus";
426
427 gcc: clock-controller@100000 {
428 compatible = "qcom,gcc-sm8350";
429 reg = <0x0 0x00100000 0x0 0x1f0000>;
430 #clock-cells = <1>;
431 #reset-cells = <1>;
432 #power-domain-cells = <1>;
433 clock-names = "bi_tcxo", "sleep_clk";
434 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
435 };
436
437 ipcc: mailbox@408000 {
438 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
439 reg = <0 0x00408000 0 0x1000>;
440 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-controller;
442 #interrupt-cells = <3>;
443 #mbox-cells = <2>;
444 };
445
446 qupv3_id_1: geniqup@9c0000 {
447 compatible = "qcom,geni-se-qup";
448 reg = <0x0 0x009c0000 0x0 0x6000>;
449 clock-names = "m-ahb", "s-ahb";
6d91e201
VK		 450 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
451 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
b7e8f433
VK		 452 #address-cells = <2>;
453 #size-cells = <2>;
454 ranges;
455 status = "disabled";
456
457 uart2: serial@98c000 {
458 compatible = "qcom,geni-debug-uart";
459 reg = <0 0x0098c000 0 0x4000>;
460 clock-names = "se";
6d91e201 461 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
b7e8f433
VK		 462 pinctrl-names = "default";
463 pinctrl-0 = <&qup_uart3_default_state>;
464 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467 status = "disabled";
468 };
469 };
470
187f65b7
VK		 471 apps_smmu: iommu@15000000 {
472 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
473 reg = <0 0x15000000 0 0x100000>;
474 #iommu-cells = <2>;
475 #global-interrupts = <2>;
476 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
574 };
575
da6b2482
VK		 576 config_noc: interconnect@1500000 {
577 compatible = "qcom,sm8350-config-noc";
578 reg = <0 0x01500000 0 0xa580>;
579 #interconnect-cells = <1>;
580 qcom,bcm-voters = <&apps_bcm_voter>;
581 };
582
583 mc_virt: interconnect@1580000 {
584 compatible = "qcom,sm8350-mc-virt";
585 reg = <0 0x01580000 0 0x1000>;
586 #interconnect-cells = <1>;
587 qcom,bcm-voters = <&apps_bcm_voter>;
588 };
589
590 system_noc: interconnect@1680000 {
591 compatible = "qcom,sm8350-system-noc";
592 reg = <0 0x01680000 0 0x1c200>;
593 #interconnect-cells = <1>;
594 qcom,bcm-voters = <&apps_bcm_voter>;
595 };
596
597 aggre1_noc: interconnect@16e0000 {
598 compatible = "qcom,sm8350-aggre1-noc";
599 reg = <0 0x016e0000 0 0x1f180>;
600 #interconnect-cells = <1>;
601 qcom,bcm-voters = <&apps_bcm_voter>;
602 };
603
604 aggre2_noc: interconnect@1700000 {
605 compatible = "qcom,sm8350-aggre2-noc";
606 reg = <0 0x01700000 0 0x33000>;
607 #interconnect-cells = <1>;
608 qcom,bcm-voters = <&apps_bcm_voter>;
609 };
610
611 mmss_noc: interconnect@1740000 {
612 compatible = "qcom,sm8350-mmss-noc";
613 reg = <0 0x01740000 0 0x1f080>;
614 #interconnect-cells = <1>;
615 qcom,bcm-voters = <&apps_bcm_voter>;
616 };
617
618 lpass_ag_noc: interconnect@3c40000 {
619 compatible = "qcom,sm8350-lpass-ag-noc";
620 reg = <0 0x03c40000 0 0xf080>;
621 #interconnect-cells = <1>;
622 qcom,bcm-voters = <&apps_bcm_voter>;
623 };
624
625 compute_noc: interconnect@a0c0000{
626 compatible = "qcom,sm8350-compute-noc";
627 reg = <0 0x0a0c0000 0 0xa180>;
628 #interconnect-cells = <1>;
629 qcom,bcm-voters = <&apps_bcm_voter>;
630 };
631
b7e8f433
VK		 632 tcsr_mutex: hwlock@1f40000 {
633 compatible = "qcom,tcsr-mutex";
634 reg = <0x0 0x01f40000 0x0 0x40000>;
635 #hwlock-cells = <1>;
636 };
637
177fcf0a
VK		 638 mpss: remoteproc@4080000 {
639 compatible = "qcom,sm8350-mpss-pas";
640 reg = <0x0 0x04080000 0x0 0x4040>;
641
642 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
643 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
644 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
645 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
646 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
647 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
648 interrupt-names = "wdog", "fatal", "ready", "handover",
649 "stop-ack", "shutdown-ack";
650
651 clocks = <&rpmhcc RPMH_CXO_CLK>;
652 clock-names = "xo";
653
654 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
655 <&rpmhpd 0>,
656 <&rpmhpd 12>;
657 power-domain-names = "load_state", "cx", "mss";
658
da6b2482
VK		 659 interconnects = <&mc_virt 0 &mc_virt 1>;
660
177fcf0a
VK		 661 memory-region = <&pil_modem_mem>;
662
663 qcom,smem-states = <&smp2p_modem_out 0>;
664 qcom,smem-state-names = "stop";
665
666 status = "disabled";
667
668 glink-edge {
669 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
670 IPCC_MPROC_SIGNAL_GLINK_QMP
671 IRQ_TYPE_EDGE_RISING>;
672 mboxes = <&ipcc IPCC_CLIENT_MPSS
673 IPCC_MPROC_SIGNAL_GLINK_QMP>;
674 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
675 label = "modem";
676 qcom,remote-pid = <1>;
677 };
678 };
679
b7e8f433
VK		 680 pdc: interrupt-controller@b220000 {
681 compatible = "qcom,sm8350-pdc", "qcom,pdc";
682 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
683 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
684 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
685 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
686 <156 716 12>;
687 #interrupt-cells = <2>;
688 interrupt-parent = <&intc>;
689 interrupt-controller;
690 };
691
20f9d94e
RF		 692 tsens0: thermal-sensor@c222000 {
693 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
694 reg = <0 0x0c263000 0 0x1ff>, /* TM */
695 <0 0x0c222000 0 0x8>; /* SROT */
696 #qcom,sensors = <15>;
697 interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
698 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
699 interrupt-names = "uplow", "critical";
700 #thermal-sensor-cells = <1>;
701 };
702
703 tsens1: thermal-sensor@c223000 {
704 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
705 reg = <0 0x0c265000 0 0x1ff>, /* TM */
706 <0 0x0c223000 0 0x8>; /* SROT */
707 #qcom,sensors = <14>;
708 interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
709 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
710 interrupt-names = "uplow", "critical";
711 #thermal-sensor-cells = <1>;
712 };
713
97832fa8 714 aoss_qmp: power-controller@c300000 {
b7e8f433
VK		 715 compatible = "qcom,sm8350-aoss-qmp";
716 reg = <0 0x0c300000 0 0x100000>;
717 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
718 IRQ_TYPE_EDGE_RISING>;
719 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
720
721 #clock-cells = <0>;
722 #power-domain-cells = <1>;
723 };
724
389cd7ac
VK		 725 spmi_bus: spmi@c440000 {
726 compatible = "qcom,spmi-pmic-arb";
727 reg = <0x0 0xc440000 0x0 0x1100>,
728 <0x0 0xc600000 0x0 0x2000000>,
729 <0x0 0xe600000 0x0 0x100000>,
730 <0x0 0xe700000 0x0 0xa0000>,
731 <0x0 0xc40a000 0x0 0x26000>;
732 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
733 interrupt-names = "periph_irq";
734 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
735 qcom,ee = <0>;
736 qcom,channel = <0>;
737 #address-cells = <2>;
738 #size-cells = <0>;
739 interrupt-controller;
740 #interrupt-cells = <4>;
741 };
742
b7e8f433
VK		 743 tlmm: pinctrl@f100000 {
744 compatible = "qcom,sm8350-tlmm";
745 reg = <0 0x0f100000 0 0x300000>;
746 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
747 gpio-controller;
748 #gpio-cells = <2>;
749 interrupt-controller;
750 #interrupt-cells = <2>;
79015857 751 gpio-ranges = <&tlmm 0 0 204>;
b7e8f433
VK		 752
753 qup_uart3_default_state: qup-uart3-default-state {
754 rx {
755 pins = "gpio18";
756 function = "qup3";
757 };
758 tx {
759 pins = "gpio19";
760 function = "qup3";
761 };
762 };
763 };
764
24e3eb2e
RF		 765 rng: rng@10d3000 {
766 compatible = "qcom,prng-ee";
767 reg = <0 0x010d3000 0 0x1000>;
768 clocks = <&rpmhcc RPMH_HWKM_CLK>;
769 clock-names = "core";
770 };
771
b7e8f433
VK		 772 intc: interrupt-controller@17a00000 {
773 compatible = "arm,gic-v3";
774 #interrupt-cells = <3>;
775 interrupt-controller;
776 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
777 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
778 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
779 };
780
781 timer@17c20000 {
782 compatible = "arm,armv7-timer-mem";
783 #address-cells = <2>;
784 #size-cells = <2>;
785 ranges;
786 reg = <0x0 0x17c20000 0x0 0x1000>;
787 clock-frequency = <19200000>;
788
789 frame@17c21000 {
790 frame-number = <0>;
791 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
793 reg = <0x0 0x17c21000 0x0 0x1000>,
794 <0x0 0x17c22000 0x0 0x1000>;
795 };
796
797 frame@17c23000 {
798 frame-number = <1>;
799 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
800 reg = <0x0 0x17c23000 0x0 0x1000>;
801 status = "disabled";
802 };
803
804 frame@17c25000 {
805 frame-number = <2>;
806 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
807 reg = <0x0 0x17c25000 0x0 0x1000>;
808 status = "disabled";
809 };
810
811 frame@17c27000 {
812 frame-number = <3>;
813 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
814 reg = <0x0 0x17c27000 0x0 0x1000>;
815 status = "disabled";
816 };
817
818 frame@17c29000 {
819 frame-number = <4>;
820 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
821 reg = <0x0 0x17c29000 0x0 0x1000>;
822 status = "disabled";
823 };
824
825 frame@17c2b000 {
826 frame-number = <5>;
827 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
828 reg = <0x0 0x17c2b000 0x0 0x1000>;
829 status = "disabled";
830 };
831
832 frame@17c2d000 {
833 frame-number = <6>;
834 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
835 reg = <0x0 0x17c2d000 0x0 0x1000>;
836 status = "disabled";
837 };
838 };
839
840 apps_rsc: rsc@18200000 {
841 label = "apps_rsc";
842 compatible = "qcom,rpmh-rsc";
843 reg = <0x0 0x18200000 0x0 0x10000>,
844 <0x0 0x18210000 0x0 0x10000>,
845 <0x0 0x18220000 0x0 0x10000>;
846 reg-names = "drv-0", "drv-1", "drv-2";
847 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
850 qcom,tcs-offset = <0xd00>;
851 qcom,drv-id = <2>;
852 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
853 <WAKE_TCS 3>, <CONTROL_TCS 1>;
854
855 rpmhcc: clock-controller {
856 compatible = "qcom,sm8350-rpmh-clk";
857 #clock-cells = <1>;
858 clock-names = "xo";
859 clocks = <&xo_board>;
860 };
861
90f57509
VK		 862 rpmhpd: power-controller {
863 compatible = "qcom,sm8350-rpmhpd";
864 #power-domain-cells = <1>;
865 operating-points-v2 = <&rpmhpd_opp_table>;
866
867 rpmhpd_opp_table: opp-table {
868 compatible = "operating-points-v2";
869
870 rpmhpd_opp_ret: opp1 {
871 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
872 };
873
874 rpmhpd_opp_min_svs: opp2 {
875 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
876 };
877
878 rpmhpd_opp_low_svs: opp3 {
879 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
880 };
881
882 rpmhpd_opp_svs: opp4 {
883 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
884 };
885
886 rpmhpd_opp_svs_l1: opp5 {
887 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
888 };
889
890 rpmhpd_opp_nom: opp6 {
891 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
892 };
893
894 rpmhpd_opp_nom_l1: opp7 {
895 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
896 };
897
898 rpmhpd_opp_nom_l2: opp8 {
899 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
900 };
901
902 rpmhpd_opp_turbo: opp9 {
903 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
904 };
905
906 rpmhpd_opp_turbo_l1: opp10 {
907 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
908 };
909 };
910 };
da6b2482
VK		 911
912 apps_bcm_voter: bcm_voter {
913 compatible = "qcom,bcm-voter";
914 };
b7e8f433 915 };
e780fb31 916
ccbb3abb
VK		 917 cpufreq_hw: cpufreq@18591000 {
918 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
919 reg = <0 0x18591000 0 0x1000>,
920 <0 0x18592000 0 0x1000>,
921 <0 0x18593000 0 0x1000>;
922 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
923
924 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
925 clock-names = "xo", "alternate";
926
927 #freq-domain-cells = <1>;
928 };
929
59c7cf81
VK		 930 ufs_mem_hc: ufshc@1d84000 {
931 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
932 "jedec,ufs-2.0";
933 reg = <0 0x01d84000 0 0x3000>;
934 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
935 phys = <&ufs_mem_phy_lanes>;
936 phy-names = "ufsphy";
937 lanes-per-direction = <2>;
938 #reset-cells = <1>;
6d91e201 939 resets = <&gcc GCC_UFS_PHY_BCR>;
59c7cf81
VK		 940 reset-names = "rst";
941
6d91e201 942 power-domains = <&gcc UFS_PHY_GDSC>;
59c7cf81
VK		 943
944 iommus = <&apps_smmu 0xe0 0x0>;
945
946 clock-names =
947 "ref_clk",
948 "core_clk",
949 "bus_aggr_clk",
950 "iface_clk",
951 "core_clk_unipro",
952 "ref_clk",
953 "tx_lane0_sync_clk",
954 "rx_lane0_sync_clk",
955 "rx_lane1_sync_clk";
956 clocks =
957 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 958 <&gcc GCC_UFS_PHY_AXI_CLK>,
959 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
960 <&gcc GCC_UFS_PHY_AHB_CLK>,
961 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
59c7cf81 962 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 963 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
964 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
965 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
59c7cf81
VK		 966 freq-table-hz =
967 <75000000 300000000>,
968 <75000000 300000000>,
969 <0 0>,
970 <0 0>,
971 <75000000 300000000>,
972 <0 0>,
973 <0 0>,
974 <75000000 300000000>,
975 <75000000 300000000>;
976 status = "disabled";
977 };
978
979 ufs_mem_phy: phy@1d87000 {
980 compatible = "qcom,sm8350-qmp-ufs-phy";
981 reg = <0 0x01d87000 0 0xe10>;
982 #address-cells = <2>;
983 #size-cells = <2>;
984 #clock-cells = <1>;
985 ranges;
986 clock-names = "ref",
987 "ref_aux";
988 clocks = <&rpmhcc RPMH_CXO_CLK>,
6d91e201 989 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
59c7cf81
VK		 990
991 resets = <&ufs_mem_hc 0>;
992 reset-names = "ufsphy";
993 status = "disabled";
994
995 ufs_mem_phy_lanes: lanes@1d87400 {
996 reg = <0 0x01d87400 0 0x108>,
997 <0 0x01d87600 0 0x1e0>,
998 <0 0x01d87c00 0 0x1dc>,
999 <0 0x01d87800 0 0x108>,
1000 <0 0x01d87a00 0 0x1e0>;
1001 #phy-cells = <0>;
1002 #clock-cells = <0>;
1003 };
1004 };
1005
177fcf0a
VK		 1006 slpi: remoteproc@5c00000 {
1007 compatible = "qcom,sm8350-slpi-pas";
1008 reg = <0 0x05c00000 0 0x4000>;
1009
1010 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1011 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1012 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1013 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1014 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1015 interrupt-names = "wdog", "fatal", "ready",
1016 "handover", "stop-ack";
1017
1018 clocks = <&rpmhcc RPMH_CXO_CLK>;
1019 clock-names = "xo";
1020
1021 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1022 <&rpmhpd 4>,
1023 <&rpmhpd 5>;
1024 power-domain-names = "load_state", "lcx", "lmx";
1025
1026 memory-region = <&pil_slpi_mem>;
1027
1028 qcom,smem-states = <&smp2p_slpi_out 0>;
1029 qcom,smem-state-names = "stop";
1030
1031 status = "disabled";
1032
1033 glink-edge {
1034 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1035 IPCC_MPROC_SIGNAL_GLINK_QMP
1036 IRQ_TYPE_EDGE_RISING>;
1037 mboxes = <&ipcc IPCC_CLIENT_SLPI
1038 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1039
1040 label = "slpi";
1041 qcom,remote-pid = <3>;
1042
1043 };
1044 };
1045
1046 cdsp: remoteproc@98900000 {
1047 compatible = "qcom,sm8350-cdsp-pas";
1048 reg = <0 0x098900000 0 0x1400000>;
1049
1050 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1051 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1052 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1053 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1054 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1055 interrupt-names = "wdog", "fatal", "ready",
1056 "handover", "stop-ack";
1057
1058 clocks = <&rpmhcc RPMH_CXO_CLK>;
1059 clock-names = "xo";
1060
1061 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1062 <&rpmhpd 0>,
1063 <&rpmhpd 10>;
1064 power-domain-names = "load_state", "cx", "mxc";
1065
da6b2482
VK		 1066 interconnects = <&compute_noc 1 &mc_virt 1>;
1067
177fcf0a
VK		 1068 memory-region = <&pil_cdsp_mem>;
1069
1070 qcom,smem-states = <&smp2p_cdsp_out 0>;
1071 qcom,smem-state-names = "stop";
1072
1073 status = "disabled";
1074
1075 glink-edge {
1076 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1077 IPCC_MPROC_SIGNAL_GLINK_QMP
1078 IRQ_TYPE_EDGE_RISING>;
1079 mboxes = <&ipcc IPCC_CLIENT_CDSP
1080 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1081
1082 label = "cdsp";
1083 qcom,remote-pid = <5>;
1084 };
1085 };
1086
e780fb31
JP		 1087 usb_1_hsphy: phy@88e3000 {
1088 compatible = "qcom,sm8350-usb-hs-phy",
1089 "qcom,usb-snps-hs-7nm-phy";
1090 reg = <0 0x088e3000 0 0x400>;
1091 status = "disabled";
1092 #phy-cells = <0>;
1093
1094 clocks = <&rpmhcc RPMH_CXO_CLK>;
1095 clock-names = "ref";
1096
6d91e201 1097 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
e780fb31
JP		 1098 };
1099
1100 usb_2_hsphy: phy@88e4000 {
1101 compatible = "qcom,sm8250-usb-hs-phy",
1102 "qcom,usb-snps-hs-7nm-phy";
1103 reg = <0 0x088e4000 0 0x400>;
1104 status = "disabled";
1105 #phy-cells = <0>;
1106
1107 clocks = <&rpmhcc RPMH_CXO_CLK>;
1108 clock-names = "ref";
1109
6d91e201 1110 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
e780fb31
JP		 1111 };
1112
1113 usb_1_qmpphy: phy-wrapper@88e9000 {
1114 compatible = "qcom,sm8350-qmp-usb3-phy";
1115 reg = <0 0x088e9000 0 0x200>,
1116 <0 0x088e8000 0 0x20>;
1117 reg-names = "reg-base", "dp_com";
1118 status = "disabled";
1119 #clock-cells = <1>;
1120 #address-cells = <2>;
1121 #size-cells = <2>;
1122 ranges;
1123
6d91e201 1124 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
e780fb31 1125 <&rpmhcc RPMH_CXO_CLK>,
6d91e201 1126 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
e780fb31
JP		 1127 clock-names = "aux", "ref_clk_src", "com_aux";
1128
6d91e201
VK		 1129 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1130 <&gcc GCC_USB3_PHY_PRIM_BCR>;
e780fb31
JP		 1131 reset-names = "phy", "common";
1132
1133 usb_1_ssphy: phy@88e9200 {
1134 reg = <0 0x088e9200 0 0x200>,
1135 <0 0x088e9400 0 0x200>,
1136 <0 0x088e9c00 0 0x400>,
1137 <0 0x088e9600 0 0x200>,
1138 <0 0x088e9800 0 0x200>,
1139 <0 0x088e9a00 0 0x100>;
1140 #phy-cells = <0>;
1141 #clock-cells = <1>;
6d91e201 1142 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
e780fb31
JP		 1143 clock-names = "pipe0";
1144 clock-output-names = "usb3_phy_pipe_clk_src";
1145 };
1146 };
1147
1148 usb_2_qmpphy: phy-wrapper@88eb000 {
1149 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
1150 reg = <0 0x088eb000 0 0x200>;
1151 status = "disabled";
1152 #clock-cells = <1>;
1153 #address-cells = <2>;
1154 #size-cells = <2>;
1155 ranges;
1156
6d91e201 1157 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
e780fb31 1158 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 1159 <&gcc GCC_USB3_SEC_CLKREF_EN>,
1160 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
e780fb31
JP		 1161 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1162
6d91e201
VK		 1163 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1164 <&gcc GCC_USB3_PHY_SEC_BCR>;
e780fb31
JP		 1165 reset-names = "phy", "common";
1166
1167 usb_2_ssphy: phy@88ebe00 {
1168 reg = <0 0x088ebe00 0 0x200>,
1169 <0 0x088ec000 0 0x200>,
1170 <0 0x088eb200 0 0x1100>;
1171 #phy-cells = <0>;
1172 #clock-cells = <1>;
6d91e201 1173 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
e780fb31
JP		 1174 clock-names = "pipe0";
1175 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1176 };
1177 };
1178
da6b2482
VK		 1179 dc_noc: interconnect@90e0000 {
1180 compatible = "qcom,sm8350-dc-noc";
1181 reg = <0 0x090c0000 0 0x4200>;
1182 #interconnect-cells = <1>;
1183 qcom,bcm-voters = <&apps_bcm_voter>;
1184 };
1185
1186 gem_noc: interconnect@9100000 {
1187 compatible = "qcom,sm8350-gem-noc";
1188 reg = <0 0x09100000 0 0xb4000>;
1189 #interconnect-cells = <1>;
1190 qcom,bcm-voters = <&apps_bcm_voter>;
1191 };
1192
e780fb31
JP		 1193 usb_1: usb@a6f8800 {
1194 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1195 reg = <0 0x0a6f8800 0 0x400>;
1196 status = "disabled";
1197 #address-cells = <2>;
1198 #size-cells = <2>;
1199 ranges;
1200
6d91e201
VK		 1201 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1202 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1203 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1204 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1205 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
e780fb31
JP		 1206 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1207 "sleep";
1208
6d91e201
VK		 1209 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1210 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
e780fb31
JP		 1211 assigned-clock-rates = <19200000>, <200000000>;
1212
1213 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1214 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1215 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1216 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1217 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1218 "dm_hs_phy_irq", "ss_phy_irq";
1219
6d91e201 1220 power-domains = <&gcc USB30_PRIM_GDSC>;
e780fb31 1221
6d91e201 1222 resets = <&gcc GCC_USB30_PRIM_BCR>;
e780fb31
JP		 1223
1224 usb_1_dwc3: dwc3@a600000 {
1225 compatible = "snps,dwc3";
1226 reg = <0 0x0a600000 0 0xcd00>;
1227 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1228 iommus = <&apps_smmu 0x0 0x0>;
1229 snps,dis_u2_susphy_quirk;
1230 snps,dis_enblslpm_quirk;
1231 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1232 phy-names = "usb2-phy", "usb3-phy";
1233 };
1234 };
1235
1236 usb_2: usb@a8f8800 {
1237 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1238 reg = <0 0x0a8f8800 0 0x400>;
1239 status = "disabled";
1240 #address-cells = <2>;
1241 #size-cells = <2>;
1242 ranges;
1243
6d91e201
VK		 1244 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1245 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1246 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1247 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1248 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1249 <&gcc GCC_USB3_SEC_CLKREF_EN>;
e780fb31
JP		 1250 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1251 "sleep", "xo";
1252
6d91e201
VK		 1253 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1254 <&gcc GCC_USB30_SEC_MASTER_CLK>;
e780fb31
JP		 1255 assigned-clock-rates = <19200000>, <200000000>;
1256
1257 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1258 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1259 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1260 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1261 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1262 "dm_hs_phy_irq", "ss_phy_irq";
1263
6d91e201 1264 power-domains = <&gcc USB30_SEC_GDSC>;
e780fb31 1265
6d91e201 1266 resets = <&gcc GCC_USB30_SEC_BCR>;
e780fb31
JP		 1267
1268 usb_2_dwc3: dwc3@a800000 {
1269 compatible = "snps,dwc3";
1270 reg = <0 0x0a800000 0 0xcd00>;
1271 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1272 iommus = <&apps_smmu 0x20 0x0>;
1273 snps,dis_u2_susphy_quirk;
1274 snps,dis_enblslpm_quirk;
1275 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1276 phy-names = "usb2-phy", "usb3-phy";
1277 };
1278 };
177fcf0a
VK		 1279
1280 adsp: remoteproc@17300000 {
1281 compatible = "qcom,sm8350-adsp-pas";
1282 reg = <0 0x17300000 0 0x100>;
1283
1284 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1285 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1286 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1287 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1288 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1289 interrupt-names = "wdog", "fatal", "ready",
1290 "handover", "stop-ack";
1291
1292 clocks = <&rpmhcc RPMH_CXO_CLK>;
1293 clock-names = "xo";
1294
1295 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
1296 <&rpmhpd 4>,
1297 <&rpmhpd 5>;
1298 power-domain-names = "load_state", "lcx", "lmx";
1299
1300 memory-region = <&pil_adsp_mem>;
1301
1302 qcom,smem-states = <&smp2p_adsp_out 0>;
1303 qcom,smem-state-names = "stop";
1304
1305 status = "disabled";
1306
1307 glink-edge {
1308 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1309 IPCC_MPROC_SIGNAL_GLINK_QMP
1310 IRQ_TYPE_EDGE_RISING>;
1311 mboxes = <&ipcc IPCC_CLIENT_LPASS
1312 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1313
1314 label = "lpass";
1315 qcom,remote-pid = <2>;
1316 };
1317 };
b7e8f433
VK		 1318 };
1319
20f9d94e
RF		 1320 thermal-zones {
1321 cpu0-thermal {
1322 polling-delay-passive = <250>;
1323 polling-delay = <1000>;
1324
1325 thermal-sensors = <&tsens0 1>;
1326
1327 trips {
1328 cpu0_alert0: trip-point0 {
1329 temperature = <90000>;
1330 hysteresis = <2000>;
1331 type = "passive";
1332 };
1333
1334 cpu0_alert1: trip-point1 {
1335 temperature = <95000>;
1336 hysteresis = <2000>;
1337 type = "passive";
1338 };
1339
1340 cpu0_crit: cpu_crit {
1341 temperature = <110000>;
1342 hysteresis = <1000>;
1343 type = "critical";
1344 };
1345 };
1346
1347 cooling-maps {
1348 map0 {
1349 trip = <&cpu0_alert0>;
1350 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1351 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1352 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1353 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1354 };
1355 map1 {
1356 trip = <&cpu0_alert1>;
1357 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1358 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1359 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1360 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1361 };
1362 };
1363 };
1364
1365 cpu1-thermal {
1366 polling-delay-passive = <250>;
1367 polling-delay = <1000>;
1368
1369 thermal-sensors = <&tsens0 2>;
1370
1371 trips {
1372 cpu1_alert0: trip-point0 {
1373 temperature = <90000>;
1374 hysteresis = <2000>;
1375 type = "passive";
1376 };
1377
1378 cpu1_alert1: trip-point1 {
1379 temperature = <95000>;
1380 hysteresis = <2000>;
1381 type = "passive";
1382 };
1383
1384 cpu1_crit: cpu_crit {
1385 temperature = <110000>;
1386 hysteresis = <1000>;
1387 type = "critical";
1388 };
1389 };
1390
1391 cooling-maps {
1392 map0 {
1393 trip = <&cpu1_alert0>;
1394 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1395 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1396 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1397 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1398 };
1399 map1 {
1400 trip = <&cpu1_alert1>;
1401 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1402 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1403 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1404 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1405 };
1406 };
1407 };
1408
1409 cpu2-thermal {
1410 polling-delay-passive = <250>;
1411 polling-delay = <1000>;
1412
1413 thermal-sensors = <&tsens0 3>;
1414
1415 trips {
1416 cpu2_alert0: trip-point0 {
1417 temperature = <90000>;
1418 hysteresis = <2000>;
1419 type = "passive";
1420 };
1421
1422 cpu2_alert1: trip-point1 {
1423 temperature = <95000>;
1424 hysteresis = <2000>;
1425 type = "passive";
1426 };
1427
1428 cpu2_crit: cpu_crit {
1429 temperature = <110000>;
1430 hysteresis = <1000>;
1431 type = "critical";
1432 };
1433 };
1434
1435 cooling-maps {
1436 map0 {
1437 trip = <&cpu2_alert0>;
1438 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1439 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1440 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1441 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1442 };
1443 map1 {
1444 trip = <&cpu2_alert1>;
1445 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1446 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1447 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1448 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1449 };
1450 };
1451 };
1452
1453 cpu3-thermal {
1454 polling-delay-passive = <250>;
1455 polling-delay = <1000>;
1456
1457 thermal-sensors = <&tsens0 4>;
1458
1459 trips {
1460 cpu3_alert0: trip-point0 {
1461 temperature = <90000>;
1462 hysteresis = <2000>;
1463 type = "passive";
1464 };
1465
1466 cpu3_alert1: trip-point1 {
1467 temperature = <95000>;
1468 hysteresis = <2000>;
1469 type = "passive";
1470 };
1471
1472 cpu3_crit: cpu_crit {
1473 temperature = <110000>;
1474 hysteresis = <1000>;
1475 type = "critical";
1476 };
1477 };
1478
1479 cooling-maps {
1480 map0 {
1481 trip = <&cpu3_alert0>;
1482 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1483 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1484 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1485 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1486 };
1487 map1 {
1488 trip = <&cpu3_alert1>;
1489 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1490 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1491 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1492 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1493 };
1494 };
1495 };
1496
1497 cpu4-top-thermal {
1498 polling-delay-passive = <250>;
1499 polling-delay = <1000>;
1500
1501 thermal-sensors = <&tsens0 7>;
1502
1503 trips {
1504 cpu4_top_alert0: trip-point0 {
1505 temperature = <90000>;
1506 hysteresis = <2000>;
1507 type = "passive";
1508 };
1509
1510 cpu4_top_alert1: trip-point1 {
1511 temperature = <95000>;
1512 hysteresis = <2000>;
1513 type = "passive";
1514 };
1515
1516 cpu4_top_crit: cpu_crit {
1517 temperature = <110000>;
1518 hysteresis = <1000>;
1519 type = "critical";
1520 };
1521 };
1522
1523 cooling-maps {
1524 map0 {
1525 trip = <&cpu4_top_alert0>;
1526 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1527 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1528 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1529 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1530 };
1531 map1 {
1532 trip = <&cpu4_top_alert1>;
1533 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1534 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1535 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1536 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1537 };
1538 };
1539 };
1540
1541 cpu5-top-thermal {
1542 polling-delay-passive = <250>;
1543 polling-delay = <1000>;
1544
1545 thermal-sensors = <&tsens0 8>;
1546
1547 trips {
1548 cpu5_top_alert0: trip-point0 {
1549 temperature = <90000>;
1550 hysteresis = <2000>;
1551 type = "passive";
1552 };
1553
1554 cpu5_top_alert1: trip-point1 {
1555 temperature = <95000>;
1556 hysteresis = <2000>;
1557 type = "passive";
1558 };
1559
1560 cpu5_top_crit: cpu_crit {
1561 temperature = <110000>;
1562 hysteresis = <1000>;
1563 type = "critical";
1564 };
1565 };
1566
1567 cooling-maps {
1568 map0 {
1569 trip = <&cpu5_top_alert0>;
1570 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1571 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1572 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1573 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1574 };
1575 map1 {
1576 trip = <&cpu5_top_alert1>;
1577 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1578 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1579 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1580 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1581 };
1582 };
1583 };
1584
1585 cpu6-top-thermal {
1586 polling-delay-passive = <250>;
1587 polling-delay = <1000>;
1588
1589 thermal-sensors = <&tsens0 9>;
1590
1591 trips {
1592 cpu6_top_alert0: trip-point0 {
1593 temperature = <90000>;
1594 hysteresis = <2000>;
1595 type = "passive";
1596 };
1597
1598 cpu6_top_alert1: trip-point1 {
1599 temperature = <95000>;
1600 hysteresis = <2000>;
1601 type = "passive";
1602 };
1603
1604 cpu6_top_crit: cpu_crit {
1605 temperature = <110000>;
1606 hysteresis = <1000>;
1607 type = "critical";
1608 };
1609 };
1610
1611 cooling-maps {
1612 map0 {
1613 trip = <&cpu6_top_alert0>;
1614 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1615 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1616 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1617 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1618 };
1619 map1 {
1620 trip = <&cpu6_top_alert1>;
1621 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1622 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1623 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1624 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1625 };
1626 };
1627 };
1628
1629 cpu7-top-thermal {
1630 polling-delay-passive = <250>;
1631 polling-delay = <1000>;
1632
1633 thermal-sensors = <&tsens0 10>;
1634
1635 trips {
1636 cpu7_top_alert0: trip-point0 {
1637 temperature = <90000>;
1638 hysteresis = <2000>;
1639 type = "passive";
1640 };
1641
1642 cpu7_top_alert1: trip-point1 {
1643 temperature = <95000>;
1644 hysteresis = <2000>;
1645 type = "passive";
1646 };
1647
1648 cpu7_top_crit: cpu_crit {
1649 temperature = <110000>;
1650 hysteresis = <1000>;
1651 type = "critical";
1652 };
1653 };
1654
1655 cooling-maps {
1656 map0 {
1657 trip = <&cpu7_top_alert0>;
1658 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1659 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1660 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1661 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1662 };
1663 map1 {
1664 trip = <&cpu7_top_alert1>;
1665 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1666 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1667 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1668 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1669 };
1670 };
1671 };
1672
1673 cpu4-bottom-thermal {
1674 polling-delay-passive = <250>;
1675 polling-delay = <1000>;
1676
1677 thermal-sensors = <&tsens0 11>;
1678
1679 trips {
1680 cpu4_bottom_alert0: trip-point0 {
1681 temperature = <90000>;
1682 hysteresis = <2000>;
1683 type = "passive";
1684 };
1685
1686 cpu4_bottom_alert1: trip-point1 {
1687 temperature = <95000>;
1688 hysteresis = <2000>;
1689 type = "passive";
1690 };
1691
1692 cpu4_bottom_crit: cpu_crit {
1693 temperature = <110000>;
1694 hysteresis = <1000>;
1695 type = "critical";
1696 };
1697 };
1698
1699 cooling-maps {
1700 map0 {
1701 trip = <&cpu4_bottom_alert0>;
1702 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1703 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1704 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1705 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1706 };
1707 map1 {
1708 trip = <&cpu4_bottom_alert1>;
1709 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1710 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1711 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1712 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1713 };
1714 };
1715 };
1716
1717 cpu5-bottom-thermal {
1718 polling-delay-passive = <250>;
1719 polling-delay = <1000>;
1720
1721 thermal-sensors = <&tsens0 12>;
1722
1723 trips {
1724 cpu5_bottom_alert0: trip-point0 {
1725 temperature = <90000>;
1726 hysteresis = <2000>;
1727 type = "passive";
1728 };
1729
1730 cpu5_bottom_alert1: trip-point1 {
1731 temperature = <95000>;
1732 hysteresis = <2000>;
1733 type = "passive";
1734 };
1735
1736 cpu5_bottom_crit: cpu_crit {
1737 temperature = <110000>;
1738 hysteresis = <1000>;
1739 type = "critical";
1740 };
1741 };
1742
1743 cooling-maps {
1744 map0 {
1745 trip = <&cpu5_bottom_alert0>;
1746 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1747 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1748 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1749 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1750 };
1751 map1 {
1752 trip = <&cpu5_bottom_alert1>;
1753 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1754 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1755 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1756 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1757 };
1758 };
1759 };
1760
1761 cpu6-bottom-thermal {
1762 polling-delay-passive = <250>;
1763 polling-delay = <1000>;
1764
1765 thermal-sensors = <&tsens0 13>;
1766
1767 trips {
1768 cpu6_bottom_alert0: trip-point0 {
1769 temperature = <90000>;
1770 hysteresis = <2000>;
1771 type = "passive";
1772 };
1773
1774 cpu6_bottom_alert1: trip-point1 {
1775 temperature = <95000>;
1776 hysteresis = <2000>;
1777 type = "passive";
1778 };
1779
1780 cpu6_bottom_crit: cpu_crit {
1781 temperature = <110000>;
1782 hysteresis = <1000>;
1783 type = "critical";
1784 };
1785 };
1786
1787 cooling-maps {
1788 map0 {
1789 trip = <&cpu6_bottom_alert0>;
1790 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1791 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1792 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1793 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1794 };
1795 map1 {
1796 trip = <&cpu6_bottom_alert1>;
1797 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1798 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1799 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1800 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1801 };
1802 };
1803 };
1804
1805 cpu7-bottom-thermal {
1806 polling-delay-passive = <250>;
1807 polling-delay = <1000>;
1808
1809 thermal-sensors = <&tsens0 14>;
1810
1811 trips {
1812 cpu7_bottom_alert0: trip-point0 {
1813 temperature = <90000>;
1814 hysteresis = <2000>;
1815 type = "passive";
1816 };
1817
1818 cpu7_bottom_alert1: trip-point1 {
1819 temperature = <95000>;
1820 hysteresis = <2000>;
1821 type = "passive";
1822 };
1823
1824 cpu7_bottom_crit: cpu_crit {
1825 temperature = <110000>;
1826 hysteresis = <1000>;
1827 type = "critical";
1828 };
1829 };
1830
1831 cooling-maps {
1832 map0 {
1833 trip = <&cpu7_bottom_alert0>;
1834 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1835 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1836 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1837 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1838 };
1839 map1 {
1840 trip = <&cpu7_bottom_alert1>;
1841 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1842 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1843 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1844 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1845 };
1846 };
1847 };
1848
1849 aoss0-thermal {
1850 polling-delay-passive = <250>;
1851 polling-delay = <1000>;
1852
1853 thermal-sensors = <&tsens0 0>;
1854
1855 trips {
1856 aoss0_alert0: trip-point0 {
1857 temperature = <90000>;
1858 hysteresis = <2000>;
1859 type = "hot";
1860 };
1861 };
1862 };
1863
1864 cluster0-thermal {
1865 polling-delay-passive = <250>;
1866 polling-delay = <1000>;
1867
1868 thermal-sensors = <&tsens0 5>;
1869
1870 trips {
1871 cluster0_alert0: trip-point0 {
1872 temperature = <90000>;
1873 hysteresis = <2000>;
1874 type = "hot";
1875 };
1876 cluster0_crit: cluster0_crit {
1877 temperature = <110000>;
1878 hysteresis = <2000>;
1879 type = "critical";
1880 };
1881 };
1882 };
1883
1884 cluster1-thermal {
1885 polling-delay-passive = <250>;
1886 polling-delay = <1000>;
1887
1888 thermal-sensors = <&tsens0 6>;
1889
1890 trips {
1891 cluster1_alert0: trip-point0 {
1892 temperature = <90000>;
1893 hysteresis = <2000>;
1894 type = "hot";
1895 };
1896 cluster1_crit: cluster1_crit {
1897 temperature = <110000>;
1898 hysteresis = <2000>;
1899 type = "critical";
1900 };
1901 };
1902 };
1903
1904 aoss1-thermal {
1905 polling-delay-passive = <250>;
1906 polling-delay = <1000>;
1907
1908 thermal-sensors = <&tsens1 0>;
1909
1910 trips {
1911 aoss1_alert0: trip-point0 {
1912 temperature = <90000>;
1913 hysteresis = <2000>;
1914 type = "hot";
1915 };
1916 };
1917 };
1918
1919 gpu-thermal-top {
1920 polling-delay-passive = <250>;
1921 polling-delay = <1000>;
1922
1923 thermal-sensors = <&tsens1 1>;
1924
1925 trips {
1926 gpu1_alert0: trip-point0 {
1927 temperature = <90000>;
1928 hysteresis = <1000>;
1929 type = "hot";
1930 };
1931 };
1932 };
1933
1934 gpu-thermal-bottom {
1935 polling-delay-passive = <250>;
1936 polling-delay = <1000>;
1937
1938 thermal-sensors = <&tsens1 2>;
1939
1940 trips {
1941 gpu2_alert0: trip-point0 {
1942 temperature = <90000>;
1943 hysteresis = <1000>;
1944 type = "hot";
1945 };
1946 };
1947 };
1948
1949 nspss1-thermal {
1950 polling-delay-passive = <250>;
1951 polling-delay = <1000>;
1952
1953 thermal-sensors = <&tsens1 3>;
1954
1955 trips {
1956 nspss1_alert0: trip-point0 {
1957 temperature = <90000>;
1958 hysteresis = <1000>;
1959 type = "hot";
1960 };
1961 };
1962 };
1963
1964 nspss2-thermal {
1965 polling-delay-passive = <250>;
1966 polling-delay = <1000>;
1967
1968 thermal-sensors = <&tsens1 4>;
1969
1970 trips {
1971 nspss2_alert0: trip-point0 {
1972 temperature = <90000>;
1973 hysteresis = <1000>;
1974 type = "hot";
1975 };
1976 };
1977 };
1978
1979 nspss3-thermal {
1980 polling-delay-passive = <250>;
1981 polling-delay = <1000>;
1982
1983 thermal-sensors = <&tsens1 5>;
1984
1985 trips {
1986 nspss3_alert0: trip-point0 {
1987 temperature = <90000>;
1988 hysteresis = <1000>;
1989 type = "hot";
1990 };
1991 };
1992 };
1993
1994 video-thermal {
1995 polling-delay-passive = <250>;
1996 polling-delay = <1000>;
1997
1998 thermal-sensors = <&tsens1 6>;
1999
2000 trips {
2001 video_alert0: trip-point0 {
2002 temperature = <90000>;
2003 hysteresis = <2000>;
2004 type = "hot";
2005 };
2006 };
2007 };
2008
2009 mem-thermal {
2010 polling-delay-passive = <250>;
2011 polling-delay = <1000>;
2012
2013 thermal-sensors = <&tsens1 7>;
2014
2015 trips {
2016 mem_alert0: trip-point0 {
2017 temperature = <90000>;
2018 hysteresis = <2000>;
2019 type = "hot";
2020 };
2021 };
2022 };
2023
2024 modem1-thermal-top {
2025 polling-delay-passive = <250>;
2026 polling-delay = <1000>;
2027
2028 thermal-sensors = <&tsens1 8>;
2029
2030 trips {
2031 modem1_alert0: trip-point0 {
2032 temperature = <90000>;
2033 hysteresis = <2000>;
2034 type = "hot";
2035 };
2036 };
2037 };
2038
2039 modem2-thermal-top {
2040 polling-delay-passive = <250>;
2041 polling-delay = <1000>;
2042
2043 thermal-sensors = <&tsens1 9>;
2044
2045 trips {
2046 modem2_alert0: trip-point0 {
2047 temperature = <90000>;
2048 hysteresis = <2000>;
2049 type = "hot";
2050 };
2051 };
2052 };
2053
2054 modem3-thermal-top {
2055 polling-delay-passive = <250>;
2056 polling-delay = <1000>;
2057
2058 thermal-sensors = <&tsens1 10>;
2059
2060 trips {
2061 modem3_alert0: trip-point0 {
2062 temperature = <90000>;
2063 hysteresis = <2000>;
2064 type = "hot";
2065 };
2066 };
2067 };
2068
2069 modem4-thermal-top {
2070 polling-delay-passive = <250>;
2071 polling-delay = <1000>;
2072
2073 thermal-sensors = <&tsens1 11>;
2074
2075 trips {
2076 modem4_alert0: trip-point0 {
2077 temperature = <90000>;
2078 hysteresis = <2000>;
2079 type = "hot";
2080 };
2081 };
2082 };
2083
2084 camera-thermal-top {
2085 polling-delay-passive = <250>;
2086 polling-delay = <1000>;
2087
2088 thermal-sensors = <&tsens1 12>;
2089
2090 trips {
2091 camera1_alert0: trip-point0 {
2092 temperature = <90000>;
2093 hysteresis = <2000>;
2094 type = "hot";
2095 };
2096 };
2097 };
2098
2099 camera-thermal-bottom {
2100 polling-delay-passive = <250>;
2101 polling-delay = <1000>;
2102
2103 thermal-sensors = <&tsens1 13>;
2104
2105 trips {
2106 camera2_alert0: trip-point0 {
2107 temperature = <90000>;
2108 hysteresis = <2000>;
2109 type = "hot";
2110 };
2111 };
2112 };
2113 };
2114
b7e8f433
VK		 2115 timer {
2116 compatible = "arm,armv8-timer";
2117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2118 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2120 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2121 };
2122};
Linux 6.x block layer and io_uring tree(s)