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arm64: dts: qcom: sm8350: finish reordering nodes
[linux-block.git] / arch / arm64 / boot / dts / qcom / sm8350.dtsi
CommitLineData
b7e8f433
VK		 1// SPDX-License-Identifier: BSD-3-Clause
2/*
4f23d2a5 3 * Copyright (c) 2020, Linaro Limited
b7e8f433
VK		 4 */
5
d4a44105 6#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433 7#include <dt-bindings/interrupt-controller/arm-gic.h>
9fd4887c 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
6d91e201 9#include <dt-bindings/clock/qcom,gcc-sm8350.h>
b7e8f433 10#include <dt-bindings/clock/qcom,rpmh.h>
bc08fbf4 11#include <dt-bindings/dma/qcom-gpi.h>
f0360a7c 12#include <dt-bindings/gpio/gpio.h>
84c856d0 13#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433 14#include <dt-bindings/mailbox/qcom-ipcc.h>
b7e8f433
VK		 15#include <dt-bindings/power/qcom-rpmpd.h>
16#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20f9d94e 17#include <dt-bindings/thermal/thermal.h>
f11d3e7d 18#include <dt-bindings/interconnect/qcom,sm8350.h>
b7e8f433
VK		 19
20/ {
21 interrupt-parent = <&intc>;
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 chosen { };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <38400000>;
33 clock-output-names = "xo_board";
34 };
35
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 clock-frequency = <32000>;
39 #clock-cells = <0>;
40 };
41 };
42
43 cpus {
44 #address-cells = <2>;
45 #size-cells = <0>;
46
47 CPU0: cpu@0 {
48 device_type = "cpu";
49 compatible = "qcom,kryo685";
50 reg = <0x0 0x0>;
51 enable-method = "psci";
52 next-level-cache = <&L2_0>;
ccbb3abb 53 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 54 power-domains = <&CPU_PD0>;
55 power-domain-names = "psci";
20f9d94e 56 #cooling-cells = <2>;
b7e8f433
VK		 57 L2_0: l2-cache {
58 compatible = "cache";
9435294c 59 cache-level = <2>;
b7e8f433
VK		 60 next-level-cache = <&L3_0>;
61 L3_0: l3-cache {
62 compatible = "cache";
9435294c 63 cache-level = <3>;
b7e8f433
VK		 64 };
65 };
66 };
67
68 CPU1: cpu@100 {
69 device_type = "cpu";
70 compatible = "qcom,kryo685";
71 reg = <0x0 0x100>;
72 enable-method = "psci";
73 next-level-cache = <&L2_100>;
ccbb3abb 74 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 75 power-domains = <&CPU_PD1>;
76 power-domain-names = "psci";
20f9d94e 77 #cooling-cells = <2>;
b7e8f433
VK		 78 L2_100: l2-cache {
79 compatible = "cache";
9435294c 80 cache-level = <2>;
b7e8f433
VK		 81 next-level-cache = <&L3_0>;
82 };
83 };
84
85 CPU2: cpu@200 {
86 device_type = "cpu";
87 compatible = "qcom,kryo685";
88 reg = <0x0 0x200>;
89 enable-method = "psci";
90 next-level-cache = <&L2_200>;
ccbb3abb 91 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 92 power-domains = <&CPU_PD2>;
93 power-domain-names = "psci";
20f9d94e 94 #cooling-cells = <2>;
b7e8f433
VK		 95 L2_200: l2-cache {
96 compatible = "cache";
9435294c 97 cache-level = <2>;
b7e8f433
VK		 98 next-level-cache = <&L3_0>;
99 };
100 };
101
102 CPU3: cpu@300 {
103 device_type = "cpu";
104 compatible = "qcom,kryo685";
105 reg = <0x0 0x300>;
106 enable-method = "psci";
107 next-level-cache = <&L2_300>;
ccbb3abb 108 qcom,freq-domain = <&cpufreq_hw 0>;
07ddb302
BA		 109 power-domains = <&CPU_PD3>;
110 power-domain-names = "psci";
20f9d94e 111 #cooling-cells = <2>;
b7e8f433
VK		 112 L2_300: l2-cache {
113 compatible = "cache";
9435294c 114 cache-level = <2>;
b7e8f433
VK		 115 next-level-cache = <&L3_0>;
116 };
117 };
118
119 CPU4: cpu@400 {
120 device_type = "cpu";
121 compatible = "qcom,kryo685";
122 reg = <0x0 0x400>;
123 enable-method = "psci";
124 next-level-cache = <&L2_400>;
ccbb3abb 125 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 126 power-domains = <&CPU_PD4>;
127 power-domain-names = "psci";
20f9d94e 128 #cooling-cells = <2>;
b7e8f433
VK		 129 L2_400: l2-cache {
130 compatible = "cache";
9435294c 131 cache-level = <2>;
b7e8f433
VK		 132 next-level-cache = <&L3_0>;
133 };
134 };
135
136 CPU5: cpu@500 {
137 device_type = "cpu";
138 compatible = "qcom,kryo685";
139 reg = <0x0 0x500>;
140 enable-method = "psci";
141 next-level-cache = <&L2_500>;
ccbb3abb 142 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 143 power-domains = <&CPU_PD5>;
144 power-domain-names = "psci";
20f9d94e 145 #cooling-cells = <2>;
b7e8f433
VK		 146 L2_500: l2-cache {
147 compatible = "cache";
9435294c 148 cache-level = <2>;
b7e8f433
VK		 149 next-level-cache = <&L3_0>;
150 };
151
152 };
153
154 CPU6: cpu@600 {
155 device_type = "cpu";
156 compatible = "qcom,kryo685";
157 reg = <0x0 0x600>;
158 enable-method = "psci";
159 next-level-cache = <&L2_600>;
ccbb3abb 160 qcom,freq-domain = <&cpufreq_hw 1>;
07ddb302
BA		 161 power-domains = <&CPU_PD6>;
162 power-domain-names = "psci";
20f9d94e 163 #cooling-cells = <2>;
b7e8f433
VK		 164 L2_600: l2-cache {
165 compatible = "cache";
9435294c 166 cache-level = <2>;
b7e8f433
VK		 167 next-level-cache = <&L3_0>;
168 };
169 };
170
171 CPU7: cpu@700 {
172 device_type = "cpu";
173 compatible = "qcom,kryo685";
174 reg = <0x0 0x700>;
175 enable-method = "psci";
176 next-level-cache = <&L2_700>;
ccbb3abb 177 qcom,freq-domain = <&cpufreq_hw 2>;
07ddb302
BA		 178 power-domains = <&CPU_PD7>;
179 power-domain-names = "psci";
20f9d94e 180 #cooling-cells = <2>;
b7e8f433
VK		 181 L2_700: l2-cache {
182 compatible = "cache";
9435294c 183 cache-level = <2>;
b7e8f433
VK		 184 next-level-cache = <&L3_0>;
185 };
186 };
07ddb302
BA		 187
188 cpu-map {
189 cluster0 {
190 core0 {
191 cpu = <&CPU0>;
192 };
193
194 core1 {
195 cpu = <&CPU1>;
196 };
197
198 core2 {
199 cpu = <&CPU2>;
200 };
201
202 core3 {
203 cpu = <&CPU3>;
204 };
205
206 core4 {
207 cpu = <&CPU4>;
208 };
209
210 core5 {
211 cpu = <&CPU5>;
212 };
213
214 core6 {
215 cpu = <&CPU6>;
216 };
217
218 core7 {
219 cpu = <&CPU7>;
220 };
221 };
222 };
223
224 idle-states {
225 entry-method = "psci";
226
227 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
228 compatible = "arm,idle-state";
229 idle-state-name = "silver-rail-power-collapse";
230 arm,psci-suspend-param = <0x40000004>;
231 entry-latency-us = <355>;
232 exit-latency-us = <909>;
233 min-residency-us = <3934>;
234 local-timer-stop;
235 };
236
237 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
238 compatible = "arm,idle-state";
239 idle-state-name = "gold-rail-power-collapse";
240 arm,psci-suspend-param = <0x40000004>;
241 entry-latency-us = <241>;
242 exit-latency-us = <1461>;
243 min-residency-us = <4488>;
244 local-timer-stop;
245 };
246 };
247
248 domain-idle-states {
249 CLUSTER_SLEEP_0: cluster-sleep-0 {
250 compatible = "domain-idle-state";
251 idle-state-name = "cluster-power-collapse";
252 arm,psci-suspend-param = <0x4100c344>;
253 entry-latency-us = <3263>;
254 exit-latency-us = <6562>;
255 min-residency-us = <9987>;
256 local-timer-stop;
257 };
258 };
b7e8f433
VK		 259 };
260
261 firmware {
262 scm: scm {
263 compatible = "qcom,scm-sm8350", "qcom,scm";
264 #reset-cells = <1>;
265 };
266 };
267
268 memory@80000000 {
269 device_type = "memory";
270 /* We expect the bootloader to fill in the size */
271 reg = <0x0 0x80000000 0x0 0x0>;
272 };
273
274 pmu {
275 compatible = "arm,armv8-pmuv3";
794d3e30 276 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
b7e8f433
VK		 277 };
278
279 psci {
280 compatible = "arm,psci-1.0";
281 method = "smc";
07ddb302 282
a9371962 283 CPU_PD0: power-domain-cpu0 {
07ddb302
BA		 284 #power-domain-cells = <0>;
285 power-domains = <&CLUSTER_PD>;
286 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
287 };
288
a9371962 289 CPU_PD1: power-domain-cpu1 {
07ddb302
BA		 290 #power-domain-cells = <0>;
291 power-domains = <&CLUSTER_PD>;
292 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
293 };
294
a9371962 295 CPU_PD2: power-domain-cpu2 {
07ddb302
BA		 296 #power-domain-cells = <0>;
297 power-domains = <&CLUSTER_PD>;
298 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
299 };
300
a9371962 301 CPU_PD3: power-domain-cpu3 {
07ddb302
BA		 302 #power-domain-cells = <0>;
303 power-domains = <&CLUSTER_PD>;
304 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
305 };
306
a9371962 307 CPU_PD4: power-domain-cpu4 {
07ddb302
BA		 308 #power-domain-cells = <0>;
309 power-domains = <&CLUSTER_PD>;
310 domain-idle-states = <&BIG_CPU_SLEEP_0>;
311 };
312
a9371962 313 CPU_PD5: power-domain-cpu5 {
07ddb302
BA		 314 #power-domain-cells = <0>;
315 power-domains = <&CLUSTER_PD>;
316 domain-idle-states = <&BIG_CPU_SLEEP_0>;
317 };
318
a9371962 319 CPU_PD6: power-domain-cpu6 {
07ddb302
BA		 320 #power-domain-cells = <0>;
321 power-domains = <&CLUSTER_PD>;
322 domain-idle-states = <&BIG_CPU_SLEEP_0>;
323 };
324
a9371962 325 CPU_PD7: power-domain-cpu7 {
07ddb302
BA		 326 #power-domain-cells = <0>;
327 power-domains = <&CLUSTER_PD>;
328 domain-idle-states = <&BIG_CPU_SLEEP_0>;
329 };
330
a9371962 331 CLUSTER_PD: power-domain-cpu-cluster0 {
07ddb302
BA		 332 #power-domain-cells = <0>;
333 domain-idle-states = <&CLUSTER_SLEEP_0>;
334 };
b7e8f433
VK		 335 };
336
e2eedde4
VK		 337 qup_opp_table_100mhz: opp-table-qup100mhz {
338 compatible = "operating-points-v2";
339
340 opp-50000000 {
341 opp-hz = /bits/ 64 <50000000>;
342 required-opps = <&rpmhpd_opp_min_svs>;
343 };
344
345 opp-75000000 {
346 opp-hz = /bits/ 64 <75000000>;
347 required-opps = <&rpmhpd_opp_low_svs>;
348 };
349
350 opp-100000000 {
351 opp-hz = /bits/ 64 <100000000>;
352 required-opps = <&rpmhpd_opp_svs>;
353 };
354 };
355
356 qup_opp_table_120mhz: opp-table-qup120mhz {
357 compatible = "operating-points-v2";
358
359 opp-50000000 {
360 opp-hz = /bits/ 64 <50000000>;
361 required-opps = <&rpmhpd_opp_min_svs>;
362 };
363
364 opp-75000000 {
365 opp-hz = /bits/ 64 <75000000>;
366 required-opps = <&rpmhpd_opp_low_svs>;
367 };
368
369 opp-120000000 {
370 opp-hz = /bits/ 64 <120000000>;
371 required-opps = <&rpmhpd_opp_svs>;
372 };
373 };
374
b7e8f433
VK		 375 reserved_memory: reserved-memory {
376 #address-cells = <2>;
377 #size-cells = <2>;
378 ranges;
379
380 hyp_mem: memory@80000000 {
381 reg = <0x0 0x80000000 0x0 0x600000>;
382 no-map;
383 };
384
385 xbl_aop_mem: memory@80700000 {
386 no-map;
387 reg = <0x0 0x80700000 0x0 0x160000>;
388 };
389
390 cmd_db: memory@80860000 {
391 compatible = "qcom,cmd-db";
392 reg = <0x0 0x80860000 0x0 0x20000>;
393 no-map;
394 };
395
396 reserved_xbl_uefi_log: memory@80880000 {
397 reg = <0x0 0x80880000 0x0 0x14000>;
398 no-map;
399 };
400
8503babc
KD		 401 smem@80900000 {
402 compatible = "qcom,smem";
b7e8f433 403 reg = <0x0 0x80900000 0x0 0x200000>;
8503babc 404 hwlocks = <&tcsr_mutex 3>;
b7e8f433
VK		 405 no-map;
406 };
407
408 cpucp_fw_mem: memory@80b00000 {
409 reg = <0x0 0x80b00000 0x0 0x100000>;
410 no-map;
411 };
412
413 cdsp_secure_heap: memory@80c00000 {
414 reg = <0x0 0x80c00000 0x0 0x4600000>;
415 no-map;
416 };
417
418 pil_camera_mem: mmeory@85200000 {
419 reg = <0x0 0x85200000 0x0 0x500000>;
420 no-map;
421 };
422
423 pil_video_mem: memory@85700000 {
424 reg = <0x0 0x85700000 0x0 0x500000>;
425 no-map;
426 };
427
428 pil_cvp_mem: memory@85c00000 {
429 reg = <0x0 0x85c00000 0x0 0x500000>;
430 no-map;
431 };
432
433 pil_adsp_mem: memory@86100000 {
434 reg = <0x0 0x86100000 0x0 0x2100000>;
435 no-map;
436 };
437
438 pil_slpi_mem: memory@88200000 {
439 reg = <0x0 0x88200000 0x0 0x1500000>;
440 no-map;
441 };
442
443 pil_cdsp_mem: memory@89700000 {
444 reg = <0x0 0x89700000 0x0 0x1e00000>;
445 no-map;
446 };
447
448 pil_ipa_fw_mem: memory@8b500000 {
449 reg = <0x0 0x8b500000 0x0 0x10000>;
450 no-map;
451 };
452
453 pil_ipa_gsi_mem: memory@8b510000 {
454 reg = <0x0 0x8b510000 0x0 0xa000>;
455 no-map;
456 };
457
458 pil_gpu_mem: memory@8b51a000 {
459 reg = <0x0 0x8b51a000 0x0 0x2000>;
460 no-map;
461 };
462
463 pil_spss_mem: memory@8b600000 {
464 reg = <0x0 0x8b600000 0x0 0x100000>;
465 no-map;
466 };
467
468 pil_modem_mem: memory@8b800000 {
469 reg = <0x0 0x8b800000 0x0 0x10000000>;
470 no-map;
471 };
472
774890c9
VK		 473 rmtfs_mem: memory@9b800000 {
474 compatible = "qcom,rmtfs-mem";
475 reg = <0x0 0x9b800000 0x0 0x280000>;
476 no-map;
477
478 qcom,client-id = <1>;
479 qcom,vmid = <15>;
480 };
481
b7e8f433
VK		 482 hyp_reserved_mem: memory@d0000000 {
483 reg = <0x0 0xd0000000 0x0 0x800000>;
484 no-map;
485 };
486
487 pil_trustedvm_mem: memory@d0800000 {
488 reg = <0x0 0xd0800000 0x0 0x76f7000>;
489 no-map;
490 };
491
492 qrtr_shbuf: memory@d7ef7000 {
493 reg = <0x0 0xd7ef7000 0x0 0x9000>;
494 no-map;
495 };
496
497 chan0_shbuf: memory@d7f00000 {
498 reg = <0x0 0xd7f00000 0x0 0x80000>;
499 no-map;
500 };
501
502 chan1_shbuf: memory@d7f80000 {
503 reg = <0x0 0xd7f80000 0x0 0x80000>;
504 no-map;
505 };
506
507 removed_mem: memory@d8800000 {
508 reg = <0x0 0xd8800000 0x0 0x6800000>;
509 no-map;
510 };
511 };
512
03a41991
VK		 513 smp2p-adsp {
514 compatible = "qcom,smp2p";
515 qcom,smem = <443>, <429>;
516 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
517 IPCC_MPROC_SIGNAL_SMP2P
518 IRQ_TYPE_EDGE_RISING>;
519 mboxes = <&ipcc IPCC_CLIENT_LPASS
520 IPCC_MPROC_SIGNAL_SMP2P>;
521
522 qcom,local-pid = <0>;
523 qcom,remote-pid = <2>;
524
525 smp2p_adsp_out: master-kernel {
526 qcom,entry-name = "master-kernel";
527 #qcom,smem-state-cells = <1>;
528 };
529
530 smp2p_adsp_in: slave-kernel {
531 qcom,entry-name = "slave-kernel";
532 interrupt-controller;
533 #interrupt-cells = <2>;
534 };
535 };
536
537 smp2p-cdsp {
538 compatible = "qcom,smp2p";
539 qcom,smem = <94>, <432>;
540 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
541 IPCC_MPROC_SIGNAL_SMP2P
542 IRQ_TYPE_EDGE_RISING>;
543 mboxes = <&ipcc IPCC_CLIENT_CDSP
544 IPCC_MPROC_SIGNAL_SMP2P>;
545
546 qcom,local-pid = <0>;
547 qcom,remote-pid = <5>;
548
549 smp2p_cdsp_out: master-kernel {
550 qcom,entry-name = "master-kernel";
551 #qcom,smem-state-cells = <1>;
552 };
553
554 smp2p_cdsp_in: slave-kernel {
555 qcom,entry-name = "slave-kernel";
556 interrupt-controller;
557 #interrupt-cells = <2>;
558 };
559 };
560
561 smp2p-modem {
562 compatible = "qcom,smp2p";
563 qcom,smem = <435>, <428>;
564 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
565 IPCC_MPROC_SIGNAL_SMP2P
566 IRQ_TYPE_EDGE_RISING>;
567 mboxes = <&ipcc IPCC_CLIENT_MPSS
568 IPCC_MPROC_SIGNAL_SMP2P>;
569
570 qcom,local-pid = <0>;
571 qcom,remote-pid = <1>;
572
573 smp2p_modem_out: master-kernel {
574 qcom,entry-name = "master-kernel";
575 #qcom,smem-state-cells = <1>;
576 };
577
578 smp2p_modem_in: slave-kernel {
579 qcom,entry-name = "slave-kernel";
580 interrupt-controller;
581 #interrupt-cells = <2>;
582 };
f11d3e7d
AE		 583
584 ipa_smp2p_out: ipa-ap-to-modem {
585 qcom,entry-name = "ipa";
586 #qcom,smem-state-cells = <1>;
587 };
588
589 ipa_smp2p_in: ipa-modem-to-ap {
590 qcom,entry-name = "ipa";
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 };
03a41991
VK		 594 };
595
596 smp2p-slpi {
597 compatible = "qcom,smp2p";
598 qcom,smem = <481>, <430>;
599 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
600 IPCC_MPROC_SIGNAL_SMP2P
601 IRQ_TYPE_EDGE_RISING>;
602 mboxes = <&ipcc IPCC_CLIENT_SLPI
603 IPCC_MPROC_SIGNAL_SMP2P>;
604
605 qcom,local-pid = <0>;
606 qcom,remote-pid = <3>;
607
608 smp2p_slpi_out: master-kernel {
609 qcom,entry-name = "master-kernel";
610 #qcom,smem-state-cells = <1>;
611 };
612
613 smp2p_slpi_in: slave-kernel {
614 qcom,entry-name = "slave-kernel";
615 interrupt-controller;
616 #interrupt-cells = <2>;
617 };
618 };
619
b7e8f433
VK		 620 soc: soc@0 {
621 #address-cells = <2>;
622 #size-cells = <2>;
623 ranges = <0 0 0 0 0x10 0>;
624 dma-ranges = <0 0 0 0 0x10 0>;
625 compatible = "simple-bus";
626
627 gcc: clock-controller@100000 {
628 compatible = "qcom,gcc-sm8350";
629 reg = <0x0 0x00100000 0x0 0x1f0000>;
630 #clock-cells = <1>;
631 #reset-cells = <1>;
632 #power-domain-cells = <1>;
9ea9eb36
KD		 633 clock-names = "bi_tcxo",
634 "sleep_clk",
635 "pcie_0_pipe_clk",
636 "pcie_1_pipe_clk",
637 "ufs_card_rx_symbol_0_clk",
638 "ufs_card_rx_symbol_1_clk",
639 "ufs_card_tx_symbol_0_clk",
640 "ufs_phy_rx_symbol_0_clk",
641 "ufs_phy_rx_symbol_1_clk",
642 "ufs_phy_tx_symbol_0_clk",
643 "usb3_phy_wrapper_gcc_usb30_pipe_clk",
644 "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
645 clocks = <&rpmhcc RPMH_CXO_CLK>,
646 <&sleep_clk>,
6daee406
DB		 647 <&pcie0_phy>,
648 <&pcie1_phy>,
9ea9eb36
KD		 649 <0>,
650 <0>,
651 <0>,
86543bc6
DB		 652 <&ufs_mem_phy_lanes 0>,
653 <&ufs_mem_phy_lanes 1>,
654 <&ufs_mem_phy_lanes 2>,
9ea9eb36
KD		 655 <0>,
656 <0>;
b7e8f433
VK		 657 };
658
659 ipcc: mailbox@408000 {
660 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
661 reg = <0 0x00408000 0 0x1000>;
662 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
663 interrupt-controller;
664 #interrupt-cells = <3>;
665 #mbox-cells = <2>;
666 };
667
bc08fbf4 668 gpi_dma2: dma-controller@800000 {
b561e225 669 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 670 reg = <0 0x00800000 0 0x60000>;
671 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
683 dma-channels = <12>;
684 dma-channel-mask = <0xff>;
685 iommus = <&apps_smmu 0x5f6 0x0>;
686 #dma-cells = <3>;
687 status = "disabled";
688 };
689
e84d04a2
KD		 690 qupv3_id_2: geniqup@8c0000 {
691 compatible = "qcom,geni-se-qup";
692 reg = <0x0 0x008c0000 0x0 0x6000>;
693 clock-names = "m-ahb", "s-ahb";
694 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
695 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
9bc2c8fe 696 iommus = <&apps_smmu 0x5e3 0x0>;
e84d04a2
KD		 697 #address-cells = <2>;
698 #size-cells = <2>;
699 ranges;
700 status = "disabled";
98374e69
KD		 701
702 i2c14: i2c@880000 {
703 compatible = "qcom,geni-i2c";
704 reg = <0 0x00880000 0 0x4000>;
705 clock-names = "se";
706 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&qup_i2c14_default>;
709 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 710 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
711 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
712 dma-names = "tx", "rx";
98374e69
KD		 713 #address-cells = <1>;
714 #size-cells = <0>;
715 status = "disabled";
716 };
717
718 spi14: spi@880000 {
719 compatible = "qcom,geni-spi";
720 reg = <0 0x00880000 0 0x4000>;
721 clock-names = "se";
722 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
723 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
724 power-domains = <&rpmhpd SM8350_CX>;
725 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 726 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
727 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
728 dma-names = "tx", "rx";
98374e69
KD		 729 #address-cells = <1>;
730 #size-cells = <0>;
731 status = "disabled";
732 };
733
734 i2c15: i2c@884000 {
735 compatible = "qcom,geni-i2c";
736 reg = <0 0x00884000 0 0x4000>;
737 clock-names = "se";
738 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
739 pinctrl-names = "default";
740 pinctrl-0 = <&qup_i2c15_default>;
741 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 742 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
743 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
744 dma-names = "tx", "rx";
98374e69
KD		 745 #address-cells = <1>;
746 #size-cells = <0>;
747 status = "disabled";
748 };
749
750 spi15: spi@884000 {
751 compatible = "qcom,geni-spi";
752 reg = <0 0x00884000 0 0x4000>;
753 clock-names = "se";
754 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
755 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
756 power-domains = <&rpmhpd SM8350_CX>;
757 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 758 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
759 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
760 dma-names = "tx", "rx";
98374e69
KD		 761 #address-cells = <1>;
762 #size-cells = <0>;
763 status = "disabled";
764 };
765
766 i2c16: i2c@888000 {
767 compatible = "qcom,geni-i2c";
768 reg = <0 0x00888000 0 0x4000>;
769 clock-names = "se";
770 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
771 pinctrl-names = "default";
772 pinctrl-0 = <&qup_i2c16_default>;
773 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 774 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
775 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
776 dma-names = "tx", "rx";
98374e69
KD		 777 #address-cells = <1>;
778 #size-cells = <0>;
779 status = "disabled";
780 };
781
782 spi16: spi@888000 {
783 compatible = "qcom,geni-spi";
784 reg = <0 0x00888000 0 0x4000>;
785 clock-names = "se";
786 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
787 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
788 power-domains = <&rpmhpd SM8350_CX>;
789 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 790 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
791 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
792 dma-names = "tx", "rx";
98374e69
KD		 793 #address-cells = <1>;
794 #size-cells = <0>;
795 status = "disabled";
796 };
797
798 i2c17: i2c@88c000 {
799 compatible = "qcom,geni-i2c";
800 reg = <0 0x0088c000 0 0x4000>;
801 clock-names = "se";
802 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
803 pinctrl-names = "default";
804 pinctrl-0 = <&qup_i2c17_default>;
805 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 806 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
807 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
808 dma-names = "tx", "rx";
98374e69
KD		 809 #address-cells = <1>;
810 #size-cells = <0>;
811 status = "disabled";
812 };
813
814 spi17: spi@88c000 {
815 compatible = "qcom,geni-spi";
816 reg = <0 0x0088c000 0 0x4000>;
817 clock-names = "se";
818 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
819 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
820 power-domains = <&rpmhpd SM8350_CX>;
821 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 822 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
823 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
824 dma-names = "tx", "rx";
98374e69
KD		 825 #address-cells = <1>;
826 #size-cells = <0>;
827 status = "disabled";
828 };
829
830 /* QUP no. 18 seems to be strictly SPI/UART-only */
831
832 spi18: spi@890000 {
833 compatible = "qcom,geni-spi";
834 reg = <0 0x00890000 0 0x4000>;
835 clock-names = "se";
836 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
837 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
838 power-domains = <&rpmhpd SM8350_CX>;
839 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 840 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
841 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
842 dma-names = "tx", "rx";
98374e69
KD		 843 #address-cells = <1>;
844 #size-cells = <0>;
845 status = "disabled";
846 };
847
848 uart18: serial@890000 {
849 compatible = "qcom,geni-uart";
850 reg = <0 0x00890000 0 0x4000>;
851 clock-names = "se";
852 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
853 pinctrl-names = "default";
854 pinctrl-0 = <&qup_uart18_default>;
855 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
856 power-domains = <&rpmhpd SM8350_CX>;
857 operating-points-v2 = <&qup_opp_table_100mhz>;
858 status = "disabled";
859 };
860
861 i2c19: i2c@894000 {
862 compatible = "qcom,geni-i2c";
863 reg = <0 0x00894000 0 0x4000>;
864 clock-names = "se";
865 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
866 pinctrl-names = "default";
867 pinctrl-0 = <&qup_i2c19_default>;
868 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 869 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
870 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
871 dma-names = "tx", "rx";
98374e69
KD		 872 #address-cells = <1>;
873 #size-cells = <0>;
874 status = "disabled";
875 };
876
877 spi19: spi@894000 {
878 compatible = "qcom,geni-spi";
879 reg = <0 0x00894000 0 0x4000>;
880 clock-names = "se";
881 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
882 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
883 power-domains = <&rpmhpd SM8350_CX>;
884 operating-points-v2 = <&qup_opp_table_100mhz>;
bc08fbf4
BA		 885 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
886 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
887 dma-names = "tx", "rx";
98374e69
KD		 888 #address-cells = <1>;
889 #size-cells = <0>;
890 status = "disabled";
891 };
e84d04a2
KD		 892 };
893
bc08fbf4 894 gpi_dma0: dma-controller@900000 {
b561e225 895 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 896 reg = <0 0x09800000 0 0x60000>;
897 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
904 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
909 dma-channels = <12>;
910 dma-channel-mask = <0x7e>;
911 iommus = <&apps_smmu 0x5b6 0x0>;
912 #dma-cells = <3>;
913 status = "disabled";
914 };
915
87f0b434 916 qupv3_id_0: geniqup@9c0000 {
b7e8f433
VK		 917 compatible = "qcom,geni-se-qup";
918 reg = <0x0 0x009c0000 0x0 0x6000>;
919 clock-names = "m-ahb", "s-ahb";
6d91e201
VK		 920 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
921 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
9bc2c8fe 922 iommus = <&apps_smmu 0x5a3 0>;
b7e8f433
VK		 923 #address-cells = <2>;
924 #size-cells = <2>;
925 ranges;
926 status = "disabled";
927
cf03cd7e
KD		 928 i2c0: i2c@980000 {
929 compatible = "qcom,geni-i2c";
930 reg = <0 0x00980000 0 0x4000>;
931 clock-names = "se";
932 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
933 pinctrl-names = "default";
934 pinctrl-0 = <&qup_i2c0_default>;
935 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 936 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
937 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
938 dma-names = "tx", "rx";
cf03cd7e
KD		 939 #address-cells = <1>;
940 #size-cells = <0>;
941 status = "disabled";
942 };
943
944 spi0: spi@980000 {
945 compatible = "qcom,geni-spi";
946 reg = <0 0x00980000 0 0x4000>;
947 clock-names = "se";
948 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
949 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
950 power-domains = <&rpmhpd SM8350_CX>;
951 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 952 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
953 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
954 dma-names = "tx", "rx";
cf03cd7e
KD		 955 #address-cells = <1>;
956 #size-cells = <0>;
957 status = "disabled";
958 };
959
960 i2c1: i2c@984000 {
961 compatible = "qcom,geni-i2c";
962 reg = <0 0x00984000 0 0x4000>;
963 clock-names = "se";
964 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&qup_i2c1_default>;
967 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 968 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
969 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
970 dma-names = "tx", "rx";
cf03cd7e
KD		 971 #address-cells = <1>;
972 #size-cells = <0>;
973 status = "disabled";
974 };
975
976 spi1: spi@984000 {
977 compatible = "qcom,geni-spi";
978 reg = <0 0x00984000 0 0x4000>;
979 clock-names = "se";
980 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
981 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
982 power-domains = <&rpmhpd SM8350_CX>;
983 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 984 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
985 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
986 dma-names = "tx", "rx";
cf03cd7e
KD		 987 #address-cells = <1>;
988 #size-cells = <0>;
989 status = "disabled";
990 };
991
992 i2c2: i2c@988000 {
993 compatible = "qcom,geni-i2c";
994 reg = <0 0x00988000 0 0x4000>;
995 clock-names = "se";
996 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
997 pinctrl-names = "default";
998 pinctrl-0 = <&qup_i2c2_default>;
999 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1000 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1001 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1002 dma-names = "tx", "rx";
cf03cd7e
KD		 1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 status = "disabled";
1006 };
1007
1008 spi2: spi@988000 {
1009 compatible = "qcom,geni-spi";
1010 reg = <0 0x00988000 0 0x4000>;
1011 clock-names = "se";
1012 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1013 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1014 power-domains = <&rpmhpd SM8350_CX>;
1015 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1016 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1017 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1018 dma-names = "tx", "rx";
cf03cd7e
KD		 1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 status = "disabled";
1022 };
1023
b7e8f433
VK		 1024 uart2: serial@98c000 {
1025 compatible = "qcom,geni-debug-uart";
1026 reg = <0 0x0098c000 0 0x4000>;
1027 clock-names = "se";
6d91e201 1028 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
b7e8f433
VK		 1029 pinctrl-names = "default";
1030 pinctrl-0 = <&qup_uart3_default_state>;
1031 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
cf03cd7e
KD		 1032 power-domains = <&rpmhpd SM8350_CX>;
1033 operating-points-v2 = <&qup_opp_table_100mhz>;
cf03cd7e
KD		 1034 status = "disabled";
1035 };
1036
1037 /* QUP no. 3 seems to be strictly SPI-only */
1038
1039 spi3: spi@98c000 {
1040 compatible = "qcom,geni-spi";
1041 reg = <0 0x0098c000 0 0x4000>;
1042 clock-names = "se";
1043 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1044 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1045 power-domains = <&rpmhpd SM8350_CX>;
1046 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1047 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1048 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1049 dma-names = "tx", "rx";
cf03cd7e
KD		 1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052 status = "disabled";
1053 };
1054
1055 i2c4: i2c@990000 {
1056 compatible = "qcom,geni-i2c";
1057 reg = <0 0x00990000 0 0x4000>;
1058 clock-names = "se";
1059 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&qup_i2c4_default>;
1062 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1063 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1064 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1065 dma-names = "tx", "rx";
cf03cd7e
KD		 1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 status = "disabled";
1069 };
1070
1071 spi4: spi@990000 {
1072 compatible = "qcom,geni-spi";
1073 reg = <0 0x00990000 0 0x4000>;
1074 clock-names = "se";
1075 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1076 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1077 power-domains = <&rpmhpd SM8350_CX>;
1078 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1079 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1080 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1081 dma-names = "tx", "rx";
cf03cd7e
KD		 1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 status = "disabled";
1085 };
1086
1087 i2c5: i2c@994000 {
1088 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00994000 0 0x4000>;
1090 clock-names = "se";
1091 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&qup_i2c5_default>;
1094 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1095 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1096 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1097 dma-names = "tx", "rx";
cf03cd7e
KD		 1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 status = "disabled";
1101 };
1102
1103 spi5: spi@994000 {
1104 compatible = "qcom,geni-spi";
1105 reg = <0 0x00994000 0 0x4000>;
1106 clock-names = "se";
1107 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1108 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1109 power-domains = <&rpmhpd SM8350_CX>;
1110 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1111 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1112 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1113 dma-names = "tx", "rx";
cf03cd7e
KD		 1114 #address-cells = <1>;
1115 #size-cells = <0>;
1116 status = "disabled";
1117 };
1118
1119 i2c6: i2c@998000 {
1120 compatible = "qcom,geni-i2c";
1121 reg = <0 0x00998000 0 0x4000>;
1122 clock-names = "se";
1123 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&qup_i2c6_default>;
1126 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1127 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1128 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1129 dma-names = "tx", "rx";
cf03cd7e
KD		 1130 #address-cells = <1>;
1131 #size-cells = <0>;
1132 status = "disabled";
1133 };
1134
1135 spi6: spi@998000 {
1136 compatible = "qcom,geni-spi";
1137 reg = <0 0x00998000 0 0x4000>;
1138 clock-names = "se";
1139 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1140 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1141 power-domains = <&rpmhpd SM8350_CX>;
1142 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1143 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1144 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1145 dma-names = "tx", "rx";
cf03cd7e
KD		 1146 #address-cells = <1>;
1147 #size-cells = <0>;
1148 status = "disabled";
1149 };
1150
1151 uart6: serial@998000 {
1152 compatible = "qcom,geni-uart";
1153 reg = <0 0x00998000 0 0x4000>;
1154 clock-names = "se";
1155 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_uart6_default>;
1158 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1159 power-domains = <&rpmhpd SM8350_CX>;
1160 operating-points-v2 = <&qup_opp_table_100mhz>;
1161 status = "disabled";
1162 };
1163
1164 i2c7: i2c@99c000 {
1165 compatible = "qcom,geni-i2c";
1166 reg = <0 0x0099c000 0 0x4000>;
1167 clock-names = "se";
1168 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1169 pinctrl-names = "default";
1170 pinctrl-0 = <&qup_i2c7_default>;
1171 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1172 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1173 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1174 dma-names = "tx", "rx";
cf03cd7e
KD		 1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 status = "disabled";
1178 };
1179
1180 spi7: spi@99c000 {
1181 compatible = "qcom,geni-spi";
1182 reg = <0 0x0099c000 0 0x4000>;
1183 clock-names = "se";
1184 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1185 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1186 power-domains = <&rpmhpd SM8350_CX>;
1187 operating-points-v2 = <&qup_opp_table_100mhz>;
bc08fbf4
BA		 1188 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1189 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1190 dma-names = "tx", "rx";
b7e8f433
VK		 1191 #address-cells = <1>;
1192 #size-cells = <0>;
1193 status = "disabled";
1194 };
1195 };
1196
bc08fbf4 1197 gpi_dma1: dma-controller@a00000 {
b561e225 1198 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
bc08fbf4
BA		 1199 reg = <0 0x00a00000 0 0x60000>;
1200 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1212 dma-channels = <12>;
1213 dma-channel-mask = <0xff>;
1214 iommus = <&apps_smmu 0x56 0x0>;
1215 #dma-cells = <3>;
1216 status = "disabled";
1217 };
1218
06bf656e
JM		 1219 qupv3_id_1: geniqup@ac0000 {
1220 compatible = "qcom,geni-se-qup";
1221 reg = <0x0 0x00ac0000 0x0 0x6000>;
1222 clock-names = "m-ahb", "s-ahb";
1223 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1224 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
9bc2c8fe 1225 iommus = <&apps_smmu 0x43 0>;
06bf656e
JM		 1226 #address-cells = <2>;
1227 #size-cells = <2>;
1228 ranges;
1229 status = "disabled";
1230
89345355
KD		 1231 i2c8: i2c@a80000 {
1232 compatible = "qcom,geni-i2c";
1233 reg = <0 0x00a80000 0 0x4000>;
1234 clock-names = "se";
1235 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&qup_i2c8_default>;
1238 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1239 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1240 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1241 dma-names = "tx", "rx";
89345355
KD		 1242 #address-cells = <1>;
1243 #size-cells = <0>;
1244 status = "disabled";
1245 };
1246
1247 spi8: spi@a80000 {
1248 compatible = "qcom,geni-spi";
1249 reg = <0 0x00a80000 0 0x4000>;
1250 clock-names = "se";
1251 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1252 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1253 power-domains = <&rpmhpd SM8350_CX>;
1254 operating-points-v2 = <&qup_opp_table_120mhz>;
ddc97e7d
BA		 1255 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1256 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1257 dma-names = "tx", "rx";
89345355
KD		 1258 #address-cells = <1>;
1259 #size-cells = <0>;
1260 status = "disabled";
1261 };
1262
1263 i2c9: i2c@a84000 {
1264 compatible = "qcom,geni-i2c";
1265 reg = <0 0x00a84000 0 0x4000>;
1266 clock-names = "se";
1267 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&qup_i2c9_default>;
1270 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1271 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1272 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1273 dma-names = "tx", "rx";
89345355
KD		 1274 #address-cells = <1>;
1275 #size-cells = <0>;
1276 status = "disabled";
1277 };
1278
1279 spi9: spi@a84000 {
1280 compatible = "qcom,geni-spi";
1281 reg = <0 0x00a84000 0 0x4000>;
1282 clock-names = "se";
1283 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1284 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1285 power-domains = <&rpmhpd SM8350_CX>;
1286 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1287 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1288 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1289 dma-names = "tx", "rx";
89345355
KD		 1290 #address-cells = <1>;
1291 #size-cells = <0>;
1292 status = "disabled";
1293 };
1294
1295 i2c10: i2c@a88000 {
1296 compatible = "qcom,geni-i2c";
1297 reg = <0 0x00a88000 0 0x4000>;
1298 clock-names = "se";
1299 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1300 pinctrl-names = "default";
1301 pinctrl-0 = <&qup_i2c10_default>;
1302 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1303 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1304 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1305 dma-names = "tx", "rx";
89345355
KD		 1306 #address-cells = <1>;
1307 #size-cells = <0>;
1308 status = "disabled";
1309 };
1310
1311 spi10: spi@a88000 {
1312 compatible = "qcom,geni-spi";
1313 reg = <0 0x00a88000 0 0x4000>;
1314 clock-names = "se";
1315 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1316 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1317 power-domains = <&rpmhpd SM8350_CX>;
1318 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1319 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1320 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1321 dma-names = "tx", "rx";
89345355
KD		 1322 #address-cells = <1>;
1323 #size-cells = <0>;
1324 status = "disabled";
1325 };
1326
1327 i2c11: i2c@a8c000 {
1328 compatible = "qcom,geni-i2c";
1329 reg = <0 0x00a8c000 0 0x4000>;
1330 clock-names = "se";
1331 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1332 pinctrl-names = "default";
1333 pinctrl-0 = <&qup_i2c11_default>;
1334 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1335 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1336 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1337 dma-names = "tx", "rx";
89345355
KD		 1338 #address-cells = <1>;
1339 #size-cells = <0>;
1340 status = "disabled";
1341 };
1342
1343 spi11: spi@a8c000 {
1344 compatible = "qcom,geni-spi";
1345 reg = <0 0x00a8c000 0 0x4000>;
1346 clock-names = "se";
1347 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1348 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1349 power-domains = <&rpmhpd SM8350_CX>;
1350 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1351 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1352 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1353 dma-names = "tx", "rx";
89345355
KD		 1354 #address-cells = <1>;
1355 #size-cells = <0>;
1356 status = "disabled";
1357 };
1358
1359 i2c12: i2c@a90000 {
1360 compatible = "qcom,geni-i2c";
1361 reg = <0 0x00a90000 0 0x4000>;
1362 clock-names = "se";
1363 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&qup_i2c12_default>;
1366 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1367 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1368 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1369 dma-names = "tx", "rx";
89345355
KD		 1370 #address-cells = <1>;
1371 #size-cells = <0>;
1372 status = "disabled";
1373 };
1374
1375 spi12: spi@a90000 {
1376 compatible = "qcom,geni-spi";
1377 reg = <0 0x00a90000 0 0x4000>;
1378 clock-names = "se";
1379 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1380 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1381 power-domains = <&rpmhpd SM8350_CX>;
1382 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1383 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1384 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1385 dma-names = "tx", "rx";
89345355
KD		 1386 #address-cells = <1>;
1387 #size-cells = <0>;
1388 status = "disabled";
1389 };
1390
06bf656e
JM		 1391 i2c13: i2c@a94000 {
1392 compatible = "qcom,geni-i2c";
1393 reg = <0 0x00a94000 0 0x4000>;
1394 clock-names = "se";
1395 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1396 pinctrl-names = "default";
89345355 1397 pinctrl-0 = <&qup_i2c13_default>;
06bf656e 1398 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
ddc97e7d
BA		 1399 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1400 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1401 dma-names = "tx", "rx";
06bf656e
JM		 1402 #address-cells = <1>;
1403 #size-cells = <0>;
1404 status = "disabled";
1405 };
89345355
KD		 1406
1407 spi13: spi@a94000 {
1408 compatible = "qcom,geni-spi";
1409 reg = <0 0x00a94000 0 0x4000>;
1410 clock-names = "se";
1411 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1412 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1413 power-domains = <&rpmhpd SM8350_CX>;
1414 operating-points-v2 = <&qup_opp_table_100mhz>;
ddc97e7d
BA		 1415 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1416 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1417 dma-names = "tx", "rx";
89345355
KD		 1418 #address-cells = <1>;
1419 #size-cells = <0>;
1420 status = "disabled";
1421 };
06bf656e
JM		 1422 };
1423
1417372f
DB		 1424 rng: rng@10d3000 {
1425 compatible = "qcom,prng-ee";
1426 reg = <0 0x010d3000 0 0x1000>;
1427 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1428 clock-names = "core";
1429 };
1430
da6b2482
VK		 1431 config_noc: interconnect@1500000 {
1432 compatible = "qcom,sm8350-config-noc";
1433 reg = <0 0x01500000 0 0xa580>;
4f287e31 1434 #interconnect-cells = <2>;
da6b2482
VK		 1435 qcom,bcm-voters = <&apps_bcm_voter>;
1436 };
1437
1438 mc_virt: interconnect@1580000 {
1439 compatible = "qcom,sm8350-mc-virt";
1440 reg = <0 0x01580000 0 0x1000>;
4f287e31 1441 #interconnect-cells = <2>;
da6b2482
VK		 1442 qcom,bcm-voters = <&apps_bcm_voter>;
1443 };
1444
1445 system_noc: interconnect@1680000 {
1446 compatible = "qcom,sm8350-system-noc";
1447 reg = <0 0x01680000 0 0x1c200>;
4f287e31 1448 #interconnect-cells = <2>;
da6b2482
VK		 1449 qcom,bcm-voters = <&apps_bcm_voter>;
1450 };
1451
1452 aggre1_noc: interconnect@16e0000 {
1453 compatible = "qcom,sm8350-aggre1-noc";
1454 reg = <0 0x016e0000 0 0x1f180>;
4f287e31 1455 #interconnect-cells = <2>;
da6b2482
VK		 1456 qcom,bcm-voters = <&apps_bcm_voter>;
1457 };
1458
1459 aggre2_noc: interconnect@1700000 {
1460 compatible = "qcom,sm8350-aggre2-noc";
1461 reg = <0 0x01700000 0 0x33000>;
4f287e31 1462 #interconnect-cells = <2>;
da6b2482
VK		 1463 qcom,bcm-voters = <&apps_bcm_voter>;
1464 };
1465
1466 mmss_noc: interconnect@1740000 {
1467 compatible = "qcom,sm8350-mmss-noc";
1468 reg = <0 0x01740000 0 0x1f080>;
4f287e31 1469 #interconnect-cells = <2>;
da6b2482
VK		 1470 qcom,bcm-voters = <&apps_bcm_voter>;
1471 };
1472
6daee406
DB		 1473 pcie0: pci@1c00000 {
1474 compatible = "qcom,pcie-sm8350";
1475 reg = <0 0x01c00000 0 0x3000>,
1476 <0 0x60000000 0 0xf1d>,
1477 <0 0x60000f20 0 0xa8>,
1478 <0 0x60001000 0 0x1000>,
1479 <0 0x60100000 0 0x100000>;
1480 reg-names = "parf", "dbi", "elbi", "atu", "config";
1481 device_type = "pci";
1482 linux,pci-domain = <0>;
1483 bus-range = <0x00 0xff>;
1484 num-lanes = <1>;
1485
1486 #address-cells = <3>;
1487 #size-cells = <2>;
1488
1489 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1490 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1491
1492 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1497 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1498 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1499 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1500 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1501 "msi4", "msi5", "msi6", "msi7";
1502 #interrupt-cells = <1>;
1503 interrupt-map-mask = <0 0 0 0x7>;
1504 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1505 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1506 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1507 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1508
1509 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1510 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1511 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1512 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1513 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1514 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1515 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1516 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1517 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
1518 clock-names = "aux",
1519 "cfg",
1520 "bus_master",
1521 "bus_slave",
1522 "slave_q2a",
1523 "tbu",
1524 "ddrss_sf_tbu",
1525 "aggre1",
1526 "aggre0";
1527
1528 iommus = <&apps_smmu 0x1c00 0x7f>;
1529 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1530 <0x100 &apps_smmu 0x1c01 0x1>;
1531
1532 resets = <&gcc GCC_PCIE_0_BCR>;
1533 reset-names = "pci";
1534
1535 power-domains = <&gcc PCIE_0_GDSC>;
1536
1537 phys = <&pcie0_phy>;
1538 phy-names = "pciephy";
1539
1540 status = "disabled";
1541 };
1542
1543 pcie0_phy: phy@1c06000 {
1544 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1545 reg = <0 0x01c06000 0 0x2000>;
1546 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1547 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1548 <&gcc GCC_PCIE_0_CLKREF_EN>,
1549 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
1550 <&gcc GCC_PCIE_0_PIPE_CLK>;
1551 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1552
1553 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1554 reset-names = "phy";
1555
1556 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1557 assigned-clock-rates = <100000000>;
1558
1559 #clock-cells = <0>;
1560 clock-output-names = "pcie_0_pipe_clk";
1561
1562 #phy-cells = <0>;
1563
1564 status = "disabled";
1565 };
1566
1567 pcie1: pci@1c08000 {
1568 compatible = "qcom,pcie-sm8350";
1569 reg = <0 0x01c08000 0 0x3000>,
1570 <0 0x40000000 0 0xf1d>,
1571 <0 0x40000f20 0 0xa8>,
1572 <0 0x40001000 0 0x1000>,
1573 <0 0x40100000 0 0x100000>;
1574 reg-names = "parf", "dbi", "elbi", "atu", "config";
1575 device_type = "pci";
1576 linux,pci-domain = <1>;
1577 bus-range = <0x00 0xff>;
1578 num-lanes = <2>;
1579
1580 #address-cells = <3>;
1581 #size-cells = <2>;
1582
1583 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1584 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1585
1586 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1587 interrupt-names = "msi";
1588 #interrupt-cells = <1>;
1589 interrupt-map-mask = <0 0 0 0x7>;
1590 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1591 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1592 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1593 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1594
1595 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1596 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1597 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1598 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1599 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1600 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1601 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1602 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1603 clock-names = "aux",
1604 "cfg",
1605 "bus_master",
1606 "bus_slave",
1607 "slave_q2a",
1608 "tbu",
1609 "ddrss_sf_tbu",
1610 "aggre1";
1611
1612 iommus = <&apps_smmu 0x1c80 0x7f>;
1613 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1614 <0x100 &apps_smmu 0x1c81 0x1>;
1615
1616 resets = <&gcc GCC_PCIE_1_BCR>;
1617 reset-names = "pci";
1618
1619 power-domains = <&gcc PCIE_1_GDSC>;
1620
1621 phys = <&pcie1_phy>;
1622 phy-names = "pciephy";
1623
1624 status = "disabled";
1625 };
1626
1627 pcie1_phy: phy@1c0f000 {
1628 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1629 reg = <0 0x01c0e000 0 0x2000>;
1630 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1631 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1632 <&gcc GCC_PCIE_1_CLKREF_EN>,
1633 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
1634 <&gcc GCC_PCIE_1_PIPE_CLK>;
1635 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1636
1637 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1638 reset-names = "phy";
1639
1640 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1641 assigned-clock-rates = <100000000>;
1642
1643 #clock-cells = <0>;
1644 clock-output-names = "pcie_1_pipe_clk";
1645
1646 #phy-cells = <0>;
1647
1648 status = "disabled";
1649 };
1650
1417372f
DB		 1651 ufs_mem_hc: ufshc@1d84000 {
1652 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1653 "jedec,ufs-2.0";
1654 reg = <0 0x01d84000 0 0x3000>;
1655 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1656 phys = <&ufs_mem_phy_lanes>;
1657 phy-names = "ufsphy";
1658 lanes-per-direction = <2>;
1659 #reset-cells = <1>;
1660 resets = <&gcc GCC_UFS_PHY_BCR>;
1661 reset-names = "rst";
1662
1663 power-domains = <&gcc UFS_PHY_GDSC>;
1664
1665 iommus = <&apps_smmu 0xe0 0x0>;
1666
1667 clock-names =
1668 "core_clk",
1669 "bus_aggr_clk",
1670 "iface_clk",
1671 "core_clk_unipro",
1672 "ref_clk",
1673 "tx_lane0_sync_clk",
1674 "rx_lane0_sync_clk",
1675 "rx_lane1_sync_clk";
1676 clocks =
1677 <&gcc GCC_UFS_PHY_AXI_CLK>,
1678 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1679 <&gcc GCC_UFS_PHY_AHB_CLK>,
1680 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1681 <&rpmhcc RPMH_CXO_CLK>,
1682 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1683 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1684 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1685 freq-table-hz =
1686 <75000000 300000000>,
1687 <0 0>,
1688 <0 0>,
1689 <75000000 300000000>,
1690 <0 0>,
1691 <0 0>,
1692 <0 0>,
1693 <0 0>;
1694 status = "disabled";
da6b2482
VK		 1695 };
1696
1417372f
DB		 1697 ufs_mem_phy: phy@1d87000 {
1698 compatible = "qcom,sm8350-qmp-ufs-phy";
1699 reg = <0 0x01d87000 0 0x1c4>;
1700 #address-cells = <2>;
1701 #size-cells = <2>;
1702 ranges;
1703 clock-names = "ref",
1704 "ref_aux";
1705 clocks = <&rpmhcc RPMH_CXO_CLK>,
1706 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1707
1708 resets = <&ufs_mem_hc 0>;
1709 reset-names = "ufsphy";
1710 status = "disabled";
1711
1712 ufs_mem_phy_lanes: phy@1d87400 {
1713 reg = <0 0x01d87400 0 0x188>,
1714 <0 0x01d87600 0 0x200>,
1715 <0 0x01d87c00 0 0x200>,
1716 <0 0x01d87800 0 0x188>,
1717 <0 0x01d87a00 0 0x200>;
1718 #clock-cells = <1>;
1719 #phy-cells = <0>;
1720 };
da6b2482
VK		 1721 };
1722
f11d3e7d
AE		 1723 ipa: ipa@1e40000 {
1724 compatible = "qcom,sm8350-ipa";
1725
1726 iommus = <&apps_smmu 0x5c0 0x0>,
1727 <&apps_smmu 0x5c2 0x0>;
f3c08ae6
KD		 1728 reg = <0 0x01e40000 0 0x8000>,
1729 <0 0x01e50000 0 0x4b20>,
1730 <0 0x01e04000 0 0x23000>;
f11d3e7d
AE		 1731 reg-names = "ipa-reg",
1732 "ipa-shared",
1733 "gsi";
1734
1735 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1736 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1737 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1738 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1739 interrupt-names = "ipa",
1740 "gsi",
1741 "ipa-clock-query",
1742 "ipa-setup-ready";
1743
1744 clocks = <&rpmhcc RPMH_IPA_CLK>;
1745 clock-names = "core";
1746
4f287e31
RF		 1747 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1748 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
84173ca3
AE		 1749 interconnect-names = "memory",
1750 "config";
f11d3e7d 1751
73419e4d
AE		 1752 qcom,qmp = <&aoss_qmp>;
1753
f11d3e7d
AE		 1754 qcom,smem-states = <&ipa_smp2p_out 0>,
1755 <&ipa_smp2p_out 1>;
1756 qcom,smem-state-names = "ipa-clock-enabled-valid",
1757 "ipa-clock-enabled";
1758
1759 status = "disabled";
1760 };
1761
b7e8f433
VK		 1762 tcsr_mutex: hwlock@1f40000 {
1763 compatible = "qcom,tcsr-mutex";
1764 reg = <0x0 0x01f40000 0x0 0x40000>;
1765 #hwlock-cells = <1>;
1766 };
1767
1417372f
DB		 1768 lpass_ag_noc: interconnect@3c40000 {
1769 compatible = "qcom,sm8350-lpass-ag-noc";
1770 reg = <0 0x03c40000 0 0xf080>;
1771 #interconnect-cells = <2>;
1772 qcom,bcm-voters = <&apps_bcm_voter>;
1773 };
1774
177fcf0a
VK		 1775 mpss: remoteproc@4080000 {
1776 compatible = "qcom,sm8350-mpss-pas";
1777 reg = <0x0 0x04080000 0x0 0x4040>;
1778
1779 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1780 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1781 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1782 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1783 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1784 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1785 interrupt-names = "wdog", "fatal", "ready", "handover",
1786 "stop-ack", "shutdown-ack";
1787
1788 clocks = <&rpmhcc RPMH_CXO_CLK>;
1789 clock-names = "xo";
1790
d0e285c3
RF		 1791 power-domains = <&rpmhpd SM8350_CX>,
1792 <&rpmhpd SM8350_MSS>;
6b7cb2d2 1793 power-domain-names = "cx", "mss";
177fcf0a 1794
4f287e31 1795 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
da6b2482 1796
177fcf0a
VK		 1797 memory-region = <&pil_modem_mem>;
1798
6b7cb2d2
SS		 1799 qcom,qmp = <&aoss_qmp>;
1800
177fcf0a
VK		 1801 qcom,smem-states = <&smp2p_modem_out 0>;
1802 qcom,smem-state-names = "stop";
1803
1804 status = "disabled";
1805
1806 glink-edge {
1807 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1808 IPCC_MPROC_SIGNAL_GLINK_QMP
1809 IRQ_TYPE_EDGE_RISING>;
1810 mboxes = <&ipcc IPCC_CLIENT_MPSS
1811 IPCC_MPROC_SIGNAL_GLINK_QMP>;
177fcf0a
VK		 1812 label = "modem";
1813 qcom,remote-pid = <1>;
1814 };
1815 };
1816
1417372f
DB		 1817 slpi: remoteproc@5c00000 {
1818 compatible = "qcom,sm8350-slpi-pas";
1819 reg = <0 0x05c00000 0 0x4000>;
1820
1821 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1822 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1823 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1824 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1825 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1826 interrupt-names = "wdog", "fatal", "ready",
1827 "handover", "stop-ack";
1828
1829 clocks = <&rpmhcc RPMH_CXO_CLK>;
1830 clock-names = "xo";
1831
1832 power-domains = <&rpmhpd SM8350_LCX>,
1833 <&rpmhpd SM8350_LMX>;
1834 power-domain-names = "lcx", "lmx";
1835
1836 memory-region = <&pil_slpi_mem>;
1837
1838 qcom,qmp = <&aoss_qmp>;
1839
1840 qcom,smem-states = <&smp2p_slpi_out 0>;
1841 qcom,smem-state-names = "stop";
1842
1843 status = "disabled";
1844
1845 glink-edge {
1846 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1847 IPCC_MPROC_SIGNAL_GLINK_QMP
1848 IRQ_TYPE_EDGE_RISING>;
1849 mboxes = <&ipcc IPCC_CLIENT_SLPI
1850 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1851
1852 label = "slpi";
1853 qcom,remote-pid = <3>;
1854
1855 fastrpc {
1856 compatible = "qcom,fastrpc";
1857 qcom,glink-channels = "fastrpcglink-apps-dsp";
1858 label = "sdsp";
1859 qcom,non-secure-domain;
1860 #address-cells = <1>;
1861 #size-cells = <0>;
1862
1863 compute-cb@1 {
1864 compatible = "qcom,fastrpc-compute-cb";
1865 reg = <1>;
1866 iommus = <&apps_smmu 0x0541 0x0>;
1867 };
1868
1869 compute-cb@2 {
1870 compatible = "qcom,fastrpc-compute-cb";
1871 reg = <2>;
1872 iommus = <&apps_smmu 0x0542 0x0>;
1873 };
1874
1875 compute-cb@3 {
1876 compatible = "qcom,fastrpc-compute-cb";
1877 reg = <3>;
1878 iommus = <&apps_smmu 0x0543 0x0>;
1879 /* note: shared-cb = <4> in downstream */
1880 };
1881 };
1882 };
1883 };
1884
f5f6bd58
DB		 1885 sdhc_2: mmc@8804000 {
1886 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
1887 reg = <0 0x08804000 0 0x1000>;
177fcf0a 1888
f5f6bd58
DB		 1889 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1890 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1891 interrupt-names = "hc_irq", "pwr_irq";
177fcf0a 1892
f5f6bd58
DB		 1893 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1894 <&gcc GCC_SDCC2_APPS_CLK>,
1895 <&rpmhcc RPMH_CXO_CLK>;
1896 clock-names = "iface", "core", "xo";
1897 resets = <&gcc GCC_SDCC2_BCR>;
1898 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
1899 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
1900 interconnect-names = "sdhc-ddr","cpu-sdhc";
1901 iommus = <&apps_smmu 0x4a0 0x0>;
1902 power-domains = <&rpmhpd SM8350_CX>;
1903 operating-points-v2 = <&sdhc2_opp_table>;
1904 bus-width = <4>;
1905 dma-coherent;
177fcf0a 1906
f5f6bd58 1907 status = "disabled";
da6b2482 1908
f5f6bd58
DB		 1909 sdhc2_opp_table: opp-table {
1910 compatible = "operating-points-v2";
177fcf0a 1911
f5f6bd58
DB		 1912 opp-100000000 {
1913 opp-hz = /bits/ 64 <100000000>;
1914 required-opps = <&rpmhpd_opp_low_svs>;
1915 };
6b7cb2d2 1916
f5f6bd58
DB		 1917 opp-202000000 {
1918 opp-hz = /bits/ 64 <202000000>;
1919 required-opps = <&rpmhpd_opp_svs_l1>;
1920 };
1921 };
1922 };
177fcf0a 1923
f5f6bd58
DB		 1924 usb_1_hsphy: phy@88e3000 {
1925 compatible = "qcom,sm8350-usb-hs-phy",
1926 "qcom,usb-snps-hs-7nm-phy";
1927 reg = <0 0x088e3000 0 0x400>;
177fcf0a 1928 status = "disabled";
f5f6bd58 1929 #phy-cells = <0>;
177fcf0a 1930
f5f6bd58
DB		 1931 clocks = <&rpmhcc RPMH_CXO_CLK>;
1932 clock-names = "ref";
177fcf0a 1933
f5f6bd58
DB		 1934 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1935 };
178056a4 1936
f5f6bd58
DB		 1937 usb_2_hsphy: phy@88e4000 {
1938 compatible = "qcom,sm8250-usb-hs-phy",
1939 "qcom,usb-snps-hs-7nm-phy";
1940 reg = <0 0x088e4000 0 0x400>;
1941 status = "disabled";
1942 #phy-cells = <0>;
178056a4 1943
f5f6bd58
DB		 1944 clocks = <&rpmhcc RPMH_CXO_CLK>;
1945 clock-names = "ref";
e780fb31 1946
6d91e201 1947 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
e780fb31
JP		 1948 };
1949
1950 usb_1_qmpphy: phy-wrapper@88e9000 {
1951 compatible = "qcom,sm8350-qmp-usb3-phy";
1952 reg = <0 0x088e9000 0 0x200>,
1953 <0 0x088e8000 0 0x20>;
e780fb31 1954 status = "disabled";
e780fb31
JP		 1955 #address-cells = <2>;
1956 #size-cells = <2>;
1957 ranges;
1958
6d91e201 1959 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
e780fb31 1960 <&rpmhcc RPMH_CXO_CLK>,
6d91e201 1961 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
e780fb31
JP		 1962 clock-names = "aux", "ref_clk_src", "com_aux";
1963
6d91e201
VK		 1964 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1965 <&gcc GCC_USB3_PHY_PRIM_BCR>;
e780fb31
JP		 1966 reset-names = "phy", "common";
1967
1968 usb_1_ssphy: phy@88e9200 {
1969 reg = <0 0x088e9200 0 0x200>,
1970 <0 0x088e9400 0 0x200>,
1971 <0 0x088e9c00 0 0x400>,
1972 <0 0x088e9600 0 0x200>,
1973 <0 0x088e9800 0 0x200>,
1974 <0 0x088e9a00 0 0x100>;
1975 #phy-cells = <0>;
af551554 1976 #clock-cells = <0>;
6d91e201 1977 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
e780fb31
JP		 1978 clock-names = "pipe0";
1979 clock-output-names = "usb3_phy_pipe_clk_src";
1980 };
1981 };
1982
1983 usb_2_qmpphy: phy-wrapper@88eb000 {
1984 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
1985 reg = <0 0x088eb000 0 0x200>;
1986 status = "disabled";
e780fb31
JP		 1987 #address-cells = <2>;
1988 #size-cells = <2>;
1989 ranges;
1990
6d91e201 1991 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
e780fb31 1992 <&rpmhcc RPMH_CXO_CLK>,
6d91e201
VK		 1993 <&gcc GCC_USB3_SEC_CLKREF_EN>,
1994 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
e780fb31
JP		 1995 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1996
6d91e201
VK		 1997 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1998 <&gcc GCC_USB3_PHY_SEC_BCR>;
e780fb31
JP		 1999 reset-names = "phy", "common";
2000
2001 usb_2_ssphy: phy@88ebe00 {
2002 reg = <0 0x088ebe00 0 0x200>,
2003 <0 0x088ec000 0 0x200>,
2004 <0 0x088eb200 0 0x1100>;
2005 #phy-cells = <0>;
af551554 2006 #clock-cells = <0>;
6d91e201 2007 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
e780fb31
JP		 2008 clock-names = "pipe0";
2009 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2010 };
2011 };
2012
1dee9e3b 2013 dc_noc: interconnect@90c0000 {
da6b2482
VK		 2014 compatible = "qcom,sm8350-dc-noc";
2015 reg = <0 0x090c0000 0 0x4200>;
4f287e31 2016 #interconnect-cells = <2>;
da6b2482
VK		 2017 qcom,bcm-voters = <&apps_bcm_voter>;
2018 };
2019
2020 gem_noc: interconnect@9100000 {
2021 compatible = "qcom,sm8350-gem-noc";
2022 reg = <0 0x09100000 0 0xb4000>;
4f287e31 2023 #interconnect-cells = <2>;
da6b2482
VK		 2024 qcom,bcm-voters = <&apps_bcm_voter>;
2025 };
2026
9ac8999e
KD		 2027 system-cache-controller@9200000 {
2028 compatible = "qcom,sm8350-llcc";
2029 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2030 reg-names = "llcc_base", "llcc_broadcast_base";
2031 };
2032
1417372f
DB		 2033 compute_noc: interconnect@a0c0000 {
2034 compatible = "qcom,sm8350-compute-noc";
2035 reg = <0 0x0a0c0000 0 0xa180>;
2036 #interconnect-cells = <2>;
2037 qcom,bcm-voters = <&apps_bcm_voter>;
2038 };
2039
e780fb31
JP		 2040 usb_1: usb@a6f8800 {
2041 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2042 reg = <0 0x0a6f8800 0 0x400>;
2043 status = "disabled";
2044 #address-cells = <2>;
2045 #size-cells = <2>;
2046 ranges;
2047
6d91e201
VK		 2048 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2049 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2050 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
8d5fd4e4
KK		 2051 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2052 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2053 clock-names = "cfg_noc",
2054 "core",
2055 "iface",
2056 "sleep",
2057 "mock_utmi";
e780fb31 2058
6d91e201
VK		 2059 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2060 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
e780fb31
JP		 2061 assigned-clock-rates = <19200000>, <200000000>;
2062
2063 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
5b7e3499 2064 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
e780fb31 2065 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
5b7e3499
JH		 2066 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2067 interrupt-names = "hs_phy_irq",
2068 "ss_phy_irq",
2069 "dm_hs_phy_irq",
2070 "dp_hs_phy_irq";
e780fb31 2071
6d91e201 2072 power-domains = <&gcc USB30_PRIM_GDSC>;
e780fb31 2073
6d91e201 2074 resets = <&gcc GCC_USB30_PRIM_BCR>;
e780fb31 2075
2aa2b50d 2076 usb_1_dwc3: usb@a600000 {
e780fb31
JP		 2077 compatible = "snps,dwc3";
2078 reg = <0 0x0a600000 0 0xcd00>;
2079 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2080 iommus = <&apps_smmu 0x0 0x0>;
2081 snps,dis_u2_susphy_quirk;
2082 snps,dis_enblslpm_quirk;
2083 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2084 phy-names = "usb2-phy", "usb3-phy";
2085 };
2086 };
2087
2088 usb_2: usb@a8f8800 {
2089 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2090 reg = <0 0x0a8f8800 0 0x400>;
2091 status = "disabled";
2092 #address-cells = <2>;
2093 #size-cells = <2>;
2094 ranges;
2095
6d91e201
VK		 2096 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2097 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2098 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
6d91e201 2099 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
8d5fd4e4 2100 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
6d91e201 2101 <&gcc GCC_USB3_SEC_CLKREF_EN>;
8d5fd4e4
KK		 2102 clock-names = "cfg_noc",
2103 "core",
2104 "iface",
2105 "sleep",
2106 "mock_utmi",
2107 "xo";
e780fb31 2108
6d91e201
VK		 2109 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2110 <&gcc GCC_USB30_SEC_MASTER_CLK>;
e780fb31
JP		 2111 assigned-clock-rates = <19200000>, <200000000>;
2112
2113 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
5b7e3499 2114 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
e780fb31 2115 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
5b7e3499
JH		 2116 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2117 interrupt-names = "hs_phy_irq",
2118 "ss_phy_irq",
2119 "dm_hs_phy_irq",
2120 "dp_hs_phy_irq";
e780fb31 2121
6d91e201 2122 power-domains = <&gcc USB30_SEC_GDSC>;
e780fb31 2123
6d91e201 2124 resets = <&gcc GCC_USB30_SEC_BCR>;
e780fb31 2125
2aa2b50d 2126 usb_2_dwc3: usb@a800000 {
e780fb31
JP		 2127 compatible = "snps,dwc3";
2128 reg = <0 0x0a800000 0 0xcd00>;
2129 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2130 iommus = <&apps_smmu 0x20 0x0>;
2131 snps,dis_u2_susphy_quirk;
2132 snps,dis_enblslpm_quirk;
2133 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2134 phy-names = "usb2-phy", "usb3-phy";
2135 };
2136 };
177fcf0a 2137
d4a44105
RF		 2138 mdss: display-subsystem@ae00000 {
2139 compatible = "qcom,sm8350-mdss";
2140 reg = <0 0x0ae00000 0 0x1000>;
2141 reg-names = "mdss";
2142
2143 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2144 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2145 interconnect-names = "mdp0-mem", "mdp1-mem";
2146
2147 power-domains = <&dispcc MDSS_GDSC>;
2148 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2149
2150 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2151 <&gcc GCC_DISP_HF_AXI_CLK>,
2152 <&gcc GCC_DISP_SF_AXI_CLK>,
2153 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2154 clock-names = "iface", "bus", "nrt_bus", "core";
2155
2156 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2157 interrupt-controller;
2158 #interrupt-cells = <1>;
2159
2160 iommus = <&apps_smmu 0x820 0x402>;
2161
2162 status = "disabled";
2163
2164 #address-cells = <2>;
2165 #size-cells = <2>;
2166 ranges;
2167
2168 dpu_opp_table: opp-table {
2169 compatible = "operating-points-v2";
2170
2171 /* TODO: opp-200000000 should work with
2172 * &rpmhpd_opp_low_svs, but one some of
2173 * sm8350_hdk boards reboot using this
2174 * opp.
2175 */
2176 opp-200000000 {
2177 opp-hz = /bits/ 64 <200000000>;
2178 required-opps = <&rpmhpd_opp_svs>;
2179 };
2180
2181 opp-300000000 {
2182 opp-hz = /bits/ 64 <300000000>;
2183 required-opps = <&rpmhpd_opp_svs>;
2184 };
2185
2186 opp-345000000 {
2187 opp-hz = /bits/ 64 <345000000>;
2188 required-opps = <&rpmhpd_opp_svs_l1>;
2189 };
2190
2191 opp-460000000 {
2192 opp-hz = /bits/ 64 <460000000>;
2193 required-opps = <&rpmhpd_opp_nom>;
2194 };
2195 };
2196
2197 mdss_mdp: display-controller@ae01000 {
2198 compatible = "qcom,sm8350-dpu";
2199 reg = <0 0x0ae01000 0 0x8f000>,
2200 <0 0x0aeb0000 0 0x2008>;
2201 reg-names = "mdp", "vbif";
2202
2203 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2204 <&gcc GCC_DISP_SF_AXI_CLK>,
2205 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2206 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2207 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2208 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2209 clock-names = "bus",
2210 "nrt_bus",
2211 "iface",
2212 "lut",
2213 "core",
2214 "vsync";
2215
2216 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2217 assigned-clock-rates = <19200000>;
2218
2219 operating-points-v2 = <&dpu_opp_table>;
2220 power-domains = <&rpmhpd SM8350_MMCX>;
2221
2222 interrupt-parent = <&mdss>;
2223 interrupts = <0>;
2224
2225 ports {
2226 #address-cells = <1>;
2227 #size-cells = <0>;
2228
2229 port@0 {
2230 reg = <0>;
2231 dpu_intf1_out: endpoint {
2a07efb8 2232 remote-endpoint = <&mdss_dsi0_in>;
d4a44105
RF		 2233 };
2234 };
b904227a
KD		 2235
2236 port@1 {
2237 reg = <1>;
2238 dpu_intf2_out: endpoint {
2239 remote-endpoint = <&mdss_dsi1_in>;
2240 };
2241 };
d4a44105
RF		 2242 };
2243 };
2244
2245 mdss_dsi0: dsi@ae94000 {
d7133d6d 2246 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
d4a44105
RF		 2247 reg = <0 0x0ae94000 0 0x400>;
2248 reg-names = "dsi_ctrl";
2249
2250 interrupt-parent = <&mdss>;
2251 interrupts = <4>;
2252
2253 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2254 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2255 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2256 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2257 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2258 <&gcc GCC_DISP_HF_AXI_CLK>;
2259 clock-names = "byte",
2260 "byte_intf",
2261 "pixel",
2262 "core",
2263 "iface",
2264 "bus";
2265
2266 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2267 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2268 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2269 <&mdss_dsi0_phy 1>;
2270
2271 operating-points-v2 = <&dsi0_opp_table>;
2272 power-domains = <&rpmhpd SM8350_MMCX>;
2273
2274 phys = <&mdss_dsi0_phy>;
2275
6636818e
KD		 2276 #address-cells = <1>;
2277 #size-cells = <0>;
2278
d4a44105
RF		 2279 status = "disabled";
2280
2281 dsi0_opp_table: opp-table {
2282 compatible = "operating-points-v2";
2283
2284 /* TODO: opp-187500000 should work with
2285 * &rpmhpd_opp_low_svs, but one some of
2286 * sm8350_hdk boards reboot using this
2287 * opp.
2288 */
2289 opp-187500000 {
2290 opp-hz = /bits/ 64 <187500000>;
2291 required-opps = <&rpmhpd_opp_svs>;
2292 };
2293
2294 opp-300000000 {
2295 opp-hz = /bits/ 64 <300000000>;
2296 required-opps = <&rpmhpd_opp_svs>;
2297 };
2298
2299 opp-358000000 {
2300 opp-hz = /bits/ 64 <358000000>;
2301 required-opps = <&rpmhpd_opp_svs_l1>;
2302 };
2303 };
2304
2305 ports {
2306 #address-cells = <1>;
2307 #size-cells = <0>;
2308
2309 port@0 {
2310 reg = <0>;
2a07efb8 2311 mdss_dsi0_in: endpoint {
d4a44105
RF		 2312 remote-endpoint = <&dpu_intf1_out>;
2313 };
2314 };
2315
2316 port@1 {
2317 reg = <1>;
2a07efb8 2318 mdss_dsi0_out: endpoint {
d4a44105
RF		 2319 };
2320 };
2321 };
2322 };
2323
51f83fbb
DB		 2324 mdss_dsi0_phy: phy@ae94400 {
2325 compatible = "qcom,sm8350-dsi-phy-5nm";
2326 reg = <0 0x0ae94400 0 0x200>,
2327 <0 0x0ae94600 0 0x280>,
2328 <0 0x0ae94900 0 0x27c>;
2329 reg-names = "dsi_phy",
2330 "dsi_phy_lane",
2331 "dsi_pll";
2332
2333 #clock-cells = <1>;
2334 #phy-cells = <0>;
2335
2336 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2337 <&rpmhcc RPMH_CXO_CLK>;
2338 clock-names = "iface", "ref";
2339
2340 status = "disabled";
2341 };
2342
2343 mdss_dsi1: dsi@ae96000 {
2344 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2345 reg = <0 0x0ae96000 0 0x400>;
2346 reg-names = "dsi_ctrl";
2347
2348 interrupt-parent = <&mdss>;
2349 interrupts = <5>;
2350
2351 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2352 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2353 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2354 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2355 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2356 <&gcc GCC_DISP_HF_AXI_CLK>;
2357 clock-names = "byte",
2358 "byte_intf",
2359 "pixel",
2360 "core",
2361 "iface",
2362 "bus";
2363
2364 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2365 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2366 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2367 <&mdss_dsi1_phy 1>;
2368
2369 operating-points-v2 = <&dsi1_opp_table>;
2370 power-domains = <&rpmhpd SM8350_MMCX>;
2371
2372 phys = <&mdss_dsi1_phy>;
2373
2374 #address-cells = <1>;
2375 #size-cells = <0>;
2376
2377 status = "disabled";
2378
2379 dsi1_opp_table: opp-table {
2380 compatible = "operating-points-v2";
2381
2382 /* TODO: opp-187500000 should work with
2383 * &rpmhpd_opp_low_svs, but one some of
2384 * sm8350_hdk boards reboot using this
2385 * opp.
2386 */
2387 opp-187500000 {
2388 opp-hz = /bits/ 64 <187500000>;
2389 required-opps = <&rpmhpd_opp_svs>;
2390 };
2391
2392 opp-300000000 {
2393 opp-hz = /bits/ 64 <300000000>;
2394 required-opps = <&rpmhpd_opp_svs>;
2395 };
2396
2397 opp-358000000 {
2398 opp-hz = /bits/ 64 <358000000>;
2399 required-opps = <&rpmhpd_opp_svs_l1>;
2400 };
2401 };
2402
2403 ports {
2404 #address-cells = <1>;
2405 #size-cells = <0>;
2406
2407 port@0 {
2408 reg = <0>;
2409 mdss_dsi1_in: endpoint {
2410 remote-endpoint = <&dpu_intf2_out>;
2411 };
2412 };
2413
2414 port@1 {
2415 reg = <1>;
2416 mdss_dsi1_out: endpoint {
2417 };
2418 };
2419 };
2420 };
2421
2422 mdss_dsi1_phy: phy@ae96400 {
2423 compatible = "qcom,sm8350-dsi-phy-5nm";
2424 reg = <0 0x0ae96400 0 0x200>,
2425 <0 0x0ae96600 0 0x280>,
2426 <0 0x0ae96900 0 0x27c>;
2427 reg-names = "dsi_phy",
2428 "dsi_phy_lane",
2429 "dsi_pll";
2430
2431 #clock-cells = <1>;
2432 #phy-cells = <0>;
2433
2434 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2435 <&rpmhcc RPMH_CXO_CLK>;
2436 clock-names = "iface", "ref";
2437
2438 status = "disabled";
2439 };
2440 };
2441
2442 dispcc: clock-controller@af00000 {
2443 compatible = "qcom,sm8350-dispcc";
2444 reg = <0 0x0af00000 0 0x10000>;
2445 clocks = <&rpmhcc RPMH_CXO_CLK>,
2446 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2447 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2448 <0>,
2449 <0>;
2450 clock-names = "bi_tcxo",
2451 "dsi0_phy_pll_out_byteclk",
2452 "dsi0_phy_pll_out_dsiclk",
2453 "dsi1_phy_pll_out_byteclk",
2454 "dsi1_phy_pll_out_dsiclk",
2455 "dp_phy_pll_link_clk",
2456 "dp_phy_pll_vco_div_clk";
2457 #clock-cells = <1>;
2458 #reset-cells = <1>;
2459 #power-domain-cells = <1>;
2460
2461 power-domains = <&rpmhpd SM8350_MMCX>;
2462 };
2463
2464 pdc: interrupt-controller@b220000 {
2465 compatible = "qcom,sm8350-pdc", "qcom,pdc";
2466 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2467 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2468 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
2469 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
2470 <156 716 12>;
2471 #interrupt-cells = <2>;
2472 interrupt-parent = <&intc>;
2473 interrupt-controller;
2474 };
2475
2476 tsens0: thermal-sensor@c263000 {
2477 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2478 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2479 <0 0x0c222000 0 0x8>; /* SROT */
2480 #qcom,sensors = <15>;
2481 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2482 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2483 interrupt-names = "uplow", "critical";
2484 #thermal-sensor-cells = <1>;
2485 };
2486
2487 tsens1: thermal-sensor@c265000 {
2488 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2489 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2490 <0 0x0c223000 0 0x8>; /* SROT */
2491 #qcom,sensors = <14>;
2492 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2493 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2494 interrupt-names = "uplow", "critical";
2495 #thermal-sensor-cells = <1>;
2496 };
2497
2498 aoss_qmp: power-management@c300000 {
2499 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2500 reg = <0 0x0c300000 0 0x400>;
2501 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2502 IRQ_TYPE_EDGE_RISING>;
2503 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2504
2505 #clock-cells = <0>;
2506 };
2507
2508 sram@c3f0000 {
2509 compatible = "qcom,rpmh-stats";
2510 reg = <0 0x0c3f0000 0 0x400>;
2511 };
2512
2513 spmi_bus: spmi@c440000 {
2514 compatible = "qcom,spmi-pmic-arb";
2515 reg = <0x0 0x0c440000 0x0 0x1100>,
2516 <0x0 0x0c600000 0x0 0x2000000>,
2517 <0x0 0x0e600000 0x0 0x100000>,
2518 <0x0 0x0e700000 0x0 0xa0000>,
2519 <0x0 0x0c40a000 0x0 0x26000>;
2520 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2521 interrupt-names = "periph_irq";
2522 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2523 qcom,ee = <0>;
2524 qcom,channel = <0>;
2525 #address-cells = <2>;
2526 #size-cells = <0>;
2527 interrupt-controller;
2528 #interrupt-cells = <4>;
2529 };
2530
2531 tlmm: pinctrl@f100000 {
2532 compatible = "qcom,sm8350-tlmm";
2533 reg = <0 0x0f100000 0 0x300000>;
2534 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2535 gpio-controller;
2536 #gpio-cells = <2>;
2537 interrupt-controller;
2538 #interrupt-cells = <2>;
2539 gpio-ranges = <&tlmm 0 0 204>;
2540 wakeup-parent = <&pdc>;
2541
2542 sdc2_default_state: sdc2-default-state {
2543 clk-pins {
2544 pins = "sdc2_clk";
2545 drive-strength = <16>;
2546 bias-disable;
2547 };
2548
2549 cmd-pins {
2550 pins = "sdc2_cmd";
2551 drive-strength = <16>;
2552 bias-pull-up;
2553 };
2554
2555 data-pins {
2556 pins = "sdc2_data";
2557 drive-strength = <16>;
2558 bias-pull-up;
2559 };
2560 };
2561
2562 sdc2_sleep_state: sdc2-sleep-state {
2563 clk-pins {
2564 pins = "sdc2_clk";
2565 drive-strength = <2>;
2566 bias-disable;
2567 };
d4a44105 2568
51f83fbb
DB		 2569 cmd-pins {
2570 pins = "sdc2_cmd";
2571 drive-strength = <2>;
2572 bias-pull-up;
2573 };
d4a44105 2574
51f83fbb
DB		 2575 data-pins {
2576 pins = "sdc2_data";
2577 drive-strength = <2>;
2578 bias-pull-up;
2579 };
d4a44105
RF		 2580 };
2581
51f83fbb
DB		 2582 qup_uart3_default_state: qup-uart3-default-state {
2583 rx-pins {
2584 pins = "gpio18";
2585 function = "qup3";
2586 };
2587 tx-pins {
2588 pins = "gpio19";
2589 function = "qup3";
2590 };
2591 };
f5f6bd58 2592
51f83fbb
DB		 2593 qup_uart6_default: qup-uart6-default-state {
2594 pins = "gpio30", "gpio31";
2595 function = "qup6";
2596 drive-strength = <2>;
2597 bias-disable;
2598 };
f5f6bd58 2599
51f83fbb
DB		 2600 qup_uart18_default: qup-uart18-default-state {
2601 pins = "gpio58", "gpio59";
2602 function = "qup18";
2603 drive-strength = <2>;
2604 bias-disable;
2605 };
f5f6bd58 2606
51f83fbb
DB		 2607 qup_i2c0_default: qup-i2c0-default-state {
2608 pins = "gpio4", "gpio5";
2609 function = "qup0";
2610 drive-strength = <2>;
2611 bias-pull-up;
2612 };
f5f6bd58 2613
51f83fbb
DB		 2614 qup_i2c1_default: qup-i2c1-default-state {
2615 pins = "gpio8", "gpio9";
2616 function = "qup1";
2617 drive-strength = <2>;
2618 bias-pull-up;
2619 };
f5f6bd58 2620
51f83fbb
DB		 2621 qup_i2c2_default: qup-i2c2-default-state {
2622 pins = "gpio12", "gpio13";
2623 function = "qup2";
2624 drive-strength = <2>;
2625 bias-pull-up;
2626 };
f5f6bd58 2627
51f83fbb
DB		 2628 qup_i2c4_default: qup-i2c4-default-state {
2629 pins = "gpio20", "gpio21";
2630 function = "qup4";
2631 drive-strength = <2>;
2632 bias-pull-up;
2633 };
f5f6bd58 2634
51f83fbb
DB		 2635 qup_i2c5_default: qup-i2c5-default-state {
2636 pins = "gpio24", "gpio25";
2637 function = "qup5";
2638 drive-strength = <2>;
2639 bias-pull-up;
2640 };
f5f6bd58 2641
51f83fbb
DB		 2642 qup_i2c6_default: qup-i2c6-default-state {
2643 pins = "gpio28", "gpio29";
2644 function = "qup6";
2645 drive-strength = <2>;
2646 bias-pull-up;
2647 };
f5f6bd58 2648
51f83fbb
DB		 2649 qup_i2c7_default: qup-i2c7-default-state {
2650 pins = "gpio32", "gpio33";
2651 function = "qup7";
2652 drive-strength = <2>;
2653 bias-disable;
2654 };
f5f6bd58 2655
51f83fbb
DB		 2656 qup_i2c8_default: qup-i2c8-default-state {
2657 pins = "gpio36", "gpio37";
2658 function = "qup8";
2659 drive-strength = <2>;
2660 bias-pull-up;
2661 };
f5f6bd58 2662
51f83fbb
DB		 2663 qup_i2c9_default: qup-i2c9-default-state {
2664 pins = "gpio40", "gpio41";
2665 function = "qup9";
2666 drive-strength = <2>;
2667 bias-pull-up;
2668 };
f5f6bd58 2669
51f83fbb
DB		 2670 qup_i2c10_default: qup-i2c10-default-state {
2671 pins = "gpio44", "gpio45";
2672 function = "qup10";
2673 drive-strength = <2>;
2674 bias-pull-up;
2675 };
f5f6bd58 2676
51f83fbb
DB		 2677 qup_i2c11_default: qup-i2c11-default-state {
2678 pins = "gpio48", "gpio49";
2679 function = "qup11";
2680 drive-strength = <2>;
2681 bias-pull-up;
2682 };
f5f6bd58 2683
51f83fbb
DB		 2684 qup_i2c12_default: qup-i2c12-default-state {
2685 pins = "gpio52", "gpio53";
2686 function = "qup12";
2687 drive-strength = <2>;
2688 bias-pull-up;
f5f6bd58
DB		 2689 };
2690
51f83fbb
DB		 2691 qup_i2c13_default: qup-i2c13-default-state {
2692 pins = "gpio0", "gpio1";
2693 function = "qup13";
2694 drive-strength = <2>;
2695 bias-pull-up;
2696 };
f5f6bd58 2697
51f83fbb
DB		 2698 qup_i2c14_default: qup-i2c14-default-state {
2699 pins = "gpio56", "gpio57";
2700 function = "qup14";
2701 drive-strength = <2>;
2702 bias-disable;
2703 };
f5f6bd58 2704
51f83fbb
DB		 2705 qup_i2c15_default: qup-i2c15-default-state {
2706 pins = "gpio60", "gpio61";
2707 function = "qup15";
2708 drive-strength = <2>;
2709 bias-disable;
2710 };
f5f6bd58 2711
51f83fbb
DB		 2712 qup_i2c16_default: qup-i2c16-default-state {
2713 pins = "gpio64", "gpio65";
2714 function = "qup16";
2715 drive-strength = <2>;
2716 bias-disable;
f5f6bd58 2717 };
f5f6bd58 2718
51f83fbb
DB		 2719 qup_i2c17_default: qup-i2c17-default-state {
2720 pins = "gpio72", "gpio73";
2721 function = "qup17";
2722 drive-strength = <2>;
2723 bias-disable;
2724 };
f5f6bd58 2725
51f83fbb
DB		 2726 qup_i2c19_default: qup-i2c19-default-state {
2727 pins = "gpio76", "gpio77";
2728 function = "qup19";
2729 drive-strength = <2>;
2730 bias-disable;
2731 };
f5f6bd58
DB		 2732 };
2733
2734 apps_smmu: iommu@15000000 {
2735 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
2736 reg = <0 0x15000000 0 0x100000>;
2737 #iommu-cells = <2>;
2738 #global-interrupts = <2>;
2739 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2740 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2741 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2742 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2743 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2744 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2745 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2746 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2747 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2748 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2749 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2750 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2751 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2752 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2753 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2754 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2755 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2756 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2757 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2758 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2759 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2760 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2761 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2762 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2763 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2764 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2765 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2766 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2767 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2768 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2769 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2770 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2771 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2772 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2773 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2774 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2775 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2776 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2777 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2778 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2779 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2780 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2781 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2782 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2783 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2784 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2785 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2786 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2787 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2788 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2789 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2790 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2791 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2792 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2793 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2794 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2795 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2796 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2797 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2798 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2799 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2800 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2801 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2802 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2803 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2804 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2805 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2806 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2807 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2808 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2809 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2810 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2811 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2813 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2814 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2815 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2816 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2817 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2818 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2819 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2820 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2821 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2822 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2823 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2824 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2825 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2826 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2827 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2828 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2829 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2830 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2831 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2832 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2833 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2834 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2835 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
2836 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
2837 };
2838
2839 adsp: remoteproc@17300000 {
2840 compatible = "qcom,sm8350-adsp-pas";
2841 reg = <0 0x17300000 0 0x100>;
2842
2843 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2844 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2845 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2846 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2847 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2848 interrupt-names = "wdog", "fatal", "ready",
2849 "handover", "stop-ack";
2850
2851 clocks = <&rpmhcc RPMH_CXO_CLK>;
2852 clock-names = "xo";
2853
2854 power-domains = <&rpmhpd SM8350_LCX>,
2855 <&rpmhpd SM8350_LMX>;
2856 power-domain-names = "lcx", "lmx";
2857
2858 memory-region = <&pil_adsp_mem>;
2859
2860 qcom,qmp = <&aoss_qmp>;
2861
2862 qcom,smem-states = <&smp2p_adsp_out 0>;
2863 qcom,smem-state-names = "stop";
2864
2865 status = "disabled";
2866
2867 glink-edge {
2868 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2869 IPCC_MPROC_SIGNAL_GLINK_QMP
2870 IRQ_TYPE_EDGE_RISING>;
2871 mboxes = <&ipcc IPCC_CLIENT_LPASS
2872 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2873
2874 label = "lpass";
2875 qcom,remote-pid = <2>;
2876
2877 fastrpc {
2878 compatible = "qcom,fastrpc";
2879 qcom,glink-channels = "fastrpcglink-apps-dsp";
2880 label = "adsp";
2881 qcom,non-secure-domain;
2882 #address-cells = <1>;
2883 #size-cells = <0>;
2884
2885 compute-cb@3 {
2886 compatible = "qcom,fastrpc-compute-cb";
2887 reg = <3>;
2888 iommus = <&apps_smmu 0x1803 0x0>;
2889 };
2890
2891 compute-cb@4 {
2892 compatible = "qcom,fastrpc-compute-cb";
2893 reg = <4>;
2894 iommus = <&apps_smmu 0x1804 0x0>;
2895 };
2896
2897 compute-cb@5 {
2898 compatible = "qcom,fastrpc-compute-cb";
2899 reg = <5>;
2900 iommus = <&apps_smmu 0x1805 0x0>;
2901 };
2902 };
2903 };
2904 };
2905
2906 intc: interrupt-controller@17a00000 {
2907 compatible = "arm,gic-v3";
2908 #interrupt-cells = <3>;
2909 interrupt-controller;
2910 #redistributor-regions = <1>;
2911 redistributor-stride = <0 0x20000>;
2912 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2913 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2914 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2915 };
2916
2917 timer@17c20000 {
2918 compatible = "arm,armv7-timer-mem";
2919 #address-cells = <1>;
2920 #size-cells = <1>;
2921 ranges = <0 0 0 0x20000000>;
2922 reg = <0x0 0x17c20000 0x0 0x1000>;
2923 clock-frequency = <19200000>;
2924
2925 frame@17c21000 {
2926 frame-number = <0>;
2927 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2928 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2929 reg = <0x17c21000 0x1000>,
2930 <0x17c22000 0x1000>;
2931 };
2932
2933 frame@17c23000 {
2934 frame-number = <1>;
2935 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2936 reg = <0x17c23000 0x1000>;
2937 status = "disabled";
2938 };
2939
2940 frame@17c25000 {
2941 frame-number = <2>;
2942 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2943 reg = <0x17c25000 0x1000>;
2944 status = "disabled";
2945 };
2946
2947 frame@17c27000 {
2948 frame-number = <3>;
2949 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2950 reg = <0x17c27000 0x1000>;
2951 status = "disabled";
2952 };
2953
2954 frame@17c29000 {
2955 frame-number = <4>;
2956 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2957 reg = <0x17c29000 0x1000>;
2958 status = "disabled";
2959 };
2960
2961 frame@17c2b000 {
2962 frame-number = <5>;
2963 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2964 reg = <0x17c2b000 0x1000>;
2965 status = "disabled";
2966 };
2967
2968 frame@17c2d000 {
2969 frame-number = <6>;
2970 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2971 reg = <0x17c2d000 0x1000>;
2972 status = "disabled";
2973 };
2974 };
d4a44105 2975
f5f6bd58
DB		 2976 apps_rsc: rsc@18200000 {
2977 label = "apps_rsc";
2978 compatible = "qcom,rpmh-rsc";
2979 reg = <0x0 0x18200000 0x0 0x10000>,
2980 <0x0 0x18210000 0x0 0x10000>,
2981 <0x0 0x18220000 0x0 0x10000>;
2982 reg-names = "drv-0", "drv-1", "drv-2";
2983 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2984 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2985 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2986 qcom,tcs-offset = <0xd00>;
2987 qcom,drv-id = <2>;
2988 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2989 <WAKE_TCS 3>, <CONTROL_TCS 0>;
2990 power-domains = <&CLUSTER_PD>;
d4a44105 2991
f5f6bd58
DB		 2992 rpmhcc: clock-controller {
2993 compatible = "qcom,sm8350-rpmh-clk";
2994 #clock-cells = <1>;
2995 clock-names = "xo";
2996 clocks = <&xo_board>;
2997 };
d4a44105 2998
f5f6bd58
DB		 2999 rpmhpd: power-controller {
3000 compatible = "qcom,sm8350-rpmhpd";
3001 #power-domain-cells = <1>;
3002 operating-points-v2 = <&rpmhpd_opp_table>;
d4a44105 3003
f5f6bd58
DB		 3004 rpmhpd_opp_table: opp-table {
3005 compatible = "operating-points-v2";
d4a44105 3006
f5f6bd58
DB		 3007 rpmhpd_opp_ret: opp1 {
3008 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3009 };
d4a44105 3010
f5f6bd58
DB		 3011 rpmhpd_opp_min_svs: opp2 {
3012 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3013 };
6636818e 3014
f5f6bd58
DB		 3015 rpmhpd_opp_low_svs: opp3 {
3016 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3017 };
d4a44105 3018
f5f6bd58
DB		 3019 rpmhpd_opp_svs: opp4 {
3020 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3021 };
d4a44105 3022
f5f6bd58
DB		 3023 rpmhpd_opp_svs_l1: opp5 {
3024 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
d4a44105
RF		 3025 };
3026
f5f6bd58
DB		 3027 rpmhpd_opp_nom: opp6 {
3028 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
d4a44105
RF		 3029 };
3030
f5f6bd58
DB		 3031 rpmhpd_opp_nom_l1: opp7 {
3032 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
d4a44105 3033 };
d4a44105 3034
f5f6bd58
DB		 3035 rpmhpd_opp_nom_l2: opp8 {
3036 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3037 };
d4a44105 3038
f5f6bd58
DB		 3039 rpmhpd_opp_turbo: opp9 {
3040 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
d4a44105
RF		 3041 };
3042
f5f6bd58
DB		 3043 rpmhpd_opp_turbo_l1: opp10 {
3044 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
d4a44105
RF		 3045 };
3046 };
3047 };
3048
f5f6bd58
DB		 3049 apps_bcm_voter: bcm-voter {
3050 compatible = "qcom,bcm-voter";
d4a44105
RF		 3051 };
3052 };
3053
f5f6bd58
DB		 3054 cpufreq_hw: cpufreq@18591000 {
3055 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3056 reg = <0 0x18591000 0 0x1000>,
3057 <0 0x18592000 0 0x1000>,
3058 <0 0x18593000 0 0x1000>;
3059 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
9fd4887c 3060
f5f6bd58
DB		 3061 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3062 clock-names = "xo", "alternate";
3063
3064 #freq-domain-cells = <1>;
9fd4887c
RF		 3065 };
3066
f5f6bd58
DB		 3067 cdsp: remoteproc@98900000 {
3068 compatible = "qcom,sm8350-cdsp-pas";
3069 reg = <0 0x98900000 0 0x1400000>;
177fcf0a 3070
f5f6bd58
DB		 3071 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3072 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3073 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3074 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3075 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
177fcf0a
VK		 3076 interrupt-names = "wdog", "fatal", "ready",
3077 "handover", "stop-ack";
3078
3079 clocks = <&rpmhcc RPMH_CXO_CLK>;
3080 clock-names = "xo";
3081
f5f6bd58
DB		 3082 power-domains = <&rpmhpd SM8350_CX>,
3083 <&rpmhpd SM8350_MXC>;
3084 power-domain-names = "cx", "mxc";
177fcf0a 3085
f5f6bd58
DB		 3086 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3087
3088 memory-region = <&pil_cdsp_mem>;
177fcf0a 3089
6b7cb2d2
SS		 3090 qcom,qmp = <&aoss_qmp>;
3091
f5f6bd58 3092 qcom,smem-states = <&smp2p_cdsp_out 0>;
177fcf0a
VK		 3093 qcom,smem-state-names = "stop";
3094
3095 status = "disabled";
3096
3097 glink-edge {
f5f6bd58 3098 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
177fcf0a
VK		 3099 IPCC_MPROC_SIGNAL_GLINK_QMP
3100 IRQ_TYPE_EDGE_RISING>;
f5f6bd58 3101 mboxes = <&ipcc IPCC_CLIENT_CDSP
177fcf0a
VK		 3102 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3103
f5f6bd58
DB		 3104 label = "cdsp";
3105 qcom,remote-pid = <5>;
178056a4
OJ		 3106
3107 fastrpc {
3108 compatible = "qcom,fastrpc";
3109 qcom,glink-channels = "fastrpcglink-apps-dsp";
f5f6bd58 3110 label = "cdsp";
8c8ce95b 3111 qcom,non-secure-domain;
178056a4
OJ		 3112 #address-cells = <1>;
3113 #size-cells = <0>;
3114
f5f6bd58
DB		 3115 compute-cb@1 {
3116 compatible = "qcom,fastrpc-compute-cb";
3117 reg = <1>;
3118 iommus = <&apps_smmu 0x2161 0x0400>,
3119 <&apps_smmu 0x1181 0x0420>;
3120 };
3121
3122 compute-cb@2 {
3123 compatible = "qcom,fastrpc-compute-cb";
3124 reg = <2>;
3125 iommus = <&apps_smmu 0x2162 0x0400>,
3126 <&apps_smmu 0x1182 0x0420>;
3127 };
3128
178056a4
OJ		 3129 compute-cb@3 {
3130 compatible = "qcom,fastrpc-compute-cb";
3131 reg = <3>;
f5f6bd58
DB		 3132 iommus = <&apps_smmu 0x2163 0x0400>,
3133 <&apps_smmu 0x1183 0x0420>;
178056a4
OJ		 3134 };
3135
3136 compute-cb@4 {
3137 compatible = "qcom,fastrpc-compute-cb";
3138 reg = <4>;
f5f6bd58
DB		 3139 iommus = <&apps_smmu 0x2164 0x0400>,
3140 <&apps_smmu 0x1184 0x0420>;
178056a4
OJ		 3141 };
3142
3143 compute-cb@5 {
3144 compatible = "qcom,fastrpc-compute-cb";
3145 reg = <5>;
f5f6bd58
DB		 3146 iommus = <&apps_smmu 0x2165 0x0400>,
3147 <&apps_smmu 0x1185 0x0420>;
3148 };
3149
3150 compute-cb@6 {
3151 compatible = "qcom,fastrpc-compute-cb";
3152 reg = <6>;
3153 iommus = <&apps_smmu 0x2166 0x0400>,
3154 <&apps_smmu 0x1186 0x0420>;
178056a4 3155 };
f5f6bd58
DB		 3156
3157 compute-cb@7 {
3158 compatible = "qcom,fastrpc-compute-cb";
3159 reg = <7>;
3160 iommus = <&apps_smmu 0x2167 0x0400>,
3161 <&apps_smmu 0x1187 0x0420>;
3162 };
3163
3164 compute-cb@8 {
3165 compatible = "qcom,fastrpc-compute-cb";
3166 reg = <8>;
3167 iommus = <&apps_smmu 0x2168 0x0400>,
3168 <&apps_smmu 0x1188 0x0420>;
3169 };
3170
3171 /* note: secure cb9 in downstream */
178056a4 3172 };
177fcf0a
VK		 3173 };
3174 };
b7e8f433
VK		 3175 };
3176
4dcaa68e 3177 thermal_zones: thermal-zones {
20f9d94e
RF		 3178 cpu0-thermal {
3179 polling-delay-passive = <250>;
3180 polling-delay = <1000>;
3181
3182 thermal-sensors = <&tsens0 1>;
3183
3184 trips {
3185 cpu0_alert0: trip-point0 {
3186 temperature = <90000>;
3187 hysteresis = <2000>;
3188 type = "passive";
3189 };
3190
3191 cpu0_alert1: trip-point1 {
3192 temperature = <95000>;
3193 hysteresis = <2000>;
3194 type = "passive";
3195 };
3196
1364acc3 3197 cpu0_crit: cpu-crit {
20f9d94e
RF		 3198 temperature = <110000>;
3199 hysteresis = <1000>;
3200 type = "critical";
3201 };
3202 };
3203
3204 cooling-maps {
3205 map0 {
3206 trip = <&cpu0_alert0>;
3207 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3208 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3209 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3210 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3211 };
3212 map1 {
3213 trip = <&cpu0_alert1>;
3214 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3215 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3216 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3217 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3218 };
3219 };
3220 };
3221
3222 cpu1-thermal {
3223 polling-delay-passive = <250>;
3224 polling-delay = <1000>;
3225
3226 thermal-sensors = <&tsens0 2>;
3227
3228 trips {
3229 cpu1_alert0: trip-point0 {
3230 temperature = <90000>;
3231 hysteresis = <2000>;
3232 type = "passive";
3233 };
3234
3235 cpu1_alert1: trip-point1 {
3236 temperature = <95000>;
3237 hysteresis = <2000>;
3238 type = "passive";
3239 };
3240
1364acc3 3241 cpu1_crit: cpu-crit {
20f9d94e
RF		 3242 temperature = <110000>;
3243 hysteresis = <1000>;
3244 type = "critical";
3245 };
3246 };
3247
3248 cooling-maps {
3249 map0 {
3250 trip = <&cpu1_alert0>;
3251 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3252 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3253 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3254 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3255 };
3256 map1 {
3257 trip = <&cpu1_alert1>;
3258 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3259 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3260 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3261 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3262 };
3263 };
3264 };
3265
3266 cpu2-thermal {
3267 polling-delay-passive = <250>;
3268 polling-delay = <1000>;
3269
3270 thermal-sensors = <&tsens0 3>;
3271
3272 trips {
3273 cpu2_alert0: trip-point0 {
3274 temperature = <90000>;
3275 hysteresis = <2000>;
3276 type = "passive";
3277 };
3278
3279 cpu2_alert1: trip-point1 {
3280 temperature = <95000>;
3281 hysteresis = <2000>;
3282 type = "passive";
3283 };
3284
1364acc3 3285 cpu2_crit: cpu-crit {
20f9d94e
RF		 3286 temperature = <110000>;
3287 hysteresis = <1000>;
3288 type = "critical";
3289 };
3290 };
3291
3292 cooling-maps {
3293 map0 {
3294 trip = <&cpu2_alert0>;
3295 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3296 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3297 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3298 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3299 };
3300 map1 {
3301 trip = <&cpu2_alert1>;
3302 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3303 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3304 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3305 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3306 };
3307 };
3308 };
3309
3310 cpu3-thermal {
3311 polling-delay-passive = <250>;
3312 polling-delay = <1000>;
3313
3314 thermal-sensors = <&tsens0 4>;
3315
3316 trips {
3317 cpu3_alert0: trip-point0 {
3318 temperature = <90000>;
3319 hysteresis = <2000>;
3320 type = "passive";
3321 };
3322
3323 cpu3_alert1: trip-point1 {
3324 temperature = <95000>;
3325 hysteresis = <2000>;
3326 type = "passive";
3327 };
3328
1364acc3 3329 cpu3_crit: cpu-crit {
20f9d94e
RF		 3330 temperature = <110000>;
3331 hysteresis = <1000>;
3332 type = "critical";
3333 };
3334 };
3335
3336 cooling-maps {
3337 map0 {
3338 trip = <&cpu3_alert0>;
3339 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3340 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3341 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3342 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3343 };
3344 map1 {
3345 trip = <&cpu3_alert1>;
3346 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3347 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3348 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3349 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3350 };
3351 };
3352 };
3353
3354 cpu4-top-thermal {
3355 polling-delay-passive = <250>;
3356 polling-delay = <1000>;
3357
3358 thermal-sensors = <&tsens0 7>;
3359
3360 trips {
3361 cpu4_top_alert0: trip-point0 {
3362 temperature = <90000>;
3363 hysteresis = <2000>;
3364 type = "passive";
3365 };
3366
3367 cpu4_top_alert1: trip-point1 {
3368 temperature = <95000>;
3369 hysteresis = <2000>;
3370 type = "passive";
3371 };
3372
1364acc3 3373 cpu4_top_crit: cpu-crit {
20f9d94e
RF		 3374 temperature = <110000>;
3375 hysteresis = <1000>;
3376 type = "critical";
3377 };
3378 };
3379
3380 cooling-maps {
3381 map0 {
3382 trip = <&cpu4_top_alert0>;
3383 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3384 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3385 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3386 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3387 };
3388 map1 {
3389 trip = <&cpu4_top_alert1>;
3390 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3391 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3392 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3393 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3394 };
3395 };
3396 };
3397
3398 cpu5-top-thermal {
3399 polling-delay-passive = <250>;
3400 polling-delay = <1000>;
3401
3402 thermal-sensors = <&tsens0 8>;
3403
3404 trips {
3405 cpu5_top_alert0: trip-point0 {
3406 temperature = <90000>;
3407 hysteresis = <2000>;
3408 type = "passive";
3409 };
3410
3411 cpu5_top_alert1: trip-point1 {
3412 temperature = <95000>;
3413 hysteresis = <2000>;
3414 type = "passive";
3415 };
3416
1364acc3 3417 cpu5_top_crit: cpu-crit {
20f9d94e
RF		 3418 temperature = <110000>;
3419 hysteresis = <1000>;
3420 type = "critical";
3421 };
3422 };
3423
3424 cooling-maps {
3425 map0 {
3426 trip = <&cpu5_top_alert0>;
3427 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3428 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3429 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3430 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3431 };
3432 map1 {
3433 trip = <&cpu5_top_alert1>;
3434 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3435 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3436 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3437 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3438 };
3439 };
3440 };
3441
3442 cpu6-top-thermal {
3443 polling-delay-passive = <250>;
3444 polling-delay = <1000>;
3445
3446 thermal-sensors = <&tsens0 9>;
3447
3448 trips {
3449 cpu6_top_alert0: trip-point0 {
3450 temperature = <90000>;
3451 hysteresis = <2000>;
3452 type = "passive";
3453 };
3454
3455 cpu6_top_alert1: trip-point1 {
3456 temperature = <95000>;
3457 hysteresis = <2000>;
3458 type = "passive";
3459 };
3460
1364acc3 3461 cpu6_top_crit: cpu-crit {
20f9d94e
RF		 3462 temperature = <110000>;
3463 hysteresis = <1000>;
3464 type = "critical";
3465 };
3466 };
3467
3468 cooling-maps {
3469 map0 {
3470 trip = <&cpu6_top_alert0>;
3471 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3472 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3473 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3474 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3475 };
3476 map1 {
3477 trip = <&cpu6_top_alert1>;
3478 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3479 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3480 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3481 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3482 };
3483 };
3484 };
3485
3486 cpu7-top-thermal {
3487 polling-delay-passive = <250>;
3488 polling-delay = <1000>;
3489
3490 thermal-sensors = <&tsens0 10>;
3491
3492 trips {
3493 cpu7_top_alert0: trip-point0 {
3494 temperature = <90000>;
3495 hysteresis = <2000>;
3496 type = "passive";
3497 };
3498
3499 cpu7_top_alert1: trip-point1 {
3500 temperature = <95000>;
3501 hysteresis = <2000>;
3502 type = "passive";
3503 };
3504
1364acc3 3505 cpu7_top_crit: cpu-crit {
20f9d94e
RF		 3506 temperature = <110000>;
3507 hysteresis = <1000>;
3508 type = "critical";
3509 };
3510 };
3511
3512 cooling-maps {
3513 map0 {
3514 trip = <&cpu7_top_alert0>;
3515 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3516 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3517 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3518 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3519 };
3520 map1 {
3521 trip = <&cpu7_top_alert1>;
3522 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3523 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3524 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3525 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3526 };
3527 };
3528 };
3529
3530 cpu4-bottom-thermal {
3531 polling-delay-passive = <250>;
3532 polling-delay = <1000>;
3533
3534 thermal-sensors = <&tsens0 11>;
3535
3536 trips {
3537 cpu4_bottom_alert0: trip-point0 {
3538 temperature = <90000>;
3539 hysteresis = <2000>;
3540 type = "passive";
3541 };
3542
3543 cpu4_bottom_alert1: trip-point1 {
3544 temperature = <95000>;
3545 hysteresis = <2000>;
3546 type = "passive";
3547 };
3548
1364acc3 3549 cpu4_bottom_crit: cpu-crit {
20f9d94e
RF		 3550 temperature = <110000>;
3551 hysteresis = <1000>;
3552 type = "critical";
3553 };
3554 };
3555
3556 cooling-maps {
3557 map0 {
3558 trip = <&cpu4_bottom_alert0>;
3559 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3560 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3561 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3562 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3563 };
3564 map1 {
3565 trip = <&cpu4_bottom_alert1>;
3566 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3567 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3568 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3569 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3570 };
3571 };
3572 };
3573
3574 cpu5-bottom-thermal {
3575 polling-delay-passive = <250>;
3576 polling-delay = <1000>;
3577
3578 thermal-sensors = <&tsens0 12>;
3579
3580 trips {
3581 cpu5_bottom_alert0: trip-point0 {
3582 temperature = <90000>;
3583 hysteresis = <2000>;
3584 type = "passive";
3585 };
3586
3587 cpu5_bottom_alert1: trip-point1 {
3588 temperature = <95000>;
3589 hysteresis = <2000>;
3590 type = "passive";
3591 };
3592
1364acc3 3593 cpu5_bottom_crit: cpu-crit {
20f9d94e
RF		 3594 temperature = <110000>;
3595 hysteresis = <1000>;
3596 type = "critical";
3597 };
3598 };
3599
3600 cooling-maps {
3601 map0 {
3602 trip = <&cpu5_bottom_alert0>;
3603 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3604 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3605 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3606 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3607 };
3608 map1 {
3609 trip = <&cpu5_bottom_alert1>;
3610 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3611 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3612 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3613 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3614 };
3615 };
3616 };
3617
3618 cpu6-bottom-thermal {
3619 polling-delay-passive = <250>;
3620 polling-delay = <1000>;
3621
3622 thermal-sensors = <&tsens0 13>;
3623
3624 trips {
3625 cpu6_bottom_alert0: trip-point0 {
3626 temperature = <90000>;
3627 hysteresis = <2000>;
3628 type = "passive";
3629 };
3630
3631 cpu6_bottom_alert1: trip-point1 {
3632 temperature = <95000>;
3633 hysteresis = <2000>;
3634 type = "passive";
3635 };
3636
1364acc3 3637 cpu6_bottom_crit: cpu-crit {
20f9d94e
RF		 3638 temperature = <110000>;
3639 hysteresis = <1000>;
3640 type = "critical";
3641 };
3642 };
3643
3644 cooling-maps {
3645 map0 {
3646 trip = <&cpu6_bottom_alert0>;
3647 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3648 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3649 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3650 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3651 };
3652 map1 {
3653 trip = <&cpu6_bottom_alert1>;
3654 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3655 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3656 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3658 };
3659 };
3660 };
3661
3662 cpu7-bottom-thermal {
3663 polling-delay-passive = <250>;
3664 polling-delay = <1000>;
3665
3666 thermal-sensors = <&tsens0 14>;
3667
3668 trips {
3669 cpu7_bottom_alert0: trip-point0 {
3670 temperature = <90000>;
3671 hysteresis = <2000>;
3672 type = "passive";
3673 };
3674
3675 cpu7_bottom_alert1: trip-point1 {
3676 temperature = <95000>;
3677 hysteresis = <2000>;
3678 type = "passive";
3679 };
3680
1364acc3 3681 cpu7_bottom_crit: cpu-crit {
20f9d94e
RF		 3682 temperature = <110000>;
3683 hysteresis = <1000>;
3684 type = "critical";
3685 };
3686 };
3687
3688 cooling-maps {
3689 map0 {
3690 trip = <&cpu7_bottom_alert0>;
3691 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3692 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3693 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3694 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3695 };
3696 map1 {
3697 trip = <&cpu7_bottom_alert1>;
3698 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3699 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3700 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3701 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3702 };
3703 };
3704 };
3705
3706 aoss0-thermal {
3707 polling-delay-passive = <250>;
3708 polling-delay = <1000>;
3709
3710 thermal-sensors = <&tsens0 0>;
3711
3712 trips {
3713 aoss0_alert0: trip-point0 {
3714 temperature = <90000>;
3715 hysteresis = <2000>;
3716 type = "hot";
3717 };
3718 };
3719 };
3720
3721 cluster0-thermal {
3722 polling-delay-passive = <250>;
3723 polling-delay = <1000>;
3724
3725 thermal-sensors = <&tsens0 5>;
3726
3727 trips {
3728 cluster0_alert0: trip-point0 {
3729 temperature = <90000>;
3730 hysteresis = <2000>;
3731 type = "hot";
3732 };
3733 cluster0_crit: cluster0_crit {
3734 temperature = <110000>;
3735 hysteresis = <2000>;
3736 type = "critical";
3737 };
3738 };
3739 };
3740
3741 cluster1-thermal {
3742 polling-delay-passive = <250>;
3743 polling-delay = <1000>;
3744
3745 thermal-sensors = <&tsens0 6>;
3746
3747 trips {
3748 cluster1_alert0: trip-point0 {
3749 temperature = <90000>;
3750 hysteresis = <2000>;
3751 type = "hot";
3752 };
3753 cluster1_crit: cluster1_crit {
3754 temperature = <110000>;
3755 hysteresis = <2000>;
3756 type = "critical";
3757 };
3758 };
3759 };
3760
3761 aoss1-thermal {
3762 polling-delay-passive = <250>;
3763 polling-delay = <1000>;
3764
3765 thermal-sensors = <&tsens1 0>;
3766
3767 trips {
3768 aoss1_alert0: trip-point0 {
3769 temperature = <90000>;
3770 hysteresis = <2000>;
3771 type = "hot";
3772 };
3773 };
3774 };
3775
7be1c395 3776 gpu-top-thermal {
20f9d94e
RF		 3777 polling-delay-passive = <250>;
3778 polling-delay = <1000>;
3779
3780 thermal-sensors = <&tsens1 1>;
3781
3782 trips {
3783 gpu1_alert0: trip-point0 {
3784 temperature = <90000>;
3785 hysteresis = <1000>;
3786 type = "hot";
3787 };
3788 };
3789 };
3790
7be1c395 3791 gpu-bottom-thermal {
20f9d94e
RF		 3792 polling-delay-passive = <250>;
3793 polling-delay = <1000>;
3794
3795 thermal-sensors = <&tsens1 2>;
3796
3797 trips {
3798 gpu2_alert0: trip-point0 {
3799 temperature = <90000>;
3800 hysteresis = <1000>;
3801 type = "hot";
3802 };
3803 };
3804 };
3805
3806 nspss1-thermal {
3807 polling-delay-passive = <250>;
3808 polling-delay = <1000>;
3809
3810 thermal-sensors = <&tsens1 3>;
3811
3812 trips {
3813 nspss1_alert0: trip-point0 {
3814 temperature = <90000>;
3815 hysteresis = <1000>;
3816 type = "hot";
3817 };
3818 };
3819 };
3820
3821 nspss2-thermal {
3822 polling-delay-passive = <250>;
3823 polling-delay = <1000>;
3824
3825 thermal-sensors = <&tsens1 4>;
3826
3827 trips {
3828 nspss2_alert0: trip-point0 {
3829 temperature = <90000>;
3830 hysteresis = <1000>;
3831 type = "hot";
3832 };
3833 };
3834 };
3835
3836 nspss3-thermal {
3837 polling-delay-passive = <250>;
3838 polling-delay = <1000>;
3839
3840 thermal-sensors = <&tsens1 5>;
3841
3842 trips {
3843 nspss3_alert0: trip-point0 {
3844 temperature = <90000>;
3845 hysteresis = <1000>;
3846 type = "hot";
3847 };
3848 };
3849 };
3850
3851 video-thermal {
3852 polling-delay-passive = <250>;
3853 polling-delay = <1000>;
3854
3855 thermal-sensors = <&tsens1 6>;
3856
3857 trips {
3858 video_alert0: trip-point0 {
3859 temperature = <90000>;
3860 hysteresis = <2000>;
3861 type = "hot";
3862 };
3863 };
3864 };
3865
3866 mem-thermal {
3867 polling-delay-passive = <250>;
3868 polling-delay = <1000>;
3869
3870 thermal-sensors = <&tsens1 7>;
3871
3872 trips {
3873 mem_alert0: trip-point0 {
3874 temperature = <90000>;
3875 hysteresis = <2000>;
3876 type = "hot";
3877 };
3878 };
3879 };
3880
7be1c395 3881 modem1-top-thermal {
20f9d94e
RF		 3882 polling-delay-passive = <250>;
3883 polling-delay = <1000>;
3884
3885 thermal-sensors = <&tsens1 8>;
3886
3887 trips {
3888 modem1_alert0: trip-point0 {
3889 temperature = <90000>;
3890 hysteresis = <2000>;
3891 type = "hot";
3892 };
3893 };
3894 };
3895
7be1c395 3896 modem2-top-thermal {
20f9d94e
RF		 3897 polling-delay-passive = <250>;
3898 polling-delay = <1000>;
3899
3900 thermal-sensors = <&tsens1 9>;
3901
3902 trips {
3903 modem2_alert0: trip-point0 {
3904 temperature = <90000>;
3905 hysteresis = <2000>;
3906 type = "hot";
3907 };
3908 };
3909 };
3910
7be1c395 3911 modem3-top-thermal {
20f9d94e
RF		 3912 polling-delay-passive = <250>;
3913 polling-delay = <1000>;
3914
3915 thermal-sensors = <&tsens1 10>;
3916
3917 trips {
3918 modem3_alert0: trip-point0 {
3919 temperature = <90000>;
3920 hysteresis = <2000>;
3921 type = "hot";
3922 };
3923 };
3924 };
3925
7be1c395 3926 modem4-top-thermal {
20f9d94e
RF		 3927 polling-delay-passive = <250>;
3928 polling-delay = <1000>;
3929
3930 thermal-sensors = <&tsens1 11>;
3931
3932 trips {
3933 modem4_alert0: trip-point0 {
3934 temperature = <90000>;
3935 hysteresis = <2000>;
3936 type = "hot";
3937 };
3938 };
3939 };
3940
7be1c395 3941 camera-top-thermal {
20f9d94e
RF		 3942 polling-delay-passive = <250>;
3943 polling-delay = <1000>;
3944
3945 thermal-sensors = <&tsens1 12>;
3946
3947 trips {
3948 camera1_alert0: trip-point0 {
3949 temperature = <90000>;
3950 hysteresis = <2000>;
3951 type = "hot";
3952 };
3953 };
3954 };
3955
7be1c395 3956 cam-bottom-thermal {
20f9d94e
RF		 3957 polling-delay-passive = <250>;
3958 polling-delay = <1000>;
3959
3960 thermal-sensors = <&tsens1 13>;
3961
3962 trips {
3963 camera2_alert0: trip-point0 {
3964 temperature = <90000>;
3965 hysteresis = <2000>;
3966 type = "hot";
3967 };
3968 };
3969 };
3970 };
3971
b7e8f433
VK		 3972 timer {
3973 compatible = "arm,armv8-timer";
3974 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3975 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3976 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3977 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3978 };
3979};
Linux 6.x block layer and io_uring tree(s)