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Merge tag 'for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux...
[linux-2.6-block.git] / arch / arm64 / boot / dts / qcom / sdm845.dtsi
CommitLineData
6d4cf750
RN		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SDM845 SoC device tree source
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */
7
07484de3 8#include <dt-bindings/clock/qcom,camcc-sdm845.h>
40019e84 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
897cf34e 10#include <dt-bindings/clock/qcom,gcc-sdm845.h>
9aa4a27e 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
ea0edd7e 12#include <dt-bindings/clock/qcom,lpass-sdm845.h>
717f2013 13#include <dt-bindings/clock/qcom,rpmh.h>
05556681 14#include <dt-bindings/clock/qcom,videocc-sdm845.h>
8f6e20ad 15#include <dt-bindings/dma/qcom-gpi.h>
dea1a788 16#include <dt-bindings/gpio/gpio.h>
54b50f21 17#include <dt-bindings/interconnect/qcom,osm-l3.h>
71f1fdd9 18#include <dt-bindings/interconnect/qcom,sdm845.h>
6d4cf750 19#include <dt-bindings/interrupt-controller/arm-gic.h>
ca4db2b5 20#include <dt-bindings/phy/phy-qcom-qusb2.h>
596a4343 21#include <dt-bindings/power/qcom-rpmpd.h>
ead5eea3 22#include <dt-bindings/reset/qcom,sdm845-aoss.h>
13393da0 23#include <dt-bindings/reset/qcom,sdm845-pdc.h>
3898fdc1 24#include <dt-bindings/soc/qcom,apr.h>
c83545d9 25#include <dt-bindings/soc/qcom,rpmh-rsc.h>
c47fc198
AK		 26#include <dt-bindings/clock/qcom,gcc-sdm845.h>
27#include <dt-bindings/thermal/thermal.h>
6d4cf750
RN		 28
29/ {
30 interrupt-parent = <&intc>;
31
32 #address-cells = <2>;
33 #size-cells = <2>;
34
897cf34e
DA		 35 aliases {
36 i2c0 = &i2c0;
37 i2c1 = &i2c1;
38 i2c2 = &i2c2;
39 i2c3 = &i2c3;
40 i2c4 = &i2c4;
41 i2c5 = &i2c5;
42 i2c6 = &i2c6;
43 i2c7 = &i2c7;
44 i2c8 = &i2c8;
45 i2c9 = &i2c9;
46 i2c10 = &i2c10;
47 i2c11 = &i2c11;
48 i2c12 = &i2c12;
49 i2c13 = &i2c13;
50 i2c14 = &i2c14;
51 i2c15 = &i2c15;
52 spi0 = &spi0;
53 spi1 = &spi1;
54 spi2 = &spi2;
55 spi3 = &spi3;
56 spi4 = &spi4;
57 spi5 = &spi5;
58 spi6 = &spi6;
59 spi7 = &spi7;
60 spi8 = &spi8;
61 spi9 = &spi9;
62 spi10 = &spi10;
63 spi11 = &spi11;
64 spi12 = &spi12;
65 spi13 = &spi13;
66 spi14 = &spi14;
67 spi15 = &spi15;
68 };
69
6d4cf750
RN		 70 chosen { };
71
72 memory@80000000 {
73 device_type = "memory";
74 /* We expect the bootloader to fill in the size */
75 reg = <0 0x80000000 0 0>;
76 };
77
71c8428e
S		 78 reserved-memory {
79 #address-cells = <2>;
80 #size-cells = <2>;
81 ranges;
82
63a4021f 83 hyp_mem: hyp-mem@85700000 {
a23b5378
BA		 84 reg = <0 0x85700000 0 0x600000>;
85 no-map;
86 };
87
63a4021f 88 xbl_mem: xbl-mem@85e00000 {
a23b5378
BA		 89 reg = <0 0x85e00000 0 0x100000>;
90 no-map;
91 };
92
63a4021f 93 aop_mem: aop-mem@85fc0000 {
71c8428e
S		 94 reg = <0 0x85fc0000 0 0x20000>;
95 no-map;
96 };
97
63a4021f 98 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
2da52398 99 compatible = "qcom,cmd-db";
a23b5378 100 reg = <0x0 0x85fe0000 0 0x20000>;
2da52398
DA		 101 no-map;
102 };
103
622adb84
BA		 104 smem@86000000 {
105 compatible = "qcom,smem";
a23b5378 106 reg = <0x0 0x86000000 0 0x200000>;
71c8428e 107 no-map;
622adb84 108 hwlocks = <&tcsr_mutex 3>;
71c8428e
S		 109 };
110
63a4021f 111 tz_mem: tz@86200000 {
71c8428e
S		 112 reg = <0 0x86200000 0 0x2d00000>;
113 no-map;
114 };
022bccb8 115
63a4021f 116 rmtfs_mem: rmtfs@88f00000 {
bdecbe6b
BA		 117 compatible = "qcom,rmtfs-mem";
118 reg = <0 0x88f00000 0 0x200000>;
119 no-map;
120
121 qcom,client-id = <1>;
122 qcom,vmid = <15>;
123 };
124
63a4021f 125 qseecom_mem: qseecom@8ab00000 {
a23b5378
BA		 126 reg = <0 0x8ab00000 0 0x1400000>;
127 no-map;
128 };
129
63a4021f 130 camera_mem: camera-mem@8bf00000 {
a23b5378
BA		 131 reg = <0 0x8bf00000 0 0x500000>;
132 no-map;
133 };
134
63a4021f 135 ipa_fw_mem: ipa-fw@8c400000 {
4420a0de 136 reg = <0 0x8c400000 0 0x10000>;
a23b5378
BA		 137 no-map;
138 };
139
63a4021f 140 ipa_gsi_mem: ipa-gsi@8c410000 {
4420a0de 141 reg = <0 0x8c410000 0 0x5000>;
a23b5378
BA		 142 no-map;
143 };
144
63a4021f 145 gpu_mem: gpu@8c415000 {
4420a0de 146 reg = <0 0x8c415000 0 0x2000>;
a23b5378
BA		 147 no-map;
148 };
149
63a4021f 150 adsp_mem: adsp@8c500000 {
4420a0de
AP		 151 reg = <0 0x8c500000 0 0x1a00000>;
152 no-map;
153 };
154
63a4021f 155 wlan_msa_mem: wlan-msa@8df00000 {
4420a0de 156 reg = <0 0x8df00000 0 0x100000>;
022bccb8
GS		 157 no-map;
158 };
8ed6d484 159
63a4021f 160 mpss_region: mpss@8e000000 {
8ed6d484
SS		 161 reg = <0 0x8e000000 0 0x7800000>;
162 no-map;
163 };
164
63a4021f 165 venus_mem: venus@95800000 {
a23b5378
BA		 166 reg = <0 0x95800000 0 0x500000>;
167 no-map;
168 };
169
63a4021f 170 cdsp_mem: cdsp@95d00000 {
a23b5378
BA		 171 reg = <0 0x95d00000 0 0x800000>;
172 no-map;
173 };
174
63a4021f 175 mba_region: mba@96500000 {
8ed6d484
SS		 176 reg = <0 0x96500000 0 0x200000>;
177 no-map;
178 };
a23b5378 179
63a4021f 180 slpi_mem: slpi@96700000 {
a23b5378
BA		 181 reg = <0 0x96700000 0 0x1400000>;
182 no-map;
183 };
184
63a4021f 185 spss_mem: spss@97b00000 {
a23b5378
BA		 186 reg = <0 0x97b00000 0 0x100000>;
187 no-map;
188 };
71c8428e
S		 189 };
190
6d4cf750
RN		 191 cpus {
192 #address-cells = <2>;
193 #size-cells = <0>;
194
195 CPU0: cpu@0 {
196 device_type = "cpu";
197 compatible = "qcom,kryo385";
198 reg = <0x0 0x0>;
199 enable-method = "psci";
9bbd0836
R		 200 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
201 &LITTLE_CPU_SLEEP_1
202 &CLUSTER_SLEEP_0>;
0e0a8e35
DB		 203 capacity-dmips-mhz = <611>;
204 dynamic-power-coefficient = <290>;
c604b82a 205 qcom,freq-domain = <&cpufreq_hw 0>;
54b50f21 206 operating-points-v2 = <&cpu0_opp_table>;
7901c2bc 207 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
54b50f21 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
c47fc198 209 #cooling-cells = <2>;
6d4cf750
RN		 210 next-level-cache = <&L2_0>;
211 L2_0: l2-cache {
212 compatible = "cache";
213 next-level-cache = <&L3_0>;
214 L3_0: l3-cache {
215 compatible = "cache";
216 };
217 };
218 };
219
220 CPU1: cpu@100 {
221 device_type = "cpu";
222 compatible = "qcom,kryo385";
223 reg = <0x0 0x100>;
224 enable-method = "psci";
9bbd0836
R		 225 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
226 &LITTLE_CPU_SLEEP_1
227 &CLUSTER_SLEEP_0>;
0e0a8e35
DB		 228 capacity-dmips-mhz = <611>;
229 dynamic-power-coefficient = <290>;
c604b82a 230 qcom,freq-domain = <&cpufreq_hw 0>;
54b50f21 231 operating-points-v2 = <&cpu0_opp_table>;
7901c2bc 232 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
54b50f21 233 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
c47fc198 234 #cooling-cells = <2>;
6d4cf750
RN		 235 next-level-cache = <&L2_100>;
236 L2_100: l2-cache {
237 compatible = "cache";
238 next-level-cache = <&L3_0>;
239 };
240 };
241
242 CPU2: cpu@200 {
243 device_type = "cpu";
244 compatible = "qcom,kryo385";
245 reg = <0x0 0x200>;
246 enable-method = "psci";
9bbd0836
R		 247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
248 &LITTLE_CPU_SLEEP_1
249 &CLUSTER_SLEEP_0>;
0e0a8e35
DB		 250 capacity-dmips-mhz = <611>;
251 dynamic-power-coefficient = <290>;
c604b82a 252 qcom,freq-domain = <&cpufreq_hw 0>;
54b50f21 253 operating-points-v2 = <&cpu0_opp_table>;
7901c2bc 254 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
54b50f21 255 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
c47fc198 256 #cooling-cells = <2>;
6d4cf750
RN		 257 next-level-cache = <&L2_200>;
258 L2_200: l2-cache {
259 compatible = "cache";
260 next-level-cache = <&L3_0>;
261 };
262 };
263
264 CPU3: cpu@300 {
265 device_type = "cpu";
266 compatible = "qcom,kryo385";
267 reg = <0x0 0x300>;
268 enable-method = "psci";
9bbd0836
R		 269 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
270 &LITTLE_CPU_SLEEP_1
271 &CLUSTER_SLEEP_0>;
0e0a8e35
DB		 272 capacity-dmips-mhz = <611>;
273 dynamic-power-coefficient = <290>;
c604b82a 274 qcom,freq-domain = <&cpufreq_hw 0>;
54b50f21 275 operating-points-v2 = <&cpu0_opp_table>;
7901c2bc 276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
54b50f21 277 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
c47fc198 278 #cooling-cells = <2>;
6d4cf750
RN		 279 next-level-cache = <&L2_300>;
280 L2_300: l2-cache {
281 compatible = "cache";
282 next-level-cache = <&L3_0>;
283 };
284 };
285
286 CPU4: cpu@400 {
287 device_type = "cpu";
288 compatible = "qcom,kryo385";
289 reg = <0x0 0x400>;
290 enable-method = "psci";
b6bc6423 291 capacity-dmips-mhz = <1024>;
9bbd0836
R		 292 cpu-idle-states = <&BIG_CPU_SLEEP_0
293 &BIG_CPU_SLEEP_1
294 &CLUSTER_SLEEP_0>;
0e0a8e35 295 dynamic-power-coefficient = <442>;
c604b82a 296 qcom,freq-domain = <&cpufreq_hw 1>;
54b50f21 297 operating-points-v2 = <&cpu4_opp_table>;
7901c2bc 298 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
54b50f21 299 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
c47fc198 300 #cooling-cells = <2>;
6d4cf750
RN		 301 next-level-cache = <&L2_400>;
302 L2_400: l2-cache {
303 compatible = "cache";
304 next-level-cache = <&L3_0>;
305 };
306 };
307
308 CPU5: cpu@500 {
309 device_type = "cpu";
310 compatible = "qcom,kryo385";
311 reg = <0x0 0x500>;
312 enable-method = "psci";
b6bc6423 313 capacity-dmips-mhz = <1024>;
9bbd0836
R		 314 cpu-idle-states = <&BIG_CPU_SLEEP_0
315 &BIG_CPU_SLEEP_1
316 &CLUSTER_SLEEP_0>;
0e0a8e35 317 dynamic-power-coefficient = <442>;
c604b82a 318 qcom,freq-domain = <&cpufreq_hw 1>;
54b50f21 319 operating-points-v2 = <&cpu4_opp_table>;
7901c2bc 320 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
54b50f21 321 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
c47fc198 322 #cooling-cells = <2>;
6d4cf750
RN		 323 next-level-cache = <&L2_500>;
324 L2_500: l2-cache {
325 compatible = "cache";
326 next-level-cache = <&L3_0>;
327 };
328 };
329
330 CPU6: cpu@600 {
331 device_type = "cpu";
332 compatible = "qcom,kryo385";
333 reg = <0x0 0x600>;
334 enable-method = "psci";
b6bc6423 335 capacity-dmips-mhz = <1024>;
9bbd0836
R		 336 cpu-idle-states = <&BIG_CPU_SLEEP_0
337 &BIG_CPU_SLEEP_1
338 &CLUSTER_SLEEP_0>;
0e0a8e35 339 dynamic-power-coefficient = <442>;
c604b82a 340 qcom,freq-domain = <&cpufreq_hw 1>;
54b50f21 341 operating-points-v2 = <&cpu4_opp_table>;
7901c2bc 342 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
54b50f21 343 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
c47fc198 344 #cooling-cells = <2>;
6d4cf750
RN		 345 next-level-cache = <&L2_600>;
346 L2_600: l2-cache {
347 compatible = "cache";
348 next-level-cache = <&L3_0>;
349 };
350 };
351
352 CPU7: cpu@700 {
353 device_type = "cpu";
354 compatible = "qcom,kryo385";
355 reg = <0x0 0x700>;
356 enable-method = "psci";
b6bc6423 357 capacity-dmips-mhz = <1024>;
9bbd0836
R		 358 cpu-idle-states = <&BIG_CPU_SLEEP_0
359 &BIG_CPU_SLEEP_1
360 &CLUSTER_SLEEP_0>;
0e0a8e35 361 dynamic-power-coefficient = <442>;
c604b82a 362 qcom,freq-domain = <&cpufreq_hw 1>;
54b50f21 363 operating-points-v2 = <&cpu4_opp_table>;
7901c2bc 364 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
54b50f21 365 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
c47fc198 366 #cooling-cells = <2>;
6d4cf750
RN		 367 next-level-cache = <&L2_700>;
368 L2_700: l2-cache {
369 compatible = "cache";
370 next-level-cache = <&L3_0>;
371 };
372 };
7b5ee83d
MK		 373
374 cpu-map {
375 cluster0 {
376 core0 {
377 cpu = <&CPU0>;
378 };
379
380 core1 {
381 cpu = <&CPU1>;
382 };
383
384 core2 {
385 cpu = <&CPU2>;
386 };
387
388 core3 {
389 cpu = <&CPU3>;
390 };
7b5ee83d 391
14d27be1 392 core4 {
7b5ee83d
MK		 393 cpu = <&CPU4>;
394 };
395
14d27be1 396 core5 {
7b5ee83d
MK		 397 cpu = <&CPU5>;
398 };
399
14d27be1 400 core6 {
7b5ee83d
MK		 401 cpu = <&CPU6>;
402 };
403
14d27be1 404 core7 {
7b5ee83d
MK		 405 cpu = <&CPU7>;
406 };
407 };
408 };
9bbd0836
R		 409
410 idle-states {
411 entry-method = "psci";
412
413 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
414 compatible = "arm,idle-state";
415 idle-state-name = "little-power-down";
416 arm,psci-suspend-param = <0x40000003>;
417 entry-latency-us = <350>;
418 exit-latency-us = <461>;
419 min-residency-us = <1890>;
420 local-timer-stop;
421 };
422
423 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
424 compatible = "arm,idle-state";
425 idle-state-name = "little-rail-power-down";
426 arm,psci-suspend-param = <0x40000004>;
427 entry-latency-us = <360>;
428 exit-latency-us = <531>;
429 min-residency-us = <3934>;
430 local-timer-stop;
431 };
432
433 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
434 compatible = "arm,idle-state";
435 idle-state-name = "big-power-down";
436 arm,psci-suspend-param = <0x40000003>;
437 entry-latency-us = <264>;
438 exit-latency-us = <621>;
439 min-residency-us = <952>;
440 local-timer-stop;
441 };
442
443 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
444 compatible = "arm,idle-state";
445 idle-state-name = "big-rail-power-down";
446 arm,psci-suspend-param = <0x40000004>;
447 entry-latency-us = <702>;
448 exit-latency-us = <1061>;
449 min-residency-us = <4488>;
450 local-timer-stop;
451 };
452
453 CLUSTER_SLEEP_0: cluster-sleep-0 {
454 compatible = "arm,idle-state";
455 idle-state-name = "cluster-power-down";
456 arm,psci-suspend-param = <0x400000F4>;
457 entry-latency-us = <3263>;
458 exit-latency-us = <6562>;
459 min-residency-us = <9987>;
460 local-timer-stop;
461 };
462 };
6d4cf750
RN		 463 };
464
54b50f21
SS		 465 cpu0_opp_table: cpu0_opp_table {
466 compatible = "operating-points-v2";
467 opp-shared;
468
469 cpu0_opp1: opp-300000000 {
470 opp-hz = /bits/ 64 <300000000>;
471 opp-peak-kBps = <800000 4800000>;
472 };
473
474 cpu0_opp2: opp-403200000 {
475 opp-hz = /bits/ 64 <403200000>;
476 opp-peak-kBps = <800000 4800000>;
477 };
478
479 cpu0_opp3: opp-480000000 {
480 opp-hz = /bits/ 64 <480000000>;
481 opp-peak-kBps = <800000 6451200>;
482 };
483
484 cpu0_opp4: opp-576000000 {
485 opp-hz = /bits/ 64 <576000000>;
486 opp-peak-kBps = <800000 6451200>;
487 };
488
489 cpu0_opp5: opp-652800000 {
490 opp-hz = /bits/ 64 <652800000>;
491 opp-peak-kBps = <800000 7680000>;
492 };
493
494 cpu0_opp6: opp-748800000 {
495 opp-hz = /bits/ 64 <748800000>;
496 opp-peak-kBps = <1804000 9216000>;
497 };
498
499 cpu0_opp7: opp-825600000 {
500 opp-hz = /bits/ 64 <825600000>;
501 opp-peak-kBps = <1804000 9216000>;
502 };
503
504 cpu0_opp8: opp-902400000 {
505 opp-hz = /bits/ 64 <902400000>;
506 opp-peak-kBps = <1804000 10444800>;
507 };
508
509 cpu0_opp9: opp-979200000 {
510 opp-hz = /bits/ 64 <979200000>;
511 opp-peak-kBps = <1804000 11980800>;
512 };
513
514 cpu0_opp10: opp-1056000000 {
515 opp-hz = /bits/ 64 <1056000000>;
516 opp-peak-kBps = <1804000 11980800>;
517 };
518
519 cpu0_opp11: opp-1132800000 {
520 opp-hz = /bits/ 64 <1132800000>;
521 opp-peak-kBps = <2188000 13516800>;
522 };
523
524 cpu0_opp12: opp-1228800000 {
525 opp-hz = /bits/ 64 <1228800000>;
526 opp-peak-kBps = <2188000 15052800>;
527 };
528
529 cpu0_opp13: opp-1324800000 {
530 opp-hz = /bits/ 64 <1324800000>;
531 opp-peak-kBps = <2188000 16588800>;
532 };
533
534 cpu0_opp14: opp-1420800000 {
535 opp-hz = /bits/ 64 <1420800000>;
536 opp-peak-kBps = <3072000 18124800>;
537 };
538
539 cpu0_opp15: opp-1516800000 {
540 opp-hz = /bits/ 64 <1516800000>;
541 opp-peak-kBps = <3072000 19353600>;
542 };
543
544 cpu0_opp16: opp-1612800000 {
545 opp-hz = /bits/ 64 <1612800000>;
546 opp-peak-kBps = <4068000 19353600>;
547 };
548
549 cpu0_opp17: opp-1689600000 {
550 opp-hz = /bits/ 64 <1689600000>;
551 opp-peak-kBps = <4068000 20889600>;
552 };
553
554 cpu0_opp18: opp-1766400000 {
555 opp-hz = /bits/ 64 <1766400000>;
556 opp-peak-kBps = <4068000 22425600>;
557 };
558 };
559
560 cpu4_opp_table: cpu4_opp_table {
561 compatible = "operating-points-v2";
562 opp-shared;
563
564 cpu4_opp1: opp-300000000 {
565 opp-hz = /bits/ 64 <300000000>;
566 opp-peak-kBps = <800000 4800000>;
567 };
568
569 cpu4_opp2: opp-403200000 {
570 opp-hz = /bits/ 64 <403200000>;
571 opp-peak-kBps = <800000 4800000>;
572 };
573
574 cpu4_opp3: opp-480000000 {
575 opp-hz = /bits/ 64 <480000000>;
576 opp-peak-kBps = <1804000 4800000>;
577 };
578
579 cpu4_opp4: opp-576000000 {
580 opp-hz = /bits/ 64 <576000000>;
581 opp-peak-kBps = <1804000 4800000>;
582 };
583
584 cpu4_opp5: opp-652800000 {
585 opp-hz = /bits/ 64 <652800000>;
586 opp-peak-kBps = <1804000 4800000>;
587 };
588
589 cpu4_opp6: opp-748800000 {
590 opp-hz = /bits/ 64 <748800000>;
591 opp-peak-kBps = <1804000 4800000>;
592 };
593
594 cpu4_opp7: opp-825600000 {
595 opp-hz = /bits/ 64 <825600000>;
596 opp-peak-kBps = <2188000 9216000>;
597 };
598
599 cpu4_opp8: opp-902400000 {
600 opp-hz = /bits/ 64 <902400000>;
601 opp-peak-kBps = <2188000 9216000>;
602 };
603
604 cpu4_opp9: opp-979200000 {
605 opp-hz = /bits/ 64 <979200000>;
606 opp-peak-kBps = <2188000 9216000>;
607 };
608
609 cpu4_opp10: opp-1056000000 {
610 opp-hz = /bits/ 64 <1056000000>;
611 opp-peak-kBps = <3072000 9216000>;
612 };
613
614 cpu4_opp11: opp-1132800000 {
615 opp-hz = /bits/ 64 <1132800000>;
616 opp-peak-kBps = <3072000 11980800>;
617 };
618
619 cpu4_opp12: opp-1209600000 {
620 opp-hz = /bits/ 64 <1209600000>;
621 opp-peak-kBps = <4068000 11980800>;
622 };
623
624 cpu4_opp13: opp-1286400000 {
625 opp-hz = /bits/ 64 <1286400000>;
626 opp-peak-kBps = <4068000 11980800>;
627 };
628
629 cpu4_opp14: opp-1363200000 {
630 opp-hz = /bits/ 64 <1363200000>;
631 opp-peak-kBps = <4068000 15052800>;
632 };
633
634 cpu4_opp15: opp-1459200000 {
635 opp-hz = /bits/ 64 <1459200000>;
636 opp-peak-kBps = <4068000 15052800>;
637 };
638
639 cpu4_opp16: opp-1536000000 {
640 opp-hz = /bits/ 64 <1536000000>;
641 opp-peak-kBps = <5412000 15052800>;
642 };
643
644 cpu4_opp17: opp-1612800000 {
645 opp-hz = /bits/ 64 <1612800000>;
646 opp-peak-kBps = <5412000 15052800>;
647 };
648
649 cpu4_opp18: opp-1689600000 {
650 opp-hz = /bits/ 64 <1689600000>;
651 opp-peak-kBps = <5412000 19353600>;
652 };
653
654 cpu4_opp19: opp-1766400000 {
655 opp-hz = /bits/ 64 <1766400000>;
656 opp-peak-kBps = <6220000 19353600>;
657 };
658
659 cpu4_opp20: opp-1843200000 {
660 opp-hz = /bits/ 64 <1843200000>;
661 opp-peak-kBps = <6220000 19353600>;
662 };
663
664 cpu4_opp21: opp-1920000000 {
665 opp-hz = /bits/ 64 <1920000000>;
666 opp-peak-kBps = <7216000 19353600>;
667 };
668
669 cpu4_opp22: opp-1996800000 {
670 opp-hz = /bits/ 64 <1996800000>;
671 opp-peak-kBps = <7216000 20889600>;
672 };
673
674 cpu4_opp23: opp-2092800000 {
675 opp-hz = /bits/ 64 <2092800000>;
676 opp-peak-kBps = <7216000 20889600>;
677 };
678
679 cpu4_opp24: opp-2169600000 {
680 opp-hz = /bits/ 64 <2169600000>;
681 opp-peak-kBps = <7216000 20889600>;
682 };
683
684 cpu4_opp25: opp-2246400000 {
685 opp-hz = /bits/ 64 <2246400000>;
686 opp-peak-kBps = <7216000 20889600>;
687 };
688
689 cpu4_opp26: opp-2323200000 {
690 opp-hz = /bits/ 64 <2323200000>;
691 opp-peak-kBps = <7216000 20889600>;
692 };
693
694 cpu4_opp27: opp-2400000000 {
695 opp-hz = /bits/ 64 <2400000000>;
696 opp-peak-kBps = <7216000 22425600>;
697 };
698
699 cpu4_opp28: opp-2476800000 {
700 opp-hz = /bits/ 64 <2476800000>;
701 opp-peak-kBps = <7216000 22425600>;
702 };
703
704 cpu4_opp29: opp-2553600000 {
705 opp-hz = /bits/ 64 <2553600000>;
706 opp-peak-kBps = <7216000 22425600>;
707 };
708
709 cpu4_opp30: opp-2649600000 {
710 opp-hz = /bits/ 64 <2649600000>;
711 opp-peak-kBps = <7216000 22425600>;
712 };
713
714 cpu4_opp31: opp-2745600000 {
715 opp-hz = /bits/ 64 <2745600000>;
716 opp-peak-kBps = <7216000 25497600>;
717 };
718
719 cpu4_opp32: opp-2803200000 {
720 opp-hz = /bits/ 64 <2803200000>;
721 opp-peak-kBps = <7216000 25497600>;
722 };
723 };
724
000c4662
SB		 725 pmu {
726 compatible = "arm,armv8-pmuv3";
727 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
728 };
729
6d4cf750
RN		 730 timer {
731 compatible = "arm,armv8-timer";
732 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
733 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
734 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
735 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
736 };
737
738 clocks {
739 xo_board: xo-board {
740 compatible = "fixed-clock";
741 #clock-cells = <0>;
5ea3939c
DA		 742 clock-frequency = <38400000>;
743 clock-output-names = "xo_board";
6d4cf750
RN		 744 };
745
746 sleep_clk: sleep-clk {
747 compatible = "fixed-clock";
748 #clock-cells = <0>;
749 clock-frequency = <32764>;
750 };
751 };
752
77bb7f94
SS		 753 firmware {
754 scm {
755 compatible = "qcom,scm-sdm845", "qcom,scm";
756 };
757 };
758
6ef7c11b
BA		 759 adsp_pas: remoteproc-adsp {
760 compatible = "qcom,sdm845-adsp-pas";
761
762 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
763 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
764 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
765 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
766 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
767 interrupt-names = "wdog", "fatal", "ready",
768 "handover", "stop-ack";
769
770 clocks = <&rpmhcc RPMH_CXO_CLK>;
771 clock-names = "xo";
772
773 memory-region = <&adsp_mem>;
774
db8e45a8
SS		 775 qcom,qmp = <&aoss_qmp>;
776
6ef7c11b
BA		 777 qcom,smem-states = <&adsp_smp2p_out 0>;
778 qcom,smem-state-names = "stop";
779
780 status = "disabled";
781
782 glink-edge {
783 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
784 label = "lpass";
785 qcom,remote-pid = <2>;
786 mboxes = <&apss_shared 8>;
3898fdc1
SK		 787
788 apr {
789 compatible = "qcom,apr-v2";
790 qcom,glink-channels = "apr_audio_svc";
2f114511 791 qcom,domain = <APR_DOMAIN_ADSP>;
3898fdc1
SK		 792 #address-cells = <1>;
793 #size-cells = <0>;
794 qcom,intents = <512 20>;
795
796 apr-service@3 {
797 reg = <APR_SVC_ADSP_CORE>;
798 compatible = "qcom,q6core";
799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
800 };
801
802 q6afe: apr-service@4 {
803 compatible = "qcom,q6afe";
804 reg = <APR_SVC_AFE>;
805 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
806 q6afedai: dais {
807 compatible = "qcom,q6afe-dais";
808 #address-cells = <1>;
809 #size-cells = <0>;
810 #sound-dai-cells = <1>;
811 };
812 };
813
814 q6asm: apr-service@7 {
815 compatible = "qcom,q6asm";
816 reg = <APR_SVC_ASM>;
817 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
818 q6asmdai: dais {
819 compatible = "qcom,q6asm-dais";
820 #address-cells = <1>;
821 #size-cells = <0>;
822 #sound-dai-cells = <1>;
823 iommus = <&apps_smmu 0x1821 0x0>;
824 };
825 };
826
827 q6adm: apr-service@8 {
828 compatible = "qcom,q6adm";
829 reg = <APR_SVC_ADM>;
830 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
831 q6routing: routing {
832 compatible = "qcom,q6adm-routing";
833 #sound-dai-cells = <0>;
834 };
835 };
836 };
837
b4d08173
SK		 838 fastrpc {
839 compatible = "qcom,fastrpc";
840 qcom,glink-channels = "fastrpcglink-apps-dsp";
841 label = "adsp";
8c8ce95b 842 qcom,non-secure-domain;
b4d08173
SK		 843 #address-cells = <1>;
844 #size-cells = <0>;
845
846 compute-cb@3 {
847 compatible = "qcom,fastrpc-compute-cb";
848 reg = <3>;
849 iommus = <&apps_smmu 0x1823 0x0>;
850 };
851
852 compute-cb@4 {
853 compatible = "qcom,fastrpc-compute-cb";
854 reg = <4>;
855 iommus = <&apps_smmu 0x1824 0x0>;
856 };
857 };
6ef7c11b
BA		 858 };
859 };
860
861 cdsp_pas: remoteproc-cdsp {
862 compatible = "qcom,sdm845-cdsp-pas";
863
864 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
865 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
866 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
867 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
868 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
869 interrupt-names = "wdog", "fatal", "ready",
870 "handover", "stop-ack";
871
872 clocks = <&rpmhcc RPMH_CXO_CLK>;
873 clock-names = "xo";
874
875 memory-region = <&cdsp_mem>;
876
db8e45a8
SS		 877 qcom,qmp = <&aoss_qmp>;
878
6ef7c11b
BA		 879 qcom,smem-states = <&cdsp_smp2p_out 0>;
880 qcom,smem-state-names = "stop";
881
882 status = "disabled";
883
884 glink-edge {
885 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
886 label = "turing";
887 qcom,remote-pid = <5>;
888 mboxes = <&apss_shared 4>;
b4d08173
SK		 889 fastrpc {
890 compatible = "qcom,fastrpc";
891 qcom,glink-channels = "fastrpcglink-apps-dsp";
892 label = "cdsp";
8c8ce95b 893 qcom,non-secure-domain;
b4d08173
SK		 894 #address-cells = <1>;
895 #size-cells = <0>;
896
897 compute-cb@1 {
898 compatible = "qcom,fastrpc-compute-cb";
899 reg = <1>;
900 iommus = <&apps_smmu 0x1401 0x30>;
901 };
902
903 compute-cb@2 {
904 compatible = "qcom,fastrpc-compute-cb";
905 reg = <2>;
906 iommus = <&apps_smmu 0x1402 0x30>;
907 };
908
909 compute-cb@3 {
910 compatible = "qcom,fastrpc-compute-cb";
911 reg = <3>;
912 iommus = <&apps_smmu 0x1403 0x30>;
913 };
914
915 compute-cb@4 {
916 compatible = "qcom,fastrpc-compute-cb";
917 reg = <4>;
918 iommus = <&apps_smmu 0x1404 0x30>;
919 };
920
921 compute-cb@5 {
922 compatible = "qcom,fastrpc-compute-cb";
923 reg = <5>;
924 iommus = <&apps_smmu 0x1405 0x30>;
925 };
926
927 compute-cb@6 {
928 compatible = "qcom,fastrpc-compute-cb";
929 reg = <6>;
930 iommus = <&apps_smmu 0x1406 0x30>;
931 };
932
933 compute-cb@7 {
934 compatible = "qcom,fastrpc-compute-cb";
935 reg = <7>;
936 iommus = <&apps_smmu 0x1407 0x30>;
937 };
938
939 compute-cb@8 {
940 compatible = "qcom,fastrpc-compute-cb";
941 reg = <8>;
942 iommus = <&apps_smmu 0x1408 0x30>;
943 };
944 };
6ef7c11b
BA		 945 };
946 };
947
71c8428e
S		 948 tcsr_mutex: hwlock {
949 compatible = "qcom,tcsr-mutex";
950 syscon = <&tcsr_mutex_regs 0 0x1000>;
951 #hwlock-cells = <1>;
952 };
953
3debb1f3
BA		 954 smp2p-cdsp {
955 compatible = "qcom,smp2p";
956 qcom,smem = <94>, <432>;
957
958 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
959
960 mboxes = <&apss_shared 6>;
961
962 qcom,local-pid = <0>;
963 qcom,remote-pid = <5>;
964
965 cdsp_smp2p_out: master-kernel {
966 qcom,entry-name = "master-kernel";
967 #qcom,smem-state-cells = <1>;
968 };
969
970 cdsp_smp2p_in: slave-kernel {
971 qcom,entry-name = "slave-kernel";
972
973 interrupt-controller;
974 #interrupt-cells = <2>;
975 };
976 };
977
978 smp2p-lpass {
979 compatible = "qcom,smp2p";
980 qcom,smem = <443>, <429>;
981
982 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
983
984 mboxes = <&apss_shared 10>;
985
986 qcom,local-pid = <0>;
987 qcom,remote-pid = <2>;
988
989 adsp_smp2p_out: master-kernel {
990 qcom,entry-name = "master-kernel";
991 #qcom,smem-state-cells = <1>;
992 };
993
994 adsp_smp2p_in: slave-kernel {
995 qcom,entry-name = "slave-kernel";
996
997 interrupt-controller;
998 #interrupt-cells = <2>;
999 };
1000 };
1001
1002 smp2p-mpss {
1003 compatible = "qcom,smp2p";
1004 qcom,smem = <435>, <428>;
1005 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1006 mboxes = <&apss_shared 14>;
1007 qcom,local-pid = <0>;
1008 qcom,remote-pid = <1>;
1009
1010 modem_smp2p_out: master-kernel {
1011 qcom,entry-name = "master-kernel";
1012 #qcom,smem-state-cells = <1>;
1013 };
1014
1015 modem_smp2p_in: slave-kernel {
1016 qcom,entry-name = "slave-kernel";
1017 interrupt-controller;
1018 #interrupt-cells = <2>;
1019 };
392a5855
AE		 1020
1021 ipa_smp2p_out: ipa-ap-to-modem {
1022 qcom,entry-name = "ipa";
1023 #qcom,smem-state-cells = <1>;
1024 };
1025
1026 ipa_smp2p_in: ipa-modem-to-ap {
1027 qcom,entry-name = "ipa";
1028 interrupt-controller;
1029 #interrupt-cells = <2>;
1030 };
3debb1f3
BA		 1031 };
1032
1033 smp2p-slpi {
1034 compatible = "qcom,smp2p";
1035 qcom,smem = <481>, <430>;
1036 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1037 mboxes = <&apss_shared 26>;
1038 qcom,local-pid = <0>;
1039 qcom,remote-pid = <3>;
1040
1041 slpi_smp2p_out: master-kernel {
1042 qcom,entry-name = "master-kernel";
1043 #qcom,smem-state-cells = <1>;
1044 };
1045
1046 slpi_smp2p_in: slave-kernel {
1047 qcom,entry-name = "slave-kernel";
1048 interrupt-controller;
1049 #interrupt-cells = <2>;
1050 };
1051 };
1052
6d4cf750
RN		 1053 psci {
1054 compatible = "arm,psci-1.0";
1055 method = "smc";
1056 };
1057
a1875bf9 1058 soc: soc@0 {
bede7d2d
BA		 1059 #address-cells = <2>;
1060 #size-cells = <2>;
9feb667d
BA		 1061 ranges = <0 0 0 0 0x10 0>;
1062 dma-ranges = <0 0 0 0 0x10 0>;
6d4cf750
RN		 1063 compatible = "simple-bus";
1064
54d7a20d
DA		 1065 gcc: clock-controller@100000 {
1066 compatible = "qcom,gcc-sdm845";
bede7d2d 1067 reg = <0 0x00100000 0 0x1f0000>;
644e4d97
DB		 1068 clocks = <&rpmhcc RPMH_CXO_CLK>,
1069 <&rpmhcc RPMH_CXO_CLK_A>,
1070 <&sleep_clk>,
1071 <&pcie0_lane>,
1072 <&pcie1_lane>;
1073 clock-names = "bi_tcxo",
1074 "bi_tcxo_ao",
1075 "sleep_clk",
1076 "pcie_0_pipe_clk",
1077 "pcie_1_pipe_clk";
54d7a20d
DA		 1078 #clock-cells = <1>;
1079 #reset-cells = <1>;
1080 #power-domain-cells = <1>;
1081 };
1082
ca4db2b5 1083 qfprom@784000 {
c8b9d64b 1084 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
bede7d2d 1085 reg = <0 0x00784000 0 0x8ff>;
ca4db2b5
MG		 1086 #address-cells = <1>;
1087 #size-cells = <1>;
1088
1089 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1090 reg = <0x1eb 0x1>;
1091 bits = <1 4>;
1092 };
1093
1094 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1095 reg = <0x1eb 0x2>;
1096 bits = <6 4>;
1097 };
1098 };
1099
6e17f814
VK		 1100 rng: rng@793000 {
1101 compatible = "qcom,prng-ee";
bede7d2d 1102 reg = <0 0x00793000 0 0x1000>;
6e17f814
VK		 1103 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1104 clock-names = "core";
1105 };
1106
13cadb34
RN		 1107 qup_opp_table: qup-opp-table {
1108 compatible = "operating-points-v2";
1109
e0b760a5
RN		 1110 opp-50000000 {
1111 opp-hz = /bits/ 64 <50000000>;
13cadb34
RN		 1112 required-opps = <&rpmhpd_opp_min_svs>;
1113 };
1114
1115 opp-75000000 {
1116 opp-hz = /bits/ 64 <75000000>;
1117 required-opps = <&rpmhpd_opp_low_svs>;
1118 };
1119
1120 opp-100000000 {
1121 opp-hz = /bits/ 64 <100000000>;
1122 required-opps = <&rpmhpd_opp_svs>;
1123 };
e0b760a5
RN		 1124
1125 opp-128000000 {
1126 opp-hz = /bits/ 64 <128000000>;
1127 required-opps = <&rpmhpd_opp_nom>;
1128 };
13cadb34
RN		 1129 };
1130
29aed4b4
VK		 1131 gpi_dma0: dma-controller@800000 {
1132 #dma-cells = <3>;
1133 compatible = "qcom,sdm845-gpi-dma";
1134 reg = <0 0x00800000 0 0x60000>;
1135 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1138 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1143 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1148 dma-channels = <13>;
1149 dma-channel-mask = <0xfa>;
1150 iommus = <&apps_smmu 0x0016 0x0>;
1151 status = "disabled";
1152 };
1153
897cf34e
DA		 1154 qupv3_id_0: geniqup@8c0000 {
1155 compatible = "qcom,geni-se-qup";
bede7d2d 1156 reg = <0 0x008c0000 0 0x6000>;
897cf34e
DA		 1157 clock-names = "m-ahb", "s-ahb";
1158 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1159 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
4785cff7 1160 iommus = <&apps_smmu 0x3 0x0>;
bede7d2d
BA		 1161 #address-cells = <2>;
1162 #size-cells = <2>;
897cf34e 1163 ranges;
05b801af
GD		 1164 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1165 interconnect-names = "qup-core";
499ff116 1166 status = "disabled";
897cf34e
DA		 1167
1168 i2c0: i2c@880000 {
1169 compatible = "qcom,geni-i2c";
bede7d2d 1170 reg = <0 0x00880000 0 0x4000>;
897cf34e
DA		 1171 clock-names = "se";
1172 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&qup_i2c0_default>;
1175 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1176 #address-cells = <1>;
1177 #size-cells = <0>;
13cadb34
RN		 1178 power-domains = <&rpmhpd SDM845_CX>;
1179 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1180 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1181 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1182 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1183 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1184 status = "disabled";
1185 };
1186
1187 spi0: spi@880000 {
1188 compatible = "qcom,geni-spi";
bede7d2d 1189 reg = <0 0x00880000 0 0x4000>;
897cf34e
DA		 1190 clock-names = "se";
1191 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_spi0_default>;
1194 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
05b801af
GD		 1197 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1198 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1199 interconnect-names = "qup-core", "qup-config";
8f6e20ad
VK		 1200 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1201 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1202 dma-names = "tx", "rx";
897cf34e
DA		 1203 status = "disabled";
1204 };
1205
bb2203d5
MK		 1206 uart0: serial@880000 {
1207 compatible = "qcom,geni-uart";
bede7d2d 1208 reg = <0 0x00880000 0 0x4000>;
bb2203d5
MK		 1209 clock-names = "se";
1210 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&qup_uart0_default>;
1213 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1214 power-domains = <&rpmhpd SDM845_CX>;
1215 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1216 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1217 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1218 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1219 status = "disabled";
1220 };
1221
897cf34e
DA		 1222 i2c1: i2c@884000 {
1223 compatible = "qcom,geni-i2c";
bede7d2d 1224 reg = <0 0x00884000 0 0x4000>;
897cf34e
DA		 1225 clock-names = "se";
1226 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1227 pinctrl-names = "default";
1228 pinctrl-0 = <&qup_i2c1_default>;
1229 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1230 #address-cells = <1>;
1231 #size-cells = <0>;
13cadb34
RN		 1232 power-domains = <&rpmhpd SDM845_CX>;
1233 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1234 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1235 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1236 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1237 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1238 status = "disabled";
1239 };
1240
1241 spi1: spi@884000 {
1242 compatible = "qcom,geni-spi";
bede7d2d 1243 reg = <0 0x00884000 0 0x4000>;
897cf34e
DA		 1244 clock-names = "se";
1245 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1246 pinctrl-names = "default";
1247 pinctrl-0 = <&qup_spi1_default>;
1248 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1249 #address-cells = <1>;
1250 #size-cells = <0>;
05b801af
GD		 1251 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1252 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1253 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1254 status = "disabled";
1255 };
1256
bb2203d5
MK		 1257 uart1: serial@884000 {
1258 compatible = "qcom,geni-uart";
bede7d2d 1259 reg = <0 0x00884000 0 0x4000>;
bb2203d5
MK		 1260 clock-names = "se";
1261 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&qup_uart1_default>;
1264 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1265 power-domains = <&rpmhpd SDM845_CX>;
1266 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1267 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1268 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1269 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1270 status = "disabled";
1271 };
1272
897cf34e
DA		 1273 i2c2: i2c@888000 {
1274 compatible = "qcom,geni-i2c";
bede7d2d 1275 reg = <0 0x00888000 0 0x4000>;
897cf34e
DA		 1276 clock-names = "se";
1277 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_i2c2_default>;
1280 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
13cadb34
RN		 1283 power-domains = <&rpmhpd SDM845_CX>;
1284 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1285 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1286 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1287 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1288 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1289 status = "disabled";
1290 };
1291
1292 spi2: spi@888000 {
1293 compatible = "qcom,geni-spi";
bede7d2d 1294 reg = <0 0x00888000 0 0x4000>;
897cf34e
DA		 1295 clock-names = "se";
1296 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&qup_spi2_default>;
1299 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1300 #address-cells = <1>;
1301 #size-cells = <0>;
05b801af
GD		 1302 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1303 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1304 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1305 status = "disabled";
1306 };
1307
bb2203d5
MK		 1308 uart2: serial@888000 {
1309 compatible = "qcom,geni-uart";
bede7d2d 1310 reg = <0 0x00888000 0 0x4000>;
bb2203d5
MK		 1311 clock-names = "se";
1312 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1313 pinctrl-names = "default";
1314 pinctrl-0 = <&qup_uart2_default>;
1315 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1316 power-domains = <&rpmhpd SDM845_CX>;
1317 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1318 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1319 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1320 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1321 status = "disabled";
1322 };
1323
897cf34e
DA		 1324 i2c3: i2c@88c000 {
1325 compatible = "qcom,geni-i2c";
bede7d2d 1326 reg = <0 0x0088c000 0 0x4000>;
897cf34e
DA		 1327 clock-names = "se";
1328 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&qup_i2c3_default>;
1331 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1332 #address-cells = <1>;
1333 #size-cells = <0>;
13cadb34
RN		 1334 power-domains = <&rpmhpd SDM845_CX>;
1335 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1336 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1337 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1338 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1339 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1340 status = "disabled";
1341 };
1342
1343 spi3: spi@88c000 {
1344 compatible = "qcom,geni-spi";
bede7d2d 1345 reg = <0 0x0088c000 0 0x4000>;
897cf34e
DA		 1346 clock-names = "se";
1347 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&qup_spi3_default>;
1350 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1351 #address-cells = <1>;
1352 #size-cells = <0>;
05b801af
GD		 1353 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1354 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1355 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1356 status = "disabled";
1357 };
1358
bb2203d5
MK		 1359 uart3: serial@88c000 {
1360 compatible = "qcom,geni-uart";
bede7d2d 1361 reg = <0 0x0088c000 0 0x4000>;
bb2203d5
MK		 1362 clock-names = "se";
1363 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&qup_uart3_default>;
1366 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1367 power-domains = <&rpmhpd SDM845_CX>;
1368 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1369 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1370 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1371 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1372 status = "disabled";
1373 };
1374
897cf34e
DA		 1375 i2c4: i2c@890000 {
1376 compatible = "qcom,geni-i2c";
bede7d2d 1377 reg = <0 0x00890000 0 0x4000>;
897cf34e
DA		 1378 clock-names = "se";
1379 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1380 pinctrl-names = "default";
1381 pinctrl-0 = <&qup_i2c4_default>;
1382 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1383 #address-cells = <1>;
1384 #size-cells = <0>;
13cadb34
RN		 1385 power-domains = <&rpmhpd SDM845_CX>;
1386 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1387 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1388 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1389 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1390 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1391 status = "disabled";
1392 };
1393
1394 spi4: spi@890000 {
1395 compatible = "qcom,geni-spi";
bede7d2d 1396 reg = <0 0x00890000 0 0x4000>;
897cf34e
DA		 1397 clock-names = "se";
1398 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1399 pinctrl-names = "default";
1400 pinctrl-0 = <&qup_spi4_default>;
1401 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1402 #address-cells = <1>;
1403 #size-cells = <0>;
05b801af
GD		 1404 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1405 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1406 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1407 status = "disabled";
1408 };
1409
bb2203d5
MK		 1410 uart4: serial@890000 {
1411 compatible = "qcom,geni-uart";
bede7d2d 1412 reg = <0 0x00890000 0 0x4000>;
bb2203d5
MK		 1413 clock-names = "se";
1414 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_uart4_default>;
1417 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1418 power-domains = <&rpmhpd SDM845_CX>;
1419 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1420 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1421 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1422 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1423 status = "disabled";
1424 };
1425
897cf34e
DA		 1426 i2c5: i2c@894000 {
1427 compatible = "qcom,geni-i2c";
bede7d2d 1428 reg = <0 0x00894000 0 0x4000>;
897cf34e
DA		 1429 clock-names = "se";
1430 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&qup_i2c5_default>;
1433 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1434 #address-cells = <1>;
1435 #size-cells = <0>;
13cadb34
RN		 1436 power-domains = <&rpmhpd SDM845_CX>;
1437 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1438 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1439 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1440 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1441 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1442 status = "disabled";
1443 };
1444
1445 spi5: spi@894000 {
1446 compatible = "qcom,geni-spi";
bede7d2d 1447 reg = <0 0x00894000 0 0x4000>;
897cf34e
DA		 1448 clock-names = "se";
1449 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_spi5_default>;
1452 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
05b801af
GD		 1455 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1456 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1457 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1458 status = "disabled";
1459 };
1460
bb2203d5
MK		 1461 uart5: serial@894000 {
1462 compatible = "qcom,geni-uart";
bede7d2d 1463 reg = <0 0x00894000 0 0x4000>;
bb2203d5
MK		 1464 clock-names = "se";
1465 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&qup_uart5_default>;
1468 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1469 power-domains = <&rpmhpd SDM845_CX>;
1470 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1471 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1472 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1473 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1474 status = "disabled";
1475 };
1476
897cf34e
DA		 1477 i2c6: i2c@898000 {
1478 compatible = "qcom,geni-i2c";
bede7d2d 1479 reg = <0 0x00898000 0 0x4000>;
897cf34e
DA		 1480 clock-names = "se";
1481 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1482 pinctrl-names = "default";
1483 pinctrl-0 = <&qup_i2c6_default>;
1484 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1485 #address-cells = <1>;
1486 #size-cells = <0>;
13cadb34
RN		 1487 power-domains = <&rpmhpd SDM845_CX>;
1488 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1489 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1490 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1491 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1492 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1493 status = "disabled";
1494 };
1495
1496 spi6: spi@898000 {
1497 compatible = "qcom,geni-spi";
bede7d2d 1498 reg = <0 0x00898000 0 0x4000>;
897cf34e
DA		 1499 clock-names = "se";
1500 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_spi6_default>;
1503 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1504 #address-cells = <1>;
1505 #size-cells = <0>;
05b801af
GD		 1506 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1507 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1508 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1509 status = "disabled";
1510 };
1511
bb2203d5
MK		 1512 uart6: serial@898000 {
1513 compatible = "qcom,geni-uart";
bede7d2d 1514 reg = <0 0x00898000 0 0x4000>;
bb2203d5
MK		 1515 clock-names = "se";
1516 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_uart6_default>;
1519 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1520 power-domains = <&rpmhpd SDM845_CX>;
1521 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1522 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1523 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1524 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1525 status = "disabled";
1526 };
1527
897cf34e
DA		 1528 i2c7: i2c@89c000 {
1529 compatible = "qcom,geni-i2c";
bede7d2d 1530 reg = <0 0x0089c000 0 0x4000>;
897cf34e
DA		 1531 clock-names = "se";
1532 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1533 pinctrl-names = "default";
1534 pinctrl-0 = <&qup_i2c7_default>;
1535 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1536 #address-cells = <1>;
1537 #size-cells = <0>;
13cadb34
RN		 1538 power-domains = <&rpmhpd SDM845_CX>;
1539 operating-points-v2 = <&qup_opp_table>;
897cf34e
DA		 1540 status = "disabled";
1541 };
1542
1543 spi7: spi@89c000 {
1544 compatible = "qcom,geni-spi";
bede7d2d 1545 reg = <0 0x0089c000 0 0x4000>;
897cf34e
DA		 1546 clock-names = "se";
1547 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1548 pinctrl-names = "default";
1549 pinctrl-0 = <&qup_spi7_default>;
1550 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1551 #address-cells = <1>;
1552 #size-cells = <0>;
05b801af
GD		 1553 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1554 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1555 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1556 status = "disabled";
1557 };
bb2203d5
MK		 1558
1559 uart7: serial@89c000 {
1560 compatible = "qcom,geni-uart";
bede7d2d 1561 reg = <0 0x0089c000 0 0x4000>;
bb2203d5
MK		 1562 clock-names = "se";
1563 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_uart7_default>;
1566 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1567 power-domains = <&rpmhpd SDM845_CX>;
1568 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1569 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1570 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1571 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1572 status = "disabled";
1573 };
897cf34e
DA		 1574 };
1575
29aed4b4
VK		 1576 gpi_dma1: dma-controller@0xa00000 {
1577 #dma-cells = <3>;
1578 compatible = "qcom,sdm845-gpi-dma";
1579 reg = <0 0x00a00000 0 0x60000>;
1580 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1582 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1583 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1584 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1585 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1587 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1588 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1589 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1590 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1591 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1592 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1593 dma-channels = <13>;
1594 dma-channel-mask = <0xfa>;
1595 iommus = <&apps_smmu 0x06d6 0x0>;
1596 status = "disabled";
1597 };
1598
897cf34e
DA		 1599 qupv3_id_1: geniqup@ac0000 {
1600 compatible = "qcom,geni-se-qup";
bede7d2d 1601 reg = <0 0x00ac0000 0 0x6000>;
897cf34e
DA		 1602 clock-names = "m-ahb", "s-ahb";
1603 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1604 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
4785cff7 1605 iommus = <&apps_smmu 0x6c3 0x0>;
bede7d2d
BA		 1606 #address-cells = <2>;
1607 #size-cells = <2>;
897cf34e 1608 ranges;
05b801af
GD		 1609 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1610 interconnect-names = "qup-core";
897cf34e
DA		 1611 status = "disabled";
1612
1613 i2c8: i2c@a80000 {
1614 compatible = "qcom,geni-i2c";
bede7d2d 1615 reg = <0 0x00a80000 0 0x4000>;
897cf34e
DA		 1616 clock-names = "se";
1617 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_i2c8_default>;
1620 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1621 #address-cells = <1>;
1622 #size-cells = <0>;
13cadb34
RN		 1623 power-domains = <&rpmhpd SDM845_CX>;
1624 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1625 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1626 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1627 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1628 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1629 status = "disabled";
1630 };
1631
1632 spi8: spi@a80000 {
1633 compatible = "qcom,geni-spi";
bede7d2d 1634 reg = <0 0x00a80000 0 0x4000>;
897cf34e
DA		 1635 clock-names = "se";
1636 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1637 pinctrl-names = "default";
1638 pinctrl-0 = <&qup_spi8_default>;
1639 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1640 #address-cells = <1>;
1641 #size-cells = <0>;
05b801af
GD		 1642 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1643 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1644 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1645 status = "disabled";
1646 };
1647
bb2203d5
MK		 1648 uart8: serial@a80000 {
1649 compatible = "qcom,geni-uart";
bede7d2d 1650 reg = <0 0x00a80000 0 0x4000>;
bb2203d5
MK		 1651 clock-names = "se";
1652 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_uart8_default>;
1655 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1656 power-domains = <&rpmhpd SDM845_CX>;
1657 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1658 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1659 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1660 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1661 status = "disabled";
1662 };
1663
897cf34e
DA		 1664 i2c9: i2c@a84000 {
1665 compatible = "qcom,geni-i2c";
bede7d2d 1666 reg = <0 0x00a84000 0 0x4000>;
897cf34e
DA		 1667 clock-names = "se";
1668 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1669 pinctrl-names = "default";
1670 pinctrl-0 = <&qup_i2c9_default>;
1671 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cells = <1>;
1673 #size-cells = <0>;
13cadb34
RN		 1674 power-domains = <&rpmhpd SDM845_CX>;
1675 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1676 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1677 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1678 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1679 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1680 status = "disabled";
1681 };
1682
1683 spi9: spi@a84000 {
1684 compatible = "qcom,geni-spi";
bede7d2d 1685 reg = <0 0x00a84000 0 0x4000>;
897cf34e
DA		 1686 clock-names = "se";
1687 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1688 pinctrl-names = "default";
1689 pinctrl-0 = <&qup_spi9_default>;
1690 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1691 #address-cells = <1>;
1692 #size-cells = <0>;
05b801af
GD		 1693 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1694 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1695 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1696 status = "disabled";
1697 };
1698
1699 uart9: serial@a84000 {
1700 compatible = "qcom,geni-debug-uart";
bede7d2d 1701 reg = <0 0x00a84000 0 0x4000>;
897cf34e
DA		 1702 clock-names = "se";
1703 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1704 pinctrl-names = "default";
1705 pinctrl-0 = <&qup_uart9_default>;
1706 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1707 power-domains = <&rpmhpd SDM845_CX>;
1708 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1709 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1710 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1711 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1712 status = "disabled";
1713 };
1714
1715 i2c10: i2c@a88000 {
1716 compatible = "qcom,geni-i2c";
bede7d2d 1717 reg = <0 0x00a88000 0 0x4000>;
897cf34e
DA		 1718 clock-names = "se";
1719 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&qup_i2c10_default>;
1722 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1723 #address-cells = <1>;
1724 #size-cells = <0>;
13cadb34
RN		 1725 power-domains = <&rpmhpd SDM845_CX>;
1726 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1727 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1728 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1729 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1730 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1731 status = "disabled";
1732 };
1733
1734 spi10: spi@a88000 {
1735 compatible = "qcom,geni-spi";
bede7d2d 1736 reg = <0 0x00a88000 0 0x4000>;
897cf34e
DA		 1737 clock-names = "se";
1738 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1739 pinctrl-names = "default";
1740 pinctrl-0 = <&qup_spi10_default>;
1741 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1742 #address-cells = <1>;
1743 #size-cells = <0>;
05b801af
GD		 1744 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1745 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1746 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1747 status = "disabled";
1748 };
1749
bb2203d5
MK		 1750 uart10: serial@a88000 {
1751 compatible = "qcom,geni-uart";
bede7d2d 1752 reg = <0 0x00a88000 0 0x4000>;
bb2203d5
MK		 1753 clock-names = "se";
1754 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1755 pinctrl-names = "default";
1756 pinctrl-0 = <&qup_uart10_default>;
1757 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1758 power-domains = <&rpmhpd SDM845_CX>;
1759 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1760 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1761 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1762 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1763 status = "disabled";
1764 };
1765
897cf34e
DA		 1766 i2c11: i2c@a8c000 {
1767 compatible = "qcom,geni-i2c";
bede7d2d 1768 reg = <0 0x00a8c000 0 0x4000>;
897cf34e
DA		 1769 clock-names = "se";
1770 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1771 pinctrl-names = "default";
1772 pinctrl-0 = <&qup_i2c11_default>;
1773 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1774 #address-cells = <1>;
1775 #size-cells = <0>;
13cadb34
RN		 1776 power-domains = <&rpmhpd SDM845_CX>;
1777 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1778 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1779 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1780 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1781 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1782 status = "disabled";
1783 };
1784
1785 spi11: spi@a8c000 {
1786 compatible = "qcom,geni-spi";
bede7d2d 1787 reg = <0 0x00a8c000 0 0x4000>;
897cf34e
DA		 1788 clock-names = "se";
1789 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1790 pinctrl-names = "default";
1791 pinctrl-0 = <&qup_spi11_default>;
1792 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cells = <1>;
1794 #size-cells = <0>;
05b801af
GD		 1795 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1798 status = "disabled";
1799 };
1800
bb2203d5
MK		 1801 uart11: serial@a8c000 {
1802 compatible = "qcom,geni-uart";
bede7d2d 1803 reg = <0 0x00a8c000 0 0x4000>;
bb2203d5
MK		 1804 clock-names = "se";
1805 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1806 pinctrl-names = "default";
1807 pinctrl-0 = <&qup_uart11_default>;
1808 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1809 power-domains = <&rpmhpd SDM845_CX>;
1810 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1811 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1812 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1813 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1814 status = "disabled";
1815 };
1816
897cf34e
DA		 1817 i2c12: i2c@a90000 {
1818 compatible = "qcom,geni-i2c";
bede7d2d 1819 reg = <0 0x00a90000 0 0x4000>;
897cf34e
DA		 1820 clock-names = "se";
1821 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1822 pinctrl-names = "default";
1823 pinctrl-0 = <&qup_i2c12_default>;
1824 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1825 #address-cells = <1>;
1826 #size-cells = <0>;
13cadb34
RN		 1827 power-domains = <&rpmhpd SDM845_CX>;
1828 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1829 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1830 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1831 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1832 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1833 status = "disabled";
1834 };
1835
1836 spi12: spi@a90000 {
1837 compatible = "qcom,geni-spi";
bede7d2d 1838 reg = <0 0x00a90000 0 0x4000>;
897cf34e
DA		 1839 clock-names = "se";
1840 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1841 pinctrl-names = "default";
1842 pinctrl-0 = <&qup_spi12_default>;
1843 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1844 #address-cells = <1>;
1845 #size-cells = <0>;
05b801af
GD		 1846 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1847 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1848 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1849 status = "disabled";
1850 };
1851
bb2203d5
MK		 1852 uart12: serial@a90000 {
1853 compatible = "qcom,geni-uart";
bede7d2d 1854 reg = <0 0x00a90000 0 0x4000>;
bb2203d5
MK		 1855 clock-names = "se";
1856 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1857 pinctrl-names = "default";
1858 pinctrl-0 = <&qup_uart12_default>;
1859 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1860 power-domains = <&rpmhpd SDM845_CX>;
1861 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1862 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1863 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1864 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1865 status = "disabled";
1866 };
1867
897cf34e
DA		 1868 i2c13: i2c@a94000 {
1869 compatible = "qcom,geni-i2c";
bede7d2d 1870 reg = <0 0x00a94000 0 0x4000>;
897cf34e
DA		 1871 clock-names = "se";
1872 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1873 pinctrl-names = "default";
1874 pinctrl-0 = <&qup_i2c13_default>;
1875 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1876 #address-cells = <1>;
1877 #size-cells = <0>;
13cadb34
RN		 1878 power-domains = <&rpmhpd SDM845_CX>;
1879 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1880 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1881 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1882 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1883 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1884 status = "disabled";
1885 };
1886
1887 spi13: spi@a94000 {
1888 compatible = "qcom,geni-spi";
bede7d2d 1889 reg = <0 0x00a94000 0 0x4000>;
897cf34e
DA		 1890 clock-names = "se";
1891 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1892 pinctrl-names = "default";
1893 pinctrl-0 = <&qup_spi13_default>;
1894 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1895 #address-cells = <1>;
1896 #size-cells = <0>;
05b801af
GD		 1897 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1898 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1899 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1900 status = "disabled";
1901 };
1902
bb2203d5
MK		 1903 uart13: serial@a94000 {
1904 compatible = "qcom,geni-uart";
bede7d2d 1905 reg = <0 0x00a94000 0 0x4000>;
bb2203d5
MK		 1906 clock-names = "se";
1907 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1908 pinctrl-names = "default";
1909 pinctrl-0 = <&qup_uart13_default>;
1910 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1911 power-domains = <&rpmhpd SDM845_CX>;
1912 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1913 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1914 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1915 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1916 status = "disabled";
1917 };
1918
897cf34e
DA		 1919 i2c14: i2c@a98000 {
1920 compatible = "qcom,geni-i2c";
bede7d2d 1921 reg = <0 0x00a98000 0 0x4000>;
897cf34e
DA		 1922 clock-names = "se";
1923 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1924 pinctrl-names = "default";
1925 pinctrl-0 = <&qup_i2c14_default>;
1926 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1927 #address-cells = <1>;
1928 #size-cells = <0>;
13cadb34
RN		 1929 power-domains = <&rpmhpd SDM845_CX>;
1930 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1931 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1932 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1933 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1934 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1935 status = "disabled";
1936 };
1937
1938 spi14: spi@a98000 {
1939 compatible = "qcom,geni-spi";
bede7d2d 1940 reg = <0 0x00a98000 0 0x4000>;
897cf34e
DA		 1941 clock-names = "se";
1942 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1943 pinctrl-names = "default";
1944 pinctrl-0 = <&qup_spi14_default>;
1945 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1946 #address-cells = <1>;
1947 #size-cells = <0>;
05b801af
GD		 1948 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1949 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1950 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 1951 status = "disabled";
1952 };
1953
bb2203d5
MK		 1954 uart14: serial@a98000 {
1955 compatible = "qcom,geni-uart";
bede7d2d 1956 reg = <0 0x00a98000 0 0x4000>;
bb2203d5
MK		 1957 clock-names = "se";
1958 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1959 pinctrl-names = "default";
1960 pinctrl-0 = <&qup_uart14_default>;
1961 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 1962 power-domains = <&rpmhpd SDM845_CX>;
1963 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 1964 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1965 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1966 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 1967 status = "disabled";
1968 };
1969
897cf34e
DA		 1970 i2c15: i2c@a9c000 {
1971 compatible = "qcom,geni-i2c";
bede7d2d 1972 reg = <0 0x00a9c000 0 0x4000>;
897cf34e
DA		 1973 clock-names = "se";
1974 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1975 pinctrl-names = "default";
1976 pinctrl-0 = <&qup_i2c15_default>;
1977 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1978 #address-cells = <1>;
1979 #size-cells = <0>;
13cadb34
RN		 1980 power-domains = <&rpmhpd SDM845_CX>;
1981 operating-points-v2 = <&qup_opp_table>;
897cf34e 1982 status = "disabled";
05b801af
GD		 1983 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1984 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1985 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1986 interconnect-names = "qup-core", "qup-config", "qup-memory";
897cf34e
DA		 1987 };
1988
1989 spi15: spi@a9c000 {
1990 compatible = "qcom,geni-spi";
bede7d2d 1991 reg = <0 0x00a9c000 0 0x4000>;
897cf34e
DA		 1992 clock-names = "se";
1993 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1994 pinctrl-names = "default";
1995 pinctrl-0 = <&qup_spi15_default>;
1996 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1997 #address-cells = <1>;
1998 #size-cells = <0>;
05b801af
GD		 1999 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2000 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2001 interconnect-names = "qup-core", "qup-config";
897cf34e
DA		 2002 status = "disabled";
2003 };
bb2203d5
MK		 2004
2005 uart15: serial@a9c000 {
2006 compatible = "qcom,geni-uart";
bede7d2d 2007 reg = <0 0x00a9c000 0 0x4000>;
bb2203d5
MK		 2008 clock-names = "se";
2009 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2010 pinctrl-names = "default";
2011 pinctrl-0 = <&qup_uart15_default>;
2012 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
13cadb34
RN		 2013 power-domains = <&rpmhpd SDM845_CX>;
2014 operating-points-v2 = <&qup_opp_table>;
05b801af
GD		 2015 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2016 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2017 interconnect-names = "qup-core", "qup-config";
bb2203d5
MK		 2018 status = "disabled";
2019 };
897cf34e
DA		 2020 };
2021
d4b34126 2022 llcc: system-cache-controller@1100000 {
ba0411dd
SPR		 2023 compatible = "qcom,sdm845-llcc";
2024 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2025 reg-names = "llcc_base", "llcc_broadcast_base";
2026 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2027 };
2028
5c538e09 2029 pcie0: pci@1c00000 {
b4f3996c 2030 compatible = "qcom,pcie-sdm845";
5c538e09
BA		 2031 reg = <0 0x01c00000 0 0x2000>,
2032 <0 0x60000000 0 0xf1d>,
2033 <0 0x60000f20 0 0xa8>,
2034 <0 0x60100000 0 0x100000>;
2035 reg-names = "parf", "dbi", "elbi", "config";
2036 device_type = "pci";
2037 linux,pci-domain = <0>;
2038 bus-range = <0x00 0xff>;
2039 num-lanes = <1>;
2040
2041 #address-cells = <3>;
2042 #size-cells = <2>;
2043
2044 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2045 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2046
2047 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2048 interrupt-names = "msi";
2049 #interrupt-cells = <1>;
2050 interrupt-map-mask = <0 0 0 0x7>;
0ac10b29
RH		 2051 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2052 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2053 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2054 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
5c538e09
BA		 2055
2056 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2057 <&gcc GCC_PCIE_0_AUX_CLK>,
2058 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2059 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2060 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2061 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2062 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2063 clock-names = "pipe",
2064 "aux",
2065 "cfg",
2066 "bus_master",
2067 "bus_slave",
2068 "slave_q2a",
2069 "tbu";
2070
2071 iommus = <&apps_smmu 0x1c10 0xf>;
2072 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2073 <0x100 &apps_smmu 0x1c11 0x1>,
2074 <0x200 &apps_smmu 0x1c12 0x1>,
2075 <0x300 &apps_smmu 0x1c13 0x1>,
2076 <0x400 &apps_smmu 0x1c14 0x1>,
2077 <0x500 &apps_smmu 0x1c15 0x1>,
2078 <0x600 &apps_smmu 0x1c16 0x1>,
2079 <0x700 &apps_smmu 0x1c17 0x1>,
2080 <0x800 &apps_smmu 0x1c18 0x1>,
2081 <0x900 &apps_smmu 0x1c19 0x1>,
2082 <0xa00 &apps_smmu 0x1c1a 0x1>,
2083 <0xb00 &apps_smmu 0x1c1b 0x1>,
2084 <0xc00 &apps_smmu 0x1c1c 0x1>,
2085 <0xd00 &apps_smmu 0x1c1d 0x1>,
2086 <0xe00 &apps_smmu 0x1c1e 0x1>,
2087 <0xf00 &apps_smmu 0x1c1f 0x1>;
2088
2089 resets = <&gcc GCC_PCIE_0_BCR>;
2090 reset-names = "pci";
2091
2092 power-domains = <&gcc PCIE_0_GDSC>;
2093
2094 phys = <&pcie0_lane>;
2095 phy-names = "pciephy";
2096
2097 status = "disabled";
2098 };
2099
2100 pcie0_phy: phy@1c06000 {
2101 compatible = "qcom,sdm845-qmp-pcie-phy";
2102 reg = <0 0x01c06000 0 0x18c>;
2103 #address-cells = <2>;
2104 #size-cells = <2>;
2105 ranges;
2106 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2107 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2108 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2109 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2110 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2111
2112 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2113 reset-names = "phy";
2114
2115 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2116 assigned-clock-rates = <100000000>;
2117
2118 status = "disabled";
2119
1351512f 2120 pcie0_lane: phy@1c06200 {
5c538e09
BA		 2121 reg = <0 0x01c06200 0 0x128>,
2122 <0 0x01c06400 0 0x1fc>,
2123 <0 0x01c06800 0 0x218>,
2124 <0 0x01c06600 0 0x70>;
2125 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2126 clock-names = "pipe0";
2127
644e4d97 2128 #clock-cells = <0>;
5c538e09
BA		 2129 #phy-cells = <0>;
2130 clock-output-names = "pcie_0_pipe_clk";
2131 };
2132 };
2133
42ad2313 2134 pcie1: pci@1c08000 {
b4f3996c 2135 compatible = "qcom,pcie-sdm845";
42ad2313
BA		 2136 reg = <0 0x01c08000 0 0x2000>,
2137 <0 0x40000000 0 0xf1d>,
2138 <0 0x40000f20 0 0xa8>,
2139 <0 0x40100000 0 0x100000>;
2140 reg-names = "parf", "dbi", "elbi", "config";
2141 device_type = "pci";
2142 linux,pci-domain = <1>;
2143 bus-range = <0x00 0xff>;
2144 num-lanes = <1>;
2145
2146 #address-cells = <3>;
2147 #size-cells = <2>;
2148
2149 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2150 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2151
2152 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2153 interrupt-names = "msi";
2154 #interrupt-cells = <1>;
2155 interrupt-map-mask = <0 0 0 0x7>;
0ac10b29
RH		 2156 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2157 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2158 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2159 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
42ad2313
BA		 2160
2161 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2162 <&gcc GCC_PCIE_1_AUX_CLK>,
2163 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2164 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2165 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2166 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2167 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2168 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2169 clock-names = "pipe",
2170 "aux",
2171 "cfg",
2172 "bus_master",
2173 "bus_slave",
2174 "slave_q2a",
2175 "ref",
2176 "tbu";
2177
2178 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2179 assigned-clock-rates = <19200000>;
2180
2181 iommus = <&apps_smmu 0x1c00 0xf>;
2182 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2183 <0x100 &apps_smmu 0x1c01 0x1>,
2184 <0x200 &apps_smmu 0x1c02 0x1>,
2185 <0x300 &apps_smmu 0x1c03 0x1>,
2186 <0x400 &apps_smmu 0x1c04 0x1>,
2187 <0x500 &apps_smmu 0x1c05 0x1>,
2188 <0x600 &apps_smmu 0x1c06 0x1>,
2189 <0x700 &apps_smmu 0x1c07 0x1>,
2190 <0x800 &apps_smmu 0x1c08 0x1>,
2191 <0x900 &apps_smmu 0x1c09 0x1>,
2192 <0xa00 &apps_smmu 0x1c0a 0x1>,
2193 <0xb00 &apps_smmu 0x1c0b 0x1>,
2194 <0xc00 &apps_smmu 0x1c0c 0x1>,
2195 <0xd00 &apps_smmu 0x1c0d 0x1>,
2196 <0xe00 &apps_smmu 0x1c0e 0x1>,
2197 <0xf00 &apps_smmu 0x1c0f 0x1>;
2198
2199 resets = <&gcc GCC_PCIE_1_BCR>;
2200 reset-names = "pci";
2201
2202 power-domains = <&gcc PCIE_1_GDSC>;
2203
2204 phys = <&pcie1_lane>;
2205 phy-names = "pciephy";
2206
2207 status = "disabled";
2208 };
2209
2210 pcie1_phy: phy@1c0a000 {
2211 compatible = "qcom,sdm845-qhp-pcie-phy";
2212 reg = <0 0x01c0a000 0 0x800>;
2213 #address-cells = <2>;
2214 #size-cells = <2>;
2215 ranges;
2216 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2217 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2218 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2219 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2220 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2221
2222 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2223 reset-names = "phy";
2224
2225 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2226 assigned-clock-rates = <100000000>;
2227
2228 status = "disabled";
2229
1351512f 2230 pcie1_lane: phy@1c06200 {
42ad2313
BA		 2231 reg = <0 0x01c0a800 0 0x800>,
2232 <0 0x01c0a800 0 0x800>,
2233 <0 0x01c0b800 0 0x400>;
2234 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2235 clock-names = "pipe0";
2236
644e4d97 2237 #clock-cells = <0>;
42ad2313
BA		 2238 #phy-cells = <0>;
2239 clock-output-names = "pcie_1_pipe_clk";
2240 };
2241 };
2242
b303f9f0
DD		 2243 mem_noc: interconnect@1380000 {
2244 compatible = "qcom,sdm845-mem-noc";
2245 reg = <0 0x01380000 0 0x27200>;
7901c2bc 2246 #interconnect-cells = <2>;
b303f9f0
DD		 2247 qcom,bcm-voters = <&apps_bcm_voter>;
2248 };
2249
2250 dc_noc: interconnect@14e0000 {
2251 compatible = "qcom,sdm845-dc-noc";
2252 reg = <0 0x014e0000 0 0x400>;
7901c2bc 2253 #interconnect-cells = <2>;
b303f9f0
DD		 2254 qcom,bcm-voters = <&apps_bcm_voter>;
2255 };
2256
2257 config_noc: interconnect@1500000 {
2258 compatible = "qcom,sdm845-config-noc";
2259 reg = <0 0x01500000 0 0x5080>;
7901c2bc 2260 #interconnect-cells = <2>;
b303f9f0
DD		 2261 qcom,bcm-voters = <&apps_bcm_voter>;
2262 };
2263
2264 system_noc: interconnect@1620000 {
2265 compatible = "qcom,sdm845-system-noc";
2266 reg = <0 0x01620000 0 0x18080>;
7901c2bc 2267 #interconnect-cells = <2>;
b303f9f0
DD		 2268 qcom,bcm-voters = <&apps_bcm_voter>;
2269 };
2270
2271 aggre1_noc: interconnect@16e0000 {
2272 compatible = "qcom,sdm845-aggre1-noc";
2273 reg = <0 0x016e0000 0 0x15080>;
7901c2bc 2274 #interconnect-cells = <2>;
b303f9f0
DD		 2275 qcom,bcm-voters = <&apps_bcm_voter>;
2276 };
2277
2278 aggre2_noc: interconnect@1700000 {
2279 compatible = "qcom,sdm845-aggre2-noc";
2280 reg = <0 0x01700000 0 0x1f300>;
7901c2bc 2281 #interconnect-cells = <2>;
b303f9f0
DD		 2282 qcom,bcm-voters = <&apps_bcm_voter>;
2283 };
2284
2285 mmss_noc: interconnect@1740000 {
2286 compatible = "qcom,sdm845-mmss-noc";
2287 reg = <0 0x01740000 0 0x1c100>;
7901c2bc 2288 #interconnect-cells = <2>;
b303f9f0
DD		 2289 qcom,bcm-voters = <&apps_bcm_voter>;
2290 };
2291
cc16687f
EG		 2292 ufs_mem_hc: ufshc@1d84000 {
2293 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2294 "jedec,ufs-2.0";
433f9a57
EB		 2295 reg = <0 0x01d84000 0 0x2500>,
2296 <0 0x01d90000 0 0x8000>;
2297 reg-names = "std", "ice";
cc16687f
EG		 2298 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2299 phys = <&ufs_mem_phy_lanes>;
2300 phy-names = "ufsphy";
2301 lanes-per-direction = <2>;
2302 power-domains = <&gcc UFS_PHY_GDSC>;
71278b05 2303 #reset-cells = <1>;
a8aa481a
VK		 2304 resets = <&gcc GCC_UFS_PHY_BCR>;
2305 reset-names = "rst";
cc16687f
EG		 2306
2307 iommus = <&apps_smmu 0x100 0xf>;
2308
2309 clock-names =
2310 "core_clk",
2311 "bus_aggr_clk",
2312 "iface_clk",
2313 "core_clk_unipro",
2314 "ref_clk",
2315 "tx_lane0_sync_clk",
2316 "rx_lane0_sync_clk",
433f9a57
EB		 2317 "rx_lane1_sync_clk",
2318 "ice_core_clk";
cc16687f
EG		 2319 clocks =
2320 <&gcc GCC_UFS_PHY_AXI_CLK>,
2321 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2322 <&gcc GCC_UFS_PHY_AHB_CLK>,
2323 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2324 <&rpmhcc RPMH_CXO_CLK>,
2325 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2326 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
433f9a57
EB		 2327 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2328 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
cc16687f
EG		 2329 freq-table-hz =
2330 <50000000 200000000>,
2331 <0 0>,
2332 <0 0>,
2333 <37500000 150000000>,
2334 <0 0>,
2335 <0 0>,
2336 <0 0>,
433f9a57
EB		 2337 <0 0>,
2338 <0 300000000>;
cc16687f
EG		 2339
2340 status = "disabled";
2341 };
2342
2343 ufs_mem_phy: phy@1d87000 {
2344 compatible = "qcom,sdm845-qmp-ufs-phy";
bede7d2d
BA		 2345 reg = <0 0x01d87000 0 0x18c>;
2346 #address-cells = <2>;
2347 #size-cells = <2>;
cc16687f
EG		 2348 ranges;
2349 clock-names = "ref",
2350 "ref_aux";
2351 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2352 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2353
71278b05
EG		 2354 resets = <&ufs_mem_hc 0>;
2355 reset-names = "ufsphy";
cc16687f
EG		 2356 status = "disabled";
2357
1351512f 2358 ufs_mem_phy_lanes: phy@1d87400 {
bede7d2d
BA		 2359 reg = <0 0x01d87400 0 0x108>,
2360 <0 0x01d87600 0 0x1e0>,
2361 <0 0x01d87c00 0 0x1dc>,
2362 <0 0x01d87800 0 0x108>,
2363 <0 0x01d87a00 0 0x1e0>;
cc16687f
EG		 2364 #phy-cells = <0>;
2365 };
2366 };
2367
bbef0142 2368 cryptobam: dma-controller@1dc4000 {
3e482859
TG		 2369 compatible = "qcom,bam-v1.7.0";
2370 reg = <0 0x01dc4000 0 0x24000>;
2371 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
eed1d9b6 2372 clocks = <&rpmhcc RPMH_CE_CLK>;
3e482859
TG		 2373 clock-names = "bam_clk";
2374 #dma-cells = <1>;
2375 qcom,ee = <0>;
1c8bf398 2376 qcom,controlled-remotely;
3e482859
TG		 2377 iommus = <&apps_smmu 0x704 0x1>,
2378 <&apps_smmu 0x706 0x1>,
2379 <&apps_smmu 0x714 0x1>,
2380 <&apps_smmu 0x716 0x1>;
2381 };
2382
2383 crypto: crypto@1dfa000 {
2384 compatible = "qcom,crypto-v5.4";
2385 reg = <0 0x01dfa000 0 0x6000>;
2386 clocks = <&gcc GCC_CE1_AHB_CLK>,
d5240f8e 2387 <&gcc GCC_CE1_AXI_CLK>,
eed1d9b6 2388 <&rpmhcc RPMH_CE_CLK>;
3e482859
TG		 2389 clock-names = "iface", "bus", "core";
2390 dmas = <&cryptobam 6>, <&cryptobam 7>;
2391 dma-names = "rx", "tx";
2392 iommus = <&apps_smmu 0x704 0x1>,
2393 <&apps_smmu 0x706 0x1>,
2394 <&apps_smmu 0x714 0x1>,
2395 <&apps_smmu 0x716 0x1>;
2396 };
2397
392a5855
AE		 2398 ipa: ipa@1e40000 {
2399 compatible = "qcom,sdm845-ipa";
e9e89c45 2400
95e6f846
BA		 2401 iommus = <&apps_smmu 0x720 0x0>,
2402 <&apps_smmu 0x722 0x0>;
392a5855
AE		 2403 reg = <0 0x1e40000 0 0x7000>,
2404 <0 0x1e47000 0 0x2000>,
2405 <0 0x1e04000 0 0x2c000>;
2406 reg-names = "ipa-reg",
2407 "ipa-shared",
2408 "gsi";
2409
0fc0f4b6
AE		 2410 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2411 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
392a5855
AE		 2412 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2413 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2414 interrupt-names = "ipa",
2415 "gsi",
2416 "ipa-clock-query",
2417 "ipa-setup-ready";
2418
2419 clocks = <&rpmhcc RPMH_IPA_CLK>;
2420 clock-names = "core";
2421
7901c2bc
GD		 2422 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2423 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2424 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
392a5855
AE		 2425 interconnect-names = "memory",
2426 "imem",
2427 "config";
2428
2429 qcom,smem-states = <&ipa_smp2p_out 0>,
2430 <&ipa_smp2p_out 1>;
2431 qcom,smem-state-names = "ipa-clock-enabled-valid",
2432 "ipa-clock-enabled";
2433
392a5855
AE		 2434 status = "disabled";
2435 };
2436
54d7a20d
DA		 2437 tcsr_mutex_regs: syscon@1f40000 {
2438 compatible = "syscon";
bede7d2d 2439 reg = <0 0x01f40000 0 0x40000>;
54d7a20d
DA		 2440 };
2441
2442 tlmm: pinctrl@3400000 {
2443 compatible = "qcom,sdm845-pinctrl";
bede7d2d 2444 reg = <0 0x03400000 0 0xc00000>;
54d7a20d
DA		 2445 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2446 gpio-controller;
2447 #gpio-cells = <2>;
2448 interrupt-controller;
2449 #interrupt-cells = <2>;
02058fc3 2450 gpio-ranges = <&tlmm 0 0 151>;
aeae948f 2451 wakeup-parent = <&pdc_intc>;
897cf34e 2452
07484de3
RF		 2453 cci0_default: cci0-default {
2454 /* SDA, SCL */
2455 pins = "gpio17", "gpio18";
2456 function = "cci_i2c";
2457
2458 bias-pull-up;
2459 drive-strength = <2>; /* 2 mA */
2460 };
2461
2462 cci0_sleep: cci0-sleep {
2463 /* SDA, SCL */
2464 pins = "gpio17", "gpio18";
2465 function = "cci_i2c";
2466
2467 drive-strength = <2>; /* 2 mA */
2468 bias-pull-down;
2469 };
2470
2471 cci1_default: cci1-default {
2472 /* SDA, SCL */
2473 pins = "gpio19", "gpio20";
2474 function = "cci_i2c";
2475
2476 bias-pull-up;
2477 drive-strength = <2>; /* 2 mA */
2478 };
2479
2480 cci1_sleep: cci1-sleep {
2481 /* SDA, SCL */
2482 pins = "gpio19", "gpio20";
2483 function = "cci_i2c";
2484
2485 drive-strength = <2>; /* 2 mA */
2486 bias-pull-down;
2487 };
2488
e1ce8539
DA		 2489 qspi_clk: qspi-clk {
2490 pinmux {
2491 pins = "gpio95";
2492 function = "qspi_clk";
2493 };
2494 };
2495
2496 qspi_cs0: qspi-cs0 {
2497 pinmux {
2498 pins = "gpio90";
2499 function = "qspi_cs";
2500 };
2501 };
2502
2503 qspi_cs1: qspi-cs1 {
2504 pinmux {
2505 pins = "gpio89";
2506 function = "qspi_cs";
2507 };
2508 };
2509
2510 qspi_data01: qspi-data01 {
2511 pinmux-data {
2512 pins = "gpio91", "gpio92";
2513 function = "qspi_data";
2514 };
2515 };
2516
2517 qspi_data12: qspi-data12 {
2518 pinmux-data {
2519 pins = "gpio93", "gpio94";
2520 function = "qspi_data";
2521 };
2522 };
2523
897cf34e
DA		 2524 qup_i2c0_default: qup-i2c0-default {
2525 pinmux {
2526 pins = "gpio0", "gpio1";
2527 function = "qup0";
2528 };
2529 };
2530
2531 qup_i2c1_default: qup-i2c1-default {
2532 pinmux {
2533 pins = "gpio17", "gpio18";
2534 function = "qup1";
2535 };
2536 };
2537
2538 qup_i2c2_default: qup-i2c2-default {
2539 pinmux {
2540 pins = "gpio27", "gpio28";
2541 function = "qup2";
2542 };
2543 };
2544
2545 qup_i2c3_default: qup-i2c3-default {
2546 pinmux {
2547 pins = "gpio41", "gpio42";
2548 function = "qup3";
2549 };
2550 };
2551
2552 qup_i2c4_default: qup-i2c4-default {
2553 pinmux {
2554 pins = "gpio89", "gpio90";
2555 function = "qup4";
2556 };
2557 };
2558
2559 qup_i2c5_default: qup-i2c5-default {
2560 pinmux {
2561 pins = "gpio85", "gpio86";
2562 function = "qup5";
2563 };
2564 };
2565
2566 qup_i2c6_default: qup-i2c6-default {
2567 pinmux {
2568 pins = "gpio45", "gpio46";
2569 function = "qup6";
2570 };
2571 };
2572
2573 qup_i2c7_default: qup-i2c7-default {
2574 pinmux {
2575 pins = "gpio93", "gpio94";
2576 function = "qup7";
2577 };
2578 };
2579
2580 qup_i2c8_default: qup-i2c8-default {
2581 pinmux {
2582 pins = "gpio65", "gpio66";
2583 function = "qup8";
2584 };
2585 };
2586
2587 qup_i2c9_default: qup-i2c9-default {
2588 pinmux {
2589 pins = "gpio6", "gpio7";
2590 function = "qup9";
2591 };
2592 };
2593
2594 qup_i2c10_default: qup-i2c10-default {
2595 pinmux {
2596 pins = "gpio55", "gpio56";
2597 function = "qup10";
2598 };
2599 };
2600
2601 qup_i2c11_default: qup-i2c11-default {
2602 pinmux {
2603 pins = "gpio31", "gpio32";
2604 function = "qup11";
2605 };
2606 };
2607
2608 qup_i2c12_default: qup-i2c12-default {
2609 pinmux {
2610 pins = "gpio49", "gpio50";
2611 function = "qup12";
2612 };
2613 };
2614
2615 qup_i2c13_default: qup-i2c13-default {
2616 pinmux {
2617 pins = "gpio105", "gpio106";
2618 function = "qup13";
2619 };
2620 };
2621
2622 qup_i2c14_default: qup-i2c14-default {
2623 pinmux {
2624 pins = "gpio33", "gpio34";
2625 function = "qup14";
2626 };
2627 };
2628
2629 qup_i2c15_default: qup-i2c15-default {
2630 pinmux {
2631 pins = "gpio81", "gpio82";
2632 function = "qup15";
2633 };
2634 };
2635
2636 qup_spi0_default: qup-spi0-default {
2637 pinmux {
2638 pins = "gpio0", "gpio1",
2639 "gpio2", "gpio3";
2640 function = "qup0";
2641 };
8f6e20ad
VK		 2642
2643 config {
2644 pins = "gpio0", "gpio1",
2645 "gpio2", "gpio3";
2646 drive-strength = <6>;
2647 bias-disable;
2648 };
897cf34e
DA		 2649 };
2650
2651 qup_spi1_default: qup-spi1-default {
2652 pinmux {
2653 pins = "gpio17", "gpio18",
2654 "gpio19", "gpio20";
2655 function = "qup1";
2656 };
2657 };
2658
2659 qup_spi2_default: qup-spi2-default {
2660 pinmux {
2661 pins = "gpio27", "gpio28",
2662 "gpio29", "gpio30";
2663 function = "qup2";
2664 };
2665 };
2666
2667 qup_spi3_default: qup-spi3-default {
2668 pinmux {
2669 pins = "gpio41", "gpio42",
2670 "gpio43", "gpio44";
2671 function = "qup3";
2672 };
2673 };
2674
2675 qup_spi4_default: qup-spi4-default {
2676 pinmux {
2677 pins = "gpio89", "gpio90",
2678 "gpio91", "gpio92";
2679 function = "qup4";
2680 };
2681 };
2682
2683 qup_spi5_default: qup-spi5-default {
2684 pinmux {
2685 pins = "gpio85", "gpio86",
2686 "gpio87", "gpio88";
2687 function = "qup5";
2688 };
2689 };
2690
2691 qup_spi6_default: qup-spi6-default {
2692 pinmux {
2693 pins = "gpio45", "gpio46",
2694 "gpio47", "gpio48";
2695 function = "qup6";
2696 };
2697 };
2698
2699 qup_spi7_default: qup-spi7-default {
2700 pinmux {
2701 pins = "gpio93", "gpio94",
2702 "gpio95", "gpio96";
2703 function = "qup7";
2704 };
2705 };
2706
2707 qup_spi8_default: qup-spi8-default {
2708 pinmux {
2709 pins = "gpio65", "gpio66",
2710 "gpio67", "gpio68";
2711 function = "qup8";
2712 };
2713 };
2714
2715 qup_spi9_default: qup-spi9-default {
2716 pinmux {
2717 pins = "gpio6", "gpio7",
2718 "gpio4", "gpio5";
2719 function = "qup9";
2720 };
2721 };
2722
2723 qup_spi10_default: qup-spi10-default {
2724 pinmux {
2725 pins = "gpio55", "gpio56",
2726 "gpio53", "gpio54";
2727 function = "qup10";
2728 };
2729 };
2730
2731 qup_spi11_default: qup-spi11-default {
2732 pinmux {
2733 pins = "gpio31", "gpio32",
2734 "gpio33", "gpio34";
2735 function = "qup11";
2736 };
2737 };
2738
2739 qup_spi12_default: qup-spi12-default {
2740 pinmux {
2741 pins = "gpio49", "gpio50",
2742 "gpio51", "gpio52";
2743 function = "qup12";
2744 };
2745 };
2746
2747 qup_spi13_default: qup-spi13-default {
2748 pinmux {
2749 pins = "gpio105", "gpio106",
2750 "gpio107", "gpio108";
2751 function = "qup13";
2752 };
2753 };
2754
2755 qup_spi14_default: qup-spi14-default {
2756 pinmux {
2757 pins = "gpio33", "gpio34",
2758 "gpio31", "gpio32";
2759 function = "qup14";
2760 };
2761 };
2762
2763 qup_spi15_default: qup-spi15-default {
2764 pinmux {
2765 pins = "gpio81", "gpio82",
2766 "gpio83", "gpio84";
2767 function = "qup15";
2768 };
2769 };
2770
bb2203d5
MK		 2771 qup_uart0_default: qup-uart0-default {
2772 pinmux {
2773 pins = "gpio2", "gpio3";
2774 function = "qup0";
2775 };
2776 };
2777
2778 qup_uart1_default: qup-uart1-default {
2779 pinmux {
2780 pins = "gpio19", "gpio20";
2781 function = "qup1";
2782 };
2783 };
2784
2785 qup_uart2_default: qup-uart2-default {
2786 pinmux {
2787 pins = "gpio29", "gpio30";
2788 function = "qup2";
2789 };
2790 };
2791
2792 qup_uart3_default: qup-uart3-default {
2793 pinmux {
2794 pins = "gpio43", "gpio44";
2795 function = "qup3";
2796 };
2797 };
2798
2799 qup_uart4_default: qup-uart4-default {
2800 pinmux {
2801 pins = "gpio91", "gpio92";
2802 function = "qup4";
2803 };
2804 };
2805
2806 qup_uart5_default: qup-uart5-default {
2807 pinmux {
2808 pins = "gpio87", "gpio88";
2809 function = "qup5";
2810 };
2811 };
2812
2813 qup_uart6_default: qup-uart6-default {
2814 pinmux {
2815 pins = "gpio47", "gpio48";
2816 function = "qup6";
2817 };
2818 };
2819
2820 qup_uart7_default: qup-uart7-default {
2821 pinmux {
2822 pins = "gpio95", "gpio96";
2823 function = "qup7";
2824 };
2825 };
2826
2827 qup_uart8_default: qup-uart8-default {
2828 pinmux {
2829 pins = "gpio67", "gpio68";
2830 function = "qup8";
2831 };
2832 };
2833
897cf34e
DA		 2834 qup_uart9_default: qup-uart9-default {
2835 pinmux {
2836 pins = "gpio4", "gpio5";
2837 function = "qup9";
2838 };
2839 };
bb2203d5
MK		 2840
2841 qup_uart10_default: qup-uart10-default {
2842 pinmux {
2843 pins = "gpio53", "gpio54";
2844 function = "qup10";
2845 };
2846 };
2847
2848 qup_uart11_default: qup-uart11-default {
2849 pinmux {
2850 pins = "gpio33", "gpio34";
2851 function = "qup11";
2852 };
2853 };
2854
2855 qup_uart12_default: qup-uart12-default {
2856 pinmux {
2857 pins = "gpio51", "gpio52";
2858 function = "qup12";
2859 };
2860 };
2861
2862 qup_uart13_default: qup-uart13-default {
2863 pinmux {
2864 pins = "gpio107", "gpio108";
2865 function = "qup13";
2866 };
2867 };
2868
2869 qup_uart14_default: qup-uart14-default {
2870 pinmux {
2871 pins = "gpio31", "gpio32";
2872 function = "qup14";
2873 };
2874 };
2875
2876 qup_uart15_default: qup-uart15-default {
2877 pinmux {
2878 pins = "gpio83", "gpio84";
2879 function = "qup15";
2880 };
2881 };
606057bd
SK		 2882
2883 quat_mi2s_sleep: quat_mi2s_sleep {
2884 mux {
2885 pins = "gpio58", "gpio59";
2886 function = "gpio";
2887 };
2888
2889 config {
2890 pins = "gpio58", "gpio59";
2891 drive-strength = <2>;
2892 bias-pull-down;
2893 input-enable;
2894 };
2895 };
2896
2897 quat_mi2s_active: quat_mi2s_active {
2898 mux {
2899 pins = "gpio58", "gpio59";
2900 function = "qua_mi2s";
2901 };
2902
2903 config {
2904 pins = "gpio58", "gpio59";
2905 drive-strength = <8>;
2906 bias-disable;
2907 output-high;
2908 };
2909 };
2910
2911 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2912 mux {
2913 pins = "gpio60";
2914 function = "gpio";
2915 };
2916
2917 config {
2918 pins = "gpio60";
2919 drive-strength = <2>;
2920 bias-pull-down;
2921 input-enable;
2922 };
2923 };
2924
2925 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2926 mux {
2927 pins = "gpio60";
2928 function = "qua_mi2s";
2929 };
2930
2931 config {
2932 pins = "gpio60";
2933 drive-strength = <8>;
2934 bias-disable;
2935 };
2936 };
2937
2938 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2939 mux {
2940 pins = "gpio61";
2941 function = "gpio";
2942 };
2943
2944 config {
2945 pins = "gpio61";
2946 drive-strength = <2>;
2947 bias-pull-down;
2948 input-enable;
2949 };
2950 };
2951
2952 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2953 mux {
2954 pins = "gpio61";
2955 function = "qua_mi2s";
2956 };
2957
2958 config {
2959 pins = "gpio61";
2960 drive-strength = <8>;
2961 bias-disable;
2962 };
2963 };
2964
2965 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2966 mux {
2967 pins = "gpio62";
2968 function = "gpio";
2969 };
2970
2971 config {
2972 pins = "gpio62";
2973 drive-strength = <2>;
2974 bias-pull-down;
2975 input-enable;
2976 };
2977 };
2978
2979 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2980 mux {
2981 pins = "gpio62";
2982 function = "qua_mi2s";
2983 };
2984
2985 config {
2986 pins = "gpio62";
2987 drive-strength = <8>;
2988 bias-disable;
2989 };
2990 };
2991
2992 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2993 mux {
2994 pins = "gpio63";
2995 function = "gpio";
2996 };
2997
2998 config {
2999 pins = "gpio63";
3000 drive-strength = <2>;
3001 bias-pull-down;
3002 input-enable;
3003 };
3004 };
3005
3006 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3007 mux {
3008 pins = "gpio63";
3009 function = "qua_mi2s";
3010 };
3011
3012 config {
3013 pins = "gpio63";
3014 drive-strength = <8>;
3015 bias-disable;
3016 };
3017 };
54d7a20d
DA		 3018 };
3019
e76c3672
SS		 3020 mss_pil: remoteproc@4080000 {
3021 compatible = "qcom,sdm845-mss-pil";
3022 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3023 reg-names = "qdsp6", "rmb";
3024
3025 interrupts-extended =
3026 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3027 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3028 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3029 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3030 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3031 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3032 interrupt-names = "wdog", "fatal", "ready",
3033 "handover", "stop-ack",
3034 "shutdown-ack";
3035
3036 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3037 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3038 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3039 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3040 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3041 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3042 <&gcc GCC_PRNG_AHB_CLK>,
3043 <&rpmhcc RPMH_CXO_CLK>;
3044 clock-names = "iface", "bus", "mem", "gpll0_mss",
3045 "snoc_axi", "mnoc_axi", "prng", "xo";
3046
db8e45a8
SS		 3047 qcom,qmp = <&aoss_qmp>;
3048
e76c3672
SS		 3049 qcom,smem-states = <&modem_smp2p_out 0>;
3050 qcom,smem-state-names = "stop";
3051
3052 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3053 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3054 reset-names = "mss_restart", "pdc_reset";
3055
3056 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3057
db8e45a8 3058 power-domains = <&rpmhpd SDM845_CX>,
e76c3672
SS		 3059 <&rpmhpd SDM845_MX>,
3060 <&rpmhpd SDM845_MSS>;
db8e45a8 3061 power-domain-names = "cx", "mx", "mss";
e76c3672 3062
7f761609 3063 status = "disabled";
e76c3672
SS		 3064
3065 mba {
3066 memory-region = <&mba_region>;
3067 };
3068
3069 mpss {
3070 memory-region = <&mpss_region>;
3071 };
3072
3073 glink-edge {
3074 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3075 label = "modem";
3076 qcom,remote-pid = <1>;
3077 mboxes = <&apss_shared 12>;
3078 };
3079 };
3080
9aa4a27e
DA		 3081 gpucc: clock-controller@5090000 {
3082 compatible = "qcom,sdm845-gpucc";
bede7d2d 3083 reg = <0 0x05090000 0 0x9000>;
9aa4a27e
DA		 3084 #clock-cells = <1>;
3085 #reset-cells = <1>;
3086 #power-domain-cells = <1>;
bb2bd9bf
DA		 3087 clocks = <&rpmhcc RPMH_CXO_CLK>,
3088 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3089 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3090 clock-names = "bi_tcxo",
3091 "gcc_gpu_gpll0_clk_src",
3092 "gcc_gpu_gpll0_div_clk_src";
9aa4a27e
DA		 3093 };
3094
ed7d6110
SPR		 3095 stm@6002000 {
3096 compatible = "arm,coresight-stm", "arm,primecell";
3097 reg = <0 0x06002000 0 0x1000>,
3098 <0 0x16280000 0 0x180000>;
3099 reg-names = "stm-base", "stm-stimulus-base";
3100
3101 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pclk";
3103
3104 out-ports {
3105 port {
3106 stm_out: endpoint {
3107 remote-endpoint =
3108 <&funnel0_in7>;
3109 };
3110 };
3111 };
3112 };
3113
3114 funnel@6041000 {
3115 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3116 reg = <0 0x06041000 0 0x1000>;
3117
3118 clocks = <&aoss_qmp>;
3119 clock-names = "apb_pclk";
3120
3121 out-ports {
3122 port {
3123 funnel0_out: endpoint {
3124 remote-endpoint =
3125 <&merge_funnel_in0>;
3126 };
3127 };
3128 };
3129
3130 in-ports {
3131 #address-cells = <1>;
3132 #size-cells = <0>;
3133
3134 port@7 {
3135 reg = <7>;
3136 funnel0_in7: endpoint {
3137 remote-endpoint = <&stm_out>;
3138 };
3139 };
3140 };
3141 };
3142
3143 funnel@6043000 {
3144 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3145 reg = <0 0x06043000 0 0x1000>;
3146
3147 clocks = <&aoss_qmp>;
3148 clock-names = "apb_pclk";
3149
3150 out-ports {
3151 port {
3152 funnel2_out: endpoint {
3153 remote-endpoint =
3154 <&merge_funnel_in2>;
3155 };
3156 };
3157 };
3158
3159 in-ports {
3160 #address-cells = <1>;
3161 #size-cells = <0>;
3162
3163 port@5 {
3164 reg = <5>;
3165 funnel2_in5: endpoint {
3166 remote-endpoint =
3167 <&apss_merge_funnel_out>;
3168 };
3169 };
3170 };
3171 };
3172
3173 funnel@6045000 {
3174 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3175 reg = <0 0x06045000 0 0x1000>;
3176
3177 clocks = <&aoss_qmp>;
3178 clock-names = "apb_pclk";
3179
3180 out-ports {
3181 port {
3182 merge_funnel_out: endpoint {
3183 remote-endpoint = <&etf_in>;
3184 };
3185 };
3186 };
3187
3188 in-ports {
3189 #address-cells = <1>;
3190 #size-cells = <0>;
3191
3192 port@0 {
3193 reg = <0>;
3194 merge_funnel_in0: endpoint {
3195 remote-endpoint =
3196 <&funnel0_out>;
3197 };
3198 };
3199
3200 port@2 {
3201 reg = <2>;
3202 merge_funnel_in2: endpoint {
3203 remote-endpoint =
3204 <&funnel2_out>;
3205 };
3206 };
3207 };
3208 };
3209
3210 replicator@6046000 {
3211 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3212 reg = <0 0x06046000 0 0x1000>;
3213
3214 clocks = <&aoss_qmp>;
3215 clock-names = "apb_pclk";
3216
3217 out-ports {
3218 port {
3219 replicator_out: endpoint {
3220 remote-endpoint = <&etr_in>;
3221 };
3222 };
3223 };
3224
3225 in-ports {
3226 port {
3227 replicator_in: endpoint {
3228 remote-endpoint = <&etf_out>;
3229 };
3230 };
3231 };
3232 };
3233
3234 etf@6047000 {
3235 compatible = "arm,coresight-tmc", "arm,primecell";
3236 reg = <0 0x06047000 0 0x1000>;
3237
3238 clocks = <&aoss_qmp>;
3239 clock-names = "apb_pclk";
3240
3241 out-ports {
3242 port {
3243 etf_out: endpoint {
3244 remote-endpoint =
3245 <&replicator_in>;
3246 };
3247 };
3248 };
3249
3250 in-ports {
3251 #address-cells = <1>;
3252 #size-cells = <0>;
3253
3254 port@1 {
3255 reg = <1>;
3256 etf_in: endpoint {
3257 remote-endpoint =
3258 <&merge_funnel_out>;
3259 };
3260 };
3261 };
3262 };
3263
3264 etr@6048000 {
3265 compatible = "arm,coresight-tmc", "arm,primecell";
3266 reg = <0 0x06048000 0 0x1000>;
3267
3268 clocks = <&aoss_qmp>;
3269 clock-names = "apb_pclk";
3270 arm,scatter-gather;
3271
3272 in-ports {
3273 port {
3274 etr_in: endpoint {
3275 remote-endpoint =
3276 <&replicator_out>;
3277 };
3278 };
3279 };
3280 };
3281
3282 etm@7040000 {
3283 compatible = "arm,coresight-etm4x", "arm,primecell";
3284 reg = <0 0x07040000 0 0x1000>;
3285
3286 cpu = <&CPU0>;
3287
3288 clocks = <&aoss_qmp>;
3289 clock-names = "apb_pclk";
4a183020 3290 arm,coresight-loses-context-with-cpu;
ed7d6110
SPR		 3291
3292 out-ports {
3293 port {
3294 etm0_out: endpoint {
3295 remote-endpoint =
3296 <&apss_funnel_in0>;
3297 };
3298 };
3299 };
3300 };
3301
3302 etm@7140000 {
3303 compatible = "arm,coresight-etm4x", "arm,primecell";
3304 reg = <0 0x07140000 0 0x1000>;
3305
3306 cpu = <&CPU1>;
3307
3308 clocks = <&aoss_qmp>;
3309 clock-names = "apb_pclk";
4a183020 3310 arm,coresight-loses-context-with-cpu;
ed7d6110
SPR		 3311
3312 out-ports {
3313 port {
3314 etm1_out: endpoint {
3315 remote-endpoint =
3316 <&apss_funnel_in1>;
3317 };
3318 };
3319 };
3320 };
3321
3322 etm@7240000 {
3323 compatible = "arm,coresight-etm4x", "arm,primecell";
3324 reg = <0 0x07240000 0 0x1000>;
3325
3326 cpu = <&CPU2>;
3327
3328 clocks = <&aoss_qmp>;
3329 clock-names = "apb_pclk";
4a183020 3330 arm,coresight-loses-context-with-cpu;
ed7d6110
SPR		 3331
3332 out-ports {
3333 port {
3334 etm2_out: endpoint {
3335 remote-endpoint =
3336 <&apss_funnel_in2>;
3337 };
3338 };
3339 };
3340 };
3341
3342 etm@7340000 {
3343 compatible = "arm,coresight-etm4x", "arm,primecell";
3344 reg = <0 0x07340000 0 0x1000>;
3345
3346 cpu = <&CPU3>;
3347
3348 clocks = <&aoss_qmp>;
3349 clock-names = "apb_pclk";
4a183020 3350 arm,coresight-loses-context-with-cpu;
ed7d6110
SPR		 3351
3352 out-ports {
3353 port {
3354 etm3_out: endpoint {
3355 remote-endpoint =
3356 <&apss_funnel_in3>;
3357 };
3358 };
3359 };
3360 };
3361
3362 etm@7440000 {
3363 compatible = "arm,coresight-etm4x", "arm,primecell";
3364 reg = <0 0x07440000 0 0x1000>;
3365
3366 cpu = <&CPU4>;
3367
3368 clocks = <&aoss_qmp>;
3369 clock-names = "apb_pclk";
4a183020 3370 arm,coresight-loses-context-with-cpu;
ed7d6110
SPR		 3371
3372 out-ports {
3373 port {
3374 etm4_out: endpoint {
3375 remote-endpoint =
3376 <&apss_funnel_in4>;
3377 };
3378 };
3379 };
3380 };
3381
3382 etm@7540000 {
3383 compatible = "arm,coresight-etm4x", "arm,primecell";
3384 reg = <0 0x07540000 0 0x1000>;
3385
3386 cpu = <&CPU5>;
3387
3388 clocks = <&aoss_qmp>;
3389 clock-names = "apb_pclk";
4a183020 3390 arm,coresight-loses-context-with-cpu;
ed7d6110
SPR		 3391
3392 out-ports {
3393 port {
3394 etm5_out: endpoint {
3395 remote-endpoint =
3396 <&apss_funnel_in5>;
3397 };
3398 };
3399 };
3400 };
3401
3402 etm@7640000 {
3403 compatible = "arm,coresight-etm4x", "arm,primecell";
3404 reg = <0 0x07640000 0 0x1000>;
3405
3406 cpu = <&CPU6>;
3407
3408 clocks = <&aoss_qmp>;
3409 clock-names = "apb_pclk";
4a183020 3410 arm,coresight-loses-context-with-cpu;
ed7d6110
SPR		 3411
3412 out-ports {
3413 port {
3414 etm6_out: endpoint {
3415 remote-endpoint =
3416 <&apss_funnel_in6>;
3417 };
3418 };
3419 };
3420 };
3421
3422 etm@7740000 {
3423 compatible = "arm,coresight-etm4x", "arm,primecell";
3424 reg = <0 0x07740000 0 0x1000>;
3425
3426 cpu = <&CPU7>;
3427
3428 clocks = <&aoss_qmp>;
3429 clock-names = "apb_pclk";
4a183020 3430 arm,coresight-loses-context-with-cpu;
ed7d6110
SPR		 3431
3432 out-ports {
3433 port {
3434 etm7_out: endpoint {
3435 remote-endpoint =
3436 <&apss_funnel_in7>;
3437 };
3438 };
3439 };
3440 };
3441
3442 funnel@7800000 { /* APSS Funnel */
3443 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3444 reg = <0 0x07800000 0 0x1000>;
3445
3446 clocks = <&aoss_qmp>;
3447 clock-names = "apb_pclk";
3448
3449 out-ports {
3450 port {
3451 apss_funnel_out: endpoint {
3452 remote-endpoint =
3453 <&apss_merge_funnel_in>;
3454 };
3455 };
3456 };
3457
3458 in-ports {
3459 #address-cells = <1>;
3460 #size-cells = <0>;
3461
3462 port@0 {
3463 reg = <0>;
3464 apss_funnel_in0: endpoint {
3465 remote-endpoint =
3466 <&etm0_out>;
3467 };
3468 };
3469
3470 port@1 {
3471 reg = <1>;
3472 apss_funnel_in1: endpoint {
3473 remote-endpoint =
3474 <&etm1_out>;
3475 };
3476 };
3477
3478 port@2 {
3479 reg = <2>;
3480 apss_funnel_in2: endpoint {
3481 remote-endpoint =
3482 <&etm2_out>;
3483 };
3484 };
3485
3486 port@3 {
3487 reg = <3>;
3488 apss_funnel_in3: endpoint {
3489 remote-endpoint =
3490 <&etm3_out>;
3491 };
3492 };
3493
3494 port@4 {
3495 reg = <4>;
3496 apss_funnel_in4: endpoint {
3497 remote-endpoint =
3498 <&etm4_out>;
3499 };
3500 };
3501
3502 port@5 {
3503 reg = <5>;
3504 apss_funnel_in5: endpoint {
3505 remote-endpoint =
3506 <&etm5_out>;
3507 };
3508 };
3509
3510 port@6 {
3511 reg = <6>;
3512 apss_funnel_in6: endpoint {
3513 remote-endpoint =
3514 <&etm6_out>;
3515 };
3516 };
3517
3518 port@7 {
3519 reg = <7>;
3520 apss_funnel_in7: endpoint {
3521 remote-endpoint =
3522 <&etm7_out>;
3523 };
3524 };
3525 };
3526 };
3527
3528 funnel@7810000 {
3529 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3530 reg = <0 0x07810000 0 0x1000>;
3531
3532 clocks = <&aoss_qmp>;
3533 clock-names = "apb_pclk";
3534
3535 out-ports {
3536 port {
3537 apss_merge_funnel_out: endpoint {
3538 remote-endpoint =
3539 <&funnel2_in5>;
3540 };
3541 };
3542 };
3543
3544 in-ports {
3545 port {
3546 apss_merge_funnel_in: endpoint {
3547 remote-endpoint =
3548 <&apss_funnel_out>;
3549 };
3550 };
3551 };
3552 };
3553
67d62e5a
EG		 3554 sdhc_2: sdhci@8804000 {
3555 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
bede7d2d 3556 reg = <0 0x08804000 0 0x1000>;
67d62e5a
EG		 3557
3558 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3560 interrupt-names = "hc_irq", "pwr_irq";
3561
3562 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
d87e9a4d
KD		 3563 <&gcc GCC_SDCC2_APPS_CLK>,
3564 <&rpmhcc RPMH_CXO_CLK>;
3565 clock-names = "iface", "core", "xo";
55fae1d5 3566 iommus = <&apps_smmu 0xa0 0xf>;
6123e744
RN		 3567 power-domains = <&rpmhpd SDM845_CX>;
3568 operating-points-v2 = <&sdhc2_opp_table>;
67d62e5a
EG		 3569
3570 status = "disabled";
6123e744
RN		 3571
3572 sdhc2_opp_table: sdhc2-opp-table {
3573 compatible = "operating-points-v2";
3574
3575 opp-9600000 {
3576 opp-hz = /bits/ 64 <9600000>;
3577 required-opps = <&rpmhpd_opp_min_svs>;
3578 };
3579
3580 opp-19200000 {
3581 opp-hz = /bits/ 64 <19200000>;
3582 required-opps = <&rpmhpd_opp_low_svs>;
3583 };
3584
3585 opp-100000000 {
3586 opp-hz = /bits/ 64 <100000000>;
3587 required-opps = <&rpmhpd_opp_svs>;
3588 };
3589
3590 opp-201500000 {
3591 opp-hz = /bits/ 64 <201500000>;
3592 required-opps = <&rpmhpd_opp_svs_l1>;
3593 };
3594 };
67d62e5a
EG		 3595 };
3596
5b4de2f8
RN		 3597 qspi_opp_table: qspi-opp-table {
3598 compatible = "operating-points-v2";
3599
3600 opp-19200000 {
3601 opp-hz = /bits/ 64 <19200000>;
3602 required-opps = <&rpmhpd_opp_min_svs>;
3603 };
3604
3605 opp-100000000 {
3606 opp-hz = /bits/ 64 <100000000>;
3607 required-opps = <&rpmhpd_opp_low_svs>;
3608 };
3609
3610 opp-150000000 {
3611 opp-hz = /bits/ 64 <150000000>;
3612 required-opps = <&rpmhpd_opp_svs>;
3613 };
3614
3615 opp-300000000 {
3616 opp-hz = /bits/ 64 <300000000>;
3617 required-opps = <&rpmhpd_opp_nom>;
3618 };
3619 };
3620
e1ce8539
DA		 3621 qspi: spi@88df000 {
3622 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
bede7d2d 3623 reg = <0 0x088df000 0 0x600>;
e1ce8539
DA		 3624 #address-cells = <1>;
3625 #size-cells = <0>;
3626 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3627 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3628 <&gcc GCC_QSPI_CORE_CLK>;
3629 clock-names = "iface", "core";
5b4de2f8
RN		 3630 power-domains = <&rpmhpd SDM845_CX>;
3631 operating-points-v2 = <&qspi_opp_table>;
e1ce8539
DA		 3632 status = "disabled";
3633 };
3634
27ca1de0
SK		 3635 slim: slim@171c0000 {
3636 compatible = "qcom,slim-ngd-v2.1.0";
3637 reg = <0 0x171c0000 0 0x2c000>;
3638 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3639
3640 qcom,apps-ch-pipes = <0x780000>;
3641 qcom,ea-pc = <0x270>;
3642 status = "okay";
3643 dmas = <&slimbam 3>, <&slimbam 4>,
3644 <&slimbam 5>, <&slimbam 6>;
3645 dma-names = "rx", "tx", "tx2", "rx2";
3646
3647 iommus = <&apps_smmu 0x1806 0x0>;
3648 #address-cells = <1>;
3649 #size-cells = <0>;
3650
3651 ngd@1 {
3652 reg = <1>;
3653 #address-cells = <2>;
3654 #size-cells = <0>;
3655
3656 wcd9340_ifd: ifd@0{
3657 compatible = "slim217,250";
3658 reg = <0 0>;
3659 };
3660
3661 wcd9340: codec@1{
3662 compatible = "slim217,250";
3663 reg = <1 0>;
3664 slim-ifc-dev = <&wcd9340_ifd>;
3665
3666 #sound-dai-cells = <1>;
3667
3668 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3669 interrupt-controller;
3670 #interrupt-cells = <1>;
3671
3672 #clock-cells = <0>;
3673 clock-frequency = <9600000>;
3674 clock-output-names = "mclk";
625c2446
DH		 3675 qcom,micbias1-microvolt = <1800000>;
3676 qcom,micbias2-microvolt = <1800000>;
3677 qcom,micbias3-microvolt = <1800000>;
3678 qcom,micbias4-microvolt = <1800000>;
27ca1de0
SK		 3679
3680 #address-cells = <1>;
3681 #size-cells = <1>;
3682
3683 wcdgpio: gpio-controller@42 {
3684 compatible = "qcom,wcd9340-gpio";
3685 gpio-controller;
3686 #gpio-cells = <2>;
3687 reg = <0x42 0x2>;
3688 };
3689
3690 swm: swm@c85 {
3691 compatible = "qcom,soundwire-v1.3.0";
3692 reg = <0xc85 0x40>;
3693 interrupts-extended = <&wcd9340 20>;
3694
3695 qcom,dout-ports = <6>;
3696 qcom,din-ports = <2>;
3697 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3698 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3699 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3700
3701 #sound-dai-cells = <1>;
3702 clocks = <&wcd9340>;
3703 clock-names = "iface";
3704 #address-cells = <2>;
3705 #size-cells = <0>;
3706
3707
3708 };
3709 };
3710 };
3711 };
3712
36c65812
TG		 3713 lmh_cluster1: lmh@17d70800 {
3714 compatible = "qcom,sdm845-lmh";
3715 reg = <0 0x17d70800 0 0x400>;
3716 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3717 cpus = <&CPU4>;
3718 qcom,lmh-temp-arm-millicelsius = <65000>;
3719 qcom,lmh-temp-low-millicelsius = <94500>;
3720 qcom,lmh-temp-high-millicelsius = <95000>;
3721 interrupt-controller;
3722 #interrupt-cells = <1>;
3723 };
3724
3725 lmh_cluster0: lmh@17d78800 {
3726 compatible = "qcom,sdm845-lmh";
3727 reg = <0 0x17d78800 0 0x400>;
3728 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3729 cpus = <&CPU0>;
3730 qcom,lmh-temp-arm-millicelsius = <65000>;
3731 qcom,lmh-temp-low-millicelsius = <94500>;
3732 qcom,lmh-temp-high-millicelsius = <95000>;
3733 interrupt-controller;
3734 #interrupt-cells = <1>;
3735 };
3736
27ca1de0
SK		 3737 sound: sound {
3738 };
3739
ca4db2b5 3740 usb_1_hsphy: phy@88e2000 {
d724b42e 3741 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
bede7d2d 3742 reg = <0 0x088e2000 0 0x400>;
ca4db2b5
MG		 3743 status = "disabled";
3744 #phy-cells = <0>;
3745
3746 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3747 <&rpmhcc RPMH_CXO_CLK>;
3748 clock-names = "cfg_ahb", "ref";
3749
3750 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3751
3752 nvmem-cells = <&qusb2p_hstx_trim>;
3753 };
3754
3755 usb_2_hsphy: phy@88e3000 {
d724b42e 3756 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
bede7d2d 3757 reg = <0 0x088e3000 0 0x400>;
ca4db2b5
MG		 3758 status = "disabled";
3759 #phy-cells = <0>;
3760
3761 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3762 <&rpmhcc RPMH_CXO_CLK>;
3763 clock-names = "cfg_ahb", "ref";
3764
3765 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3766
3767 nvmem-cells = <&qusb2s_hstx_trim>;
3768 };
3769
3770 usb_1_qmpphy: phy@88e9000 {
3771 compatible = "qcom,sdm845-qmp-usb3-phy";
bede7d2d
BA		 3772 reg = <0 0x088e9000 0 0x18c>,
3773 <0 0x088e8000 0 0x10>;
ca4db2b5 3774 status = "disabled";
bede7d2d
BA		 3775 #address-cells = <2>;
3776 #size-cells = <2>;
ca4db2b5
MG		 3777 ranges;
3778
3779 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3780 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3781 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3782 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3783 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3784
3785 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3786 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3787 reset-names = "phy", "common";
3788
1351512f 3789 usb_1_ssphy: phy@88e9200 {
bede7d2d
BA		 3790 reg = <0 0x088e9200 0 0x128>,
3791 <0 0x088e9400 0 0x200>,
3792 <0 0x088e9c00 0 0x218>,
3793 <0 0x088e9600 0 0x128>,
3794 <0 0x088e9800 0 0x200>,
3795 <0 0x088e9a00 0 0x100>;
7178d4cc 3796 #clock-cells = <0>;
ca4db2b5
MG		 3797 #phy-cells = <0>;
3798 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3799 clock-names = "pipe0";
3800 clock-output-names = "usb3_phy_pipe_clk_src";
3801 };
3802 };
3803
3804 usb_2_qmpphy: phy@88eb000 {
3805 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
bede7d2d 3806 reg = <0 0x088eb000 0 0x18c>;
ca4db2b5 3807 status = "disabled";
bede7d2d
BA		 3808 #address-cells = <2>;
3809 #size-cells = <2>;
ca4db2b5
MG		 3810 ranges;
3811
3812 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3813 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3814 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3815 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3816 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3817
3818 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3819 <&gcc GCC_USB3_PHY_SEC_BCR>;
3820 reset-names = "phy", "common";
3821
1351512f 3822 usb_2_ssphy: phy@88eb200 {
bede7d2d
BA		 3823 reg = <0 0x088eb200 0 0x128>,
3824 <0 0x088eb400 0 0x1fc>,
3825 <0 0x088eb800 0 0x218>,
3826 <0 0x088eb600 0 0x70>;
7178d4cc 3827 #clock-cells = <0>;
ca4db2b5
MG		 3828 #phy-cells = <0>;
3829 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3830 clock-names = "pipe0";
3831 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3832 };
3833 };
3834
3835 usb_1: usb@a6f8800 {
3836 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
bede7d2d 3837 reg = <0 0x0a6f8800 0 0x400>;
ca4db2b5 3838 status = "disabled";
bede7d2d
BA		 3839 #address-cells = <2>;
3840 #size-cells = <2>;
ca4db2b5 3841 ranges;
9a8a9d17 3842 dma-ranges;
ca4db2b5
MG		 3843
3844 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3845 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3846 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3847 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3848 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3849 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3850 "sleep";
3851
3852 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3853 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3854 assigned-clock-rates = <19200000>, <150000000>;
3855
3856 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3857 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3858 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3859 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3860 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3861 "dm_hs_phy_irq", "dp_hs_phy_irq";
3862
3863 power-domains = <&gcc USB30_PRIM_GDSC>;
3864
3865 resets = <&gcc GCC_USB30_PRIM_BCR>;
3866
7901c2bc
GD		 3867 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3868 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
11a8b115
SM		 3869 interconnect-names = "usb-ddr", "apps-usb";
3870
1f958f3d 3871 usb_1_dwc3: dwc3@a600000 {
ca4db2b5 3872 compatible = "snps,dwc3";
bede7d2d 3873 reg = <0 0x0a600000 0 0xcd00>;
ca4db2b5 3874 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
9a8a9d17 3875 iommus = <&apps_smmu 0x740 0>;
ca4db2b5
MG		 3876 snps,dis_u2_susphy_quirk;
3877 snps,dis_enblslpm_quirk;
3878 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3879 phy-names = "usb2-phy", "usb3-phy";
3880 };
3881 };
3882
3883 usb_2: usb@a8f8800 {
3884 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
bede7d2d 3885 reg = <0 0x0a8f8800 0 0x400>;
ca4db2b5 3886 status = "disabled";
bede7d2d
BA		 3887 #address-cells = <2>;
3888 #size-cells = <2>;
ca4db2b5 3889 ranges;
9a8a9d17 3890 dma-ranges;
ca4db2b5
MG		 3891
3892 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3893 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3894 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3895 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3896 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3897 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3898 "sleep";
3899
3900 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3901 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3902 assigned-clock-rates = <19200000>, <150000000>;
3903
3904 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3905 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3906 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3907 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3908 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3909 "dm_hs_phy_irq", "dp_hs_phy_irq";
3910
3911 power-domains = <&gcc USB30_SEC_GDSC>;
3912
3913 resets = <&gcc GCC_USB30_SEC_BCR>;
3914
7901c2bc
GD		 3915 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3916 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
11a8b115
SM		 3917 interconnect-names = "usb-ddr", "apps-usb";
3918
1f958f3d 3919 usb_2_dwc3: dwc3@a800000 {
ca4db2b5 3920 compatible = "snps,dwc3";
bede7d2d 3921 reg = <0 0x0a800000 0 0xcd00>;
ca4db2b5 3922 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
9a8a9d17 3923 iommus = <&apps_smmu 0x760 0>;
ca4db2b5
MG		 3924 snps,dis_u2_susphy_quirk;
3925 snps,dis_enblslpm_quirk;
3926 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3927 phy-names = "usb2-phy", "usb3-phy";
3928 };
3929 };
3930
48a0585b 3931 venus: video-codec@aa00000 {
1222783e 3932 compatible = "qcom,sdm845-venus-v2";
36a80df4
MG		 3933 reg = <0 0x0aa00000 0 0xff000>;
3934 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1222783e
SV		 3935 power-domains = <&videocc VENUS_GDSC>,
3936 <&videocc VCODEC0_GDSC>,
13715487
RN		 3937 <&videocc VCODEC1_GDSC>,
3938 <&rpmhpd SDM845_CX>;
3939 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3940 operating-points-v2 = <&venus_opp_table>;
36a80df4
MG		 3941 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3942 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
1222783e
SV		 3943 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3944 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3945 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3946 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3947 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3948 clock-names = "core", "iface", "bus",
3949 "vcodec0_core", "vcodec0_bus",
3950 "vcodec1_core", "vcodec1_bus";
36a80df4
MG		 3951 iommus = <&apps_smmu 0x10a0 0x8>,
3952 <&apps_smmu 0x10b0 0x0>;
3953 memory-region = <&venus_mem>;
c422aa82
SV		 3954 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3955 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3956 interconnect-names = "video-mem", "cpu-cfg";
36a80df4 3957
7f761609
KD		 3958 status = "disabled";
3959
36a80df4
MG		 3960 video-core0 {
3961 compatible = "venus-decoder";
36a80df4
MG		 3962 };
3963
3964 video-core1 {
3965 compatible = "venus-encoder";
36a80df4 3966 };
13715487
RN		 3967
3968 venus_opp_table: venus-opp-table {
3969 compatible = "operating-points-v2";
3970
3971 opp-100000000 {
3972 opp-hz = /bits/ 64 <100000000>;
3973 required-opps = <&rpmhpd_opp_min_svs>;
3974 };
3975
3976 opp-200000000 {
3977 opp-hz = /bits/ 64 <200000000>;
3978 required-opps = <&rpmhpd_opp_low_svs>;
3979 };
3980
3981 opp-320000000 {
3982 opp-hz = /bits/ 64 <320000000>;
3983 required-opps = <&rpmhpd_opp_svs>;
3984 };
3985
3986 opp-380000000 {
3987 opp-hz = /bits/ 64 <380000000>;
3988 required-opps = <&rpmhpd_opp_svs_l1>;
3989 };
3990
3991 opp-444000000 {
3992 opp-hz = /bits/ 64 <444000000>;
3993 required-opps = <&rpmhpd_opp_nom>;
3994 };
3995
3996 opp-533000097 {
3997 opp-hz = /bits/ 64 <533000097>;
3998 required-opps = <&rpmhpd_opp_turbo>;
3999 };
4000 };
36a80df4
MG		 4001 };
4002
05556681
TD		 4003 videocc: clock-controller@ab00000 {
4004 compatible = "qcom,sdm845-videocc";
bede7d2d 4005 reg = <0 0x0ab00000 0 0x10000>;
af85ef13
DA		 4006 clocks = <&rpmhcc RPMH_CXO_CLK>;
4007 clock-names = "bi_tcxo";
05556681
TD		 4008 #clock-cells = <1>;
4009 #power-domain-cells = <1>;
4010 #reset-cells = <1>;
4011 };
4012
d48a6698
RF		 4013 camss: camss@a00000 {
4014 compatible = "qcom,sdm845-camss";
4015
4016 reg = <0 0xacb3000 0 0x1000>,
4017 <0 0xacba000 0 0x1000>,
4018 <0 0xacc8000 0 0x1000>,
4019 <0 0xac65000 0 0x1000>,
4020 <0 0xac66000 0 0x1000>,
4021 <0 0xac67000 0 0x1000>,
4022 <0 0xac68000 0 0x1000>,
4023 <0 0xacaf000 0 0x4000>,
4024 <0 0xacb6000 0 0x4000>,
4025 <0 0xacc4000 0 0x4000>;
4026 reg-names = "csid0",
4027 "csid1",
4028 "csid2",
4029 "csiphy0",
4030 "csiphy1",
4031 "csiphy2",
4032 "csiphy3",
4033 "vfe0",
4034 "vfe1",
4035 "vfe_lite";
4036
4037 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4038 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4039 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4040 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4041 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4042 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4043 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4044 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4045 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4046 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4047 interrupt-names = "csid0",
4048 "csid1",
4049 "csid2",
4050 "csiphy0",
4051 "csiphy1",
4052 "csiphy2",
4053 "csiphy3",
4054 "vfe0",
4055 "vfe1",
4056 "vfe_lite";
4057
4058 power-domains = <&clock_camcc IFE_0_GDSC>,
4059 <&clock_camcc IFE_1_GDSC>,
4060 <&clock_camcc TITAN_TOP_GDSC>;
4061
4062 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4063 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4064 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4065 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4066 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4067 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4068 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4069 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4070 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4071 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4072 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4073 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4074 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4075 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4076 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4077 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4078 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4079 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4080 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4081 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4082 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4083 <&gcc GCC_CAMERA_AHB_CLK>,
4084 <&gcc GCC_CAMERA_AXI_CLK>,
4085 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4086 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4087 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4088 <&clock_camcc CAM_CC_IFE_0_CLK>,
4089 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4090 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4091 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4092 <&clock_camcc CAM_CC_IFE_1_CLK>,
4093 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4094 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4095 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4096 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4097 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4098 clock-names = "camnoc_axi",
4099 "cpas_ahb",
4100 "cphy_rx_src",
4101 "csi0",
4102 "csi0_src",
4103 "csi1",
4104 "csi1_src",
4105 "csi2",
4106 "csi2_src",
4107 "csiphy0",
4108 "csiphy0_timer",
4109 "csiphy0_timer_src",
4110 "csiphy1",
4111 "csiphy1_timer",
4112 "csiphy1_timer_src",
4113 "csiphy2",
4114 "csiphy2_timer",
4115 "csiphy2_timer_src",
4116 "csiphy3",
4117 "csiphy3_timer",
4118 "csiphy3_timer_src",
4119 "gcc_camera_ahb",
4120 "gcc_camera_axi",
4121 "slow_ahb_src",
4122 "soc_ahb",
4123 "vfe0_axi",
4124 "vfe0",
4125 "vfe0_cphy_rx",
4126 "vfe0_src",
4127 "vfe1_axi",
4128 "vfe1",
4129 "vfe1_cphy_rx",
4130 "vfe1_src",
4131 "vfe_lite",
4132 "vfe_lite_cphy_rx",
4133 "vfe_lite_src";
4134
4135 iommus = <&apps_smmu 0x0808 0x0>,
4136 <&apps_smmu 0x0810 0x8>,
4137 <&apps_smmu 0x0c08 0x0>,
4138 <&apps_smmu 0x0c10 0x8>;
4139
4140 status = "disabled";
4141
4142 ports {
4143 #address-cells = <1>;
4144 #size-cells = <0>;
4145 };
4146 };
4147
07484de3
RF		 4148 cci: cci@ac4a000 {
4149 compatible = "qcom,sdm845-cci";
4150 #address-cells = <1>;
4151 #size-cells = <0>;
4152
4153 reg = <0 0x0ac4a000 0 0x4000>;
4154 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4155 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4156
4157 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4158 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4159 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4160 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4161 <&clock_camcc CAM_CC_CCI_CLK>,
4162 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4163 clock-names = "camnoc_axi",
4164 "soc_ahb",
4165 "slow_ahb_src",
4166 "cpas_ahb",
4167 "cci",
4168 "cci_src";
4169
4170 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4171 <&clock_camcc CAM_CC_CCI_CLK>;
4172 assigned-clock-rates = <80000000>, <37500000>;
4173
4174 pinctrl-names = "default", "sleep";
4175 pinctrl-0 = <&cci0_default &cci1_default>;
4176 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4177
4178 status = "disabled";
4179
4180 cci_i2c0: i2c-bus@0 {
4181 reg = <0>;
4182 clock-frequency = <1000000>;
4183 #address-cells = <1>;
4184 #size-cells = <0>;
4185 };
4186
4187 cci_i2c1: i2c-bus@1 {
4188 reg = <1>;
4189 clock-frequency = <1000000>;
4190 #address-cells = <1>;
4191 #size-cells = <0>;
4192 };
4193 };
4194
4195 clock_camcc: clock-controller@ad00000 {
4196 compatible = "qcom,sdm845-camcc";
4197 reg = <0 0x0ad00000 0 0x10000>;
4198 #clock-cells = <1>;
4199 #reset-cells = <1>;
4200 #power-domain-cells = <1>;
cfc090a0
DB		 4201 clocks = <&rpmhcc RPMH_CXO_CLK>;
4202 clock-names = "bi_tcxo";
07484de3
RF		 4203 };
4204
19ecbc84
RN		 4205 dsi_opp_table: dsi-opp-table {
4206 compatible = "operating-points-v2";
4207
4208 opp-19200000 {
4209 opp-hz = /bits/ 64 <19200000>;
4210 required-opps = <&rpmhpd_opp_min_svs>;
4211 };
4212
4213 opp-180000000 {
4214 opp-hz = /bits/ 64 <180000000>;
4215 required-opps = <&rpmhpd_opp_low_svs>;
4216 };
4217
4218 opp-275000000 {
4219 opp-hz = /bits/ 64 <275000000>;
4220 required-opps = <&rpmhpd_opp_svs>;
4221 };
4222
4223 opp-328580000 {
4224 opp-hz = /bits/ 64 <328580000>;
4225 required-opps = <&rpmhpd_opp_svs_l1>;
4226 };
4227
4228 opp-358000000 {
4229 opp-hz = /bits/ 64 <358000000>;
4230 required-opps = <&rpmhpd_opp_nom>;
4231 };
4232 };
4233
08c2a076
JS		 4234 mdss: mdss@ae00000 {
4235 compatible = "qcom,sdm845-mdss";
bede7d2d 4236 reg = <0 0x0ae00000 0 0x1000>;
08c2a076
JS		 4237 reg-names = "mdss";
4238
4239 power-domains = <&dispcc MDSS_GDSC>;
4240
4241 clocks = <&gcc GCC_DISP_AHB_CLK>,
08c2a076 4242 <&dispcc DISP_CC_MDSS_MDP_CLK>;
111c5285 4243 clock-names = "iface", "core";
08c2a076
JS		 4244
4245 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
4246 assigned-clock-rates = <300000000>;
4247
4248 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4249 interrupt-controller;
4250 #interrupt-cells = <1>;
4251
c8c61c09
GD		 4252 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4253 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4254 interconnect-names = "mdp0-mem", "mdp1-mem";
4255
08c2a076
JS		 4256 iommus = <&apps_smmu 0x880 0x8>,
4257 <&apps_smmu 0xc80 0x8>;
4258
4259 status = "disabled";
4260
bede7d2d
BA		 4261 #address-cells = <2>;
4262 #size-cells = <2>;
08c2a076
JS		 4263 ranges;
4264
4265 mdss_mdp: mdp@ae01000 {
4266 compatible = "qcom,sdm845-dpu";
bede7d2d
BA		 4267 reg = <0 0x0ae01000 0 0x8f000>,
4268 <0 0x0aeb0000 0 0x2008>;
08c2a076
JS		 4269 reg-names = "mdp", "vbif";
4270
111c5285
DB		 4271 clocks = <&gcc GCC_DISP_AXI_CLK>,
4272 <&dispcc DISP_CC_MDSS_AHB_CLK>,
08c2a076
JS		 4273 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4274 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4275 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
111c5285 4276 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
08c2a076
JS		 4277
4278 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4279 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4280 assigned-clock-rates = <300000000>,
4281 <19200000>;
19ecbc84
RN		 4282 operating-points-v2 = <&mdp_opp_table>;
4283 power-domains = <&rpmhpd SDM845_CX>;
08c2a076
JS		 4284
4285 interrupt-parent = <&mdss>;
0316da6b 4286 interrupts = <0>;
08c2a076 4287
08c2a076
JS		 4288 ports {
4289 #address-cells = <1>;
4290 #size-cells = <0>;
4291
4292 port@0 {
4293 reg = <0>;
4294 dpu_intf1_out: endpoint {
4295 remote-endpoint = <&dsi0_in>;
4296 };
4297 };
4298
4299 port@1 {
4300 reg = <1>;
4301 dpu_intf2_out: endpoint {
4302 remote-endpoint = <&dsi1_in>;
4303 };
4304 };
4305 };
19ecbc84
RN		 4306
4307 mdp_opp_table: mdp-opp-table {
4308 compatible = "operating-points-v2";
4309
4310 opp-19200000 {
4311 opp-hz = /bits/ 64 <19200000>;
4312 required-opps = <&rpmhpd_opp_min_svs>;
4313 };
4314
4315 opp-171428571 {
4316 opp-hz = /bits/ 64 <171428571>;
4317 required-opps = <&rpmhpd_opp_low_svs>;
4318 };
4319
4320 opp-344000000 {
4321 opp-hz = /bits/ 64 <344000000>;
4322 required-opps = <&rpmhpd_opp_svs_l1>;
4323 };
4324
4325 opp-430000000 {
4326 opp-hz = /bits/ 64 <430000000>;
4327 required-opps = <&rpmhpd_opp_nom>;
4328 };
4329 };
08c2a076
JS		 4330 };
4331
4332 dsi0: dsi@ae94000 {
4333 compatible = "qcom,mdss-dsi-ctrl";
bede7d2d 4334 reg = <0 0x0ae94000 0 0x400>;
08c2a076
JS		 4335 reg-names = "dsi_ctrl";
4336
4337 interrupt-parent = <&mdss>;
0316da6b 4338 interrupts = <4>;
08c2a076
JS		 4339
4340 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4341 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4342 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4343 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4344 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4345 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4346 clock-names = "byte",
4347 "byte_intf",
4348 "pixel",
4349 "core",
4350 "iface",
4351 "bus";
3289022b
DB		 4352 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4353 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4354
19ecbc84
RN		 4355 operating-points-v2 = <&dsi_opp_table>;
4356 power-domains = <&rpmhpd SDM845_CX>;
08c2a076
JS		 4357
4358 phys = <&dsi0_phy>;
4359 phy-names = "dsi";
4360
4361 status = "disabled";
4362
26b59eb5
KD		 4363 #address-cells = <1>;
4364 #size-cells = <0>;
4365
08c2a076
JS		 4366 ports {
4367 #address-cells = <1>;
4368 #size-cells = <0>;
4369
4370 port@0 {
4371 reg = <0>;
4372 dsi0_in: endpoint {
4373 remote-endpoint = <&dpu_intf1_out>;
4374 };
4375 };
4376
4377 port@1 {
4378 reg = <1>;
4379 dsi0_out: endpoint {
4380 };
4381 };
4382 };
4383 };
4384
4385 dsi0_phy: dsi-phy@ae94400 {
4386 compatible = "qcom,dsi-phy-10nm";
bede7d2d
BA		 4387 reg = <0 0x0ae94400 0 0x200>,
4388 <0 0x0ae94600 0 0x280>,
4389 <0 0x0ae94a00 0 0x1e0>;
08c2a076
JS		 4390 reg-names = "dsi_phy",
4391 "dsi_phy_lane",
4392 "dsi_pll";
4393
4394 #clock-cells = <1>;
4395 #phy-cells = <0>;
4396
0c0e7270
MK		 4397 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4398 <&rpmhcc RPMH_CXO_CLK>;
4399 clock-names = "iface", "ref";
08c2a076
JS		 4400
4401 status = "disabled";
4402 };
4403
4404 dsi1: dsi@ae96000 {
4405 compatible = "qcom,mdss-dsi-ctrl";
bede7d2d 4406 reg = <0 0x0ae96000 0 0x400>;
08c2a076
JS		 4407 reg-names = "dsi_ctrl";
4408
4409 interrupt-parent = <&mdss>;
0316da6b 4410 interrupts = <5>;
08c2a076
JS		 4411
4412 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4413 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4414 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4415 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4416 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4417 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4418 clock-names = "byte",
4419 "byte_intf",
4420 "pixel",
4421 "core",
4422 "iface",
4423 "bus";
3289022b
DB		 4424 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4425 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4426
19ecbc84
RN		 4427 operating-points-v2 = <&dsi_opp_table>;
4428 power-domains = <&rpmhpd SDM845_CX>;
08c2a076
JS		 4429
4430 phys = <&dsi1_phy>;
4431 phy-names = "dsi";
4432
4433 status = "disabled";
4434
26b59eb5
KD		 4435 #address-cells = <1>;
4436 #size-cells = <0>;
4437
08c2a076
JS		 4438 ports {
4439 #address-cells = <1>;
4440 #size-cells = <0>;
4441
4442 port@0 {
4443 reg = <0>;
4444 dsi1_in: endpoint {
4445 remote-endpoint = <&dpu_intf2_out>;
4446 };
4447 };
4448
4449 port@1 {
4450 reg = <1>;
4451 dsi1_out: endpoint {
4452 };
4453 };
4454 };
4455 };
4456
4457 dsi1_phy: dsi-phy@ae96400 {
4458 compatible = "qcom,dsi-phy-10nm";
bede7d2d
BA		 4459 reg = <0 0x0ae96400 0 0x200>,
4460 <0 0x0ae96600 0 0x280>,
4461 <0 0x0ae96a00 0 0x10e>;
08c2a076
JS		 4462 reg-names = "dsi_phy",
4463 "dsi_phy_lane",
4464 "dsi_pll";
4465
4466 #clock-cells = <1>;
4467 #phy-cells = <0>;
4468
0c0e7270
MK		 4469 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4470 <&rpmhcc RPMH_CXO_CLK>;
4471 clock-names = "iface", "ref";
08c2a076
JS		 4472
4473 status = "disabled";
4474 };
4475 };
4476
f489b13d 4477 gpu: gpu@5000000 {
c7980010 4478 compatible = "qcom,adreno-630.2", "qcom,adreno";
c7980010
JC		 4479
4480 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4481 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4482
4483 /*
4484 * Look ma, no clocks! The GPU clocks and power are
4485 * controlled entirely by the GMU
4486 */
4487
4488 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4489
4490 iommus = <&adreno_smmu 0>;
4491
4492 operating-points-v2 = <&gpu_opp_table>;
4493
4494 qcom,gmu = <&gmu>;
4495
7901c2bc 4496 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
338bdbcc
SM		 4497 interconnect-names = "gfx-mem";
4498
7f761609
KD		 4499 status = "disabled";
4500
c7980010
JC		 4501 gpu_opp_table: opp-table {
4502 compatible = "operating-points-v2";
4503
4504 opp-710000000 {
4505 opp-hz = /bits/ 64 <710000000>;
4506 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
338bdbcc 4507 opp-peak-kBps = <7216000>;
c7980010
JC		 4508 };
4509
4510 opp-675000000 {
4511 opp-hz = /bits/ 64 <675000000>;
4512 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
338bdbcc 4513 opp-peak-kBps = <7216000>;
c7980010
JC		 4514 };
4515
4516 opp-596000000 {
4517 opp-hz = /bits/ 64 <596000000>;
4518 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
338bdbcc 4519 opp-peak-kBps = <6220000>;
c7980010
JC		 4520 };
4521
4522 opp-520000000 {
4523 opp-hz = /bits/ 64 <520000000>;
4524 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
338bdbcc 4525 opp-peak-kBps = <6220000>;
c7980010
JC		 4526 };
4527
4528 opp-414000000 {
4529 opp-hz = /bits/ 64 <414000000>;
4530 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
338bdbcc 4531 opp-peak-kBps = <4068000>;
c7980010
JC		 4532 };
4533
4534 opp-342000000 {
4535 opp-hz = /bits/ 64 <342000000>;
4536 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
338bdbcc 4537 opp-peak-kBps = <2724000>;
c7980010
JC		 4538 };
4539
4540 opp-257000000 {
4541 opp-hz = /bits/ 64 <257000000>;
4542 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
338bdbcc 4543 opp-peak-kBps = <1648000>;
c7980010
JC		 4544 };
4545 };
4546 };
4547
4548 adreno_smmu: iommu@5040000 {
7e5258b0 4549 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
c7980010
JC		 4550 reg = <0 0x5040000 0 0x10000>;
4551 #iommu-cells = <1>;
4552 #global-interrupts = <2>;
4553 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4554 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4555 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4556 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4557 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4558 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4559 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4560 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4561 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4562 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4563 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4564 <&gcc GCC_GPU_CFG_AHB_CLK>;
4565 clock-names = "bus", "iface";
4566
4567 power-domains = <&gpucc GPU_CX_GDSC>;
4568 };
4569
4570 gmu: gmu@506a000 {
4571 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4572
4573 reg = <0 0x506a000 0 0x30000>,
4574 <0 0xb280000 0 0x10000>,
4575 <0 0xb480000 0 0x10000>;
4576 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4577
4578 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4579 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4580 interrupt-names = "hfi", "gmu";
4581
4582 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4583 <&gpucc GPU_CC_CXO_CLK>,
4584 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4585 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4586 clock-names = "gmu", "cxo", "axi", "memnoc";
4587
4588 power-domains = <&gpucc GPU_CX_GDSC>,
4589 <&gpucc GPU_GX_GDSC>;
4590 power-domain-names = "cx", "gx";
4591
4592 iommus = <&adreno_smmu 5>;
4593
4594 operating-points-v2 = <&gmu_opp_table>;
4595
7f761609
KD		 4596 status = "disabled";
4597
c7980010
JC		 4598 gmu_opp_table: opp-table {
4599 compatible = "operating-points-v2";
4600
4601 opp-400000000 {
4602 opp-hz = /bits/ 64 <400000000>;
4603 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4604 };
4605
4606 opp-200000000 {
4607 opp-hz = /bits/ 64 <200000000>;
4608 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4609 };
4610 };
4611 };
4612
40019e84
MK		 4613 dispcc: clock-controller@af00000 {
4614 compatible = "qcom,sdm845-dispcc";
bede7d2d 4615 reg = <0 0x0af00000 0 0x10000>;
0997882f
DA		 4616 clocks = <&rpmhcc RPMH_CXO_CLK>,
4617 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4618 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4619 <&dsi0_phy 0>,
4620 <&dsi0_phy 1>,
4621 <&dsi1_phy 0>,
4622 <&dsi1_phy 1>,
4623 <0>,
4624 <0>;
4625 clock-names = "bi_tcxo",
4626 "gcc_disp_gpll0_clk_src",
4627 "gcc_disp_gpll0_div_clk_src",
4628 "dsi0_phy_pll_out_byteclk",
4629 "dsi0_phy_pll_out_dsiclk",
4630 "dsi1_phy_pll_out_byteclk",
4631 "dsi1_phy_pll_out_dsiclk",
4632 "dp_link_clk_divsel_ten",
4633 "dp_vco_divided_clk_src_mux";
40019e84
MK		 4634 #clock-cells = <1>;
4635 #reset-cells = <1>;
4636 #power-domain-cells = <1>;
4637 };
4638
72b67ebf
LI		 4639 pdc_intc: interrupt-controller@b220000 {
4640 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4641 reg = <0 0x0b220000 0 0x30000>;
4642 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4643 #interrupt-cells = <2>;
4644 interrupt-parent = <&intc>;
4645 interrupt-controller;
4646 };
4647
13393da0
SS		 4648 pdc_reset: reset-controller@b2e0000 {
4649 compatible = "qcom,sdm845-pdc-global";
bede7d2d 4650 reg = <0 0x0b2e0000 0 0x20000>;
13393da0
SS		 4651 #reset-cells = <1>;
4652 };
4653
cda676b5
AK		 4654 tsens0: thermal-sensor@c263000 {
4655 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
bede7d2d
BA		 4656 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4657 <0 0x0c222000 0 0x1ff>; /* SROT */
cda676b5 4658 #qcom,sensors = <13>;
e68ca6b6
AK		 4659 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4660 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4661 interrupt-names = "uplow", "critical";
cda676b5
AK		 4662 #thermal-sensor-cells = <1>;
4663 };
4664
4665 tsens1: thermal-sensor@c265000 {
4666 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
bede7d2d
BA		 4667 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4668 <0 0x0c223000 0 0x1ff>; /* SROT */
cda676b5 4669 #qcom,sensors = <8>;
e68ca6b6
AK		 4670 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4671 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4672 interrupt-names = "uplow", "critical";
cda676b5
AK		 4673 #thermal-sensor-cells = <1>;
4674 };
4675
ead5eea3
SS		 4676 aoss_reset: reset-controller@c2a0000 {
4677 compatible = "qcom,sdm845-aoss-cc";
bede7d2d 4678 reg = <0 0x0c2a0000 0 0x31000>;
ead5eea3
SS		 4679 #reset-cells = <1>;
4680 };
4681
f81c1e51 4682 aoss_qmp: power-controller@c300000 {
3b87b01d 4683 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
a7977438
BA		 4684 reg = <0 0x0c300000 0 0x100000>;
4685 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4686 mboxes = <&apss_shared 0>;
4687
4688 #clock-cells = <0>;
7e4b5f24
TG		 4689
4690 cx_cdev: cx {
4691 #cooling-cells = <2>;
4692 };
4693
4694 ebi_cdev: ebi {
4695 #cooling-cells = <2>;
4696 };
a7977438
BA		 4697 };
4698
54d7a20d
DA		 4699 spmi_bus: spmi@c440000 {
4700 compatible = "qcom,spmi-pmic-arb";
bede7d2d
BA		 4701 reg = <0 0x0c440000 0 0x1100>,
4702 <0 0x0c600000 0 0x2000000>,
4703 <0 0x0e600000 0 0x100000>,
4704 <0 0x0e700000 0 0xa0000>,
4705 <0 0x0c40a000 0 0x26000>;
54d7a20d
DA		 4706 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4707 interrupt-names = "periph_irq";
4708 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4709 qcom,ee = <0>;
4710 qcom,channel = <0>;
4711 #address-cells = <2>;
4712 #size-cells = <0>;
4713 interrupt-controller;
4714 #interrupt-cells = <4>;
4715 cell-index = <0>;
4716 };
4717
948f6161
BA		 4718 imem@146bf000 {
4719 compatible = "simple-mfd";
4720 reg = <0 0x146bf000 0 0x1000>;
4721
4722 #address-cells = <1>;
4723 #size-cells = <1>;
4724
4725 ranges = <0 0 0x146bf000 0x1000>;
4726
4727 pil-reloc@94c {
4728 compatible = "qcom,pil-reloc-info";
4729 reg = <0x94c 0xc8>;
4730 };
4731 };
4732
4429e575
VG		 4733 apps_smmu: iommu@15000000 {
4734 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
bede7d2d 4735 reg = <0 0x15000000 0 0x80000>;
4429e575
VG		 4736 #iommu-cells = <2>;
4737 #global-interrupts = <1>;
4738 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4739 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4740 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4741 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4742 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4743 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4744 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4745 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4746 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4747 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4748 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4749 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4750 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4751 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4752 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4753 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4754 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4755 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4756 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4757 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4758 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4759 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4760 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4761 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4762 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4763 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4764 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4765 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4766 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4767 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4768 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4769 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4770 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4771 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4772 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4773 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4774 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4775 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4776 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4777 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4778 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4779 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4780 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4781 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4782 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4783 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4784 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4785 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4786 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4787 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4788 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4789 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4790 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4791 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4792 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4793 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4794 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4795 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4796 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4797 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4798 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4799 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4800 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4801 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4802 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
4803 };
4804
0cef5dd4
TD		 4805 lpasscc: clock-controller@17014000 {
4806 compatible = "qcom,sdm845-lpasscc";
1d918e9a 4807 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
0cef5dd4
TD		 4808 reg-names = "cc", "qdsp6ss";
4809 #clock-cells = <1>;
4810 status = "disabled";
4811 };
4812
b303f9f0
DD		 4813 gladiator_noc: interconnect@17900000 {
4814 compatible = "qcom,sdm845-gladiator-noc";
4815 reg = <0 0x17900000 0 0xd080>;
7901c2bc 4816 #interconnect-cells = <2>;
b303f9f0
DD		 4817 qcom,bcm-voters = <&apps_bcm_voter>;
4818 };
4819
ef857678
BA		 4820 watchdog@17980000 {
4821 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4822 reg = <0 0x17980000 0 0x1000>;
4823 clocks = <&sleep_clk>;
36c436b0 4824 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
ef857678
BA		 4825 };
4826
54d7a20d
DA		 4827 apss_shared: mailbox@17990000 {
4828 compatible = "qcom,sdm845-apss-shared";
bede7d2d 4829 reg = <0 0x17990000 0 0x1000>;
54d7a20d
DA		 4830 #mbox-cells = <1>;
4831 };
4832
c83545d9
DA		 4833 apps_rsc: rsc@179c0000 {
4834 label = "apps_rsc";
4835 compatible = "qcom,rpmh-rsc";
bede7d2d
BA		 4836 reg = <0 0x179c0000 0 0x10000>,
4837 <0 0x179d0000 0 0x10000>,
4838 <0 0x179e0000 0 0x10000>;
c83545d9
DA		 4839 reg-names = "drv-0", "drv-1", "drv-2";
4840 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4841 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4842 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4843 qcom,tcs-offset = <0xd00>;
4844 qcom,drv-id = <2>;
4845 qcom,tcs-config = <ACTIVE_TCS 2>,
4846 <SLEEP_TCS 3>,
4847 <WAKE_TCS 3>,
4848 <CONTROL_TCS 1>;
717f2013 4849
b303f9f0
DD		 4850 apps_bcm_voter: bcm-voter {
4851 compatible = "qcom,bcm-voter";
4852 };
4853
717f2013
DA		 4854 rpmhcc: clock-controller {
4855 compatible = "qcom,sdm845-rpmh-clk";
4856 #clock-cells = <1>;
1dd70853
VK		 4857 clock-names = "xo";
4858 clocks = <&xo_board>;
717f2013 4859 };
5b6f186f
RN		 4860
4861 rpmhpd: power-controller {
4862 compatible = "qcom,sdm845-rpmhpd";
4863 #power-domain-cells = <1>;
4864 operating-points-v2 = <&rpmhpd_opp_table>;
4865
4866 rpmhpd_opp_table: opp-table {
4867 compatible = "operating-points-v2";
4868
4869 rpmhpd_opp_ret: opp1 {
596a4343 4870 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5b6f186f
RN		 4871 };
4872
4873 rpmhpd_opp_min_svs: opp2 {
596a4343 4874 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5b6f186f
RN		 4875 };
4876
4877 rpmhpd_opp_low_svs: opp3 {
596a4343 4878 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5b6f186f
RN		 4879 };
4880
4881 rpmhpd_opp_svs: opp4 {
596a4343 4882 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5b6f186f
RN		 4883 };
4884
4885 rpmhpd_opp_svs_l1: opp5 {
596a4343 4886 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5b6f186f
RN		 4887 };
4888
4889 rpmhpd_opp_nom: opp6 {
596a4343 4890 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5b6f186f
RN		 4891 };
4892
4893 rpmhpd_opp_nom_l1: opp7 {
596a4343 4894 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5b6f186f
RN		 4895 };
4896
4897 rpmhpd_opp_nom_l2: opp8 {
596a4343 4898 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5b6f186f
RN		 4899 };
4900
4901 rpmhpd_opp_turbo: opp9 {
596a4343 4902 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5b6f186f
RN		 4903 };
4904
4905 rpmhpd_opp_turbo_l1: opp10 {
596a4343 4906 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5b6f186f
RN		 4907 };
4908 };
4909 };
c83545d9
DA		 4910 };
4911
6d4cf750
RN		 4912 intc: interrupt-controller@17a00000 {
4913 compatible = "arm,gic-v3";
bede7d2d
BA		 4914 #address-cells = <2>;
4915 #size-cells = <2>;
6d4cf750
RN		 4916 ranges;
4917 #interrupt-cells = <3>;
4918 interrupt-controller;
bede7d2d
BA		 4919 reg = <0 0x17a00000 0 0x10000>, /* GICD */
4920 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
6d4cf750
RN		 4921 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4922
276bb28c 4923 msi-controller@17a40000 {
6d4cf750
RN		 4924 compatible = "arm,gic-v3-its";
4925 msi-controller;
4926 #msi-cells = <1>;
bede7d2d 4927 reg = <0 0x17a40000 0 0x20000>;
6d4cf750
RN		 4928 status = "disabled";
4929 };
4930 };
4931
a8fbc8bd 4932 slimbam: dma-controller@17184000 {
27ca1de0
SK		 4933 compatible = "qcom,bam-v1.7.0";
4934 qcom,controlled-remotely;
4935 reg = <0 0x17184000 0 0x2a000>;
4936 num-channels = <31>;
4937 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
4938 #dma-cells = <1>;
4939 qcom,ee = <1>;
4940 qcom,num-ees = <2>;
4941 iommus = <&apps_smmu 0x1806 0x0>;
4942 };
4943
6d4cf750 4944 timer@17c90000 {
bede7d2d
BA		 4945 #address-cells = <2>;
4946 #size-cells = <2>;
6d4cf750
RN		 4947 ranges;
4948 compatible = "arm,armv7-timer-mem";
bede7d2d 4949 reg = <0 0x17c90000 0 0x1000>;
6d4cf750
RN		 4950
4951 frame@17ca0000 {
4952 frame-number = <0>;
4953 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
4954 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
bede7d2d
BA		 4955 reg = <0 0x17ca0000 0 0x1000>,
4956 <0 0x17cb0000 0 0x1000>;
6d4cf750
RN		 4957 };
4958
4959 frame@17cc0000 {
4960 frame-number = <1>;
4961 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
bede7d2d 4962 reg = <0 0x17cc0000 0 0x1000>;
6d4cf750
RN		 4963 status = "disabled";
4964 };
4965
4966 frame@17cd0000 {
4967 frame-number = <2>;
4968 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
bede7d2d 4969 reg = <0 0x17cd0000 0 0x1000>;
6d4cf750
RN		 4970 status = "disabled";
4971 };
4972
4973 frame@17ce0000 {
4974 frame-number = <3>;
4975 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
bede7d2d 4976 reg = <0 0x17ce0000 0 0x1000>;
6d4cf750
RN		 4977 status = "disabled";
4978 };
4979
4980 frame@17cf0000 {
4981 frame-number = <4>;
4982 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
bede7d2d 4983 reg = <0 0x17cf0000 0 0x1000>;
6d4cf750
RN		 4984 status = "disabled";
4985 };
4986
4987 frame@17d00000 {
4988 frame-number = <5>;
4989 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
bede7d2d 4990 reg = <0 0x17d00000 0 0x1000>;
6d4cf750
RN		 4991 status = "disabled";
4992 };
4993
4994 frame@17d10000 {
4995 frame-number = <6>;
4996 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
bede7d2d 4997 reg = <0 0x17d10000 0 0x1000>;
6d4cf750
RN		 4998 status = "disabled";
4999 };
5000 };
c604b82a 5001
74f26599
SS		 5002 osm_l3: interconnect@17d41000 {
5003 compatible = "qcom,sdm845-osm-l3";
5004 reg = <0 0x17d41000 0 0x1400>;
5005
5006 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5007 clock-names = "xo", "alternate";
5008
5009 #interconnect-cells = <1>;
5010 };
5011
c604b82a
TD		 5012 cpufreq_hw: cpufreq@17d43000 {
5013 compatible = "qcom,cpufreq-hw";
bede7d2d 5014 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
c604b82a
TD		 5015 reg-names = "freq-domain0", "freq-domain1";
5016
36c65812
TG		 5017 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5018
c604b82a
TD		 5019 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5020 clock-names = "xo", "alternate";
5021
5022 #freq-domain-cells = <1>;
5023 };
022bccb8
GS		 5024
5025 wifi: wifi@18800000 {
5026 compatible = "qcom,wcn3990-wifi";
5027 status = "disabled";
bede7d2d 5028 reg = <0 0x18800000 0 0x800000>;
022bccb8
GS		 5029 reg-names = "membase";
5030 memory-region = <&wlan_msa_mem>;
bc94e5f4
DA		 5031 clock-names = "cxo_ref_clk_pin";
5032 clocks = <&rpmhcc RPMH_RF_CLK2>;
022bccb8
GS		 5033 interrupts =
5034 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5035 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5036 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5037 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5038 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5039 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5040 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5041 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5042 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5043 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5045 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
bc94e5f4 5046 iommus = <&apps_smmu 0x0040 0x1>;
022bccb8 5047 };
6d4cf750 5048 };
4884788b
AK		 5049
5050 thermal-zones {
5051 cpu0-thermal {
5052 polling-delay-passive = <250>;
5053 polling-delay = <1000>;
5054
5055 thermal-sensors = <&tsens0 1>;
5056
5057 trips {
19e684e8 5058 cpu0_alert0: trip-point0 {
c47fc198
AK		 5059 temperature = <90000>;
5060 hysteresis = <2000>;
5061 type = "passive";
5062 };
5063
19e684e8 5064 cpu0_alert1: trip-point1 {
c47fc198 5065 temperature = <95000>;
4884788b
AK		 5066 hysteresis = <2000>;
5067 type = "passive";
5068 };
5069
c47fc198 5070 cpu0_crit: cpu_crit {
4884788b
AK		 5071 temperature = <110000>;
5072 hysteresis = <1000>;
5073 type = "critical";
5074 };
5075 };
5076 };
5077
5078 cpu1-thermal {
5079 polling-delay-passive = <250>;
5080 polling-delay = <1000>;
5081
5082 thermal-sensors = <&tsens0 2>;
5083
5084 trips {
19e684e8 5085 cpu1_alert0: trip-point0 {
c47fc198 5086 temperature = <90000>;
4884788b
AK		 5087 hysteresis = <2000>;
5088 type = "passive";
5089 };
5090
19e684e8 5091 cpu1_alert1: trip-point1 {
c47fc198
AK		 5092 temperature = <95000>;
5093 hysteresis = <2000>;
5094 type = "passive";
5095 };
5096
5097 cpu1_crit: cpu_crit {
4884788b
AK		 5098 temperature = <110000>;
5099 hysteresis = <1000>;
5100 type = "critical";
5101 };
5102 };
5103 };
5104
5105 cpu2-thermal {
5106 polling-delay-passive = <250>;
5107 polling-delay = <1000>;
5108
5109 thermal-sensors = <&tsens0 3>;
5110
5111 trips {
19e684e8 5112 cpu2_alert0: trip-point0 {
c47fc198 5113 temperature = <90000>;
4884788b
AK		 5114 hysteresis = <2000>;
5115 type = "passive";
5116 };
5117
19e684e8 5118 cpu2_alert1: trip-point1 {
c47fc198
AK		 5119 temperature = <95000>;
5120 hysteresis = <2000>;
5121 type = "passive";
5122 };
5123
5124 cpu2_crit: cpu_crit {
4884788b
AK		 5125 temperature = <110000>;
5126 hysteresis = <1000>;
5127 type = "critical";
5128 };
5129 };
5130 };
5131
5132 cpu3-thermal {
5133 polling-delay-passive = <250>;
5134 polling-delay = <1000>;
5135
5136 thermal-sensors = <&tsens0 4>;
5137
5138 trips {
19e684e8 5139 cpu3_alert0: trip-point0 {
c47fc198 5140 temperature = <90000>;
4884788b
AK		 5141 hysteresis = <2000>;
5142 type = "passive";
5143 };
5144
19e684e8 5145 cpu3_alert1: trip-point1 {
c47fc198
AK		 5146 temperature = <95000>;
5147 hysteresis = <2000>;
5148 type = "passive";
5149 };
5150
5151 cpu3_crit: cpu_crit {
4884788b
AK		 5152 temperature = <110000>;
5153 hysteresis = <1000>;
5154 type = "critical";
5155 };
5156 };
5157 };
5158
5159 cpu4-thermal {
5160 polling-delay-passive = <250>;
5161 polling-delay = <1000>;
5162
5163 thermal-sensors = <&tsens0 7>;
5164
5165 trips {
19e684e8 5166 cpu4_alert0: trip-point0 {
c47fc198 5167 temperature = <90000>;
4884788b
AK		 5168 hysteresis = <2000>;
5169 type = "passive";
5170 };
5171
19e684e8 5172 cpu4_alert1: trip-point1 {
c47fc198
AK		 5173 temperature = <95000>;
5174 hysteresis = <2000>;
5175 type = "passive";
5176 };
5177
5178 cpu4_crit: cpu_crit {
4884788b
AK		 5179 temperature = <110000>;
5180 hysteresis = <1000>;
5181 type = "critical";
5182 };
5183 };
5184 };
5185
5186 cpu5-thermal {
5187 polling-delay-passive = <250>;
5188 polling-delay = <1000>;
5189
5190 thermal-sensors = <&tsens0 8>;
5191
5192 trips {
19e684e8 5193 cpu5_alert0: trip-point0 {
c47fc198 5194 temperature = <90000>;
4884788b
AK		 5195 hysteresis = <2000>;
5196 type = "passive";
5197 };
5198
19e684e8 5199 cpu5_alert1: trip-point1 {
c47fc198
AK		 5200 temperature = <95000>;
5201 hysteresis = <2000>;
5202 type = "passive";
5203 };
5204
5205 cpu5_crit: cpu_crit {
4884788b
AK		 5206 temperature = <110000>;
5207 hysteresis = <1000>;
5208 type = "critical";
5209 };
5210 };
5211 };
5212
5213 cpu6-thermal {
5214 polling-delay-passive = <250>;
5215 polling-delay = <1000>;
5216
5217 thermal-sensors = <&tsens0 9>;
5218
5219 trips {
19e684e8 5220 cpu6_alert0: trip-point0 {
c47fc198 5221 temperature = <90000>;
4884788b
AK		 5222 hysteresis = <2000>;
5223 type = "passive";
5224 };
5225
19e684e8 5226 cpu6_alert1: trip-point1 {
c47fc198
AK		 5227 temperature = <95000>;
5228 hysteresis = <2000>;
5229 type = "passive";
5230 };
5231
5232 cpu6_crit: cpu_crit {
4884788b
AK		 5233 temperature = <110000>;
5234 hysteresis = <1000>;
5235 type = "critical";
5236 };
5237 };
5238 };
5239
5240 cpu7-thermal {
5241 polling-delay-passive = <250>;
5242 polling-delay = <1000>;
5243
5244 thermal-sensors = <&tsens0 10>;
5245
5246 trips {
19e684e8 5247 cpu7_alert0: trip-point0 {
c47fc198 5248 temperature = <90000>;
4884788b
AK		 5249 hysteresis = <2000>;
5250 type = "passive";
5251 };
5252
19e684e8 5253 cpu7_alert1: trip-point1 {
c47fc198
AK		 5254 temperature = <95000>;
5255 hysteresis = <2000>;
5256 type = "passive";
5257 };
5258
5259 cpu7_crit: cpu_crit {
4884788b
AK		 5260 temperature = <110000>;
5261 hysteresis = <1000>;
5262 type = "critical";
5263 };
5264 };
5265 };
1c403ec2
AK		 5266
5267 aoss0-thermal {
5268 polling-delay-passive = <250>;
5269 polling-delay = <1000>;
5270
5271 thermal-sensors = <&tsens0 0>;
5272
5273 trips {
19e684e8 5274 aoss0_alert0: trip-point0 {
1c403ec2
AK		 5275 temperature = <90000>;
5276 hysteresis = <2000>;
5277 type = "hot";
5278 };
5279 };
5280 };
5281
5282 cluster0-thermal {
5283 polling-delay-passive = <250>;
5284 polling-delay = <1000>;
5285
5286 thermal-sensors = <&tsens0 5>;
5287
5288 trips {
19e684e8 5289 cluster0_alert0: trip-point0 {
1c403ec2
AK		 5290 temperature = <90000>;
5291 hysteresis = <2000>;
5292 type = "hot";
5293 };
5294 cluster0_crit: cluster0_crit {
5295 temperature = <110000>;
5296 hysteresis = <2000>;
5297 type = "critical";
5298 };
5299 };
5300 };
5301
5302 cluster1-thermal {
5303 polling-delay-passive = <250>;
5304 polling-delay = <1000>;
5305
5306 thermal-sensors = <&tsens0 6>;
5307
5308 trips {
19e684e8 5309 cluster1_alert0: trip-point0 {
1c403ec2
AK		 5310 temperature = <90000>;
5311 hysteresis = <2000>;
5312 type = "hot";
5313 };
5314 cluster1_crit: cluster1_crit {
5315 temperature = <110000>;
5316 hysteresis = <2000>;
5317 type = "critical";
5318 };
5319 };
5320 };
5321
7be1c395 5322 gpu-top-thermal {
1c403ec2
AK		 5323 polling-delay-passive = <250>;
5324 polling-delay = <1000>;
5325
5326 thermal-sensors = <&tsens0 11>;
5327
5328 trips {
19e684e8 5329 gpu1_alert0: trip-point0 {
1c403ec2
AK		 5330 temperature = <90000>;
5331 hysteresis = <2000>;
5332 type = "hot";
5333 };
5334 };
5335 };
5336
7be1c395 5337 gpu-bottom-thermal {
1c403ec2
AK		 5338 polling-delay-passive = <250>;
5339 polling-delay = <1000>;
5340
5341 thermal-sensors = <&tsens0 12>;
5342
5343 trips {
19e684e8 5344 gpu2_alert0: trip-point0 {
1c403ec2
AK		 5345 temperature = <90000>;
5346 hysteresis = <2000>;
5347 type = "hot";
5348 };
5349 };
5350 };
5351
5352 aoss1-thermal {
5353 polling-delay-passive = <250>;
5354 polling-delay = <1000>;
5355
5356 thermal-sensors = <&tsens1 0>;
5357
5358 trips {
19e684e8 5359 aoss1_alert0: trip-point0 {
1c403ec2
AK		 5360 temperature = <90000>;
5361 hysteresis = <2000>;
5362 type = "hot";
5363 };
5364 };
5365 };
5366
5367 q6-modem-thermal {
5368 polling-delay-passive = <250>;
5369 polling-delay = <1000>;
5370
5371 thermal-sensors = <&tsens1 1>;
5372
5373 trips {
19e684e8 5374 q6_modem_alert0: trip-point0 {
1c403ec2
AK		 5375 temperature = <90000>;
5376 hysteresis = <2000>;
5377 type = "hot";
5378 };
5379 };
5380 };
5381
5382 mem-thermal {
5383 polling-delay-passive = <250>;
5384 polling-delay = <1000>;
5385
5386 thermal-sensors = <&tsens1 2>;
5387
5388 trips {
19e684e8 5389 mem_alert0: trip-point0 {
1c403ec2
AK		 5390 temperature = <90000>;
5391 hysteresis = <2000>;
5392 type = "hot";
5393 };
5394 };
5395 };
5396
5397 wlan-thermal {
5398 polling-delay-passive = <250>;
5399 polling-delay = <1000>;
5400
5401 thermal-sensors = <&tsens1 3>;
5402
5403 trips {
19e684e8 5404 wlan_alert0: trip-point0 {
1c403ec2
AK		 5405 temperature = <90000>;
5406 hysteresis = <2000>;
5407 type = "hot";
5408 };
5409 };
5410 };
5411
5412 q6-hvx-thermal {
5413 polling-delay-passive = <250>;
5414 polling-delay = <1000>;
5415
5416 thermal-sensors = <&tsens1 4>;
5417
5418 trips {
19e684e8 5419 q6_hvx_alert0: trip-point0 {
1c403ec2
AK		 5420 temperature = <90000>;
5421 hysteresis = <2000>;
5422 type = "hot";
5423 };
5424 };
5425 };
5426
5427 camera-thermal {
5428 polling-delay-passive = <250>;
5429 polling-delay = <1000>;
5430
5431 thermal-sensors = <&tsens1 5>;
5432
5433 trips {
19e684e8 5434 camera_alert0: trip-point0 {
1c403ec2
AK		 5435 temperature = <90000>;
5436 hysteresis = <2000>;
5437 type = "hot";
5438 };
5439 };
5440 };
5441
5442 video-thermal {
5443 polling-delay-passive = <250>;
5444 polling-delay = <1000>;
5445
5446 thermal-sensors = <&tsens1 6>;
5447
5448 trips {
19e684e8 5449 video_alert0: trip-point0 {
1c403ec2
AK		 5450 temperature = <90000>;
5451 hysteresis = <2000>;
5452 type = "hot";
5453 };
5454 };
5455 };
5456
5457 modem-thermal {
5458 polling-delay-passive = <250>;
5459 polling-delay = <1000>;
5460
5461 thermal-sensors = <&tsens1 7>;
5462
5463 trips {
19e684e8 5464 modem_alert0: trip-point0 {
1c403ec2
AK		 5465 temperature = <90000>;
5466 hysteresis = <2000>;
5467 type = "hot";
5468 };
5469 };
5470 };
4884788b 5471 };
6d4cf750 5472};
Linux 6.x block layer and io_uring tree(s)