[linux-2.6-block.git] / arch / arm64 / boot / dts / qcom / sdm845.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * SDM845 SoC device tree source
 *
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0 0x80000000 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		memory@85fc0000 {
			reg = <0 0x85fc0000 0 0x20000>;
			no-map;
		};

		memory@85fe0000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85fe0000 0x0 0x20000>;
			no-map;
		};

		smem_mem: memory@86000000 {
			reg = <0x0 0x86000000 0x0 0x200000>;
			no-map;
		};

		memory@86200000 {
			reg = <0 0x86200000 0 0x2d00000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
				L3_0: l3-cache {
				      compatible = "cache";
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_100>;
			L2_100: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&L2_200>;
			L2_200: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&L2_300>;
			L2_300: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x400>;
			enable-method = "psci";
			next-level-cache = <&L2_400>;
			L2_400: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x500>;
			enable-method = "psci";
			next-level-cache = <&L2_500>;
			L2_500: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x600>;
			enable-method = "psci";
			next-level-cache = <&L2_600>;
			L2_600: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x700>;
			enable-method = "psci";
			next-level-cache = <&L2_700>;
			L2_700: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
		};
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sdm845";
			reg = <0x100000 0x1f0000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		tcsr_mutex_regs: syscon@1f40000 {
			compatible = "syscon";
			reg = <0x1f40000 0x40000>;
		};

		tlmm: pinctrl@3400000 {
			compatible = "qcom,sdm845-pinctrl";
			reg = <0x03400000 0xc00000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0xc440000 0x1100>,
			      <0xc600000 0x2000000>,
			      <0xe600000 0x100000>,
			      <0xe700000 0xa0000>,
			      <0xc40a000 0x26000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
			cell-index = <0>;
		};

		apss_shared: mailbox@17990000 {
			compatible = "qcom,sdm845-apss-shared";
			reg = <0x17990000 0x1000>;
			#mbox-cells = <1>;
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x17a00000 0x10000>,     /* GICD */
			      <0x17a60000 0x100000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic-its@17a40000 {
				compatible = "arm,gic-v3-its";
				msi-controller;
				#msi-cells = <1>;
				reg = <0x17a40000 0x20000>;
				status = "disabled";
			};
		};

		timer@17c90000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17c90000 0x1000>;

			frame@17ca0000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17ca0000 0x1000>,
				      <0x17cb0000 0x1000>;
			};

			frame@17cc0000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cc0000 0x1000>;
				status = "disabled";
			};

			frame@17cd0000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cd0000 0x1000>;
				status = "disabled";
			};

			frame@17ce0000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17ce0000 0x1000>;
				status = "disabled";
			};

			frame@17cf0000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cf0000 0x1000>;
				status = "disabled";
			};

			frame@17d00000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17d00000 0x1000>;
				status = "disabled";
			};

			frame@17d10000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17d10000 0x1000>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
6d4cf750 RN	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* SDM845 SoC device tree source
	4	*
	5	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
	6	*/
	7
	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
	9
	10	/ {
	11	interrupt-parent = <&intc>;
	12
	13	#address-cells = <2>;
	14	#size-cells = <2>;
	15
	16	chosen { };
	17
	18	memory@80000000 {
	19	device_type = "memory";
	20	/* We expect the bootloader to fill in the size */
	21	reg = <0 0x80000000 0 0>;
	22	};
	23
71c8428e S	24	reserved-memory {
	25	#address-cells = <2>;
	26	#size-cells = <2>;
	27	ranges;
	28
	29	memory@85fc0000 {
	30	reg = <0 0x85fc0000 0 0x20000>;
	31	no-map;
	32	};
	33
2da52398 DA	34	memory@85fe0000 {
	35	compatible = "qcom,cmd-db";
	36	reg = <0x0 0x85fe0000 0x0 0x20000>;
	37	no-map;
	38	};
	39
71c8428e S	40	smem_mem: memory@86000000 {
	41	reg = <0x0 0x86000000 0x0 0x200000>;
	42	no-map;
	43	};
	44
	45	memory@86200000 {
	46	reg = <0 0x86200000 0 0x2d00000>;
	47	no-map;
	48	};
	49	};
	50
6d4cf750 RN	51	cpus {
	52	#address-cells = <2>;
	53	#size-cells = <0>;
	54
	55	CPU0: cpu@0 {
	56	device_type = "cpu";
	57	compatible = "qcom,kryo385";
	58	reg = <0x0 0x0>;
	59	enable-method = "psci";
	60	next-level-cache = <&L2_0>;
	61	L2_0: l2-cache {
	62	compatible = "cache";
	63	next-level-cache = <&L3_0>;
	64	L3_0: l3-cache {
	65	compatible = "cache";
	66	};
	67	};
	68	};
	69
	70	CPU1: cpu@100 {
	71	device_type = "cpu";
	72	compatible = "qcom,kryo385";
	73	reg = <0x0 0x100>;
	74	enable-method = "psci";
	75	next-level-cache = <&L2_100>;
	76	L2_100: l2-cache {
	77	compatible = "cache";
	78	next-level-cache = <&L3_0>;
	79	};
	80	};
	81
	82	CPU2: cpu@200 {
	83	device_type = "cpu";
	84	compatible = "qcom,kryo385";
	85	reg = <0x0 0x200>;
	86	enable-method = "psci";
	87	next-level-cache = <&L2_200>;
	88	L2_200: l2-cache {
	89	compatible = "cache";
	90	next-level-cache = <&L3_0>;
	91	};
	92	};
	93
	94	CPU3: cpu@300 {
	95	device_type = "cpu";
	96	compatible = "qcom,kryo385";
	97	reg = <0x0 0x300>;
	98	enable-method = "psci";
	99	next-level-cache = <&L2_300>;
	100	L2_300: l2-cache {
	101	compatible = "cache";
	102	next-level-cache = <&L3_0>;
	103	};
	104	};
	105
	106	CPU4: cpu@400 {
	107	device_type = "cpu";
	108	compatible = "qcom,kryo385";
	109	reg = <0x0 0x400>;
	110	enable-method = "psci";
	111	next-level-cache = <&L2_400>;
	112	L2_400: l2-cache {
	113	compatible = "cache";
	114	next-level-cache = <&L3_0>;
115	};
116	};
117
118	CPU5: cpu@500 {
119	device_type = "cpu";
120	compatible = "qcom,kryo385";
121	reg = <0x0 0x500>;
122	enable-method = "psci";
123	next-level-cache = <&L2_500>;
124	L2_500: l2-cache {
125	compatible = "cache";
126	next-level-cache = <&L3_0>;
127	};
128	};
129
130	CPU6: cpu@600 {
131	device_type = "cpu";
132	compatible = "qcom,kryo385";
133	reg = <0x0 0x600>;
134	enable-method = "psci";
135	next-level-cache = <&L2_600>;
136	L2_600: l2-cache {
137	compatible = "cache";
138	next-level-cache = <&L3_0>;
139	};
140	};
141
142	CPU7: cpu@700 {
143	device_type = "cpu";
144	compatible = "qcom,kryo385";
145	reg = <0x0 0x700>;
146	enable-method = "psci";
147	next-level-cache = <&L2_700>;
148	L2_700: l2-cache {
149	compatible = "cache";
150	next-level-cache = <&L3_0>;
151	};
152	};
153	};
154
000c4662 SB	155	pmu {
	156	compatible = "arm,armv8-pmuv3";
	157	interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	158	};
	159
6d4cf750 RN	160	timer {
	161	compatible = "arm,armv8-timer";
	162	interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
	163	<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
	164	<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
	165	<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	166	};
	167
	168	clocks {
	169	xo_board: xo-board {
	170	compatible = "fixed-clock";
	171	#clock-cells = <0>;
5ea3939c DA	172	clock-frequency = <38400000>;
5ea3939c DA	173	clock-output-names = "xo_board";
6d4cf750 RN	174	};
	175
	176	sleep_clk: sleep-clk {
	177	compatible = "fixed-clock";
	178	#clock-cells = <0>;
	179	clock-frequency = <32764>;
	180	};
	181	};
	182
71c8428e S	183	tcsr_mutex: hwlock {
	184	compatible = "qcom,tcsr-mutex";
	185	syscon = <&tcsr_mutex_regs 0 0x1000>;
	186	#hwlock-cells = <1>;
	187	};
	188
	189	smem {
	190	compatible = "qcom,smem";
	191	memory-region = <&smem_mem>;
	192	hwlocks = <&tcsr_mutex 3>;
	193	};
	194
6d4cf750 RN	195	psci {
	196	compatible = "arm,psci-1.0";
	197	method = "smc";
	198	};
	199
	200	soc: soc {
	201	#address-cells = <1>;
	202	#size-cells = <1>;
	203	ranges = <0 0 0 0xffffffff>;
	204	compatible = "simple-bus";
	205
54d7a20d DA	206	gcc: clock-controller@100000 {
	207	compatible = "qcom,gcc-sdm845";
	208	reg = <0x100000 0x1f0000>;
	209	#clock-cells = <1>;
	210	#reset-cells = <1>;
	211	#power-domain-cells = <1>;
	212	};
	213
	214	tcsr_mutex_regs: syscon@1f40000 {
	215	compatible = "syscon";
	216	reg = <0x1f40000 0x40000>;
	217	};
	218
	219	tlmm: pinctrl@3400000 {
	220	compatible = "qcom,sdm845-pinctrl";
	221	reg = <0x03400000 0xc00000>;
	222	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	223	gpio-controller;
	224	#gpio-cells = <2>;
	225	interrupt-controller;
	226	#interrupt-cells = <2>;
	227	};
	228
	229	spmi_bus: spmi@c440000 {
	230	compatible = "qcom,spmi-pmic-arb";
	231	reg = <0xc440000 0x1100>,
	232	<0xc600000 0x2000000>,
	233	<0xe600000 0x100000>,
	234	<0xe700000 0xa0000>,
	235	<0xc40a000 0x26000>;
	236	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	237	interrupt-names = "periph_irq";
	238	interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
	239	qcom,ee = <0>;
	240	qcom,channel = <0>;
	241	#address-cells = <2>;
	242	#size-cells = <0>;
	243	interrupt-controller;
	244	#interrupt-cells = <4>;
	245	cell-index = <0>;
	246	};
	247
	248	apss_shared: mailbox@17990000 {
	249	compatible = "qcom,sdm845-apss-shared";
	250	reg = <0x17990000 0x1000>;
	251	#mbox-cells = <1>;
	252	};
	253
6d4cf750 RN	254	intc: interrupt-controller@17a00000 {
	255	compatible = "arm,gic-v3";
	256	#address-cells = <1>;
	257	#size-cells = <1>;
	258	ranges;
	259	#interrupt-cells = <3>;
	260	interrupt-controller;
	261	reg = <0x17a00000 0x10000>, /* GICD */
	262	<0x17a60000 0x100000>; /* GICR * 8 */
	263	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	264
	265	gic-its@17a40000 {
	266	compatible = "arm,gic-v3-its";
	267	msi-controller;
	268	#msi-cells = <1>;
	269	reg = <0x17a40000 0x20000>;
	270	status = "disabled";
	271	};
	272	};
	273
6d4cf750 RN	274	timer@17c90000 {
	275	#address-cells = <1>;
	276	#size-cells = <1>;
	277	ranges;
	278	compatible = "arm,armv7-timer-mem";
	279	reg = <0x17c90000 0x1000>;
	280
	281	frame@17ca0000 {
	282	frame-number = <0>;
	283	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	284	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	285	reg = <0x17ca0000 0x1000>,
	286	<0x17cb0000 0x1000>;
	287	};
	288
	289	frame@17cc0000 {
	290	frame-number = <1>;
	291	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	292	reg = <0x17cc0000 0x1000>;
	293	status = "disabled";
	294	};
	295
	296	frame@17cd0000 {
	297	frame-number = <2>;
	298	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	299	reg = <0x17cd0000 0x1000>;
	300	status = "disabled";
	301	};
	302
	303	frame@17ce0000 {
	304	frame-number = <3>;
	305	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	306	reg = <0x17ce0000 0x1000>;
	307	status = "disabled";
	308	};
	309
	310	frame@17cf0000 {
	311	frame-number = <4>;
	312	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	313	reg = <0x17cf0000 0x1000>;
	314	status = "disabled";
	315	};
	316
	317	frame@17d00000 {
	318	frame-number = <5>;
	319	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	320	reg = <0x17d00000 0x1000>;
	321	status = "disabled";
	322	};
	323
	324	frame@17d10000 {
	325	frame-number = <6>;
	326	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	327	reg = <0x17d10000 0x1000>;
	328	status = "disabled";
	329	};
	330	};
6d4cf750 RN	331	};
6d4cf750 RN	332	};