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b4d82f4d VK |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2018, Linaro Limited | |
3 | ||
4 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
5 | #include <dt-bindings/clock/qcom,gcc-qcs404.h> | |
0b0c3390 | 6 | #include <dt-bindings/clock/qcom,turingcc-qcs404.h> |
bf75731d | 7 | #include <dt-bindings/clock/qcom,rpmcc.h> |
11f61210 | 8 | #include <dt-bindings/power/qcom-rpmpd.h> |
f48cee32 | 9 | #include <dt-bindings/thermal/thermal.h> |
b4d82f4d VK |
10 | |
11 | / { | |
12 | interrupt-parent = <&intc>; | |
13 | ||
14 | #address-cells = <2>; | |
15 | #size-cells = <2>; | |
16 | ||
17 | chosen { }; | |
18 | ||
19 | clocks { | |
20 | xo_board: xo-board { | |
21 | compatible = "fixed-clock"; | |
22 | #clock-cells = <0>; | |
23 | clock-frequency = <19200000>; | |
24 | }; | |
10c71fd1 JRO |
25 | |
26 | sleep_clk: sleep-clk { | |
27 | compatible = "fixed-clock"; | |
28 | #clock-cells = <0>; | |
29 | clock-frequency = <32768>; | |
30 | }; | |
b4d82f4d VK |
31 | }; |
32 | ||
33 | cpus { | |
34 | #address-cells = <1>; | |
35 | #size-cells = <0>; | |
36 | ||
37 | CPU0: cpu@100 { | |
38 | device_type = "cpu"; | |
39 | compatible = "arm,cortex-a53"; | |
40 | reg = <0x100>; | |
41 | enable-method = "psci"; | |
45ea8f32 | 42 | cpu-idle-states = <&CPU_SLEEP_0>; |
b4d82f4d | 43 | next-level-cache = <&L2_0>; |
8291e151 | 44 | #cooling-cells = <2>; |
cbccc6bc JRO |
45 | clocks = <&apcs_glb>; |
46 | operating-points-v2 = <&cpu_opp_table>; | |
04aadcaa NC |
47 | power-domains = <&cpr>; |
48 | power-domain-names = "cpr"; | |
b4d82f4d VK |
49 | }; |
50 | ||
51 | CPU1: cpu@101 { | |
52 | device_type = "cpu"; | |
53 | compatible = "arm,cortex-a53"; | |
54 | reg = <0x101>; | |
55 | enable-method = "psci"; | |
45ea8f32 | 56 | cpu-idle-states = <&CPU_SLEEP_0>; |
b4d82f4d | 57 | next-level-cache = <&L2_0>; |
8291e151 | 58 | #cooling-cells = <2>; |
cbccc6bc JRO |
59 | clocks = <&apcs_glb>; |
60 | operating-points-v2 = <&cpu_opp_table>; | |
04aadcaa NC |
61 | power-domains = <&cpr>; |
62 | power-domain-names = "cpr"; | |
b4d82f4d VK |
63 | }; |
64 | ||
65 | CPU2: cpu@102 { | |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a53"; | |
68 | reg = <0x102>; | |
69 | enable-method = "psci"; | |
45ea8f32 | 70 | cpu-idle-states = <&CPU_SLEEP_0>; |
b4d82f4d | 71 | next-level-cache = <&L2_0>; |
8291e151 | 72 | #cooling-cells = <2>; |
cbccc6bc JRO |
73 | clocks = <&apcs_glb>; |
74 | operating-points-v2 = <&cpu_opp_table>; | |
04aadcaa NC |
75 | power-domains = <&cpr>; |
76 | power-domain-names = "cpr"; | |
b4d82f4d VK |
77 | }; |
78 | ||
79 | CPU3: cpu@103 { | |
80 | device_type = "cpu"; | |
81 | compatible = "arm,cortex-a53"; | |
82 | reg = <0x103>; | |
83 | enable-method = "psci"; | |
45ea8f32 | 84 | cpu-idle-states = <&CPU_SLEEP_0>; |
b4d82f4d | 85 | next-level-cache = <&L2_0>; |
8291e151 | 86 | #cooling-cells = <2>; |
cbccc6bc JRO |
87 | clocks = <&apcs_glb>; |
88 | operating-points-v2 = <&cpu_opp_table>; | |
04aadcaa NC |
89 | power-domains = <&cpr>; |
90 | power-domain-names = "cpr"; | |
b4d82f4d VK |
91 | }; |
92 | ||
93 | L2_0: l2-cache { | |
94 | compatible = "cache"; | |
95 | cache-level = <2>; | |
96 | }; | |
45ea8f32 NC |
97 | |
98 | idle-states { | |
99 | entry-method = "psci"; | |
100 | ||
101 | CPU_SLEEP_0: cpu-sleep-0 { | |
102 | compatible = "arm,idle-state"; | |
103 | idle-state-name = "standalone-power-collapse"; | |
104 | arm,psci-suspend-param = <0x40000003>; | |
105 | entry-latency-us = <125>; | |
106 | exit-latency-us = <180>; | |
107 | min-residency-us = <595>; | |
108 | local-timer-stop; | |
109 | }; | |
110 | }; | |
b4d82f4d VK |
111 | }; |
112 | ||
b7072cc5 | 113 | cpu_opp_table: opp-table-cpu { |
04aadcaa | 114 | compatible = "operating-points-v2-kryo-cpu"; |
cbccc6bc JRO |
115 | opp-shared; |
116 | ||
117 | opp-1094400000 { | |
118 | opp-hz = /bits/ 64 <1094400000>; | |
04aadcaa | 119 | required-opps = <&cpr_opp1>; |
cbccc6bc JRO |
120 | }; |
121 | opp-1248000000 { | |
122 | opp-hz = /bits/ 64 <1248000000>; | |
04aadcaa | 123 | required-opps = <&cpr_opp2>; |
cbccc6bc JRO |
124 | }; |
125 | opp-1401600000 { | |
126 | opp-hz = /bits/ 64 <1401600000>; | |
04aadcaa NC |
127 | required-opps = <&cpr_opp3>; |
128 | }; | |
129 | }; | |
130 | ||
b7072cc5 | 131 | cpr_opp_table: opp-table-cpr { |
04aadcaa NC |
132 | compatible = "operating-points-v2-qcom-level"; |
133 | ||
134 | cpr_opp1: opp1 { | |
135 | opp-level = <1>; | |
136 | qcom,opp-fuse-level = <1>; | |
137 | }; | |
138 | cpr_opp2: opp2 { | |
139 | opp-level = <2>; | |
140 | qcom,opp-fuse-level = <2>; | |
141 | }; | |
142 | cpr_opp3: opp3 { | |
143 | opp-level = <3>; | |
144 | qcom,opp-fuse-level = <3>; | |
cbccc6bc JRO |
145 | }; |
146 | }; | |
147 | ||
e7fd184f BA |
148 | firmware { |
149 | scm: scm { | |
150 | compatible = "qcom,scm-qcs404", "qcom,scm"; | |
151 | #reset-cells = <1>; | |
152 | }; | |
153 | }; | |
154 | ||
b4d82f4d VK |
155 | memory@80000000 { |
156 | device_type = "memory"; | |
157 | /* We expect the bootloader to fill in the size */ | |
158 | reg = <0 0x80000000 0 0>; | |
159 | }; | |
160 | ||
161 | psci { | |
162 | compatible = "arm,psci-1.0"; | |
163 | method = "smc"; | |
164 | }; | |
165 | ||
d59117ab BA |
166 | reserved-memory { |
167 | #address-cells = <2>; | |
168 | #size-cells = <2>; | |
169 | ranges; | |
170 | ||
a87fa5bc BA |
171 | tz_apps_mem: memory@85900000 { |
172 | reg = <0 0x85900000 0 0x500000>; | |
173 | no-map; | |
174 | }; | |
175 | ||
176 | xbl_mem: memory@85e00000 { | |
177 | reg = <0 0x85e00000 0 0x100000>; | |
d59117ab BA |
178 | no-map; |
179 | }; | |
180 | ||
181 | smem_region: memory@85f00000 { | |
182 | reg = <0 0x85f00000 0 0x200000>; | |
183 | no-map; | |
184 | }; | |
185 | ||
a87fa5bc | 186 | tz_mem: memory@86100000 { |
d59117ab BA |
187 | reg = <0 0x86100000 0 0x300000>; |
188 | no-map; | |
189 | }; | |
190 | ||
191 | wlan_fw_mem: memory@86400000 { | |
a87fa5bc BA |
192 | reg = <0 0x86400000 0 0x1100000>; |
193 | no-map; | |
194 | }; | |
195 | ||
196 | adsp_fw_mem: memory@87500000 { | |
197 | reg = <0 0x87500000 0 0x1a00000>; | |
d59117ab BA |
198 | no-map; |
199 | }; | |
200 | ||
a87fa5bc BA |
201 | cdsp_fw_mem: memory@88f00000 { |
202 | reg = <0 0x88f00000 0 0x600000>; | |
d59117ab BA |
203 | no-map; |
204 | }; | |
205 | ||
a87fa5bc BA |
206 | wlan_msa_mem: memory@89500000 { |
207 | reg = <0 0x89500000 0 0x100000>; | |
d59117ab BA |
208 | no-map; |
209 | }; | |
210 | ||
a87fa5bc BA |
211 | uefi_mem: memory@9f800000 { |
212 | reg = <0 0x9f800000 0 0x800000>; | |
d59117ab BA |
213 | no-map; |
214 | }; | |
215 | }; | |
216 | ||
7fc7089d BA |
217 | rpm-glink { |
218 | compatible = "qcom,glink-rpm"; | |
219 | ||
220 | interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; | |
221 | qcom,rpm-msg-ram = <&rpm_msg_ram>; | |
222 | mboxes = <&apcs_glb 0>; | |
223 | ||
224 | rpm_requests: glink-channel { | |
225 | compatible = "qcom,rpm-qcs404"; | |
226 | qcom,glink-channels = "rpm_requests"; | |
bf75731d BA |
227 | |
228 | rpmcc: clock-controller { | |
229 | compatible = "qcom,rpmcc-qcs404"; | |
230 | #clock-cells = <1>; | |
231 | }; | |
11f61210 BA |
232 | |
233 | rpmpd: power-controller { | |
234 | compatible = "qcom,qcs404-rpmpd"; | |
235 | #power-domain-cells = <1>; | |
236 | operating-points-v2 = <&rpmpd_opp_table>; | |
237 | ||
238 | rpmpd_opp_table: opp-table { | |
239 | compatible = "operating-points-v2"; | |
240 | ||
241 | rpmpd_opp_ret: opp1 { | |
242 | opp-level = <16>; | |
243 | }; | |
244 | ||
245 | rpmpd_opp_ret_plus: opp2 { | |
246 | opp-level = <32>; | |
247 | }; | |
248 | ||
249 | rpmpd_opp_min_svs: opp3 { | |
250 | opp-level = <48>; | |
251 | }; | |
252 | ||
253 | rpmpd_opp_low_svs: opp4 { | |
254 | opp-level = <64>; | |
255 | }; | |
256 | ||
257 | rpmpd_opp_svs: opp5 { | |
258 | opp-level = <128>; | |
259 | }; | |
260 | ||
261 | rpmpd_opp_svs_plus: opp6 { | |
262 | opp-level = <192>; | |
263 | }; | |
264 | ||
265 | rpmpd_opp_nom: opp7 { | |
266 | opp-level = <256>; | |
267 | }; | |
268 | ||
269 | rpmpd_opp_nom_plus: opp8 { | |
270 | opp-level = <320>; | |
271 | }; | |
272 | ||
273 | rpmpd_opp_turbo: opp9 { | |
274 | opp-level = <384>; | |
275 | }; | |
276 | ||
277 | rpmpd_opp_turbo_no_cpr: opp10 { | |
278 | opp-level = <416>; | |
279 | }; | |
280 | ||
281 | rpmpd_opp_turbo_plus: opp11 { | |
282 | opp-level = <512>; | |
283 | }; | |
284 | }; | |
285 | }; | |
7fc7089d BA |
286 | }; |
287 | }; | |
288 | ||
289 | smem { | |
290 | compatible = "qcom,smem"; | |
291 | ||
292 | memory-region = <&smem_region>; | |
293 | qcom,rpm-msg-ram = <&rpm_msg_ram>; | |
294 | ||
295 | hwlocks = <&tcsr_mutex 3>; | |
296 | }; | |
297 | ||
298 | tcsr_mutex: hwlock { | |
299 | compatible = "qcom,tcsr-mutex"; | |
300 | syscon = <&tcsr_mutex_regs 0 0x1000>; | |
301 | #hwlock-cells = <1>; | |
302 | }; | |
303 | ||
b4d82f4d VK |
304 | soc: soc@0 { |
305 | #address-cells = <1>; | |
306 | #size-cells = <1>; | |
307 | ranges = <0 0 0 0xffffffff>; | |
308 | compatible = "simple-bus"; | |
309 | ||
0b0c3390 BA |
310 | turingcc: clock-controller@800000 { |
311 | compatible = "qcom,qcs404-turingcc"; | |
312 | reg = <0x00800000 0x30000>; | |
313 | clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; | |
314 | ||
315 | #clock-cells = <1>; | |
316 | #reset-cells = <1>; | |
317 | ||
318 | status = "disabled"; | |
319 | }; | |
320 | ||
179811be | 321 | rpm_msg_ram: sram@60000 { |
7fc7089d BA |
322 | compatible = "qcom,rpm-msg-ram"; |
323 | reg = <0x00060000 0x6000>; | |
324 | }; | |
325 | ||
9375e7d7 BA |
326 | usb3_phy: phy@78000 { |
327 | compatible = "qcom,usb-ss-28nm-phy"; | |
328 | reg = <0x00078000 0x400>; | |
329 | #phy-cells = <0>; | |
330 | clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, | |
331 | <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, | |
332 | <&gcc GCC_USB3_PHY_PIPE_CLK>; | |
333 | clock-names = "ref", "ahb", "pipe"; | |
334 | resets = <&gcc GCC_USB3_PHY_BCR>, | |
335 | <&gcc GCC_USB3PHY_PHY_BCR>; | |
336 | reset-names = "com", "phy"; | |
337 | status = "disabled"; | |
338 | }; | |
339 | ||
340 | usb2_phy_prim: phy@7a000 { | |
341 | compatible = "qcom,usb-hs-28nm-femtophy"; | |
342 | reg = <0x0007a000 0x200>; | |
343 | #phy-cells = <0>; | |
344 | clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, | |
345 | <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, | |
346 | <&gcc GCC_USB2A_PHY_SLEEP_CLK>; | |
347 | clock-names = "ref", "ahb", "sleep"; | |
348 | resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, | |
349 | <&gcc GCC_USB2A_PHY_BCR>; | |
350 | reset-names = "phy", "por"; | |
351 | status = "disabled"; | |
352 | }; | |
353 | ||
354 | usb2_phy_sec: phy@7c000 { | |
355 | compatible = "qcom,usb-hs-28nm-femtophy"; | |
356 | reg = <0x0007c000 0x200>; | |
357 | #phy-cells = <0>; | |
358 | clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, | |
359 | <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, | |
360 | <&gcc GCC_USB2A_PHY_SLEEP_CLK>; | |
361 | clock-names = "ref", "ahb", "sleep"; | |
362 | resets = <&gcc GCC_QUSB2_PHY_BCR>, | |
363 | <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; | |
364 | reset-names = "phy", "por"; | |
365 | status = "disabled"; | |
366 | }; | |
367 | ||
64cf50d0 AK |
368 | qfprom: qfprom@a4000 { |
369 | compatible = "qcom,qfprom"; | |
370 | reg = <0x000a4000 0x1000>; | |
371 | #address-cells = <1>; | |
372 | #size-cells = <1>; | |
373 | tsens_caldata: caldata@d0 { | |
374 | reg = <0x1f8 0x14>; | |
375 | }; | |
04aadcaa NC |
376 | cpr_efuse_speedbin: speedbin@13c { |
377 | reg = <0x13c 0x4>; | |
378 | bits = <2 3>; | |
379 | }; | |
380 | cpr_efuse_quot_offset1: qoffset1@231 { | |
381 | reg = <0x231 0x4>; | |
382 | bits = <4 7>; | |
383 | }; | |
384 | cpr_efuse_quot_offset2: qoffset2@232 { | |
385 | reg = <0x232 0x4>; | |
386 | bits = <3 7>; | |
387 | }; | |
388 | cpr_efuse_quot_offset3: qoffset3@233 { | |
389 | reg = <0x233 0x4>; | |
390 | bits = <2 7>; | |
391 | }; | |
392 | cpr_efuse_init_voltage1: ivoltage1@229 { | |
393 | reg = <0x229 0x4>; | |
394 | bits = <4 6>; | |
395 | }; | |
396 | cpr_efuse_init_voltage2: ivoltage2@22a { | |
397 | reg = <0x22a 0x4>; | |
398 | bits = <2 6>; | |
399 | }; | |
400 | cpr_efuse_init_voltage3: ivoltage3@22b { | |
401 | reg = <0x22b 0x4>; | |
402 | bits = <0 6>; | |
403 | }; | |
404 | cpr_efuse_quot1: quot1@22b { | |
405 | reg = <0x22b 0x4>; | |
406 | bits = <6 12>; | |
407 | }; | |
408 | cpr_efuse_quot2: quot2@22d { | |
409 | reg = <0x22d 0x4>; | |
410 | bits = <2 12>; | |
411 | }; | |
412 | cpr_efuse_quot3: quot3@230 { | |
413 | reg = <0x230 0x4>; | |
414 | bits = <0 12>; | |
415 | }; | |
416 | cpr_efuse_ring1: ring1@228 { | |
417 | reg = <0x228 0x4>; | |
418 | bits = <0 3>; | |
419 | }; | |
420 | cpr_efuse_ring2: ring2@228 { | |
421 | reg = <0x228 0x4>; | |
422 | bits = <4 3>; | |
423 | }; | |
424 | cpr_efuse_ring3: ring3@229 { | |
425 | reg = <0x229 0x4>; | |
426 | bits = <0 3>; | |
427 | }; | |
428 | cpr_efuse_revision: revision@218 { | |
429 | reg = <0x218 0x4>; | |
430 | bits = <3 3>; | |
431 | }; | |
64cf50d0 AK |
432 | }; |
433 | ||
df96c65c VK |
434 | rng: rng@e3000 { |
435 | compatible = "qcom,prng-ee"; | |
436 | reg = <0x000e3000 0x1000>; | |
437 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | |
438 | clock-names = "core"; | |
439 | }; | |
440 | ||
668c7603 GD |
441 | bimc: interconnect@400000 { |
442 | reg = <0x00400000 0x80000>; | |
443 | compatible = "qcom,qcs404-bimc"; | |
444 | #interconnect-cells = <1>; | |
445 | clock-names = "bus", "bus_a"; | |
446 | clocks = <&rpmcc RPM_SMD_BIMC_CLK>, | |
447 | <&rpmcc RPM_SMD_BIMC_A_CLK>; | |
448 | }; | |
449 | ||
64cf50d0 AK |
450 | tsens: thermal-sensor@4a9000 { |
451 | compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; | |
452 | reg = <0x004a9000 0x1000>, /* TM */ | |
453 | <0x004a8000 0x1000>; /* SROT */ | |
454 | nvmem-cells = <&tsens_caldata>; | |
455 | nvmem-cell-names = "calib"; | |
456 | #qcom,sensors = <10>; | |
e51f7ff4 AK |
457 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
458 | interrupt-names = "uplow"; | |
64cf50d0 AK |
459 | #thermal-sensor-cells = <1>; |
460 | }; | |
461 | ||
668c7603 GD |
462 | pcnoc: interconnect@500000 { |
463 | reg = <0x00500000 0x15080>; | |
464 | compatible = "qcom,qcs404-pcnoc"; | |
465 | #interconnect-cells = <1>; | |
466 | clock-names = "bus", "bus_a"; | |
467 | clocks = <&rpmcc RPM_SMD_PNOC_CLK>, | |
468 | <&rpmcc RPM_SMD_PNOC_A_CLK>; | |
469 | }; | |
470 | ||
471 | snoc: interconnect@580000 { | |
472 | reg = <0x00580000 0x23080>; | |
473 | compatible = "qcom,qcs404-snoc"; | |
474 | #interconnect-cells = <1>; | |
475 | clock-names = "bus", "bus_a"; | |
476 | clocks = <&rpmcc RPM_SMD_SNOC_CLK>, | |
477 | <&rpmcc RPM_SMD_SNOC_A_CLK>; | |
478 | }; | |
479 | ||
f4dd04a8 BA |
480 | remoteproc_cdsp: remoteproc@b00000 { |
481 | compatible = "qcom,qcs404-cdsp-pas"; | |
482 | reg = <0x00b00000 0x4040>; | |
483 | ||
484 | interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, | |
485 | <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
486 | <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, | |
487 | <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, | |
488 | <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; | |
489 | interrupt-names = "wdog", "fatal", "ready", | |
490 | "handover", "stop-ack"; | |
491 | ||
492 | clocks = <&xo_board>, | |
493 | <&gcc GCC_CDSP_CFG_AHB_CLK>, | |
494 | <&gcc GCC_CDSP_TBU_CLK>, | |
495 | <&gcc GCC_BIMC_CDSP_CLK>, | |
496 | <&turingcc TURING_WRAPPER_AON_CLK>, | |
497 | <&turingcc TURING_Q6SS_AHBS_AON_CLK>, | |
498 | <&turingcc TURING_Q6SS_AHBM_AON_CLK>, | |
499 | <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; | |
500 | clock-names = "xo", | |
501 | "sway", | |
502 | "tbu", | |
503 | "bimc", | |
504 | "ahb_aon", | |
505 | "q6ss_slave", | |
506 | "q6ss_master", | |
507 | "q6_axim"; | |
508 | ||
509 | resets = <&gcc GCC_CDSP_RESTART>; | |
510 | reset-names = "restart"; | |
511 | ||
512 | qcom,halt-regs = <&tcsr 0x19004>; | |
513 | ||
514 | memory-region = <&cdsp_fw_mem>; | |
515 | ||
516 | qcom,smem-states = <&cdsp_smp2p_out 0>; | |
517 | qcom,smem-state-names = "stop"; | |
518 | ||
519 | status = "disabled"; | |
520 | ||
521 | glink-edge { | |
522 | interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; | |
523 | ||
524 | qcom,remote-pid = <5>; | |
525 | mboxes = <&apcs_glb 12>; | |
526 | ||
527 | label = "cdsp"; | |
528 | }; | |
529 | }; | |
530 | ||
9375e7d7 BA |
531 | usb3: usb@7678800 { |
532 | compatible = "qcom,dwc3"; | |
533 | reg = <0x07678800 0x400>; | |
534 | #address-cells = <1>; | |
535 | #size-cells = <1>; | |
536 | ranges; | |
537 | clocks = <&gcc GCC_USB30_MASTER_CLK>, | |
538 | <&gcc GCC_SYS_NOC_USB3_CLK>, | |
539 | <&gcc GCC_USB30_SLEEP_CLK>, | |
540 | <&gcc GCC_USB30_MOCK_UTMI_CLK>; | |
541 | clock-names = "core", "iface", "sleep", "mock_utmi"; | |
542 | assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, | |
543 | <&gcc GCC_USB30_MASTER_CLK>; | |
544 | assigned-clock-rates = <19200000>, <200000000>; | |
545 | status = "disabled"; | |
546 | ||
1f958f3d | 547 | dwc3@7580000 { |
9375e7d7 BA |
548 | compatible = "snps,dwc3"; |
549 | reg = <0x07580000 0xcd00>; | |
550 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
551 | phys = <&usb2_phy_sec>, <&usb3_phy>; | |
552 | phy-names = "usb2-phy", "usb3-phy"; | |
553 | snps,has-lpm-erratum; | |
554 | snps,hird-threshold = /bits/ 8 <0x10>; | |
555 | snps,usb3_lpm_capable; | |
556 | dr_mode = "otg"; | |
557 | }; | |
558 | }; | |
559 | ||
560 | usb2: usb@79b8800 { | |
561 | compatible = "qcom,dwc3"; | |
562 | reg = <0x079b8800 0x400>; | |
563 | #address-cells = <1>; | |
564 | #size-cells = <1>; | |
565 | ranges; | |
566 | clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, | |
567 | <&gcc GCC_PCNOC_USB2_CLK>, | |
568 | <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, | |
569 | <&gcc GCC_USB20_MOCK_UTMI_CLK>; | |
570 | clock-names = "core", "iface", "sleep", "mock_utmi"; | |
571 | assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, | |
572 | <&gcc GCC_USB_HS_SYSTEM_CLK>; | |
573 | assigned-clock-rates = <19200000>, <133333333>; | |
574 | status = "disabled"; | |
575 | ||
1f958f3d | 576 | dwc3@78c0000 { |
9375e7d7 BA |
577 | compatible = "snps,dwc3"; |
578 | reg = <0x078c0000 0xcc00>; | |
579 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
580 | phys = <&usb2_phy_prim>; | |
581 | phy-names = "usb2-phy"; | |
582 | snps,has-lpm-erratum; | |
583 | snps,hird-threshold = /bits/ 8 <0x10>; | |
584 | snps,usb3_lpm_capable; | |
585 | dr_mode = "peripheral"; | |
586 | }; | |
587 | }; | |
588 | ||
75f6e6d9 BA |
589 | tlmm: pinctrl@1000000 { |
590 | compatible = "qcom,qcs404-pinctrl"; | |
591 | reg = <0x01000000 0x200000>, | |
592 | <0x01300000 0x200000>, | |
593 | <0x07b00000 0x200000>; | |
594 | reg-names = "south", "north", "east"; | |
595 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
596 | gpio-ranges = <&tlmm 0 0 120>; | |
597 | gpio-controller; | |
598 | #gpio-cells = <2>; | |
599 | interrupt-controller; | |
600 | #interrupt-cells = <2>; | |
5bb9ab94 | 601 | |
734e6d02 BA |
602 | blsp1_i2c0_default: blsp1-i2c0-default { |
603 | pins = "gpio32", "gpio33"; | |
604 | function = "blsp_i2c0"; | |
605 | }; | |
606 | ||
607 | blsp1_i2c1_default: blsp1-i2c1-default { | |
608 | pins = "gpio24", "gpio25"; | |
609 | function = "blsp_i2c1"; | |
610 | }; | |
611 | ||
612 | blsp1_i2c2_default: blsp1-i2c2-default { | |
613 | sda { | |
614 | pins = "gpio19"; | |
615 | function = "blsp_i2c_sda_a2"; | |
616 | }; | |
617 | ||
618 | scl { | |
619 | pins = "gpio20"; | |
620 | function = "blsp_i2c_scl_a2"; | |
621 | }; | |
622 | }; | |
623 | ||
624 | blsp1_i2c3_default: blsp1-i2c3-default { | |
625 | pins = "gpio84", "gpio85"; | |
626 | function = "blsp_i2c3"; | |
627 | }; | |
628 | ||
629 | blsp1_i2c4_default: blsp1-i2c4-default { | |
630 | pins = "gpio117", "gpio118"; | |
631 | function = "blsp_i2c4"; | |
632 | }; | |
633 | ||
bf9aa8a4 BA |
634 | blsp1_uart0_default: blsp1-uart0-default { |
635 | pins = "gpio30", "gpio31", "gpio32", "gpio33"; | |
636 | function = "blsp_uart0"; | |
637 | }; | |
638 | ||
639 | blsp1_uart1_default: blsp1-uart1-default { | |
640 | pins = "gpio22", "gpio23"; | |
641 | function = "blsp_uart1"; | |
642 | }; | |
643 | ||
5bb9ab94 BA |
644 | blsp1_uart2_default: blsp1-uart2-default { |
645 | rx { | |
646 | pins = "gpio18"; | |
647 | function = "blsp_uart_rx_a2"; | |
648 | }; | |
649 | ||
650 | tx { | |
651 | pins = "gpio17"; | |
652 | function = "blsp_uart_tx_a2"; | |
653 | }; | |
654 | }; | |
bf9aa8a4 BA |
655 | |
656 | blsp1_uart3_default: blsp1-uart3-default { | |
657 | pins = "gpio82", "gpio83", "gpio84", "gpio85"; | |
658 | function = "blsp_uart3"; | |
659 | }; | |
660 | ||
734e6d02 BA |
661 | blsp2_i2c0_default: blsp2-i2c0-default { |
662 | pins = "gpio28", "gpio29"; | |
663 | function = "blsp_i2c5"; | |
664 | }; | |
665 | ||
666 | blsp1_spi0_default: blsp1-spi0-default { | |
667 | pins = "gpio30", "gpio31", "gpio32", "gpio33"; | |
668 | function = "blsp_spi0"; | |
669 | }; | |
670 | ||
671 | blsp1_spi1_default: blsp1-spi1-default { | |
672 | pins = "gpio22", "gpio23", "gpio24", "gpio25"; | |
673 | function = "blsp_spi1"; | |
674 | }; | |
675 | ||
676 | blsp1_spi2_default: blsp1-spi2-default { | |
677 | pins = "gpio17", "gpio18", "gpio19", "gpio20"; | |
678 | function = "blsp_spi2"; | |
679 | }; | |
680 | ||
681 | blsp1_spi3_default: blsp1-spi3-default { | |
682 | pins = "gpio82", "gpio83", "gpio84", "gpio85"; | |
683 | function = "blsp_spi3"; | |
684 | }; | |
685 | ||
686 | blsp1_spi4_default: blsp1-spi4-default { | |
687 | pins = "gpio37", "gpio38", "gpio117", "gpio118"; | |
688 | function = "blsp_spi4"; | |
689 | }; | |
690 | ||
691 | blsp2_spi0_default: blsp2-spi0-default { | |
692 | pins = "gpio26", "gpio27", "gpio28", "gpio29"; | |
693 | function = "blsp_spi5"; | |
694 | }; | |
695 | ||
bf9aa8a4 BA |
696 | blsp2_uart0_default: blsp2-uart0-default { |
697 | pins = "gpio26", "gpio27", "gpio28", "gpio29"; | |
698 | function = "blsp_uart5"; | |
699 | }; | |
75f6e6d9 BA |
700 | }; |
701 | ||
b4d82f4d VK |
702 | gcc: clock-controller@1800000 { |
703 | compatible = "qcom,gcc-qcs404"; | |
704 | reg = <0x01800000 0x80000>; | |
705 | #clock-cells = <1>; | |
4b2c7ea8 | 706 | #reset-cells = <1>; |
b4d82f4d VK |
707 | |
708 | assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; | |
709 | assigned-clock-rates = <19200000>; | |
710 | }; | |
711 | ||
7fc7089d BA |
712 | tcsr_mutex_regs: syscon@1905000 { |
713 | compatible = "syscon"; | |
714 | reg = <0x01905000 0x20000>; | |
715 | }; | |
716 | ||
560ad5e7 BA |
717 | tcsr: syscon@1937000 { |
718 | compatible = "syscon"; | |
719 | reg = <0x01937000 0x25000>; | |
720 | }; | |
721 | ||
290bc684 MS |
722 | sram@290000 { |
723 | compatible = "qcom,rpm-stats"; | |
724 | reg = <0x00290000 0x10000>; | |
725 | }; | |
726 | ||
1a94b65b VK |
727 | spmi_bus: spmi@200f000 { |
728 | compatible = "qcom,spmi-pmic-arb"; | |
729 | reg = <0x0200f000 0x001000>, | |
730 | <0x02400000 0x800000>, | |
731 | <0x02c00000 0x800000>, | |
732 | <0x03800000 0x200000>, | |
733 | <0x0200a000 0x002100>; | |
734 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
735 | interrupt-names = "periph_irq"; | |
736 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | |
737 | qcom,ee = <0>; | |
738 | qcom,channel = <0>; | |
739 | #address-cells = <2>; | |
740 | #size-cells = <0>; | |
741 | interrupt-controller; | |
742 | #interrupt-cells = <4>; | |
743 | }; | |
744 | ||
67779ca2 BA |
745 | remoteproc_wcss: remoteproc@7400000 { |
746 | compatible = "qcom,qcs404-wcss-pas"; | |
747 | reg = <0x07400000 0x4040>; | |
748 | ||
749 | interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, | |
750 | <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
751 | <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, | |
752 | <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, | |
753 | <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; | |
754 | interrupt-names = "wdog", "fatal", "ready", | |
755 | "handover", "stop-ack"; | |
756 | ||
757 | clocks = <&xo_board>; | |
758 | clock-names = "xo"; | |
759 | ||
760 | memory-region = <&wlan_fw_mem>; | |
761 | ||
762 | qcom,smem-states = <&wcss_smp2p_out 0>; | |
763 | qcom,smem-state-names = "stop"; | |
764 | ||
765 | status = "disabled"; | |
766 | ||
767 | glink-edge { | |
768 | interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; | |
769 | ||
770 | qcom,remote-pid = <1>; | |
771 | mboxes = <&apcs_glb 16>; | |
772 | ||
773 | label = "wcss"; | |
774 | }; | |
775 | }; | |
776 | ||
431f6464 BA |
777 | pcie_phy: phy@7786000 { |
778 | compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; | |
779 | reg = <0x07786000 0xb8>; | |
780 | ||
781 | clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; | |
782 | resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, | |
783 | <&gcc 21>; | |
784 | reset-names = "phy", "pipe"; | |
785 | ||
786 | clock-output-names = "pcie_0_pipe_clk"; | |
787 | #phy-cells = <0>; | |
788 | ||
789 | status = "disabled"; | |
790 | }; | |
791 | ||
7241ab94 | 792 | sdcc1: sdcc@7804000 { |
f8c84813 | 793 | compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; |
7241ab94 | 794 | reg = <0x07804000 0x1000>, <0x7805000 0x1000>; |
557a2aba | 795 | reg-names = "hc", "cqhci"; |
7241ab94 BA |
796 | |
797 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
798 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
799 | interrupt-names = "hc_irq", "pwr_irq"; | |
800 | ||
801 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, | |
802 | <&gcc GCC_SDCC1_AHB_CLK>, | |
803 | <&xo_board>; | |
804 | clock-names = "core", "iface", "xo"; | |
805 | ||
806 | status = "disabled"; | |
807 | }; | |
808 | ||
6bd61ef4 | 809 | blsp1_dma: dma-controller@7884000 { |
e77c5206 VK |
810 | compatible = "qcom,bam-v1.7.0"; |
811 | reg = <0x07884000 0x25000>; | |
812 | interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; | |
813 | clocks = <&gcc GCC_BLSP1_AHB_CLK>; | |
814 | clock-names = "bam_clk"; | |
815 | #dma-cells = <1>; | |
e77c5206 VK |
816 | qcom,ee = <0>; |
817 | status = "okay"; | |
818 | }; | |
819 | ||
bf9aa8a4 BA |
820 | blsp1_uart0: serial@78af000 { |
821 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
822 | reg = <0x078af000 0x200>; | |
823 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
824 | clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
825 | clock-names = "core", "iface"; | |
0e1b27f4 KK |
826 | dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; |
827 | dma-names = "tx", "rx"; | |
bf9aa8a4 BA |
828 | pinctrl-names = "default"; |
829 | pinctrl-0 = <&blsp1_uart0_default>; | |
830 | status = "disabled"; | |
831 | }; | |
832 | ||
833 | blsp1_uart1: serial@78b0000 { | |
834 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
835 | reg = <0x078b0000 0x200>; | |
836 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
837 | clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
838 | clock-names = "core", "iface"; | |
0e1b27f4 KK |
839 | dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; |
840 | dma-names = "tx", "rx"; | |
bf9aa8a4 BA |
841 | pinctrl-names = "default"; |
842 | pinctrl-0 = <&blsp1_uart1_default>; | |
843 | status = "disabled"; | |
844 | }; | |
845 | ||
b4d82f4d VK |
846 | blsp1_uart2: serial@78b1000 { |
847 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
848 | reg = <0x078b1000 0x200>; | |
849 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
850 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
851 | clock-names = "core", "iface"; | |
0e1b27f4 KK |
852 | dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; |
853 | dma-names = "tx", "rx"; | |
5bb9ab94 BA |
854 | pinctrl-names = "default"; |
855 | pinctrl-0 = <&blsp1_uart2_default>; | |
b4d82f4d VK |
856 | status = "okay"; |
857 | }; | |
858 | ||
4dfa70ea VK |
859 | ethernet: ethernet@7a80000 { |
860 | compatible = "qcom,qcs404-ethqos"; | |
861 | reg = <0x07a80000 0x10000>, | |
862 | <0x07a96000 0x100>; | |
863 | reg-names = "stmmaceth", "rgmii"; | |
864 | clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; | |
865 | clocks = <&gcc GCC_ETH_AXI_CLK>, | |
866 | <&gcc GCC_ETH_SLAVE_AHB_CLK>, | |
867 | <&gcc GCC_ETH_PTP_CLK>, | |
868 | <&gcc GCC_ETH_RGMII_CLK>; | |
869 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
870 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
871 | interrupt-names = "macirq", "eth_lpi"; | |
872 | ||
873 | snps,tso; | |
874 | rx-fifo-depth = <4096>; | |
875 | tx-fifo-depth = <4096>; | |
876 | ||
877 | status = "disabled"; | |
878 | }; | |
879 | ||
4bbbca1e GS |
880 | wifi: wifi@a000000 { |
881 | compatible = "qcom,wcn3990-wifi"; | |
882 | reg = <0xa000000 0x800000>; | |
883 | reg-names = "membase"; | |
884 | memory-region = <&wlan_msa_mem>; | |
885 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, | |
886 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, | |
887 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
888 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, | |
889 | <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, | |
890 | <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, | |
891 | <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, | |
892 | <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, | |
893 | <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, | |
894 | <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, | |
895 | <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, | |
896 | <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
897 | status = "disabled"; | |
898 | }; | |
899 | ||
bf9aa8a4 BA |
900 | blsp1_uart3: serial@78b2000 { |
901 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
902 | reg = <0x078b2000 0x200>; | |
903 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
904 | clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
905 | clock-names = "core", "iface"; | |
0e1b27f4 KK |
906 | dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; |
907 | dma-names = "tx", "rx"; | |
bf9aa8a4 BA |
908 | pinctrl-names = "default"; |
909 | pinctrl-0 = <&blsp1_uart3_default>; | |
910 | status = "disabled"; | |
911 | }; | |
912 | ||
734e6d02 BA |
913 | blsp1_i2c0: i2c@78b5000 { |
914 | compatible = "qcom,i2c-qup-v2.2.1"; | |
915 | reg = <0x078b5000 0x600>; | |
916 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
917 | clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, |
918 | <&gcc GCC_BLSP1_AHB_CLK>; | |
919 | clock-names = "core", "iface"; | |
734e6d02 BA |
920 | pinctrl-names = "default"; |
921 | pinctrl-0 = <&blsp1_i2c0_default>; | |
922 | #address-cells = <1>; | |
923 | #size-cells = <0>; | |
924 | status = "disabled"; | |
925 | }; | |
926 | ||
927 | blsp1_spi0: spi@78b5000 { | |
928 | compatible = "qcom,spi-qup-v2.2.1"; | |
929 | reg = <0x078b5000 0x600>; | |
930 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
931 | clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, |
932 | <&gcc GCC_BLSP1_AHB_CLK>; | |
933 | clock-names = "core", "iface"; | |
734e6d02 BA |
934 | pinctrl-names = "default"; |
935 | pinctrl-0 = <&blsp1_spi0_default>; | |
936 | #address-cells = <1>; | |
937 | #size-cells = <0>; | |
938 | status = "disabled"; | |
939 | }; | |
940 | ||
941 | blsp1_i2c1: i2c@78b6000 { | |
942 | compatible = "qcom,i2c-qup-v2.2.1"; | |
943 | reg = <0x078b6000 0x600>; | |
944 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
945 | clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, |
946 | <&gcc GCC_BLSP1_AHB_CLK>; | |
947 | clock-names = "core", "iface"; | |
734e6d02 BA |
948 | pinctrl-names = "default"; |
949 | pinctrl-0 = <&blsp1_i2c1_default>; | |
950 | #address-cells = <1>; | |
951 | #size-cells = <0>; | |
952 | status = "disabled"; | |
953 | }; | |
954 | ||
955 | blsp1_spi1: spi@78b6000 { | |
956 | compatible = "qcom,spi-qup-v2.2.1"; | |
957 | reg = <0x078b6000 0x600>; | |
958 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
959 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, |
960 | <&gcc GCC_BLSP1_AHB_CLK>; | |
961 | clock-names = "core", "iface"; | |
734e6d02 BA |
962 | pinctrl-names = "default"; |
963 | pinctrl-0 = <&blsp1_spi1_default>; | |
964 | #address-cells = <1>; | |
965 | #size-cells = <0>; | |
966 | status = "disabled"; | |
967 | }; | |
968 | ||
969 | blsp1_i2c2: i2c@78b7000 { | |
970 | compatible = "qcom,i2c-qup-v2.2.1"; | |
971 | reg = <0x078b7000 0x600>; | |
972 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
973 | clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, |
974 | <&gcc GCC_BLSP1_AHB_CLK>; | |
975 | clock-names = "core", "iface"; | |
734e6d02 BA |
976 | pinctrl-names = "default"; |
977 | pinctrl-0 = <&blsp1_i2c2_default>; | |
978 | #address-cells = <1>; | |
979 | #size-cells = <0>; | |
980 | status = "disabled"; | |
981 | }; | |
982 | ||
983 | blsp1_spi2: spi@78b7000 { | |
984 | compatible = "qcom,spi-qup-v2.2.1"; | |
985 | reg = <0x078b7000 0x600>; | |
986 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
987 | clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, |
988 | <&gcc GCC_BLSP1_AHB_CLK>; | |
989 | clock-names = "core", "iface"; | |
734e6d02 BA |
990 | pinctrl-names = "default"; |
991 | pinctrl-0 = <&blsp1_spi2_default>; | |
992 | #address-cells = <1>; | |
993 | #size-cells = <0>; | |
994 | status = "disabled"; | |
995 | }; | |
996 | ||
997 | blsp1_i2c3: i2c@78b8000 { | |
998 | compatible = "qcom,i2c-qup-v2.2.1"; | |
999 | reg = <0x078b8000 0x600>; | |
1000 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
1001 | clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, |
1002 | <&gcc GCC_BLSP1_AHB_CLK>; | |
1003 | clock-names = "core", "iface"; | |
734e6d02 BA |
1004 | pinctrl-names = "default"; |
1005 | pinctrl-0 = <&blsp1_i2c3_default>; | |
1006 | #address-cells = <1>; | |
1007 | #size-cells = <0>; | |
1008 | status = "disabled"; | |
1009 | }; | |
1010 | ||
1011 | blsp1_spi3: spi@78b8000 { | |
1012 | compatible = "qcom,spi-qup-v2.2.1"; | |
1013 | reg = <0x078b8000 0x600>; | |
1014 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
1015 | clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, |
1016 | <&gcc GCC_BLSP1_AHB_CLK>; | |
1017 | clock-names = "core", "iface"; | |
734e6d02 BA |
1018 | pinctrl-names = "default"; |
1019 | pinctrl-0 = <&blsp1_spi3_default>; | |
1020 | #address-cells = <1>; | |
1021 | #size-cells = <0>; | |
1022 | status = "disabled"; | |
1023 | }; | |
1024 | ||
1025 | blsp1_i2c4: i2c@78b9000 { | |
1026 | compatible = "qcom,i2c-qup-v2.2.1"; | |
1027 | reg = <0x078b9000 0x600>; | |
1028 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
1029 | clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, |
1030 | <&gcc GCC_BLSP1_AHB_CLK>; | |
1031 | clock-names = "core", "iface"; | |
734e6d02 BA |
1032 | pinctrl-names = "default"; |
1033 | pinctrl-0 = <&blsp1_i2c4_default>; | |
1034 | #address-cells = <1>; | |
1035 | #size-cells = <0>; | |
1036 | status = "disabled"; | |
1037 | }; | |
1038 | ||
1039 | blsp1_spi4: spi@78b9000 { | |
1040 | compatible = "qcom,spi-qup-v2.2.1"; | |
1041 | reg = <0x078b9000 0x600>; | |
1042 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
1043 | clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, |
1044 | <&gcc GCC_BLSP1_AHB_CLK>; | |
1045 | clock-names = "core", "iface"; | |
734e6d02 BA |
1046 | pinctrl-names = "default"; |
1047 | pinctrl-0 = <&blsp1_spi4_default>; | |
1048 | #address-cells = <1>; | |
1049 | #size-cells = <0>; | |
1050 | status = "disabled"; | |
1051 | }; | |
1052 | ||
6bd61ef4 | 1053 | blsp2_dma: dma-controller@7ac4000 { |
bf9aa8a4 BA |
1054 | compatible = "qcom,bam-v1.7.0"; |
1055 | reg = <0x07ac4000 0x17000>; | |
1056 | interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; | |
1057 | clocks = <&gcc GCC_BLSP2_AHB_CLK>; | |
1058 | clock-names = "bam_clk"; | |
1059 | #dma-cells = <1>; | |
bf9aa8a4 BA |
1060 | qcom,ee = <0>; |
1061 | status = "disabled"; | |
1062 | }; | |
1063 | ||
1064 | blsp2_uart0: serial@7aef000 { | |
1065 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
1066 | reg = <0x07aef000 0x200>; | |
1067 | interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; | |
1068 | clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; | |
1069 | clock-names = "core", "iface"; | |
0e1b27f4 KK |
1070 | dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; |
1071 | dma-names = "tx", "rx"; | |
bf9aa8a4 BA |
1072 | pinctrl-names = "default"; |
1073 | pinctrl-0 = <&blsp2_uart0_default>; | |
1074 | status = "disabled"; | |
1075 | }; | |
1076 | ||
734e6d02 BA |
1077 | blsp2_i2c0: i2c@7af5000 { |
1078 | compatible = "qcom,i2c-qup-v2.2.1"; | |
1079 | reg = <0x07af5000 0x600>; | |
1080 | interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
1081 | clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, |
1082 | <&gcc GCC_BLSP2_AHB_CLK>; | |
1083 | clock-names = "core", "iface"; | |
734e6d02 BA |
1084 | pinctrl-names = "default"; |
1085 | pinctrl-0 = <&blsp2_i2c0_default>; | |
1086 | #address-cells = <1>; | |
1087 | #size-cells = <0>; | |
1088 | status = "disabled"; | |
1089 | }; | |
1090 | ||
1091 | blsp2_spi0: spi@7af5000 { | |
1092 | compatible = "qcom,spi-qup-v2.2.1"; | |
1093 | reg = <0x07af5000 0x600>; | |
1094 | interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
1095 | clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, |
1096 | <&gcc GCC_BLSP2_AHB_CLK>; | |
1097 | clock-names = "core", "iface"; | |
734e6d02 BA |
1098 | pinctrl-names = "default"; |
1099 | pinctrl-0 = <&blsp2_spi0_default>; | |
1100 | #address-cells = <1>; | |
1101 | #size-cells = <0>; | |
1102 | status = "disabled"; | |
1103 | }; | |
1104 | ||
809cc579 BA |
1105 | imem@8600000 { |
1106 | compatible = "simple-mfd"; | |
1107 | reg = <0x08600000 0x1000>; | |
1108 | ||
1109 | #address-cells = <1>; | |
1110 | #size-cells = <1>; | |
1111 | ||
1112 | ranges = <0 0x08600000 0x1000>; | |
1113 | ||
1114 | pil-reloc@94c { | |
1115 | compatible = "qcom,pil-reloc-info"; | |
1116 | reg = <0x94c 0xc8>; | |
1117 | }; | |
1118 | }; | |
1119 | ||
b4d82f4d VK |
1120 | intc: interrupt-controller@b000000 { |
1121 | compatible = "qcom,msm-qgic2"; | |
1122 | interrupt-controller; | |
1123 | #interrupt-cells = <3>; | |
1124 | reg = <0x0b000000 0x1000>, | |
1125 | <0x0b002000 0x1000>; | |
1126 | }; | |
1127 | ||
7fc7089d BA |
1128 | apcs_glb: mailbox@b011000 { |
1129 | compatible = "qcom,qcs404-apcs-apps-global", "syscon"; | |
1130 | reg = <0x0b011000 0x1000>; | |
1131 | #mbox-cells = <1>; | |
01163a20 JRO |
1132 | clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; |
1133 | clock-names = "pll", "aux"; | |
1134 | #clock-cells = <0>; | |
7fc7089d BA |
1135 | }; |
1136 | ||
40b3d940 JRO |
1137 | apcs_hfpll: clock-controller@b016000 { |
1138 | compatible = "qcom,hfpll"; | |
1139 | reg = <0x0b016000 0x30>; | |
1140 | #clock-cells = <0>; | |
1141 | clock-output-names = "apcs_hfpll"; | |
1142 | clocks = <&xo_board>; | |
1143 | clock-names = "xo"; | |
1144 | }; | |
1145 | ||
8a250aa6 | 1146 | watchdog@b017000 { |
9692d9ff | 1147 | compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; |
8a250aa6 JRO |
1148 | reg = <0x0b017000 0x1000>; |
1149 | clocks = <&sleep_clk>; | |
1150 | }; | |
1151 | ||
04aadcaa NC |
1152 | cpr: power-controller@b018000 { |
1153 | compatible = "qcom,qcs404-cpr", "qcom,cpr"; | |
1154 | reg = <0x0b018000 0x1000>; | |
1155 | interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; | |
1156 | clocks = <&xo_board>; | |
1157 | clock-names = "ref"; | |
1158 | vdd-apc-supply = <&pms405_s3>; | |
1159 | #power-domain-cells = <0>; | |
1160 | operating-points-v2 = <&cpr_opp_table>; | |
1161 | acc-syscon = <&tcsr>; | |
1162 | ||
1163 | nvmem-cells = <&cpr_efuse_quot_offset1>, | |
1164 | <&cpr_efuse_quot_offset2>, | |
1165 | <&cpr_efuse_quot_offset3>, | |
1166 | <&cpr_efuse_init_voltage1>, | |
1167 | <&cpr_efuse_init_voltage2>, | |
1168 | <&cpr_efuse_init_voltage3>, | |
1169 | <&cpr_efuse_quot1>, | |
1170 | <&cpr_efuse_quot2>, | |
1171 | <&cpr_efuse_quot3>, | |
1172 | <&cpr_efuse_ring1>, | |
1173 | <&cpr_efuse_ring2>, | |
1174 | <&cpr_efuse_ring3>, | |
1175 | <&cpr_efuse_revision>; | |
1176 | nvmem-cell-names = "cpr_quotient_offset1", | |
1177 | "cpr_quotient_offset2", | |
1178 | "cpr_quotient_offset3", | |
1179 | "cpr_init_voltage1", | |
1180 | "cpr_init_voltage2", | |
1181 | "cpr_init_voltage3", | |
1182 | "cpr_quotient1", | |
1183 | "cpr_quotient2", | |
1184 | "cpr_quotient3", | |
1185 | "cpr_ring_osc1", | |
1186 | "cpr_ring_osc2", | |
1187 | "cpr_ring_osc3", | |
1188 | "cpr_fuse_revision"; | |
1189 | }; | |
1190 | ||
b4d82f4d VK |
1191 | timer@b120000 { |
1192 | #address-cells = <1>; | |
1193 | #size-cells = <1>; | |
1194 | ranges; | |
1195 | compatible = "arm,armv7-timer-mem"; | |
1196 | reg = <0x0b120000 0x1000>; | |
1197 | clock-frequency = <19200000>; | |
1198 | ||
1199 | frame@b121000 { | |
1200 | frame-number = <0>; | |
1201 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
1202 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
1203 | reg = <0x0b121000 0x1000>, | |
1204 | <0x0b122000 0x1000>; | |
1205 | }; | |
1206 | ||
1207 | frame@b123000 { | |
1208 | frame-number = <1>; | |
1209 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
1210 | reg = <0x0b123000 0x1000>; | |
1211 | status = "disabled"; | |
1212 | }; | |
1213 | ||
1214 | frame@b124000 { | |
1215 | frame-number = <2>; | |
1216 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
1217 | reg = <0x0b124000 0x1000>; | |
1218 | status = "disabled"; | |
1219 | }; | |
1220 | ||
1221 | frame@b125000 { | |
1222 | frame-number = <3>; | |
1223 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
1224 | reg = <0x0b125000 0x1000>; | |
1225 | status = "disabled"; | |
1226 | }; | |
1227 | ||
1228 | frame@b126000 { | |
1229 | frame-number = <4>; | |
1230 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
1231 | reg = <0x0b126000 0x1000>; | |
1232 | status = "disabled"; | |
1233 | }; | |
1234 | ||
1235 | frame@b127000 { | |
1236 | frame-number = <5>; | |
1237 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
1238 | reg = <0xb127000 0x1000>; | |
1239 | status = "disabled"; | |
1240 | }; | |
1241 | ||
1242 | frame@b128000 { | |
1243 | frame-number = <6>; | |
1244 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
1245 | reg = <0x0b128000 0x1000>; | |
1246 | status = "disabled"; | |
1247 | }; | |
1248 | }; | |
67779ca2 BA |
1249 | |
1250 | remoteproc_adsp: remoteproc@c700000 { | |
1251 | compatible = "qcom,qcs404-adsp-pas"; | |
1252 | reg = <0x0c700000 0x4040>; | |
1253 | ||
1254 | interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, | |
1255 | <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
1256 | <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, | |
1257 | <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, | |
1258 | <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; | |
1259 | interrupt-names = "wdog", "fatal", "ready", | |
1260 | "handover", "stop-ack"; | |
1261 | ||
1262 | clocks = <&xo_board>; | |
1263 | clock-names = "xo"; | |
1264 | ||
1265 | memory-region = <&adsp_fw_mem>; | |
1266 | ||
1267 | qcom,smem-states = <&adsp_smp2p_out 0>; | |
1268 | qcom,smem-state-names = "stop"; | |
1269 | ||
1270 | status = "disabled"; | |
1271 | ||
1272 | glink-edge { | |
1273 | interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; | |
1274 | ||
1275 | qcom,remote-pid = <2>; | |
1276 | mboxes = <&apcs_glb 8>; | |
1277 | ||
1278 | label = "adsp"; | |
1279 | }; | |
1280 | }; | |
431f6464 BA |
1281 | |
1282 | pcie: pci@10000000 { | |
1283 | compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; | |
1284 | reg = <0x10000000 0xf1d>, | |
1285 | <0x10000f20 0xa8>, | |
1286 | <0x07780000 0x2000>, | |
1287 | <0x10001000 0x2000>; | |
1288 | reg-names = "dbi", "elbi", "parf", "config"; | |
1289 | device_type = "pci"; | |
1290 | linux,pci-domain = <0>; | |
1291 | bus-range = <0x00 0xff>; | |
1292 | num-lanes = <1>; | |
1293 | #address-cells = <3>; | |
1294 | #size-cells = <2>; | |
1295 | ||
1296 | ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ | |
1297 | <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ | |
1298 | ||
1299 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; | |
1300 | interrupt-names = "msi"; | |
1301 | #interrupt-cells = <1>; | |
1302 | interrupt-map-mask = <0 0 0 0x7>; | |
1303 | interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
1304 | <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
1305 | <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
1306 | <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
1307 | clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, | |
1308 | <&gcc GCC_PCIE_0_AUX_CLK>, | |
1309 | <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, | |
1310 | <&gcc GCC_PCIE_0_SLV_AXI_CLK>; | |
1311 | clock-names = "iface", "aux", "master_bus", "slave_bus"; | |
1312 | ||
1313 | resets = <&gcc 18>, | |
1314 | <&gcc 17>, | |
1315 | <&gcc 15>, | |
1316 | <&gcc 19>, | |
1317 | <&gcc GCC_PCIE_0_BCR>, | |
1318 | <&gcc 16>; | |
1319 | reset-names = "axi_m", | |
1320 | "axi_s", | |
1321 | "axi_m_sticky", | |
1322 | "pipe_sticky", | |
1323 | "pwr", | |
1324 | "ahb"; | |
1325 | ||
1326 | phys = <&pcie_phy>; | |
1327 | phy-names = "pciephy"; | |
1328 | ||
1329 | status = "disabled"; | |
1330 | }; | |
b4d82f4d VK |
1331 | }; |
1332 | ||
1333 | timer { | |
1334 | compatible = "arm,armv8-timer"; | |
1335 | interrupts = <GIC_PPI 2 0xff08>, | |
1336 | <GIC_PPI 3 0xff08>, | |
1337 | <GIC_PPI 4 0xff08>, | |
1338 | <GIC_PPI 1 0xff08>; | |
1339 | }; | |
afdfb0b3 VK |
1340 | |
1341 | smp2p-adsp { | |
1342 | compatible = "qcom,smp2p"; | |
1343 | qcom,smem = <443>, <429>; | |
1344 | interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; | |
1345 | mboxes = <&apcs_glb 10>; | |
1346 | qcom,local-pid = <0>; | |
1347 | qcom,remote-pid = <2>; | |
1348 | ||
1349 | adsp_smp2p_out: master-kernel { | |
1350 | qcom,entry-name = "master-kernel"; | |
1351 | #qcom,smem-state-cells = <1>; | |
1352 | }; | |
1353 | ||
1354 | adsp_smp2p_in: slave-kernel { | |
1355 | qcom,entry-name = "slave-kernel"; | |
1356 | interrupt-controller; | |
1357 | #interrupt-cells = <2>; | |
1358 | }; | |
1359 | }; | |
1360 | ||
1361 | smp2p-cdsp { | |
1362 | compatible = "qcom,smp2p"; | |
1363 | qcom,smem = <94>, <432>; | |
1364 | interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; | |
1365 | mboxes = <&apcs_glb 14>; | |
1366 | qcom,local-pid = <0>; | |
1367 | qcom,remote-pid = <5>; | |
1368 | ||
1369 | cdsp_smp2p_out: master-kernel { | |
1370 | qcom,entry-name = "master-kernel"; | |
1371 | #qcom,smem-state-cells = <1>; | |
1372 | }; | |
1373 | ||
1374 | cdsp_smp2p_in: slave-kernel { | |
1375 | qcom,entry-name = "slave-kernel"; | |
1376 | interrupt-controller; | |
1377 | #interrupt-cells = <2>; | |
1378 | }; | |
1379 | }; | |
1380 | ||
1381 | smp2p-wcss { | |
1382 | compatible = "qcom,smp2p"; | |
1383 | qcom,smem = <435>, <428>; | |
1384 | interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; | |
1385 | mboxes = <&apcs_glb 18>; | |
1386 | qcom,local-pid = <0>; | |
1387 | qcom,remote-pid = <1>; | |
1388 | ||
1389 | wcss_smp2p_out: master-kernel { | |
1390 | qcom,entry-name = "master-kernel"; | |
1391 | #qcom,smem-state-cells = <1>; | |
1392 | }; | |
1393 | ||
1394 | wcss_smp2p_in: slave-kernel { | |
1395 | qcom,entry-name = "slave-kernel"; | |
1396 | interrupt-controller; | |
1397 | #interrupt-cells = <2>; | |
1398 | }; | |
1399 | }; | |
f48cee32 AK |
1400 | |
1401 | thermal-zones { | |
1402 | aoss-thermal { | |
1403 | polling-delay-passive = <250>; | |
1404 | polling-delay = <1000>; | |
1405 | ||
1406 | thermal-sensors = <&tsens 0>; | |
1407 | ||
1408 | trips { | |
e8c48eb0 | 1409 | aoss_alert0: trip-point0 { |
f48cee32 AK |
1410 | temperature = <105000>; |
1411 | hysteresis = <2000>; | |
1412 | type = "hot"; | |
1413 | }; | |
1414 | }; | |
1415 | }; | |
1416 | ||
1417 | q6-hvx-thermal { | |
1418 | polling-delay-passive = <250>; | |
1419 | polling-delay = <1000>; | |
1420 | ||
1421 | thermal-sensors = <&tsens 1>; | |
1422 | ||
1423 | trips { | |
e8c48eb0 | 1424 | q6_hvx_alert0: trip-point0 { |
f48cee32 AK |
1425 | temperature = <105000>; |
1426 | hysteresis = <2000>; | |
1427 | type = "hot"; | |
1428 | }; | |
1429 | }; | |
1430 | }; | |
1431 | ||
1432 | lpass-thermal { | |
1433 | polling-delay-passive = <250>; | |
1434 | polling-delay = <1000>; | |
1435 | ||
1436 | thermal-sensors = <&tsens 2>; | |
1437 | ||
1438 | trips { | |
e8c48eb0 | 1439 | lpass_alert0: trip-point0 { |
f48cee32 AK |
1440 | temperature = <105000>; |
1441 | hysteresis = <2000>; | |
1442 | type = "hot"; | |
1443 | }; | |
1444 | }; | |
1445 | }; | |
1446 | ||
1447 | wlan-thermal { | |
1448 | polling-delay-passive = <250>; | |
1449 | polling-delay = <1000>; | |
1450 | ||
1451 | thermal-sensors = <&tsens 3>; | |
1452 | ||
1453 | trips { | |
e8c48eb0 | 1454 | wlan_alert0: trip-point0 { |
f48cee32 AK |
1455 | temperature = <105000>; |
1456 | hysteresis = <2000>; | |
1457 | type = "hot"; | |
1458 | }; | |
1459 | }; | |
1460 | }; | |
1461 | ||
1462 | cluster-thermal { | |
1463 | polling-delay-passive = <250>; | |
1464 | polling-delay = <1000>; | |
1465 | ||
1466 | thermal-sensors = <&tsens 4>; | |
1467 | ||
1468 | trips { | |
e8c48eb0 | 1469 | cluster_alert0: trip-point0 { |
f48cee32 AK |
1470 | temperature = <95000>; |
1471 | hysteresis = <2000>; | |
1472 | type = "hot"; | |
1473 | }; | |
e8c48eb0 | 1474 | cluster_alert1: trip-point1 { |
f48cee32 AK |
1475 | temperature = <105000>; |
1476 | hysteresis = <2000>; | |
1477 | type = "passive"; | |
1478 | }; | |
1479 | cluster_crit: cluster_crit { | |
1480 | temperature = <120000>; | |
1481 | hysteresis = <2000>; | |
1482 | type = "critical"; | |
1483 | }; | |
1484 | }; | |
1485 | cooling-maps { | |
1486 | map0 { | |
1487 | trip = <&cluster_alert1>; | |
1488 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1489 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1490 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1491 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1492 | }; | |
1493 | }; | |
1494 | }; | |
1495 | ||
1496 | cpu0-thermal { | |
1497 | polling-delay-passive = <250>; | |
1498 | polling-delay = <1000>; | |
1499 | ||
1500 | thermal-sensors = <&tsens 5>; | |
1501 | ||
1502 | trips { | |
e8c48eb0 | 1503 | cpu0_alert0: trip-point0 { |
f48cee32 AK |
1504 | temperature = <95000>; |
1505 | hysteresis = <2000>; | |
1506 | type = "hot"; | |
1507 | }; | |
e8c48eb0 | 1508 | cpu0_alert1: trip-point1 { |
f48cee32 AK |
1509 | temperature = <105000>; |
1510 | hysteresis = <2000>; | |
1511 | type = "passive"; | |
1512 | }; | |
1513 | cpu0_crit: cpu_crit { | |
1514 | temperature = <120000>; | |
1515 | hysteresis = <2000>; | |
1516 | type = "critical"; | |
1517 | }; | |
1518 | }; | |
1519 | cooling-maps { | |
1520 | map0 { | |
1521 | trip = <&cpu0_alert1>; | |
1522 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1523 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1524 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1525 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1526 | }; | |
1527 | }; | |
1528 | }; | |
1529 | ||
1530 | cpu1-thermal { | |
1531 | polling-delay-passive = <250>; | |
1532 | polling-delay = <1000>; | |
1533 | ||
1534 | thermal-sensors = <&tsens 6>; | |
1535 | ||
1536 | trips { | |
e8c48eb0 | 1537 | cpu1_alert0: trip-point0 { |
f48cee32 AK |
1538 | temperature = <95000>; |
1539 | hysteresis = <2000>; | |
1540 | type = "hot"; | |
1541 | }; | |
e8c48eb0 | 1542 | cpu1_alert1: trip-point1 { |
f48cee32 AK |
1543 | temperature = <105000>; |
1544 | hysteresis = <2000>; | |
1545 | type = "passive"; | |
1546 | }; | |
1547 | cpu1_crit: cpu_crit { | |
1548 | temperature = <120000>; | |
1549 | hysteresis = <2000>; | |
1550 | type = "critical"; | |
1551 | }; | |
1552 | }; | |
1553 | cooling-maps { | |
1554 | map0 { | |
1555 | trip = <&cpu1_alert1>; | |
1556 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1557 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1558 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1559 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1560 | }; | |
1561 | }; | |
1562 | }; | |
1563 | ||
1564 | cpu2-thermal { | |
1565 | polling-delay-passive = <250>; | |
1566 | polling-delay = <1000>; | |
1567 | ||
1568 | thermal-sensors = <&tsens 7>; | |
1569 | ||
1570 | trips { | |
e8c48eb0 | 1571 | cpu2_alert0: trip-point0 { |
f48cee32 AK |
1572 | temperature = <95000>; |
1573 | hysteresis = <2000>; | |
1574 | type = "hot"; | |
1575 | }; | |
e8c48eb0 | 1576 | cpu2_alert1: trip-point1 { |
f48cee32 AK |
1577 | temperature = <105000>; |
1578 | hysteresis = <2000>; | |
1579 | type = "passive"; | |
1580 | }; | |
1581 | cpu2_crit: cpu_crit { | |
1582 | temperature = <120000>; | |
1583 | hysteresis = <2000>; | |
1584 | type = "critical"; | |
1585 | }; | |
1586 | }; | |
1587 | cooling-maps { | |
1588 | map0 { | |
1589 | trip = <&cpu2_alert1>; | |
1590 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1591 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1592 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1593 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1594 | }; | |
1595 | }; | |
1596 | }; | |
1597 | ||
1598 | cpu3-thermal { | |
1599 | polling-delay-passive = <250>; | |
1600 | polling-delay = <1000>; | |
1601 | ||
1602 | thermal-sensors = <&tsens 8>; | |
1603 | ||
1604 | trips { | |
e8c48eb0 | 1605 | cpu3_alert0: trip-point0 { |
f48cee32 AK |
1606 | temperature = <95000>; |
1607 | hysteresis = <2000>; | |
1608 | type = "hot"; | |
1609 | }; | |
e8c48eb0 | 1610 | cpu3_alert1: trip-point1 { |
f48cee32 AK |
1611 | temperature = <105000>; |
1612 | hysteresis = <2000>; | |
1613 | type = "passive"; | |
1614 | }; | |
1615 | cpu3_crit: cpu_crit { | |
1616 | temperature = <120000>; | |
1617 | hysteresis = <2000>; | |
1618 | type = "critical"; | |
1619 | }; | |
1620 | }; | |
1621 | cooling-maps { | |
1622 | map0 { | |
1623 | trip = <&cpu3_alert1>; | |
1624 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1625 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1626 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1627 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1628 | }; | |
1629 | }; | |
1630 | }; | |
1631 | ||
1632 | gpu-thermal { | |
1633 | polling-delay-passive = <250>; | |
1634 | polling-delay = <1000>; | |
1635 | ||
1636 | thermal-sensors = <&tsens 9>; | |
1637 | ||
1638 | trips { | |
e8c48eb0 | 1639 | gpu_alert0: trip-point0 { |
f48cee32 AK |
1640 | temperature = <95000>; |
1641 | hysteresis = <2000>; | |
1642 | type = "hot"; | |
1643 | }; | |
1644 | }; | |
1645 | }; | |
1646 | }; | |
b4d82f4d | 1647 | }; |