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Merge tag 'csky-for-linus-4.20-fixup-dtb' of https://github.com/c-sky/csky-linux
[linux-block.git] / arch / arm64 / boot / dts / qcom / msm8996.dtsi
CommitLineData
4558e9b3
SB		 1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/qcom,gcc-msm8996.h>
15#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
00f8497f 16#include <dt-bindings/clock/qcom,rpmcc.h>
4558e9b3
SB		 17
18/ {
4558e9b3
SB		 19 interrupt-parent = <&intc>;
20
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 chosen { };
25
26 memory {
27 device_type = "memory";
28 /* We expect the bootloader to fill in the reg */
29 reg = <0 0 0 0>;
30 };
31
ee17692c 32 reserved-memory {
33 #address-cells = <2>;
34 #size-cells = <2>;
35 ranges;
36
13eb40eb 37 mba_region: mba@91500000 {
38 reg = <0x0 0x91500000 0x0 0x200000>;
39 no-map;
40 };
41
42 slpi_region: slpi@90b00000 {
43 reg = <0x0 0x90b00000 0x0 0xa00000>;
44 no-map;
45 };
46
47 venus_region: venus@90400000 {
48 reg = <0x0 0x90400000 0x0 0x700000>;
49 no-map;
50 };
51
52 adsp_region: adsp@8ea00000 {
53 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
54 no-map;
55 };
56
57 mpss_region: mpss@88800000 {
58 reg = <0x0 0x88800000 0x0 0x6200000>;
59 no-map;
60 };
61
ee17692c 62 smem_mem: smem-mem@86000000 {
63 reg = <0x0 0x86000000 0x0 0x200000>;
64 no-map;
65 };
e9112936
SB		 66
67 memory@85800000 {
68 reg = <0x0 0x85800000 0x0 0x800000>;
69 no-map;
70 };
71
72 memory@86200000 {
73 reg = <0x0 0x86200000 0x0 0x2600000>;
74 no-map;
75 };
68ae3d0c
BA		 76
77 rmtfs@86700000 {
78 compatible = "qcom,rmtfs-mem";
79
80 size = <0x0 0x200000>;
81 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
82 no-map;
83
84 qcom,client-id = <1>;
85 qcom,vmid = <15>;
86 };
ee17692c 87 };
88
4558e9b3
SB		 89 cpus {
90 #address-cells = <2>;
91 #size-cells = <0>;
92
93 CPU0: cpu@0 {
94 device_type = "cpu";
95 compatible = "qcom,kryo";
96 reg = <0x0 0x0>;
97 enable-method = "psci";
98 next-level-cache = <&L2_0>;
99 L2_0: l2-cache {
100 compatible = "cache";
101 cache-level = <2>;
102 };
103 };
104
105 CPU1: cpu@1 {
106 device_type = "cpu";
107 compatible = "qcom,kryo";
108 reg = <0x0 0x1>;
109 enable-method = "psci";
110 next-level-cache = <&L2_0>;
111 };
112
113 CPU2: cpu@100 {
114 device_type = "cpu";
115 compatible = "qcom,kryo";
116 reg = <0x0 0x100>;
117 enable-method = "psci";
118 next-level-cache = <&L2_1>;
119 L2_1: l2-cache {
120 compatible = "cache";
121 cache-level = <2>;
122 };
123 };
124
125 CPU3: cpu@101 {
126 device_type = "cpu";
127 compatible = "qcom,kryo";
128 reg = <0x0 0x101>;
129 enable-method = "psci";
130 next-level-cache = <&L2_1>;
131 };
132
133 cpu-map {
134 cluster0 {
135 core0 {
136 cpu = <&CPU0>;
137 };
138
139 core1 {
140 cpu = <&CPU1>;
141 };
142 };
143
144 cluster1 {
145 core0 {
146 cpu = <&CPU2>;
147 };
148
149 core1 {
150 cpu = <&CPU3>;
151 };
152 };
153 };
154 };
155
7422ee8e
RN		 156 thermal-zones {
157 cpu-thermal0 {
158 polling-delay-passive = <250>;
159 polling-delay = <1000>;
160
161 thermal-sensors = <&tsens0 3>;
162
163 trips {
164 cpu_alert0: trip0 {
165 temperature = <75000>;
166 hysteresis = <2000>;
167 type = "passive";
168 };
169
170 cpu_crit0: trip1 {
171 temperature = <110000>;
172 hysteresis = <2000>;
173 type = "critical";
174 };
175 };
176 };
177
178 cpu-thermal1 {
179 polling-delay-passive = <250>;
180 polling-delay = <1000>;
181
182 thermal-sensors = <&tsens0 5>;
183
184 trips {
185 cpu_alert1: trip0 {
186 temperature = <75000>;
187 hysteresis = <2000>;
188 type = "passive";
189 };
190
191 cpu_crit1: trip1 {
192 temperature = <110000>;
193 hysteresis = <2000>;
194 type = "critical";
195 };
196 };
197 };
198
199 cpu-thermal2 {
200 polling-delay-passive = <250>;
201 polling-delay = <1000>;
202
203 thermal-sensors = <&tsens0 8>;
204
205 trips {
206 cpu_alert2: trip0 {
207 temperature = <75000>;
208 hysteresis = <2000>;
209 type = "passive";
210 };
211
212 cpu_crit2: trip1 {
213 temperature = <110000>;
214 hysteresis = <2000>;
215 type = "critical";
216 };
217 };
218 };
219
220 cpu-thermal3 {
221 polling-delay-passive = <250>;
222 polling-delay = <1000>;
223
224 thermal-sensors = <&tsens0 10>;
225
226 trips {
227 cpu_alert3: trip0 {
228 temperature = <75000>;
229 hysteresis = <2000>;
230 type = "passive";
231 };
232
233 cpu_crit3: trip1 {
234 temperature = <110000>;
235 hysteresis = <2000>;
236 type = "critical";
237 };
238 };
239 };
240 };
241
4558e9b3
SB		 242 timer {
243 compatible = "arm,armv8-timer";
4a92b6d7
RN		 244 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
245 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
4558e9b3
SB		 248 };
249
250 clocks {
dfce0738 251 xo_board: xo_board {
4558e9b3
SB		 252 compatible = "fixed-clock";
253 #clock-cells = <0>;
254 clock-frequency = <19200000>;
255 clock-output-names = "xo_board";
256 };
257
dfce0738 258 sleep_clk: sleep_clk {
4558e9b3
SB		 259 compatible = "fixed-clock";
260 #clock-cells = <0>;
261 clock-frequency = <32764>;
262 clock-output-names = "sleep_clk";
263 };
264 };
265
266 psci {
267 compatible = "arm,psci-1.0";
268 method = "smc";
269 };
270
702956a1 271 firmware {
272 scm {
273 compatible = "qcom,scm-msm8996";
1f34d644
BA		 274
275 qcom,dload-mode = <&tcsr 0x13000>;
702956a1 276 };
277 };
278
da3d658e
BA		 279 tcsr_mutex: hwlock {
280 compatible = "qcom,tcsr-mutex";
281 syscon = <&tcsr_mutex_regs 0 0x1000>;
282 #hwlock-cells = <1>;
283 };
284
285 smem {
286 compatible = "qcom,smem";
287 memory-region = <&smem_mem>;
288 hwlocks = <&tcsr_mutex 3>;
289 };
290
f742f878
BA		 291 rpm-glink {
292 compatible = "qcom,glink-rpm";
293
294 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
295
296 qcom,rpm-msg-ram = <&rpm_msg_ram>;
297
298 mboxes = <&apcs_glb 0>;
299
300 rpm_requests {
301 compatible = "qcom,rpm-msm8996";
302 qcom,glink-channels = "rpm_requests";
303
00f8497f
RN		 304 rpmcc: qcom,rpmcc {
305 compatible = "qcom,rpmcc-msm8996";
306 #clock-cells = <1>;
307 };
308
f742f878
BA		 309 pm8994-regulators {
310 compatible = "qcom,rpm-pm8994-regulators";
311
312 pm8994_s1: s1 {};
313 pm8994_s2: s2 {};
314 pm8994_s3: s3 {};
315 pm8994_s4: s4 {};
316 pm8994_s5: s5 {};
317 pm8994_s6: s6 {};
318 pm8994_s7: s7 {};
319 pm8994_s8: s8 {};
320 pm8994_s9: s9 {};
321 pm8994_s10: s10 {};
322 pm8994_s11: s11 {};
323 pm8994_s12: s12 {};
324
325 pm8994_l1: l1 {};
326 pm8994_l2: l2 {};
327 pm8994_l3: l3 {};
328 pm8994_l4: l4 {};
329 pm8994_l5: l5 {};
330 pm8994_l6: l6 {};
331 pm8994_l7: l7 {};
332 pm8994_l8: l8 {};
333 pm8994_l9: l9 {};
334 pm8994_l10: l10 {};
335 pm8994_l11: l11 {};
336 pm8994_l12: l12 {};
337 pm8994_l13: l13 {};
338 pm8994_l14: l14 {};
339 pm8994_l15: l15 {};
340 pm8994_l16: l16 {};
341 pm8994_l17: l17 {};
342 pm8994_l18: l18 {};
343 pm8994_l19: l19 {};
344 pm8994_l20: l20 {};
345 pm8994_l21: l21 {};
346 pm8994_l22: l22 {};
347 pm8994_l23: l23 {};
348 pm8994_l24: l24 {};
349 pm8994_l25: l25 {};
350 pm8994_l26: l26 {};
351 pm8994_l27: l27 {};
352 pm8994_l28: l28 {};
353 pm8994_l29: l29 {};
354 pm8994_l30: l30 {};
355 pm8994_l31: l31 {};
356 pm8994_l32: l32 {};
357 };
358
359 };
360 };
361
4558e9b3
SB		 362 soc: soc {
363 #address-cells = <1>;
364 #size-cells = <1>;
365 ranges = <0 0 0 0xffffffff>;
366 compatible = "simple-bus";
367
f742f878
BA		 368 rpm_msg_ram: memory@68000 {
369 compatible = "qcom,rpm-msg-ram";
370 reg = <0x68000 0x6000>;
371 };
372
da3d658e
BA		 373 tcsr_mutex_regs: syscon@740000 {
374 compatible = "syscon";
375 reg = <0x740000 0x20000>;
376 };
377
f35c11b0
AK		 378 tsens0: thermal-sensor@4a9000 {
379 compatible = "qcom,msm8996-tsens";
380 reg = <0x4a9000 0x1000>, /* TM */
381 <0x4a8000 0x1000>; /* SROT */
382 #qcom,sensors = <13>;
383 #thermal-sensor-cells = <1>;
384 };
385
386 tsens1: thermal-sensor@4ad000 {
387 compatible = "qcom,msm8996-tsens";
388 reg = <0x4ad000 0x1000>, /* TM */
389 <0x4ac000 0x1000>; /* SROT */
390 #qcom,sensors = <8>;
391 #thermal-sensor-cells = <1>;
392 };
393
1f34d644
BA		 394 tcsr: syscon@7a0000 {
395 compatible = "qcom,tcsr-msm8996", "syscon";
396 reg = <0x7a0000 0x18000>;
397 };
398
4558e9b3
SB		 399 intc: interrupt-controller@9bc0000 {
400 compatible = "arm,gic-v3";
401 #interrupt-cells = <3>;
402 interrupt-controller;
403 #redistributor-regions = <1>;
404 redistributor-stride = <0x0 0x40000>;
405 reg = <0x09bc0000 0x10000>,
406 <0x09c00000 0x100000>;
407 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
408 };
409
f742f878
BA		 410 apcs_glb: mailbox@9820000 {
411 compatible = "qcom,msm8996-apcs-hmss-global";
412 reg = <0x9820000 0x1000>;
413
414 #mbox-cells = <1>;
415 };
416
4558e9b3
SB		 417 gcc: clock-controller@300000 {
418 compatible = "qcom,gcc-msm8996";
419 #clock-cells = <1>;
420 #reset-cells = <1>;
a70d7449 421 #power-domain-cells = <1>;
4558e9b3
SB		 422 reg = <0x300000 0x90000>;
423 };
424
99c3334d
RN		 425 kryocc: clock-controller@6400000 {
426 compatible = "qcom,apcc-msm8996";
427 reg = <0x6400000 0x90000>;
428 #clock-cells = <1>;
429 };
430
3e4cb730
TE		 431 blsp1_uart1: serial@7570000 {
432 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
433 reg = <0x07570000 0x1000>;
434 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
436 <&gcc GCC_BLSP1_AHB_CLK>;
437 clock-names = "core", "iface";
438 status = "disabled";
439 };
440
d8bcaabe 441 blsp1_spi0: spi@7575000 {
604677b4
SK		 442 compatible = "qcom,spi-qup-v2.2.1";
443 reg = <0x07575000 0x600>;
444 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
446 <&gcc GCC_BLSP1_AHB_CLK>;
447 clock-names = "core", "iface";
448 pinctrl-names = "default", "sleep";
449 pinctrl-0 = <&blsp1_spi0_default>;
450 pinctrl-1 = <&blsp1_spi0_sleep>;
451 #address-cells = <1>;
452 #size-cells = <0>;
453 status = "disabled";
454 };
455
d8bcaabe 456 blsp2_i2c0: i2c@75b5000 {
bf5443bc
SK		 457 compatible = "qcom,i2c-qup-v2.2.1";
458 reg = <0x075b5000 0x1000>;
242579dd 459 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
bf5443bc
SK		 460 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
461 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
462 clock-names = "iface", "core";
463 pinctrl-names = "default", "sleep";
464 pinctrl-0 = <&blsp2_i2c0_default>;
465 pinctrl-1 = <&blsp2_i2c0_sleep>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
470
4558e9b3
SB		 471 blsp2_uart1: serial@75b0000 {
472 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
473 reg = <0x75b0000 0x1000>;
474 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
476 <&gcc GCC_BLSP2_AHB_CLK>;
477 clock-names = "core", "iface";
478 status = "disabled";
479 };
480
d8bcaabe 481 blsp2_i2c1: i2c@75b6000 {
d41d0cee
SK		 482 compatible = "qcom,i2c-qup-v2.2.1";
483 reg = <0x075b6000 0x1000>;
242579dd 484 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
d41d0cee
SK		 485 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
486 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
487 clock-names = "iface", "core";
488 pinctrl-names = "default", "sleep";
489 pinctrl-0 = <&blsp2_i2c1_default>;
490 pinctrl-1 = <&blsp2_i2c1_sleep>;
491 #address-cells = <1>;
492 #size-cells = <0>;
493 status = "disabled";
494 };
495
fda48e61
SK		 496 blsp2_uart2: serial@75b1000 {
497 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
498 reg = <0x075b1000 0x1000>;
499 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
501 <&gcc GCC_BLSP2_AHB_CLK>;
502 clock-names = "core", "iface";
503 status = "disabled";
504 };
505
d8bcaabe 506 blsp1_i2c2: i2c@7577000 {
21a40384
SK		 507 compatible = "qcom,i2c-qup-v2.2.1";
508 reg = <0x07577000 0x1000>;
242579dd 509 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
21a40384
SK		 510 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
511 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
512 clock-names = "iface", "core";
513 pinctrl-names = "default", "sleep";
514 pinctrl-0 = <&blsp1_i2c2_default>;
515 pinctrl-1 = <&blsp1_i2c2_sleep>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 status = "disabled";
519 };
520
d8bcaabe 521 blsp2_spi5: spi@75ba000{
db6c8c83
SK		 522 compatible = "qcom,spi-qup-v2.2.1";
523 reg = <0x075ba000 0x600>;
e723795c
IL		 524 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
db6c8c83
SK		 526 <&gcc GCC_BLSP2_AHB_CLK>;
527 clock-names = "core", "iface";
528 pinctrl-names = "default", "sleep";
529 pinctrl-0 = <&blsp2_spi5_default>;
530 pinctrl-1 = <&blsp2_spi5_sleep>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 status = "disabled";
534 };
535
a6702798
SK		 536 sdhc2: sdhci@74a4900 {
537 status = "disabled";
538 compatible = "qcom,sdhci-msm-v4";
539 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
540 reg-names = "hc_mem", "core_mem";
541
242579dd
TE		 542 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
543 <0 221 IRQ_TYPE_LEVEL_HIGH>;
a6702798
SK		 544 interrupt-names = "hc_irq", "pwr_irq";
545
dfce0738 546 clock-names = "iface", "core", "xo";
a6702798 547 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
dfce0738
RH		 548 <&gcc GCC_SDCC2_APPS_CLK>,
549 <&xo_board>;
a6702798
SK		 550 bus-width = <4>;
551 };
552
84361086 553 msmgpio: pinctrl@1010000 {
4558e9b3
SB		 554 compatible = "qcom,msm8996-pinctrl";
555 reg = <0x01010000 0x300000>;
556 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
561 };
562
d8bcaabe 563 timer@9840000 {
4558e9b3
SB		 564 #address-cells = <1>;
565 #size-cells = <1>;
566 ranges;
567 compatible = "arm,armv7-timer-mem";
568 reg = <0x09840000 0x1000>;
569 clock-frequency = <19200000>;
570
571 frame@9850000 {
572 frame-number = <0>;
573 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
575 reg = <0x09850000 0x1000>,
576 <0x09860000 0x1000>;
577 };
578
579 frame@9870000 {
580 frame-number = <1>;
581 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
582 reg = <0x09870000 0x1000>;
583 status = "disabled";
584 };
585
586 frame@9880000 {
587 frame-number = <2>;
588 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
589 reg = <0x09880000 0x1000>;
590 status = "disabled";
591 };
592
593 frame@9890000 {
594 frame-number = <3>;
595 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
596 reg = <0x09890000 0x1000>;
597 status = "disabled";
598 };
599
600 frame@98a0000 {
601 frame-number = <4>;
602 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
603 reg = <0x098a0000 0x1000>;
604 status = "disabled";
605 };
606
607 frame@98b0000 {
608 frame-number = <5>;
609 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
610 reg = <0x098b0000 0x1000>;
611 status = "disabled";
612 };
613
614 frame@98c0000 {
615 frame-number = <6>;
616 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
617 reg = <0x098c0000 0x1000>;
618 status = "disabled";
619 };
620 };
621
622 spmi_bus: qcom,spmi@400f000 {
623 compatible = "qcom,spmi-pmic-arb";
624 reg = <0x400f000 0x1000>,
625 <0x4400000 0x800000>,
626 <0x4c00000 0x800000>,
627 <0x5800000 0x200000>,
628 <0x400a000 0x002100>;
629 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
630 interrupt-names = "periph_irq";
0f6625fd 631 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
4558e9b3
SB		 632 qcom,ee = <0>;
633 qcom,channel = <0>;
634 #address-cells = <2>;
635 #size-cells = <0>;
636 interrupt-controller;
637 #interrupt-cells = <4>;
638 };
639
57fc67ef
BA		 640 ufsphy: phy@627000 {
641 compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
642 reg = <0x627000 0xda8>;
643 reg-names = "phy_mem";
644 #phy-cells = <0>;
645
646 vdda-phy-supply = <&pm8994_l28>;
647 vdda-pll-supply = <&pm8994_l12>;
648
649 vdda-phy-max-microamp = <18380>;
650 vdda-pll-max-microamp = <9440>;
651
652 vddp-ref-clk-supply = <&pm8994_l25>;
653 vddp-ref-clk-max-microamp = <100>;
654 vddp-ref-clk-always-on;
655
656 clock-names = "ref_clk_src", "ref_clk";
657 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
658 <&gcc GCC_UFS_CLKREF_CLK>;
659 status = "disabled";
57fc67ef
BA		 660 };
661
662 ufshc@624000 {
663 compatible = "qcom,ufshc";
664 reg = <0x624000 0x2500>;
665 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
666
667 phys = <&ufsphy>;
668 phy-names = "ufsphy";
669
670 vcc-supply = <&pm8994_l20>;
671 vccq-supply = <&pm8994_l25>;
672 vccq2-supply = <&pm8994_s4>;
673
674 vcc-max-microamp = <600000>;
675 vccq-max-microamp = <450000>;
676 vccq2-max-microamp = <450000>;
677
94dc9f48
BA		 678 power-domains = <&gcc UFS_GDSC>;
679
57fc67ef
BA		 680 clock-names =
681 "core_clk_src",
682 "core_clk",
683 "bus_clk",
684 "bus_aggr_clk",
685 "iface_clk",
686 "core_clk_unipro_src",
687 "core_clk_unipro",
688 "core_clk_ice",
689 "ref_clk",
690 "tx_lane0_sync_clk",
691 "rx_lane0_sync_clk";
692 clocks =
693 <&gcc UFS_AXI_CLK_SRC>,
694 <&gcc GCC_UFS_AXI_CLK>,
695 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
696 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
697 <&gcc GCC_UFS_AHB_CLK>,
698 <&gcc UFS_ICE_CORE_CLK_SRC>,
699 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
700 <&gcc GCC_UFS_ICE_CORE_CLK>,
701 <&rpmcc RPM_SMD_LN_BB_CLK>,
702 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
703 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
704 freq-table-hz =
705 <100000000 200000000>,
706 <0 0>,
707 <0 0>,
708 <0 0>,
709 <0 0>,
710 <150000000 300000000>,
711 <0 0>,
712 <0 0>,
713 <0 0>,
714 <0 0>,
715 <0 0>;
716
717 lanes-per-direction = <1>;
718 status = "disabled";
719
720 ufs_variant {
721 compatible = "qcom,ufs_variant";
722 };
723 };
724
4558e9b3
SB		 725 mmcc: clock-controller@8c0000 {
726 compatible = "qcom,mmcc-msm8996";
727 #clock-cells = <1>;
728 #reset-cells = <1>;
a70d7449 729 #power-domain-cells = <1>;
4558e9b3
SB		 730 reg = <0x8c0000 0x40000>;
731 assigned-clocks = <&mmcc MMPLL9_PLL>,
732 <&mmcc MMPLL1_PLL>,
733 <&mmcc MMPLL3_PLL>,
734 <&mmcc MMPLL4_PLL>,
735 <&mmcc MMPLL5_PLL>;
736 assigned-clock-rates = <624000000>,
737 <810000000>,
738 <980000000>,
739 <960000000>,
740 <825000000>;
741 };
6785fa95
VG		 742
743 qfprom@74000 {
744 compatible = "qcom,qfprom";
745 reg = <0x74000 0x8ff>;
746 #address-cells = <1>;
747 #size-cells = <1>;
748
749 qusb2p_hstx_trim: hstx_trim@24e {
750 reg = <0x24e 0x2>;
751 bits = <5 4>;
752 };
753
754 qusb2s_hstx_trim: hstx_trim@24f {
755 reg = <0x24f 0x1>;
756 bits = <1 4>;
757 };
758 };
759
12c67fe6
VG		 760 phy@34000 {
761 compatible = "qcom,msm8996-qmp-pcie-phy";
762 reg = <0x34000 0x488>;
763 #clock-cells = <1>;
764 #address-cells = <1>;
765 #size-cells = <1>;
766 ranges;
767
768 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
769 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
770 <&gcc GCC_PCIE_CLKREF_CLK>;
771 clock-names = "aux", "cfg_ahb", "ref";
772
773 vdda-phy-supply = <&pm8994_l28>;
774 vdda-pll-supply = <&pm8994_l12>;
775
776 resets = <&gcc GCC_PCIE_PHY_BCR>,
777 <&gcc GCC_PCIE_PHY_COM_BCR>,
778 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
779 reset-names = "phy", "common", "cfg";
780 status = "disabled";
781
782 pciephy_0: lane@35000 {
783 reg = <0x035000 0x130>,
784 <0x035200 0x200>,
785 <0x035400 0x1dc>;
786 #phy-cells = <0>;
787
788 clock-output-names = "pcie_0_pipe_clk_src";
789 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
790 clock-names = "pipe0";
791 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
792 reset-names = "lane0";
793 };
794
795 pciephy_1: lane@36000 {
796 reg = <0x036000 0x130>,
797 <0x036200 0x200>,
798 <0x036400 0x1dc>;
799 #phy-cells = <0>;
800
801 clock-output-names = "pcie_1_pipe_clk_src";
802 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
803 clock-names = "pipe1";
804 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
805 reset-names = "lane1";
806 };
807
808 pciephy_2: lane@37000 {
809 reg = <0x037000 0x130>,
810 <0x037200 0x200>,
811 <0x037400 0x1dc>;
812 #phy-cells = <0>;
813
814 clock-output-names = "pcie_2_pipe_clk_src";
815 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
816 clock-names = "pipe2";
817 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
818 reset-names = "lane2";
819 };
820 };
821
42bd0544
VG		 822 phy@7410000 {
823 compatible = "qcom,msm8996-qmp-usb3-phy";
824 reg = <0x7410000 0x1c4>;
825 #clock-cells = <1>;
826 #address-cells = <1>;
827 #size-cells = <1>;
828 ranges;
829
830 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
831 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
832 <&gcc GCC_USB3_CLKREF_CLK>;
833 clock-names = "aux", "cfg_ahb", "ref";
834
835 vdda-phy-supply = <&pm8994_l28>;
836 vdda-pll-supply = <&pm8994_l12>;
837
838 resets = <&gcc GCC_USB3_PHY_BCR>,
839 <&gcc GCC_USB3PHY_PHY_BCR>;
840 reset-names = "phy", "common";
841 status = "disabled";
842
843 ssusb_phy_0: lane@7410200 {
844 reg = <0x7410200 0x200>,
845 <0x7410400 0x130>,
846 <0x7410600 0x1a8>;
847 #phy-cells = <0>;
848
849 clock-output-names = "usb3_phy_pipe_clk_src";
850 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
851 clock-names = "pipe0";
852 };
853 };
854
6785fa95
VG		 855 hsusb_phy1: phy@7411000 {
856 compatible = "qcom,msm8996-qusb2-phy";
857 reg = <0x7411000 0x180>;
858 #phy-cells = <0>;
859
860 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
861 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
862 clock-names = "cfg_ahb", "ref";
863
864 vdda-pll-supply = <&pm8994_l12>;
865 vdda-phy-dpdm-supply = <&pm8994_l24>;
866
867 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
868 nvmem-cells = <&qusb2p_hstx_trim>;
869 status = "disabled";
870 };
871
872 hsusb_phy2: phy@7412000 {
873 compatible = "qcom,msm8996-qusb2-phy";
874 reg = <0x7412000 0x180>;
875 #phy-cells = <0>;
876
877 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
878 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
879 clock-names = "cfg_ahb", "ref";
880
881 vdda-pll-supply = <&pm8994_l12>;
882 vdda-phy-dpdm-supply = <&pm8994_l24>;
883
884 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
885 nvmem-cells = <&qusb2s_hstx_trim>;
886 status = "disabled";
887 };
1e39255e
VG		 888
889 usb2: usb@7600000 {
890 compatible = "qcom,dwc3";
891 #address-cells = <1>;
892 #size-cells = <1>;
893 ranges;
894
895 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
896 <&gcc GCC_USB20_MASTER_CLK>,
897 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
898 <&gcc GCC_USB20_SLEEP_CLK>,
899 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
900
901 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
902 <&gcc GCC_USB20_MASTER_CLK>;
903 assigned-clock-rates = <19200000>, <60000000>;
904
905 power-domains = <&gcc USB30_GDSC>;
906 status = "disabled";
907
908 dwc3@7600000 {
909 compatible = "snps,dwc3";
910 reg = <0x7600000 0xcc00>;
242579dd 911 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1e39255e
VG		 912 phys = <&hsusb_phy2>;
913 phy-names = "usb2-phy";
914 };
915 };
916
917 usb3: usb@6a00000 {
918 compatible = "qcom,dwc3";
919 #address-cells = <1>;
920 #size-cells = <1>;
921 ranges;
922
923 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
924 <&gcc GCC_USB30_MASTER_CLK>,
925 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
926 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
927 <&gcc GCC_USB30_SLEEP_CLK>,
928 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
929
930 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
931 <&gcc GCC_USB30_MASTER_CLK>;
932 assigned-clock-rates = <19200000>, <120000000>;
933
934 power-domains = <&gcc USB30_GDSC>;
935 status = "disabled";
936
937 dwc3@6a00000 {
938 compatible = "snps,dwc3";
939 reg = <0x6a00000 0xcc00>;
242579dd 940 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1e39255e
VG		 941 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
942 phy-names = "usb2-phy", "usb3-phy";
943 };
944 };
ed965ef8
SK		 945
946 agnoc@0 {
947 power-domains = <&gcc AGGRE0_NOC_GDSC>;
948 compatible = "simple-pm-bus";
949 #address-cells = <1>;
950 #size-cells = <1>;
951 ranges;
952
228b9cae 953 pcie0: pcie@600000 {
ed965ef8
SK		 954 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
955 status = "disabled";
956 power-domains = <&gcc PCIE0_GDSC>;
957 bus-range = <0x00 0xff>;
958 num-lanes = <1>;
959
960 reg = <0x00600000 0x2000>,
961 <0x0c000000 0xf1d>,
962 <0x0c000f20 0xa8>,
963 <0x0c100000 0x100000>;
964 reg-names = "parf", "dbi", "elbi","config";
965
966 phys = <&pciephy_0>;
967 phy-names = "pciephy";
968
969 #address-cells = <3>;
970 #size-cells = <2>;
971 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
972 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
973
242579dd 974 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
ed965ef8
SK		 975 interrupt-names = "msi";
976 #interrupt-cells = <1>;
977 interrupt-map-mask = <0 0 0 0x7>;
978 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
979 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
980 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
981 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
982
983 pinctrl-names = "default", "sleep";
984 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
985 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
986
987
988 vdda-supply = <&pm8994_l28>;
989
990 linux,pci-domain = <0>;
991
992 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
993 <&gcc GCC_PCIE_0_AUX_CLK>,
994 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
995 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
996 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
997
998 clock-names = "pipe",
999 "aux",
1000 "cfg",
1001 "bus_master",
1002 "bus_slave";
1003
1004 };
1005
228b9cae 1006 pcie1: pcie@608000 {
ed965ef8
SK		 1007 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1008 power-domains = <&gcc PCIE1_GDSC>;
1009 bus-range = <0x00 0xff>;
1010 num-lanes = <1>;
1011
1012 status = "disabled";
1013
1014 reg = <0x00608000 0x2000>,
1015 <0x0d000000 0xf1d>,
1016 <0x0d000f20 0xa8>,
1017 <0x0d100000 0x100000>;
1018
1019 reg-names = "parf", "dbi", "elbi","config";
1020
1021 phys = <&pciephy_1>;
1022 phy-names = "pciephy";
1023
1024 #address-cells = <3>;
1025 #size-cells = <2>;
1026 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1027 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1028
242579dd 1029 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
ed965ef8
SK		 1030 interrupt-names = "msi";
1031 #interrupt-cells = <1>;
1032 interrupt-map-mask = <0 0 0 0x7>;
1033 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1034 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1035 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1036 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1037
1038 pinctrl-names = "default", "sleep";
1039 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1040 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1041
1042
1043 vdda-supply = <&pm8994_l28>;
1044 linux,pci-domain = <1>;
1045
1046 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1047 <&gcc GCC_PCIE_1_AUX_CLK>,
1048 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1049 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1050 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1051
1052 clock-names = "pipe",
1053 "aux",
1054 "cfg",
1055 "bus_master",
1056 "bus_slave";
1057 };
1058
228b9cae 1059 pcie2: pcie@610000 {
ed965ef8
SK		 1060 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1061 power-domains = <&gcc PCIE2_GDSC>;
1062 bus-range = <0x00 0xff>;
1063 num-lanes = <1>;
1064 status = "disabled";
1065 reg = <0x00610000 0x2000>,
1066 <0x0e000000 0xf1d>,
1067 <0x0e000f20 0xa8>,
1068 <0x0e100000 0x100000>;
1069
1070 reg-names = "parf", "dbi", "elbi","config";
1071
1072 phys = <&pciephy_2>;
1073 phy-names = "pciephy";
1074
1075 #address-cells = <3>;
1076 #size-cells = <2>;
1077 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1078 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1079
1080 device_type = "pci";
1081
242579dd 1082 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
ed965ef8
SK		 1083 interrupt-names = "msi";
1084 #interrupt-cells = <1>;
1085 interrupt-map-mask = <0 0 0 0x7>;
1086 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1087 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1088 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1089 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1090
1091 pinctrl-names = "default", "sleep";
1092 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1093 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
1094
1095 vdda-supply = <&pm8994_l28>;
1096
1097 linux,pci-domain = <2>;
1098 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1099 <&gcc GCC_PCIE_2_AUX_CLK>,
1100 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1101 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1102 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1103
1104 clock-names = "pipe",
1105 "aux",
1106 "cfg",
1107 "bus_master",
1108 "bus_slave";
1109 };
1110 };
4558e9b3 1111 };
2f45d9fc 1112
6c8583d6 1113 adsp-pil {
1114 compatible = "qcom,msm8996-adsp-pil";
1115
1116 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
1117 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1118 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1119 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1120 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1121 interrupt-names = "wdog", "fatal", "ready",
1122 "handover", "stop-ack";
1123
1124 clocks = <&xo_board>;
1125 clock-names = "xo";
1126
1127 memory-region = <&adsp_region>;
1128
1129 qcom,smem-states = <&adsp_smp2p_out 0>;
1130 qcom,smem-state-names = "stop";
cadcd35f
BA		 1131
1132 smd-edge {
1133 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1134
1135 label = "lpass";
447c9dad 1136 mboxes = <&apcs_glb 8>;
cadcd35f
BA		 1137 qcom,smd-edge = <1>;
1138 qcom,remote-pid = <2>;
1139 };
6c8583d6 1140 };
1141
2f45d9fc 1142 adsp-smp2p {
1143 compatible = "qcom,smp2p";
1144 qcom,smem = <443>, <429>;
1145
1146 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
1147
447c9dad 1148 mboxes = <&apcs_glb 10>;
2f45d9fc 1149
1150 qcom,local-pid = <0>;
1151 qcom,remote-pid = <2>;
1152
1153 adsp_smp2p_out: master-kernel {
1154 qcom,entry-name = "master-kernel";
a2940f36 1155 #qcom,smem-state-cells = <1>;
2f45d9fc 1156 };
1157
1158 adsp_smp2p_in: slave-kernel {
1159 qcom,entry-name = "slave-kernel";
1160
1161 interrupt-controller;
1162 #interrupt-cells = <2>;
1163 };
1164 };
3f1802f8 1165
a147eda7
BA		 1166 modem-smp2p {
1167 compatible = "qcom,smp2p";
1168 qcom,smem = <435>, <428>;
1169
1170 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1171
447c9dad 1172 mboxes = <&apcs_glb 14>;
a147eda7
BA		 1173
1174 qcom,local-pid = <0>;
1175 qcom,remote-pid = <1>;
1176
1177 modem_smp2p_out: master-kernel {
1178 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cells = <1>;
1180 };
1181
1182 modem_smp2p_in: slave-kernel {
1183 qcom,entry-name = "slave-kernel";
1184
1185 interrupt-controller;
1186 #interrupt-cells = <2>;
1187 };
1188 };
1189
3f1802f8 1190 smp2p-slpi {
1191 compatible = "qcom,smp2p";
1192 qcom,smem = <481>, <430>;
1193
1194 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
1195
447c9dad 1196 mboxes = <&apcs_glb 26>;
3f1802f8 1197
1198 qcom,local-pid = <0>;
1199 qcom,remote-pid = <3>;
1200
1201 slpi_smp2p_in: slave-kernel {
1202 qcom,entry-name = "slave-kernel";
1203 interrupt-controller;
1204 #interrupt-cells = <2>;
1205 };
1206
1207 slpi_smp2p_out: master-kernel {
1208 qcom,entry-name = "master-kernel";
1209 #qcom,smem-state-cells = <1>;
1210 };
1211 };
1212
4558e9b3 1213};
22e6789f 1214#include "msm8996-pins.dtsi"
Linux 6.x block layer and io_uring tree(s)