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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
79b185d0 KD |
2 | /* |
3 | * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. | |
feeaf56a BK |
4 | */ |
5 | ||
6 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
7 | #include <dt-bindings/clock/qcom,gcc-msm8994.h> | |
e9b0eb54 KD |
8 | #include <dt-bindings/clock/qcom,mmcc-msm8994.h> |
9 | #include <dt-bindings/clock/qcom,rpmcc.h> | |
36c9d012 | 10 | #include <dt-bindings/gpio/gpio.h> |
0f7273c3 | 11 | #include <dt-bindings/power/qcom-rpmpd.h> |
feeaf56a BK |
12 | |
13 | / { | |
feeaf56a BK |
14 | interrupt-parent = <&intc>; |
15 | ||
16 | #address-cells = <2>; | |
17 | #size-cells = <2>; | |
18 | ||
d8023f3a KD |
19 | aliases { |
20 | mmc1 = &sdhc1; | |
21 | mmc2 = &sdhc2; | |
22 | }; | |
23 | ||
feeaf56a BK |
24 | chosen { }; |
25 | ||
7c865b09 | 26 | clocks { |
8c678bec | 27 | xo_board: xo-board { |
7c865b09 KD |
28 | compatible = "fixed-clock"; |
29 | #clock-cells = <0>; | |
30 | clock-frequency = <19200000>; | |
8c678bec | 31 | clock-output-names = "xo_board"; |
7c865b09 KD |
32 | }; |
33 | ||
8c678bec | 34 | sleep_clk: sleep-clk { |
7c865b09 KD |
35 | compatible = "fixed-clock"; |
36 | #clock-cells = <0>; | |
37 | clock-frequency = <32768>; | |
8c678bec | 38 | clock-output-names = "sleep_clk"; |
7c865b09 KD |
39 | }; |
40 | }; | |
41 | ||
feeaf56a | 42 | cpus { |
02d8091b | 43 | #address-cells = <2>; |
feeaf56a | 44 | #size-cells = <0>; |
02d8091b KD |
45 | |
46 | CPU0: cpu@0 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a53"; | |
49 | reg = <0x0 0x0>; | |
50 | enable-method = "psci"; | |
51 | next-level-cache = <&L2_0>; | |
52 | L2_0: l2-cache { | |
53 | compatible = "cache"; | |
54 | cache-level = <2>; | |
9c6e72fb | 55 | cache-unified; |
02d8091b KD |
56 | }; |
57 | }; | |
58 | ||
59 | CPU1: cpu@1 { | |
60 | device_type = "cpu"; | |
61 | compatible = "arm,cortex-a53"; | |
62 | reg = <0x0 0x1>; | |
63 | enable-method = "psci"; | |
64 | next-level-cache = <&L2_0>; | |
65 | }; | |
66 | ||
67 | CPU2: cpu@2 { | |
68 | device_type = "cpu"; | |
69 | compatible = "arm,cortex-a53"; | |
70 | reg = <0x0 0x2>; | |
71 | enable-method = "psci"; | |
72 | next-level-cache = <&L2_0>; | |
73 | }; | |
74 | ||
75 | CPU3: cpu@3 { | |
76 | device_type = "cpu"; | |
77 | compatible = "arm,cortex-a53"; | |
78 | reg = <0x0 0x3>; | |
79 | enable-method = "psci"; | |
80 | next-level-cache = <&L2_0>; | |
81 | }; | |
82 | ||
83 | CPU4: cpu@100 { | |
84 | device_type = "cpu"; | |
85 | compatible = "arm,cortex-a57"; | |
86 | reg = <0x0 0x100>; | |
87 | enable-method = "psci"; | |
88 | next-level-cache = <&L2_1>; | |
89 | L2_1: l2-cache { | |
90 | compatible = "cache"; | |
91 | cache-level = <2>; | |
9c6e72fb | 92 | cache-unified; |
02d8091b KD |
93 | }; |
94 | }; | |
95 | ||
96 | CPU5: cpu@101 { | |
97 | device_type = "cpu"; | |
98 | compatible = "arm,cortex-a57"; | |
99 | reg = <0x0 0x101>; | |
100 | enable-method = "psci"; | |
101 | next-level-cache = <&L2_1>; | |
102 | }; | |
103 | ||
104 | CPU6: cpu@102 { | |
105 | device_type = "cpu"; | |
106 | compatible = "arm,cortex-a57"; | |
47bf59c4 | 107 | reg = <0x0 0x102>; |
02d8091b KD |
108 | enable-method = "psci"; |
109 | next-level-cache = <&L2_1>; | |
110 | }; | |
111 | ||
112 | CPU7: cpu@103 { | |
113 | device_type = "cpu"; | |
114 | compatible = "arm,cortex-a57"; | |
47bf59c4 | 115 | reg = <0x0 0x103>; |
02d8091b KD |
116 | enable-method = "psci"; |
117 | next-level-cache = <&L2_1>; | |
118 | }; | |
119 | ||
feeaf56a BK |
120 | cpu-map { |
121 | cluster0 { | |
122 | core0 { | |
123 | cpu = <&CPU0>; | |
124 | }; | |
02d8091b KD |
125 | |
126 | core1 { | |
127 | cpu = <&CPU1>; | |
128 | }; | |
129 | ||
130 | core2 { | |
131 | cpu = <&CPU2>; | |
132 | }; | |
133 | ||
134 | core3 { | |
135 | cpu = <&CPU3>; | |
136 | }; | |
feeaf56a | 137 | }; |
feeaf56a | 138 | |
02d8091b KD |
139 | cluster1 { |
140 | core0 { | |
141 | cpu = <&CPU4>; | |
142 | }; | |
143 | ||
144 | core1 { | |
145 | cpu = <&CPU5>; | |
146 | }; | |
147 | ||
976d321f | 148 | cpu6_map: core2 { |
02d8091b KD |
149 | cpu = <&CPU6>; |
150 | }; | |
151 | ||
976d321f | 152 | cpu7_map: core3 { |
02d8091b KD |
153 | cpu = <&CPU7>; |
154 | }; | |
feeaf56a BK |
155 | }; |
156 | }; | |
157 | }; | |
158 | ||
e4faf75d KD |
159 | firmware { |
160 | scm { | |
161 | compatible = "qcom,scm-msm8994", "qcom,scm"; | |
162 | }; | |
163 | }; | |
164 | ||
c0dffc3f | 165 | memory@80000000 { |
7c865b09 KD |
166 | device_type = "memory"; |
167 | /* We expect the bootloader to fill in the reg */ | |
c0dffc3f | 168 | reg = <0 0x80000000 0 0>; |
7c865b09 KD |
169 | }; |
170 | ||
a1026ca2 KD |
171 | pmu { |
172 | compatible = "arm,cortex-a53-pmu"; | |
173 | interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; | |
174 | }; | |
175 | ||
c21e7c06 KD |
176 | psci { |
177 | compatible = "arm,psci-0.2"; | |
178 | method = "hvc"; | |
179 | }; | |
180 | ||
091efd56 SG |
181 | rpm: remoteproc { |
182 | compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc"; | |
183 | ||
184 | smd-edge { | |
185 | interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; | |
186 | qcom,ipc = <&apcs 8 0>; | |
187 | qcom,smd-edge = <15>; | |
188 | qcom,remote-pid = <6>; | |
189 | ||
190 | rpm_requests: rpm-requests { | |
191 | compatible = "qcom,rpm-msm8994"; | |
192 | qcom,smd-channels = "rpm_requests"; | |
193 | ||
194 | rpmcc: clock-controller { | |
195 | compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; | |
196 | #clock-cells = <1>; | |
197 | }; | |
198 | ||
199 | rpmpd: power-controller { | |
200 | compatible = "qcom,msm8994-rpmpd"; | |
201 | #power-domain-cells = <1>; | |
202 | operating-points-v2 = <&rpmpd_opp_table>; | |
203 | ||
204 | rpmpd_opp_table: opp-table { | |
205 | compatible = "operating-points-v2"; | |
206 | ||
207 | rpmpd_opp_ret: opp1 { | |
208 | opp-level = <1>; | |
209 | }; | |
210 | rpmpd_opp_svs_krait: opp2 { | |
211 | opp-level = <2>; | |
212 | }; | |
213 | rpmpd_opp_svs_soc: opp3 { | |
214 | opp-level = <3>; | |
215 | }; | |
216 | rpmpd_opp_nom: opp4 { | |
217 | opp-level = <4>; | |
218 | }; | |
219 | rpmpd_opp_turbo: opp5 { | |
220 | opp-level = <5>; | |
221 | }; | |
222 | rpmpd_opp_super_turbo: opp6 { | |
223 | opp-level = <6>; | |
224 | }; | |
225 | }; | |
226 | }; | |
227 | }; | |
228 | }; | |
229 | }; | |
230 | ||
7c865b09 KD |
231 | reserved-memory { |
232 | #address-cells = <2>; | |
233 | #size-cells = <2>; | |
234 | ranges; | |
235 | ||
408e1776 | 236 | dfps_data_mem: dfps-data@3400000 { |
74d6d0a1 KD |
237 | reg = <0 0x03400000 0 0x1000>; |
238 | no-map; | |
239 | }; | |
240 | ||
049c46f3 KD |
241 | cont_splash_mem: memory@3401000 { |
242 | reg = <0 0x03401000 0 0x2200000>; | |
74d6d0a1 KD |
243 | no-map; |
244 | }; | |
245 | ||
408e1776 | 246 | smem_mem: smem@6a00000 { |
74d6d0a1 KD |
247 | reg = <0 0x06a00000 0 0x200000>; |
248 | no-map; | |
249 | }; | |
250 | ||
251 | mpss_mem: memory@7000000 { | |
252 | reg = <0 0x07000000 0 0x5a00000>; | |
253 | no-map; | |
254 | }; | |
255 | ||
256 | peripheral_region: memory@ca00000 { | |
257 | reg = <0 0x0ca00000 0 0x1f00000>; | |
258 | no-map; | |
259 | }; | |
260 | ||
261 | rmtfs_mem: memory@c6400000 { | |
262 | compatible = "qcom,rmtfs-mem"; | |
263 | reg = <0 0xc6400000 0 0x180000>; | |
264 | no-map; | |
265 | ||
266 | qcom,client-id = <1>; | |
267 | }; | |
268 | ||
269 | mba_mem: memory@c6700000 { | |
270 | reg = <0 0xc6700000 0 0x100000>; | |
271 | no-map; | |
272 | }; | |
273 | ||
274 | audio_mem: memory@c7000000 { | |
275 | reg = <0 0xc7000000 0 0x800000>; | |
276 | no-map; | |
277 | }; | |
278 | ||
279 | adsp_mem: memory@c9400000 { | |
280 | reg = <0 0xc9400000 0 0x3f00000>; | |
7c865b09 KD |
281 | no-map; |
282 | }; | |
c85c8a99 | 283 | |
bf80e606 | 284 | res_hyp_mem: reserved@6c00000 { |
c85c8a99 PV |
285 | reg = <0 0x06c00000 0 0x400000>; |
286 | no-map; | |
287 | }; | |
7c865b09 KD |
288 | }; |
289 | ||
290 | smem { | |
291 | compatible = "qcom,smem"; | |
292 | memory-region = <&smem_mem>; | |
01104518 | 293 | qcom,rpm-msg-ram = <&rpm_msg_ram>; |
7c865b09 | 294 | hwlocks = <&tcsr_mutex 3>; |
feeaf56a BK |
295 | }; |
296 | ||
886ddcfe KD |
297 | smp2p-lpass { |
298 | compatible = "qcom,smp2p"; | |
299 | qcom,smem = <443>, <429>; | |
300 | ||
301 | interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; | |
302 | ||
303 | qcom,ipc = <&apcs 8 10>; | |
304 | ||
305 | qcom,local-pid = <0>; | |
306 | qcom,remote-pid = <2>; | |
307 | ||
308 | adsp_smp2p_out: master-kernel { | |
309 | qcom,entry-name = "master-kernel"; | |
310 | #qcom,smem-state-cells = <1>; | |
311 | }; | |
312 | ||
313 | adsp_smp2p_in: slave-kernel { | |
314 | qcom,entry-name = "slave-kernel"; | |
315 | ||
316 | interrupt-controller; | |
317 | #interrupt-cells = <2>; | |
318 | }; | |
319 | }; | |
320 | ||
321 | smp2p-modem { | |
322 | compatible = "qcom,smp2p"; | |
323 | qcom,smem = <435>, <428>; | |
324 | ||
325 | interrupt-parent = <&intc>; | |
326 | interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; | |
327 | ||
328 | qcom,ipc = <&apcs 8 14>; | |
329 | ||
330 | qcom,local-pid = <0>; | |
331 | qcom,remote-pid = <1>; | |
332 | ||
333 | modem_smp2p_out: master-kernel { | |
334 | qcom,entry-name = "master-kernel"; | |
335 | #qcom,smem-state-cells = <1>; | |
336 | }; | |
337 | ||
338 | modem_smp2p_in: slave-kernel { | |
339 | qcom,entry-name = "slave-kernel"; | |
340 | ||
341 | interrupt-controller; | |
342 | #interrupt-cells = <2>; | |
343 | }; | |
344 | }; | |
345 | ||
f7fd546d | 346 | soc: soc@0 { |
feeaf56a BK |
347 | #address-cells = <1>; |
348 | #size-cells = <1>; | |
349 | ranges = <0 0 0 0xffffffff>; | |
350 | compatible = "simple-bus"; | |
351 | ||
352 | intc: interrupt-controller@f9000000 { | |
353 | compatible = "qcom,msm-qgic2"; | |
354 | interrupt-controller; | |
355 | #interrupt-cells = <3>; | |
356 | reg = <0xf9000000 0x1000>, | |
7c865b09 | 357 | <0xf9002000 0x1000>; |
feeaf56a BK |
358 | }; |
359 | ||
01104518 KD |
360 | apcs: mailbox@f900d000 { |
361 | compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; | |
362 | reg = <0xf900d000 0x2000>; | |
363 | #mbox-cells = <1>; | |
364 | }; | |
365 | ||
e0be93fb KD |
366 | watchdog@f9017000 { |
367 | compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; | |
368 | reg = <0xf9017000 0x1000>; | |
369 | interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, | |
370 | <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; | |
371 | clocks = <&sleep_clk>; | |
372 | timeout-sec = <10>; | |
373 | }; | |
374 | ||
feeaf56a BK |
375 | timer@f9020000 { |
376 | #address-cells = <1>; | |
377 | #size-cells = <1>; | |
378 | ranges; | |
379 | compatible = "arm,armv7-timer-mem"; | |
380 | reg = <0xf9020000 0x1000>; | |
381 | ||
382 | frame@f9021000 { | |
383 | frame-number = <0>; | |
384 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
385 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
386 | reg = <0xf9021000 0x1000>, | |
387 | <0xf9022000 0x1000>; | |
388 | }; | |
389 | ||
390 | frame@f9023000 { | |
391 | frame-number = <1>; | |
392 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
393 | reg = <0xf9023000 0x1000>; | |
394 | status = "disabled"; | |
395 | }; | |
396 | ||
397 | frame@f9024000 { | |
398 | frame-number = <2>; | |
399 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
400 | reg = <0xf9024000 0x1000>; | |
401 | status = "disabled"; | |
402 | }; | |
403 | ||
404 | frame@f9025000 { | |
405 | frame-number = <3>; | |
406 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
407 | reg = <0xf9025000 0x1000>; | |
408 | status = "disabled"; | |
409 | }; | |
410 | ||
411 | frame@f9026000 { | |
412 | frame-number = <4>; | |
413 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
414 | reg = <0xf9026000 0x1000>; | |
415 | status = "disabled"; | |
416 | }; | |
417 | ||
418 | frame@f9027000 { | |
419 | frame-number = <5>; | |
420 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
421 | reg = <0xf9027000 0x1000>; | |
422 | status = "disabled"; | |
423 | }; | |
424 | ||
425 | frame@f9028000 { | |
426 | frame-number = <6>; | |
427 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
428 | reg = <0xf9028000 0x1000>; | |
429 | status = "disabled"; | |
430 | }; | |
431 | }; | |
432 | ||
d9be0bc9 | 433 | usb3: usb@f92f8800 { |
b7f1528e | 434 | compatible = "qcom,msm8994-dwc3", "qcom,dwc3"; |
d9be0bc9 KD |
435 | reg = <0xf92f8800 0x400>; |
436 | #address-cells = <1>; | |
437 | #size-cells = <1>; | |
438 | ranges; | |
439 | ||
440 | clocks = <&gcc GCC_USB30_MASTER_CLK>, | |
441 | <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, | |
442 | <&gcc GCC_USB30_SLEEP_CLK>, | |
443 | <&gcc GCC_USB30_MOCK_UTMI_CLK>; | |
8d5fd4e4 KK |
444 | clock-names = "core", |
445 | "iface", | |
446 | "sleep", | |
447 | "mock_utmi"; | |
d9be0bc9 KD |
448 | |
449 | assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, | |
450 | <&gcc GCC_USB30_MASTER_CLK>; | |
451 | assigned-clock-rates = <19200000>, <120000000>; | |
452 | ||
453 | power-domains = <&gcc USB30_GDSC>; | |
454 | qcom,select-utmi-as-pipe-clk; | |
455 | ||
2aa2b50d | 456 | usb@f9200000 { |
d9be0bc9 KD |
457 | compatible = "snps,dwc3"; |
458 | reg = <0xf9200000 0xcc00>; | |
b79663a5 | 459 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
d9be0bc9 KD |
460 | snps,dis_u2_susphy_quirk; |
461 | snps,dis_enblslpm_quirk; | |
462 | maximum-speed = "high-speed"; | |
463 | dr_mode = "peripheral"; | |
464 | }; | |
465 | }; | |
466 | ||
96bb736f | 467 | sdhc1: mmc@f9824900 { |
4ec48ebf | 468 | compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; |
448d9c22 | 469 | reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; |
eddc917d | 470 | reg-names = "hc", "core"; |
448d9c22 KD |
471 | |
472 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
473 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
474 | interrupt-names = "hc_irq", "pwr_irq"; | |
475 | ||
4ff12270 BS |
476 | clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
477 | <&gcc GCC_SDCC1_APPS_CLK>, | |
448d9c22 | 478 | <&xo_board>; |
4ff12270 | 479 | clock-names = "iface", "core", "xo"; |
448d9c22 KD |
480 | |
481 | pinctrl-names = "default", "sleep"; | |
482 | pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; | |
483 | pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; | |
484 | ||
485 | bus-width = <8>; | |
486 | non-removable; | |
487 | status = "disabled"; | |
488 | }; | |
489 | ||
96bb736f | 490 | sdhc2: mmc@f98a4900 { |
4ec48ebf | 491 | compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; |
f3d1939f | 492 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; |
eddc917d | 493 | reg-names = "hc", "core"; |
f3d1939f KD |
494 | |
495 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
496 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
497 | interrupt-names = "hc_irq", "pwr_irq"; | |
498 | ||
4ff12270 BS |
499 | clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
500 | <&gcc GCC_SDCC2_APPS_CLK>, | |
501 | <&xo_board>; | |
502 | clock-names = "iface", "core", "xo"; | |
f3d1939f KD |
503 | |
504 | pinctrl-names = "default", "sleep"; | |
505 | pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; | |
506 | pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; | |
507 | ||
36c9d012 | 508 | cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; |
f3d1939f KD |
509 | bus-width = <4>; |
510 | status = "disabled"; | |
511 | }; | |
512 | ||
828896c5 | 513 | blsp1_dma: dma-controller@f9904000 { |
d3d071a0 KD |
514 | compatible = "qcom,bam-v1.7.0"; |
515 | reg = <0xf9904000 0x19000>; | |
516 | interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; | |
517 | clocks = <&gcc GCC_BLSP1_AHB_CLK>; | |
518 | clock-names = "bam_clk"; | |
519 | #dma-cells = <1>; | |
520 | qcom,ee = <0>; | |
521 | qcom,controlled-remotely; | |
1ae438d2 | 522 | num-channels = <24>; |
d3d071a0 KD |
523 | qcom,num-ees = <4>; |
524 | }; | |
525 | ||
7c865b09 KD |
526 | blsp1_uart2: serial@f991e000 { |
527 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
528 | reg = <0xf991e000 0x1000>; | |
529 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
7c865b09 KD |
530 | clock-names = "core", "iface"; |
531 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, | |
532 | <&gcc GCC_BLSP1_AHB_CLK>; | |
d3d071a0 KD |
533 | pinctrl-names = "default", "sleep"; |
534 | pinctrl-0 = <&blsp1_uart2_default>; | |
535 | pinctrl-1 = <&blsp1_uart2_sleep>; | |
536 | status = "disabled"; | |
537 | }; | |
538 | ||
e093d1a2 | 539 | blsp1_i2c1: i2c@f9923000 { |
d3d071a0 KD |
540 | compatible = "qcom,i2c-qup-v2.2.1"; |
541 | reg = <0xf9923000 0x500>; | |
542 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
543 | clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, |
544 | <&gcc GCC_BLSP1_AHB_CLK>; | |
545 | clock-names = "core", "iface"; | |
d3d071a0 | 546 | clock-frequency = <400000>; |
e093d1a2 GM |
547 | dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; |
548 | dma-names = "tx", "rx"; | |
d3d071a0 KD |
549 | pinctrl-names = "default", "sleep"; |
550 | pinctrl-0 = <&i2c1_default>; | |
551 | pinctrl-1 = <&i2c1_sleep>; | |
552 | #address-cells = <1>; | |
553 | #size-cells = <0>; | |
554 | status = "disabled"; | |
555 | }; | |
556 | ||
e093d1a2 | 557 | blsp1_spi1: spi@f9923000 { |
d3d071a0 KD |
558 | compatible = "qcom,spi-qup-v2.2.1"; |
559 | reg = <0xf9923000 0x500>; | |
560 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
561 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, | |
562 | <&gcc GCC_BLSP1_AHB_CLK>; | |
563 | clock-names = "core", "iface"; | |
d3d071a0 KD |
564 | dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; |
565 | dma-names = "tx", "rx"; | |
566 | pinctrl-names = "default", "sleep"; | |
e093d1a2 GM |
567 | pinctrl-0 = <&blsp1_spi1_default>; |
568 | pinctrl-1 = <&blsp1_spi1_sleep>; | |
d3d071a0 KD |
569 | #address-cells = <1>; |
570 | #size-cells = <0>; | |
571 | status = "disabled"; | |
572 | }; | |
573 | ||
e093d1a2 | 574 | blsp1_i2c2: i2c@f9924000 { |
d3d071a0 KD |
575 | compatible = "qcom,i2c-qup-v2.2.1"; |
576 | reg = <0xf9924000 0x500>; | |
577 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
578 | clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, |
579 | <&gcc GCC_BLSP1_AHB_CLK>; | |
580 | clock-names = "core", "iface"; | |
e093d1a2 | 581 | clock-frequency = <400000>; |
d3d071a0 KD |
582 | dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; |
583 | dma-names = "tx", "rx"; | |
584 | pinctrl-names = "default", "sleep"; | |
585 | pinctrl-0 = <&i2c2_default>; | |
586 | pinctrl-1 = <&i2c2_sleep>; | |
587 | #address-cells = <1>; | |
588 | #size-cells = <0>; | |
589 | status = "disabled"; | |
590 | }; | |
591 | ||
592 | /* I2C3 doesn't exist */ | |
593 | ||
e093d1a2 | 594 | blsp1_i2c4: i2c@f9926000 { |
d3d071a0 KD |
595 | compatible = "qcom,i2c-qup-v2.2.1"; |
596 | reg = <0xf9926000 0x500>; | |
597 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
598 | clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, |
599 | <&gcc GCC_BLSP1_AHB_CLK>; | |
600 | clock-names = "core", "iface"; | |
e093d1a2 GM |
601 | clock-frequency = <400000>; |
602 | dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; | |
603 | dma-names = "tx", "rx"; | |
d3d071a0 KD |
604 | pinctrl-names = "default", "sleep"; |
605 | pinctrl-0 = <&i2c4_default>; | |
606 | pinctrl-1 = <&i2c4_sleep>; | |
607 | #address-cells = <1>; | |
608 | #size-cells = <0>; | |
609 | status = "disabled"; | |
610 | }; | |
611 | ||
e093d1a2 GM |
612 | blsp1_i2c5: i2c@f9927000 { |
613 | compatible = "qcom,i2c-qup-v2.2.1"; | |
614 | reg = <0xf9927000 0x500>; | |
615 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
616 | clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, |
617 | <&gcc GCC_BLSP1_AHB_CLK>; | |
618 | clock-names = "core", "iface"; | |
e093d1a2 GM |
619 | clock-frequency = <400000>; |
620 | dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; | |
621 | dma-names = "tx", "rx"; | |
622 | pinctrl-names = "default", "sleep"; | |
623 | pinctrl-0 = <&i2c5_default>; | |
624 | pinctrl-1 = <&i2c5_sleep>; | |
625 | #address-cells = <1>; | |
626 | #size-cells = <0>; | |
627 | status = "disabled"; | |
d3d071a0 KD |
628 | }; |
629 | ||
e093d1a2 | 630 | blsp1_i2c6: i2c@f9928000 { |
d3d071a0 KD |
631 | compatible = "qcom,i2c-qup-v2.2.1"; |
632 | reg = <0xf9928000 0x500>; | |
633 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
634 | clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, |
635 | <&gcc GCC_BLSP1_AHB_CLK>; | |
636 | clock-names = "core", "iface"; | |
e093d1a2 | 637 | clock-frequency = <400000>; |
d3d071a0 KD |
638 | dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; |
639 | dma-names = "tx", "rx"; | |
640 | pinctrl-names = "default", "sleep"; | |
641 | pinctrl-0 = <&i2c6_default>; | |
642 | pinctrl-1 = <&i2c6_sleep>; | |
643 | #address-cells = <1>; | |
644 | #size-cells = <0>; | |
645 | status = "disabled"; | |
646 | }; | |
647 | ||
e093d1a2 GM |
648 | blsp2_dma: dma-controller@f9944000 { |
649 | compatible = "qcom,bam-v1.7.0"; | |
650 | reg = <0xf9944000 0x19000>; | |
651 | interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; | |
652 | clocks = <&gcc GCC_BLSP2_AHB_CLK>; | |
653 | clock-names = "bam_clk"; | |
654 | #dma-cells = <1>; | |
655 | qcom,ee = <0>; | |
656 | qcom,controlled-remotely; | |
1ae438d2 | 657 | num-channels = <24>; |
e093d1a2 GM |
658 | qcom,num-ees = <4>; |
659 | }; | |
660 | ||
d3d071a0 KD |
661 | blsp2_uart2: serial@f995e000 { |
662 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
663 | reg = <0xf995e000 0x1000>; | |
a046032c | 664 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
d3d071a0 KD |
665 | clock-names = "core", "iface"; |
666 | clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, | |
667 | <&gcc GCC_BLSP2_AHB_CLK>; | |
668 | dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; | |
669 | dma-names = "tx", "rx"; | |
670 | pinctrl-names = "default", "sleep"; | |
671 | pinctrl-0 = <&blsp2_uart2_default>; | |
672 | pinctrl-1 = <&blsp2_uart2_sleep>; | |
673 | status = "disabled"; | |
674 | }; | |
675 | ||
e093d1a2 GM |
676 | blsp2_i2c1: i2c@f9963000 { |
677 | compatible = "qcom,i2c-qup-v2.2.1"; | |
678 | reg = <0xf9963000 0x500>; | |
679 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
680 | clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, |
681 | <&gcc GCC_BLSP2_AHB_CLK>; | |
682 | clock-names = "core", "iface"; | |
e093d1a2 GM |
683 | clock-frequency = <400000>; |
684 | dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; | |
685 | dma-names = "tx", "rx"; | |
686 | pinctrl-names = "default", "sleep"; | |
687 | pinctrl-0 = <&i2c7_default>; | |
688 | pinctrl-1 = <&i2c7_sleep>; | |
689 | #address-cells = <1>; | |
690 | #size-cells = <0>; | |
691 | status = "disabled"; | |
692 | }; | |
693 | ||
694 | blsp2_spi4: spi@f9966000 { | |
695 | compatible = "qcom,spi-qup-v2.2.1"; | |
696 | reg = <0xf9966000 0x500>; | |
697 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
698 | clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, | |
699 | <&gcc GCC_BLSP2_AHB_CLK>; | |
700 | clock-names = "core", "iface"; | |
e093d1a2 GM |
701 | dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; |
702 | dma-names = "tx", "rx"; | |
703 | pinctrl-names = "default", "sleep"; | |
704 | pinctrl-0 = <&blsp2_spi10_default>; | |
705 | pinctrl-1 = <&blsp2_spi10_sleep>; | |
706 | #address-cells = <1>; | |
707 | #size-cells = <0>; | |
708 | status = "disabled"; | |
709 | }; | |
710 | ||
711 | blsp2_i2c5: i2c@f9967000 { | |
d3d071a0 KD |
712 | compatible = "qcom,i2c-qup-v2.2.1"; |
713 | reg = <0xf9967000 0x500>; | |
714 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
2374b99e KK |
715 | clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, |
716 | <&gcc GCC_BLSP2_AHB_CLK>; | |
717 | clock-names = "core", "iface"; | |
d3d071a0 KD |
718 | clock-frequency = <355000>; |
719 | dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; | |
720 | dma-names = "tx", "rx"; | |
721 | pinctrl-names = "default", "sleep"; | |
e093d1a2 GM |
722 | pinctrl-0 = <&i2c11_default>; |
723 | pinctrl-1 = <&i2c11_sleep>; | |
d3d071a0 KD |
724 | #address-cells = <1>; |
725 | #size-cells = <0>; | |
726 | status = "disabled"; | |
7c865b09 KD |
727 | }; |
728 | ||
729 | gcc: clock-controller@fc400000 { | |
730 | compatible = "qcom,gcc-msm8994"; | |
731 | #clock-cells = <1>; | |
732 | #reset-cells = <1>; | |
733 | #power-domain-cells = <1>; | |
734 | reg = <0xfc400000 0x2000>; | |
4dd1ad61 | 735 | |
5827e283 | 736 | clock-names = "xo", "sleep"; |
4dd1ad61 | 737 | clocks = <&xo_board>, <&sleep_clk>; |
7c865b09 KD |
738 | }; |
739 | ||
179811be | 740 | rpm_msg_ram: sram@fc428000 { |
01104518 KD |
741 | compatible = "qcom,rpm-msg-ram"; |
742 | reg = <0xfc428000 0x4000>; | |
743 | }; | |
744 | ||
feeaf56a BK |
745 | restart@fc4ab000 { |
746 | compatible = "qcom,pshold"; | |
747 | reg = <0xfc4ab000 0x4>; | |
748 | }; | |
749 | ||
24f0f6a8 | 750 | spmi_bus: spmi@fc4cf000 { |
b0ad598f KD |
751 | compatible = "qcom,spmi-pmic-arb"; |
752 | reg = <0xfc4cf000 0x1000>, | |
753 | <0xfc4cb000 0x1000>, | |
754 | <0xfc4ca000 0x1000>; | |
755 | reg-names = "core", "intr", "cnfg"; | |
756 | interrupt-names = "periph_irq"; | |
757 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | |
758 | qcom,ee = <0>; | |
759 | qcom,channel = <0>; | |
760 | #address-cells = <2>; | |
761 | #size-cells = <0>; | |
762 | interrupt-controller; | |
763 | #interrupt-cells = <4>; | |
764 | }; | |
765 | ||
9e826e05 KK |
766 | tcsr_mutex: hwlock@fd484000 { |
767 | compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex"; | |
768 | reg = <0xfd484000 0x1000>; | |
769 | #hwlock-cells = <1>; | |
7c865b09 KD |
770 | }; |
771 | ||
772 | tlmm: pinctrl@fd510000 { | |
feeaf56a BK |
773 | compatible = "qcom,msm8994-pinctrl"; |
774 | reg = <0xfd510000 0x4000>; | |
775 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
776 | gpio-controller; | |
7c865b09 | 777 | gpio-ranges = <&tlmm 0 0 146>; |
feeaf56a BK |
778 | #gpio-cells = <2>; |
779 | interrupt-controller; | |
780 | #interrupt-cells = <2>; | |
feeaf56a | 781 | |
9d7d01da | 782 | blsp1_uart2_default: blsp1-uart2-default-state { |
7c865b09 | 783 | pins = "gpio4", "gpio5"; |
9d7d01da | 784 | function = "blsp_uart2"; |
7c865b09 KD |
785 | drive-strength = <16>; |
786 | bias-disable; | |
787 | }; | |
feeaf56a | 788 | |
9d7d01da | 789 | blsp1_uart2_sleep: blsp1-uart2-sleep-state { |
7c865b09 | 790 | pins = "gpio4", "gpio5"; |
9d7d01da | 791 | function = "gpio"; |
7c865b09 KD |
792 | drive-strength = <2>; |
793 | bias-pull-down; | |
794 | }; | |
feeaf56a | 795 | |
9d7d01da KK |
796 | blsp2_uart2_default: blsp2-uart2-default-state { |
797 | pins = "gpio45", "gpio46", "gpio47", "gpio48"; | |
7c865b09 | 798 | function = "blsp_uart8"; |
a046032c | 799 | drive-strength = <16>; |
7c865b09 KD |
800 | bias-disable; |
801 | }; | |
feeaf56a | 802 | |
9d7d01da KK |
803 | blsp2_uart2_sleep: blsp2-uart2-sleep-state { |
804 | pins = "gpio45", "gpio46", "gpio47", "gpio48"; | |
7c865b09 | 805 | function = "gpio"; |
7c865b09 | 806 | drive-strength = <2>; |
a046032c | 807 | bias-disable; |
7c865b09 | 808 | }; |
feeaf56a | 809 | |
9d7d01da | 810 | i2c1_default: i2c1-default-state { |
7c865b09 | 811 | pins = "gpio2", "gpio3"; |
9d7d01da | 812 | function = "blsp_i2c1"; |
7c865b09 KD |
813 | drive-strength = <2>; |
814 | bias-disable; | |
815 | }; | |
feeaf56a | 816 | |
9d7d01da | 817 | i2c1_sleep: i2c1-sleep-state { |
7c865b09 | 818 | pins = "gpio2", "gpio3"; |
9d7d01da | 819 | function = "gpio"; |
7c865b09 KD |
820 | drive-strength = <2>; |
821 | bias-disable; | |
822 | }; | |
feeaf56a | 823 | |
9d7d01da | 824 | i2c2_default: i2c2-default-state { |
7c865b09 | 825 | pins = "gpio6", "gpio7"; |
9d7d01da | 826 | function = "blsp_i2c2"; |
7c865b09 KD |
827 | drive-strength = <2>; |
828 | bias-disable; | |
829 | }; | |
feeaf56a | 830 | |
9d7d01da | 831 | i2c2_sleep: i2c2-sleep-state { |
7c865b09 | 832 | pins = "gpio6", "gpio7"; |
9d7d01da | 833 | function = "gpio"; |
7c865b09 KD |
834 | drive-strength = <2>; |
835 | bias-disable; | |
836 | }; | |
837 | ||
9d7d01da | 838 | i2c4_default: i2c4-default-state { |
7c865b09 | 839 | pins = "gpio19", "gpio20"; |
9d7d01da | 840 | function = "blsp_i2c4"; |
7c865b09 KD |
841 | drive-strength = <2>; |
842 | bias-disable; | |
843 | }; | |
844 | ||
9d7d01da | 845 | i2c4_sleep: i2c4-sleep-state { |
7c865b09 | 846 | pins = "gpio19", "gpio20"; |
9d7d01da | 847 | function = "gpio"; |
7c865b09 KD |
848 | drive-strength = <2>; |
849 | bias-pull-down; | |
7c865b09 KD |
850 | }; |
851 | ||
9d7d01da | 852 | i2c5_default: i2c5-default-state { |
7c865b09 | 853 | pins = "gpio23", "gpio24"; |
9d7d01da | 854 | function = "blsp_i2c5"; |
7c865b09 KD |
855 | drive-strength = <2>; |
856 | bias-disable; | |
857 | }; | |
858 | ||
9d7d01da | 859 | i2c5_sleep: i2c5-sleep-state { |
7c865b09 | 860 | pins = "gpio23", "gpio24"; |
9d7d01da | 861 | function = "gpio"; |
7c865b09 KD |
862 | drive-strength = <2>; |
863 | bias-disable; | |
864 | }; | |
865 | ||
9d7d01da | 866 | i2c6_default: i2c6-default-state { |
7c865b09 | 867 | pins = "gpio28", "gpio27"; |
9d7d01da | 868 | function = "blsp_i2c6"; |
7c865b09 KD |
869 | drive-strength = <2>; |
870 | bias-disable; | |
871 | }; | |
872 | ||
9d7d01da | 873 | i2c6_sleep: i2c6-sleep-state { |
7c865b09 | 874 | pins = "gpio28", "gpio27"; |
9d7d01da | 875 | function = "gpio"; |
7c865b09 KD |
876 | drive-strength = <2>; |
877 | bias-disable; | |
878 | }; | |
879 | ||
9d7d01da | 880 | i2c7_default: i2c7-default-state { |
e093d1a2 | 881 | pins = "gpio44", "gpio43"; |
9d7d01da | 882 | function = "blsp_i2c7"; |
e093d1a2 GM |
883 | drive-strength = <2>; |
884 | bias-disable; | |
885 | }; | |
886 | ||
9d7d01da | 887 | i2c7_sleep: i2c7-sleep-state { |
e093d1a2 | 888 | pins = "gpio44", "gpio43"; |
9d7d01da | 889 | function = "gpio"; |
e093d1a2 GM |
890 | drive-strength = <2>; |
891 | bias-disable; | |
892 | }; | |
893 | ||
9d7d01da KK |
894 | blsp2_spi10_default: blsp2-spi10-default-state { |
895 | default-pins { | |
e093d1a2 | 896 | pins = "gpio53", "gpio54", "gpio55"; |
9d7d01da | 897 | function = "blsp_spi10"; |
e093d1a2 GM |
898 | drive-strength = <10>; |
899 | bias-pull-down; | |
900 | }; | |
9d7d01da KK |
901 | |
902 | cs-pins { | |
5d76dfb8 | 903 | pins = "gpio67"; |
9d7d01da | 904 | function = "gpio"; |
e093d1a2 GM |
905 | drive-strength = <2>; |
906 | bias-disable; | |
907 | }; | |
908 | }; | |
909 | ||
9d7d01da | 910 | blsp2_spi10_sleep: blsp2-spi10-sleep-state { |
e093d1a2 | 911 | pins = "gpio53", "gpio54", "gpio55"; |
9d7d01da | 912 | function = "gpio"; |
e093d1a2 GM |
913 | drive-strength = <2>; |
914 | bias-disable; | |
915 | }; | |
916 | ||
9d7d01da | 917 | i2c11_default: i2c11-default-state { |
e093d1a2 | 918 | pins = "gpio83", "gpio84"; |
9d7d01da | 919 | function = "blsp_i2c11"; |
e093d1a2 GM |
920 | drive-strength = <2>; |
921 | bias-disable; | |
922 | }; | |
923 | ||
9d7d01da | 924 | i2c11_sleep: i2c11-sleep-state { |
e093d1a2 | 925 | pins = "gpio83", "gpio84"; |
9d7d01da | 926 | function = "gpio"; |
e093d1a2 GM |
927 | drive-strength = <2>; |
928 | bias-disable; | |
929 | }; | |
930 | ||
9d7d01da KK |
931 | blsp1_spi1_default: blsp1-spi1-default-state { |
932 | default-pins { | |
7c865b09 | 933 | pins = "gpio0", "gpio1", "gpio3"; |
9d7d01da | 934 | function = "blsp_spi1"; |
7c865b09 KD |
935 | drive-strength = <10>; |
936 | bias-pull-down; | |
937 | }; | |
9d7d01da KK |
938 | |
939 | cs-pins { | |
7c865b09 | 940 | pins = "gpio8"; |
9d7d01da | 941 | function = "gpio"; |
7c865b09 KD |
942 | drive-strength = <2>; |
943 | bias-disable; | |
944 | }; | |
945 | }; | |
946 | ||
9d7d01da | 947 | blsp1_spi1_sleep: blsp1-spi1-sleep-state { |
7c865b09 | 948 | pins = "gpio0", "gpio1", "gpio3"; |
9d7d01da | 949 | function = "gpio"; |
7c865b09 KD |
950 | drive-strength = <2>; |
951 | bias-disable; | |
952 | }; | |
953 | ||
9d7d01da | 954 | sdc1_clk_on: clk-on-state { |
7c865b09 KD |
955 | pins = "sdc1_clk"; |
956 | bias-disable; | |
957 | drive-strength = <16>; | |
958 | }; | |
959 | ||
9d7d01da | 960 | sdc1_clk_off: clk-off-state { |
7c865b09 KD |
961 | pins = "sdc1_clk"; |
962 | bias-disable; | |
963 | drive-strength = <2>; | |
964 | }; | |
965 | ||
9d7d01da | 966 | sdc1_cmd_on: cmd-on-state { |
7c865b09 KD |
967 | pins = "sdc1_cmd"; |
968 | bias-pull-up; | |
969 | drive-strength = <8>; | |
970 | }; | |
971 | ||
9d7d01da | 972 | sdc1_cmd_off: cmd-off-state { |
7c865b09 KD |
973 | pins = "sdc1_cmd"; |
974 | bias-pull-up; | |
975 | drive-strength = <2>; | |
976 | }; | |
977 | ||
9d7d01da | 978 | sdc1_data_on: data-on-state { |
7c865b09 KD |
979 | pins = "sdc1_data"; |
980 | bias-pull-up; | |
981 | drive-strength = <8>; | |
982 | }; | |
983 | ||
9d7d01da | 984 | sdc1_data_off: data-off-state { |
7c865b09 KD |
985 | pins = "sdc1_data"; |
986 | bias-pull-up; | |
987 | drive-strength = <2>; | |
988 | }; | |
989 | ||
9d7d01da | 990 | sdc1_rclk_on: rclk-on-state { |
7c865b09 KD |
991 | pins = "sdc1_rclk"; |
992 | bias-pull-down; | |
993 | }; | |
994 | ||
9d7d01da | 995 | sdc1_rclk_off: rclk-off-state { |
7c865b09 KD |
996 | pins = "sdc1_rclk"; |
997 | bias-pull-down; | |
998 | }; | |
f3d1939f | 999 | |
9d7d01da | 1000 | sdc2_clk_on: sdc2-clk-on-state { |
f3d1939f KD |
1001 | pins = "sdc2_clk"; |
1002 | bias-disable; | |
1003 | drive-strength = <10>; | |
1004 | }; | |
1005 | ||
9d7d01da | 1006 | sdc2_clk_off: sdc2-clk-off-state { |
f3d1939f KD |
1007 | pins = "sdc2_clk"; |
1008 | bias-disable; | |
1009 | drive-strength = <2>; | |
1010 | }; | |
1011 | ||
9d7d01da | 1012 | sdc2_cmd_on: sdc2-cmd-on-state { |
f3d1939f KD |
1013 | pins = "sdc2_cmd"; |
1014 | bias-pull-up; | |
1015 | drive-strength = <10>; | |
1016 | }; | |
1017 | ||
9d7d01da | 1018 | sdc2_cmd_off: sdc2-cmd-off-state { |
f3d1939f KD |
1019 | pins = "sdc2_cmd"; |
1020 | bias-pull-up; | |
1021 | drive-strength = <2>; | |
1022 | }; | |
1023 | ||
9d7d01da | 1024 | sdc2_data_on: sdc2-data-on-state { |
f3d1939f KD |
1025 | pins = "sdc2_data"; |
1026 | bias-pull-up; | |
1027 | drive-strength = <10>; | |
1028 | }; | |
1029 | ||
9d7d01da | 1030 | sdc2_data_off: sdc2-data-off-state { |
f3d1939f KD |
1031 | pins = "sdc2_data"; |
1032 | bias-pull-up; | |
1033 | drive-strength = <2>; | |
1034 | }; | |
feeaf56a | 1035 | }; |
e9b0eb54 KD |
1036 | |
1037 | mmcc: clock-controller@fd8c0000 { | |
1038 | compatible = "qcom,mmcc-msm8994"; | |
1039 | reg = <0xfd8c0000 0x5200>; | |
1040 | #clock-cells = <1>; | |
1041 | #reset-cells = <1>; | |
1042 | #power-domain-cells = <1>; | |
1043 | ||
1044 | clock-names = "xo", | |
1045 | "gpll0", | |
1046 | "mmssnoc_ahb", | |
1047 | "oxili_gfx3d_clk_src", | |
1048 | "dsi0pll", | |
1049 | "dsi0pllbyte", | |
1050 | "dsi1pll", | |
1051 | "dsi1pllbyte", | |
1052 | "hdmipll"; | |
1053 | clocks = <&xo_board>, | |
1054 | <&gcc GPLL0_OUT_MMSSCC>, | |
1055 | <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, | |
1056 | <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, | |
1057 | <0>, | |
1058 | <0>, | |
1059 | <0>, | |
1060 | <0>, | |
1061 | <0>; | |
1062 | ||
1063 | assigned-clocks = <&mmcc MMPLL0_PLL>, | |
1064 | <&mmcc MMPLL1_PLL>, | |
1065 | <&mmcc MMPLL3_PLL>, | |
1066 | <&mmcc MMPLL4_PLL>, | |
1067 | <&mmcc MMPLL5_PLL>; | |
1068 | assigned-clock-rates = <800000000>, | |
1069 | <1167000000>, | |
1070 | <1020000000>, | |
1071 | <960000000>, | |
1072 | <600000000>; | |
1073 | }; | |
9d511d0a | 1074 | |
bed08556 | 1075 | ocmem: sram@fdd00000 { |
9d511d0a KD |
1076 | compatible = "qcom,msm8974-ocmem"; |
1077 | reg = <0xfdd00000 0x2000>, | |
1078 | <0xfec00000 0x200000>; | |
1079 | reg-names = "ctrl", "mem"; | |
07f3c7a1 | 1080 | ranges = <0 0xfec00000 0x200000>; |
9d511d0a KD |
1081 | clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, |
1082 | <&mmcc OCMEMCX_OCMEMNOC_CLK>; | |
1083 | clock-names = "core", "iface"; | |
1084 | ||
1085 | #address-cells = <1>; | |
1086 | #size-cells = <1>; | |
1087 | ||
1088 | gmu_sram: gmu-sram@0 { | |
1089 | reg = <0x0 0x180000>; | |
1090 | }; | |
1091 | }; | |
feeaf56a BK |
1092 | }; |
1093 | ||
976d321f | 1094 | timer: timer { |
7c865b09 KD |
1095 | compatible = "arm,armv8-timer"; |
1096 | interrupts = <GIC_PPI 2 0xff08>, | |
1097 | <GIC_PPI 3 0xff08>, | |
1098 | <GIC_PPI 4 0xff08>, | |
1099 | <GIC_PPI 1 0xff08>; | |
feeaf56a | 1100 | }; |
01104518 | 1101 | |
53364cfc | 1102 | vph_pwr: vph-pwr-regulator { |
01104518 | 1103 | compatible = "regulator-fixed"; |
53364cfc | 1104 | regulator-name = "vph_pwr"; |
01104518 KD |
1105 | |
1106 | regulator-min-microvolt = <3600000>; | |
1107 | regulator-max-microvolt = <3600000>; | |
1108 | ||
1109 | regulator-always-on; | |
1110 | }; | |
feeaf56a BK |
1111 | }; |
1112 |