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arm64: dts: qcom: msm8994: Fix remaining BLSP errors/mistakes
[linux-2.6-block.git] / arch / arm64 / boot / dts / qcom / msm8994.dtsi
CommitLineData
97fb5e8d 1// SPDX-License-Identifier: GPL-2.0-only
feeaf56a 2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
feeaf56a
BK		 3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8994.h>
0f7273c3 7#include <dt-bindings/power/qcom-rpmpd.h>
feeaf56a
BK		 8
9/ {
feeaf56a
BK		 10 interrupt-parent = <&intc>;
11
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 chosen { };
16
7c865b09
KD		 17 clocks {
18 xo_board: xo_board {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <19200000>;
22 };
23
24 sleep_clk: sleep_clk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <32768>;
28 };
29 };
30
feeaf56a 31 cpus {
02d8091b 32 #address-cells = <2>;
feeaf56a 33 #size-cells = <0>;
02d8091b
KD		 34
35 CPU0: cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a53";
38 reg = <0x0 0x0>;
39 enable-method = "psci";
40 next-level-cache = <&L2_0>;
41 L2_0: l2-cache {
42 compatible = "cache";
43 cache-level = <2>;
44 };
45 };
46
47 CPU1: cpu@1 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a53";
50 reg = <0x0 0x1>;
51 enable-method = "psci";
52 next-level-cache = <&L2_0>;
53 };
54
55 CPU2: cpu@2 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a53";
58 reg = <0x0 0x2>;
59 enable-method = "psci";
60 next-level-cache = <&L2_0>;
61 };
62
63 CPU3: cpu@3 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a53";
66 reg = <0x0 0x3>;
67 enable-method = "psci";
68 next-level-cache = <&L2_0>;
69 };
70
71 CPU4: cpu@100 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a57";
74 reg = <0x0 0x100>;
75 enable-method = "psci";
76 next-level-cache = <&L2_1>;
77 L2_1: l2-cache {
78 compatible = "cache";
79 cache-level = <2>;
80 };
81 };
82
83 CPU5: cpu@101 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a57";
86 reg = <0x0 0x101>;
87 enable-method = "psci";
88 next-level-cache = <&L2_1>;
89 };
90
91 CPU6: cpu@102 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a57";
94 reg = <0x0 0x101>;
95 enable-method = "psci";
96 next-level-cache = <&L2_1>;
97 };
98
99 CPU7: cpu@103 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a57";
102 reg = <0x0 0x101>;
103 enable-method = "psci";
104 next-level-cache = <&L2_1>;
105 };
106
feeaf56a
BK		 107 cpu-map {
108 cluster0 {
109 core0 {
110 cpu = <&CPU0>;
111 };
02d8091b
KD		 112
113 core1 {
114 cpu = <&CPU1>;
115 };
116
117 core2 {
118 cpu = <&CPU2>;
119 };
120
121 core3 {
122 cpu = <&CPU3>;
123 };
feeaf56a 124 };
feeaf56a 125
02d8091b
KD		 126 cluster1 {
127 core0 {
128 cpu = <&CPU4>;
129 };
130
131 core1 {
132 cpu = <&CPU5>;
133 };
134
135 core2 {
136 cpu = <&CPU6>;
137 };
138
139 core3 {
140 cpu = <&CPU7>;
141 };
feeaf56a
BK		 142 };
143 };
144 };
145
e4faf75d
KD		 146 firmware {
147 scm {
148 compatible = "qcom,scm-msm8994", "qcom,scm";
149 };
150 };
151
7c865b09
KD		 152 memory {
153 device_type = "memory";
154 /* We expect the bootloader to fill in the reg */
155 reg = <0 0 0 0>;
156 };
157
a1026ca2
KD		 158 pmu {
159 compatible = "arm,cortex-a53-pmu";
160 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
161 };
162
c21e7c06
KD		 163 psci {
164 compatible = "arm,psci-0.2";
165 method = "hvc";
166 };
167
7c865b09
KD		 168 reserved-memory {
169 #address-cells = <2>;
170 #size-cells = <2>;
171 ranges;
172
74d6d0a1
KD		 173 dfps_data_mem: dfps_data_mem@3400000 {
174 reg = <0 0x03400000 0 0x1000>;
175 no-map;
176 };
177
178 cont_splash_mem: memory@3800000 {
179 reg = <0 0x03800000 0 0x2400000>;
180 no-map;
181 };
182
7c865b09 183 smem_mem: smem_region@6a00000 {
74d6d0a1
KD		 184 reg = <0 0x06a00000 0 0x200000>;
185 no-map;
186 };
187
188 mpss_mem: memory@7000000 {
189 reg = <0 0x07000000 0 0x5a00000>;
190 no-map;
191 };
192
193 peripheral_region: memory@ca00000 {
194 reg = <0 0x0ca00000 0 0x1f00000>;
195 no-map;
196 };
197
198 rmtfs_mem: memory@c6400000 {
199 compatible = "qcom,rmtfs-mem";
200 reg = <0 0xc6400000 0 0x180000>;
201 no-map;
202
203 qcom,client-id = <1>;
204 };
205
206 mba_mem: memory@c6700000 {
207 reg = <0 0xc6700000 0 0x100000>;
208 no-map;
209 };
210
211 audio_mem: memory@c7000000 {
212 reg = <0 0xc7000000 0 0x800000>;
213 no-map;
214 };
215
216 adsp_mem: memory@c9400000 {
217 reg = <0 0xc9400000 0 0x3f00000>;
7c865b09
KD		 218 no-map;
219 };
220 };
221
01104518
KD		 222 smd {
223 compatible = "qcom,smd";
224 rpm {
225 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
226 qcom,ipc = <&apcs 8 0>;
227 qcom,smd-edge = <15>;
228 qcom,local-pid = <0>;
229 qcom,remote-pid = <6>;
230
231 rpm_requests: rpm-requests {
232 compatible = "qcom,rpm-msm8994";
233 qcom,smd-channels = "rpm_requests";
234
235 rpmcc: rpmcc {
236 compatible = "qcom,rpmcc-msm8994";
237 #clock-cells = <1>;
238 };
0f7273c3
KD		 239
240 rpmpd: power-controller {
241 compatible = "qcom,msm8994-rpmpd";
242 #power-domain-cells = <1>;
243 operating-points-v2 = <&rpmpd_opp_table>;
244
245 rpmpd_opp_table: opp-table {
246 compatible = "operating-points-v2";
247
248 rpmpd_opp_ret: opp1 {
249 opp-level = <1>;
250 };
251 rpmpd_opp_svs_krait: opp2 {
252 opp-level = <2>;
253 };
254 rpmpd_opp_svs_soc: opp3 {
255 opp-level = <3>;
256 };
257 rpmpd_opp_nom: opp4 {
258 opp-level = <4>;
259 };
260 rpmpd_opp_turbo: opp5 {
261 opp-level = <5>;
262 };
263 rpmpd_opp_super_turbo: opp6 {
264 opp-level = <6>;
265 };
266 };
267 };
01104518
KD		 268 };
269 };
270 };
271
7c865b09
KD		 272 smem {
273 compatible = "qcom,smem";
274 memory-region = <&smem_mem>;
01104518 275 qcom,rpm-msg-ram = <&rpm_msg_ram>;
7c865b09 276 hwlocks = <&tcsr_mutex 3>;
feeaf56a
BK		 277 };
278
886ddcfe
KD		 279 smp2p-lpass {
280 compatible = "qcom,smp2p";
281 qcom,smem = <443>, <429>;
282
283 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
284
285 qcom,ipc = <&apcs 8 10>;
286
287 qcom,local-pid = <0>;
288 qcom,remote-pid = <2>;
289
290 adsp_smp2p_out: master-kernel {
291 qcom,entry-name = "master-kernel";
292 #qcom,smem-state-cells = <1>;
293 };
294
295 adsp_smp2p_in: slave-kernel {
296 qcom,entry-name = "slave-kernel";
297
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 };
301 };
302
303 smp2p-modem {
304 compatible = "qcom,smp2p";
305 qcom,smem = <435>, <428>;
306
307 interrupt-parent = <&intc>;
308 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
309
310 qcom,ipc = <&apcs 8 14>;
311
312 qcom,local-pid = <0>;
313 qcom,remote-pid = <1>;
314
315 modem_smp2p_out: master-kernel {
316 qcom,entry-name = "master-kernel";
317 #qcom,smem-state-cells = <1>;
318 };
319
320 modem_smp2p_in: slave-kernel {
321 qcom,entry-name = "slave-kernel";
322
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 };
326 };
327
feeaf56a
BK		 328 soc: soc {
329
330 #address-cells = <1>;
331 #size-cells = <1>;
332 ranges = <0 0 0 0xffffffff>;
333 compatible = "simple-bus";
334
335 intc: interrupt-controller@f9000000 {
336 compatible = "qcom,msm-qgic2";
337 interrupt-controller;
338 #interrupt-cells = <3>;
339 reg = <0xf9000000 0x1000>,
7c865b09 340 <0xf9002000 0x1000>;
feeaf56a
BK		 341 };
342
01104518
KD		 343 apcs: mailbox@f900d000 {
344 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
345 reg = <0xf900d000 0x2000>;
346 #mbox-cells = <1>;
347 };
348
feeaf56a
BK		 349 timer@f9020000 {
350 #address-cells = <1>;
351 #size-cells = <1>;
352 ranges;
353 compatible = "arm,armv7-timer-mem";
354 reg = <0xf9020000 0x1000>;
355
356 frame@f9021000 {
357 frame-number = <0>;
358 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
360 reg = <0xf9021000 0x1000>,
361 <0xf9022000 0x1000>;
362 };
363
364 frame@f9023000 {
365 frame-number = <1>;
366 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
367 reg = <0xf9023000 0x1000>;
368 status = "disabled";
369 };
370
371 frame@f9024000 {
372 frame-number = <2>;
373 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
374 reg = <0xf9024000 0x1000>;
375 status = "disabled";
376 };
377
378 frame@f9025000 {
379 frame-number = <3>;
380 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
381 reg = <0xf9025000 0x1000>;
382 status = "disabled";
383 };
384
385 frame@f9026000 {
386 frame-number = <4>;
387 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
388 reg = <0xf9026000 0x1000>;
389 status = "disabled";
390 };
391
392 frame@f9027000 {
393 frame-number = <5>;
394 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
395 reg = <0xf9027000 0x1000>;
396 status = "disabled";
397 };
398
399 frame@f9028000 {
400 frame-number = <6>;
401 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
402 reg = <0xf9028000 0x1000>;
403 status = "disabled";
404 };
405 };
406
d9be0bc9
KD		 407 usb3: usb@f92f8800 {
408 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
409 reg = <0xf92f8800 0x400>;
410 #address-cells = <1>;
411 #size-cells = <1>;
412 ranges;
413
414 clocks = <&gcc GCC_USB30_MASTER_CLK>,
415 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
416 <&gcc GCC_USB30_SLEEP_CLK>,
417 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
418 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
419
420 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
421 <&gcc GCC_USB30_MASTER_CLK>;
422 assigned-clock-rates = <19200000>, <120000000>;
423
424 power-domains = <&gcc USB30_GDSC>;
425 qcom,select-utmi-as-pipe-clk;
426
427 dwc3@f9200000 {
428 compatible = "snps,dwc3";
429 reg = <0xf9200000 0xcc00>;
430 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
431 snps,dis_u2_susphy_quirk;
432 snps,dis_enblslpm_quirk;
433 maximum-speed = "high-speed";
434 dr_mode = "peripheral";
435 };
436 };
437
448d9c22
KD		 438 sdhc1: sdhci@f9824900 {
439 compatible = "qcom,sdhci-msm-v4";
440 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
441 reg-names = "hc_mem", "core_mem";
442
443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "hc_irq", "pwr_irq";
446
447 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
448 <&gcc GCC_SDCC1_AHB_CLK>,
449 <&xo_board>;
450 clock-names = "core", "iface", "xo";
451
452 pinctrl-names = "default", "sleep";
453 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
454 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
455
456 bus-width = <8>;
457 non-removable;
458 status = "disabled";
459 };
460
f3d1939f
KD		 461 sdhc2: sdhci@f98a4900 {
462 compatible = "qcom,sdhci-msm-v4";
463 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
464 reg-names = "hc_mem", "core_mem";
465
466 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
468 interrupt-names = "hc_irq", "pwr_irq";
469
470 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
471 <&gcc GCC_SDCC2_AHB_CLK>,
472 <&xo_board>;
473 clock-names = "core", "iface", "xo";
474
475 pinctrl-names = "default", "sleep";
476 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
477 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
478
479 cd-gpios = <&tlmm 100 0>;
480 bus-width = <4>;
481 status = "disabled";
482 };
483
828896c5 484 blsp1_dma: dma-controller@f9904000 {
d3d071a0
KD		 485 compatible = "qcom,bam-v1.7.0";
486 reg = <0xf9904000 0x19000>;
487 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
489 clock-names = "bam_clk";
490 #dma-cells = <1>;
491 qcom,ee = <0>;
492 qcom,controlled-remotely;
493 num-channels = <18>;
494 qcom,num-ees = <4>;
495 };
496
7c865b09
KD		 497 blsp1_uart2: serial@f991e000 {
498 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
499 reg = <0xf991e000 0x1000>;
500 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
7c865b09
KD		 501 clock-names = "core", "iface";
502 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
503 <&gcc GCC_BLSP1_AHB_CLK>;
d3d071a0
KD		 504 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&blsp1_uart2_default>;
506 pinctrl-1 = <&blsp1_uart2_sleep>;
507 status = "disabled";
508 };
509
e093d1a2 510 blsp1_i2c1: i2c@f9923000 {
d3d071a0
KD		 511 compatible = "qcom,i2c-qup-v2.2.1";
512 reg = <0xf9923000 0x500>;
513 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
515 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
516 clock-names = "iface", "core";
517 clock-frequency = <400000>;
e093d1a2
GM		 518 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
519 dma-names = "tx", "rx";
d3d071a0
KD		 520 pinctrl-names = "default", "sleep";
521 pinctrl-0 = <&i2c1_default>;
522 pinctrl-1 = <&i2c1_sleep>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 status = "disabled";
526 };
527
e093d1a2 528 blsp1_spi1: spi@f9923000 {
d3d071a0
KD		 529 compatible = "qcom,spi-qup-v2.2.1";
530 reg = <0xf9923000 0x500>;
531 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
533 <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", "iface";
535 spi-max-frequency = <19200000>;
536 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
537 dma-names = "tx", "rx";
538 pinctrl-names = "default", "sleep";
e093d1a2
GM		 539 pinctrl-0 = <&blsp1_spi1_default>;
540 pinctrl-1 = <&blsp1_spi1_sleep>;
d3d071a0
KD		 541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
545
e093d1a2 546 blsp1_i2c2: i2c@f9924000 {
d3d071a0
KD		 547 compatible = "qcom,i2c-qup-v2.2.1";
548 reg = <0xf9924000 0x500>;
549 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
551 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
552 clock-names = "iface", "core";
e093d1a2 553 clock-frequency = <400000>;
d3d071a0
KD		 554 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
555 dma-names = "tx", "rx";
556 pinctrl-names = "default", "sleep";
557 pinctrl-0 = <&i2c2_default>;
558 pinctrl-1 = <&i2c2_sleep>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 status = "disabled";
562 };
563
564 /* I2C3 doesn't exist */
565
e093d1a2 566 blsp1_i2c4: i2c@f9926000 {
d3d071a0
KD		 567 compatible = "qcom,i2c-qup-v2.2.1";
568 reg = <0xf9926000 0x500>;
569 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
571 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
572 clock-names = "iface", "core";
e093d1a2
GM		 573 clock-frequency = <400000>;
574 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
575 dma-names = "tx", "rx";
d3d071a0
KD		 576 pinctrl-names = "default", "sleep";
577 pinctrl-0 = <&i2c4_default>;
578 pinctrl-1 = <&i2c4_sleep>;
579 #address-cells = <1>;
580 #size-cells = <0>;
581 status = "disabled";
582 };
583
e093d1a2
GM		 584 blsp1_i2c5: i2c@f9927000 {
585 compatible = "qcom,i2c-qup-v2.2.1";
586 reg = <0xf9927000 0x500>;
587 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
589 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
590 clock-names = "iface", "core";
591 clock-frequency = <400000>;
592 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
593 dma-names = "tx", "rx";
594 pinctrl-names = "default", "sleep";
595 pinctrl-0 = <&i2c5_default>;
596 pinctrl-1 = <&i2c5_sleep>;
597 #address-cells = <1>;
598 #size-cells = <0>;
599 status = "disabled";
d3d071a0
KD		 600 };
601
e093d1a2 602 blsp1_i2c6: i2c@f9928000 {
d3d071a0
KD		 603 compatible = "qcom,i2c-qup-v2.2.1";
604 reg = <0xf9928000 0x500>;
605 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
607 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
608 clock-names = "iface", "core";
e093d1a2 609 clock-frequency = <400000>;
d3d071a0
KD		 610 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
611 dma-names = "tx", "rx";
612 pinctrl-names = "default", "sleep";
613 pinctrl-0 = <&i2c6_default>;
614 pinctrl-1 = <&i2c6_sleep>;
615 #address-cells = <1>;
616 #size-cells = <0>;
617 status = "disabled";
618 };
619
e093d1a2
GM		 620 blsp2_dma: dma-controller@f9944000 {
621 compatible = "qcom,bam-v1.7.0";
622 reg = <0xf9944000 0x19000>;
623 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
625 clock-names = "bam_clk";
626 #dma-cells = <1>;
627 qcom,ee = <0>;
628 qcom,controlled-remotely;
629 num-channels = <18>;
630 qcom,num-ees = <4>;
631 };
632
d3d071a0
KD		 633 blsp2_uart2: serial@f995e000 {
634 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
635 reg = <0xf995e000 0x1000>;
a046032c 636 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
d3d071a0
KD		 637 clock-names = "core", "iface";
638 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
639 <&gcc GCC_BLSP2_AHB_CLK>;
640 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
641 dma-names = "tx", "rx";
642 pinctrl-names = "default", "sleep";
643 pinctrl-0 = <&blsp2_uart2_default>;
644 pinctrl-1 = <&blsp2_uart2_sleep>;
645 status = "disabled";
646 };
647
e093d1a2
GM		 648 blsp2_i2c1: i2c@f9963000 {
649 compatible = "qcom,i2c-qup-v2.2.1";
650 reg = <0xf9963000 0x500>;
651 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
653 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
654 clock-names = "iface", "core";
655 clock-frequency = <400000>;
656 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
657 dma-names = "tx", "rx";
658 pinctrl-names = "default", "sleep";
659 pinctrl-0 = <&i2c7_default>;
660 pinctrl-1 = <&i2c7_sleep>;
661 #address-cells = <1>;
662 #size-cells = <0>;
663 status = "disabled";
664 };
665
666 blsp2_spi4: spi@f9966000 {
667 compatible = "qcom,spi-qup-v2.2.1";
668 reg = <0xf9966000 0x500>;
669 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
671 <&gcc GCC_BLSP2_AHB_CLK>;
672 clock-names = "core", "iface";
673 spi-max-frequency = <19200000>;
674 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
675 dma-names = "tx", "rx";
676 pinctrl-names = "default", "sleep";
677 pinctrl-0 = <&blsp2_spi10_default>;
678 pinctrl-1 = <&blsp2_spi10_sleep>;
679 #address-cells = <1>;
680 #size-cells = <0>;
681 status = "disabled";
682 };
683
684 blsp2_i2c5: i2c@f9967000 {
d3d071a0
KD		 685 compatible = "qcom,i2c-qup-v2.2.1";
686 reg = <0xf9967000 0x500>;
687 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
689 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
690 clock-names = "iface", "core";
691 clock-frequency = <355000>;
692 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
693 dma-names = "tx", "rx";
694 pinctrl-names = "default", "sleep";
e093d1a2
GM		 695 pinctrl-0 = <&i2c11_default>;
696 pinctrl-1 = <&i2c11_sleep>;
d3d071a0
KD		 697 #address-cells = <1>;
698 #size-cells = <0>;
699 status = "disabled";
7c865b09
KD		 700 };
701
702 gcc: clock-controller@fc400000 {
703 compatible = "qcom,gcc-msm8994";
704 #clock-cells = <1>;
705 #reset-cells = <1>;
706 #power-domain-cells = <1>;
707 reg = <0xfc400000 0x2000>;
708 };
709
01104518
KD		 710 rpm_msg_ram: memory@fc428000 {
711 compatible = "qcom,rpm-msg-ram";
712 reg = <0xfc428000 0x4000>;
713 };
714
feeaf56a
BK		 715 restart@fc4ab000 {
716 compatible = "qcom,pshold";
717 reg = <0xfc4ab000 0x4>;
718 };
719
b0ad598f
KD		 720 spmi_bus: spmi@fc4c0000 {
721 compatible = "qcom,spmi-pmic-arb";
722 reg = <0xfc4cf000 0x1000>,
723 <0xfc4cb000 0x1000>,
724 <0xfc4ca000 0x1000>;
725 reg-names = "core", "intr", "cnfg";
726 interrupt-names = "periph_irq";
727 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
728 qcom,ee = <0>;
729 qcom,channel = <0>;
730 #address-cells = <2>;
731 #size-cells = <0>;
732 interrupt-controller;
733 #interrupt-cells = <4>;
734 };
735
7c865b09
KD		 736 tcsr_mutex_regs: syscon@fd484000 {
737 compatible = "syscon";
738 reg = <0xfd484000 0x2000>;
739 };
740
741 tlmm: pinctrl@fd510000 {
feeaf56a
BK		 742 compatible = "qcom,msm8994-pinctrl";
743 reg = <0xfd510000 0x4000>;
744 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
745 gpio-controller;
7c865b09 746 gpio-ranges = <&tlmm 0 0 146>;
feeaf56a
BK		 747 #gpio-cells = <2>;
748 interrupt-controller;
749 #interrupt-cells = <2>;
feeaf56a 750
7c865b09
KD		 751 blsp1_uart2_default: blsp1-uart2-default {
752 function = "blsp_uart2";
753 pins = "gpio4", "gpio5";
754 drive-strength = <16>;
755 bias-disable;
756 };
feeaf56a 757
7c865b09
KD		 758 blsp1_uart2_sleep: blsp1-uart2-sleep {
759 function = "gpio";
760 pins = "gpio4", "gpio5";
761 drive-strength = <2>;
762 bias-pull-down;
763 };
feeaf56a 764
7c865b09
KD		 765 blsp2_uart2_default: blsp2-uart2-default {
766 function = "blsp_uart8";
a046032c
KD		 767 pins = "gpio45", "gpio46",
768 "gpio47", "gpio48";
769 drive-strength = <16>;
7c865b09
KD		 770 bias-disable;
771 };
feeaf56a 772
7c865b09
KD		 773 blsp2_uart2_sleep: blsp2-uart2-sleep {
774 function = "gpio";
a046032c
KD		 775 pins = "gpio45", "gpio46",
776 "gpio47", "gpio48";
7c865b09 777 drive-strength = <2>;
a046032c 778 bias-disable;
7c865b09 779 };
feeaf56a 780
7c865b09
KD		 781 i2c1_default: i2c1-default {
782 function = "blsp_i2c1";
783 pins = "gpio2", "gpio3";
784 drive-strength = <2>;
785 bias-disable;
786 };
feeaf56a 787
7c865b09
KD		 788 i2c1_sleep: i2c1-sleep {
789 function = "gpio";
790 pins = "gpio2", "gpio3";
791 drive-strength = <2>;
792 bias-disable;
793 };
feeaf56a 794
7c865b09
KD		 795 i2c2_default: i2c2-default {
796 function = "blsp_i2c2";
797 pins = "gpio6", "gpio7";
798 drive-strength = <2>;
799 bias-disable;
800 };
feeaf56a 801
7c865b09
KD		 802 i2c2_sleep: i2c2-sleep {
803 function = "gpio";
804 pins = "gpio6", "gpio7";
805 drive-strength = <2>;
806 bias-disable;
807 };
808
809 i2c4_default: i2c4-default {
810 function = "blsp_i2c4";
811 pins = "gpio19", "gpio20";
812 drive-strength = <2>;
813 bias-disable;
814 };
815
816 i2c4_sleep: i2c4-sleep {
817 function = "gpio";
818 pins = "gpio19", "gpio20";
819 drive-strength = <2>;
820 bias-pull-down;
821 input-enable;
822 };
823
824 i2c5_default: i2c5-default {
825 function = "blsp_i2c5";
826 pins = "gpio23", "gpio24";
827 drive-strength = <2>;
828 bias-disable;
829 };
830
831 i2c5_sleep: i2c5-sleep {
832 function = "gpio";
833 pins = "gpio23", "gpio24";
834 drive-strength = <2>;
835 bias-disable;
836 };
837
838 i2c6_default: i2c6-default {
839 function = "blsp_i2c6";
840 pins = "gpio28", "gpio27";
841 drive-strength = <2>;
842 bias-disable;
843 };
844
845 i2c6_sleep: i2c6-sleep {
846 function = "gpio";
847 pins = "gpio28", "gpio27";
848 drive-strength = <2>;
849 bias-disable;
850 };
851
e093d1a2
GM		 852 i2c7_default: i2c7-default {
853 function = "blsp_i2c7";
854 pins = "gpio44", "gpio43";
855 drive-strength = <2>;
856 bias-disable;
857 };
858
859 i2c7_sleep: i2c7-sleep {
860 function = "gpio";
861 pins = "gpio44", "gpio43";
862 drive-strength = <2>;
863 bias-disable;
864 };
865
866 blsp2_spi10_default: blsp2-spi10-default {
867 default {
868 function = "blsp_spi10";
869 pins = "gpio53", "gpio54", "gpio55";
870 drive-strength = <10>;
871 bias-pull-down;
872 };
873 cs {
874 function = "gpio";
875 pins = "gpio55";
876 drive-strength = <2>;
877 bias-disable;
878 };
879 };
880
881 blsp2_spi10_sleep: blsp2-spi10-sleep {
882 pins = "gpio53", "gpio54", "gpio55";
883 drive-strength = <2>;
884 bias-disable;
885 };
886
887 i2c11_default: i2c11-default {
888 function = "blsp_i2c11";
889 pins = "gpio83", "gpio84";
890 drive-strength = <2>;
891 bias-disable;
892 };
893
894 i2c11_sleep: i2c11-sleep {
895 function = "gpio";
896 pins = "gpio83", "gpio84";
897 drive-strength = <2>;
898 bias-disable;
899 };
900
901 blsp1_spi1_default: blsp1-spi1-default {
7c865b09
KD		 902 default {
903 function = "blsp_spi1";
904 pins = "gpio0", "gpio1", "gpio3";
905 drive-strength = <10>;
906 bias-pull-down;
907 };
908 cs {
909 function = "gpio";
910 pins = "gpio8";
911 drive-strength = <2>;
912 bias-disable;
913 };
914 };
915
e093d1a2 916 blsp1_spi1_sleep: blsp1-spi1-sleep {
7c865b09
KD		 917 pins = "gpio0", "gpio1", "gpio3";
918 drive-strength = <2>;
919 bias-disable;
920 };
921
922 sdc1_clk_on: clk-on {
923 pins = "sdc1_clk";
924 bias-disable;
925 drive-strength = <16>;
926 };
927
928 sdc1_clk_off: clk-off {
929 pins = "sdc1_clk";
930 bias-disable;
931 drive-strength = <2>;
932 };
933
934 sdc1_cmd_on: cmd-on {
935 pins = "sdc1_cmd";
936 bias-pull-up;
937 drive-strength = <8>;
938 };
939
940 sdc1_cmd_off: cmd-off {
941 pins = "sdc1_cmd";
942 bias-pull-up;
943 drive-strength = <2>;
944 };
945
946 sdc1_data_on: data-on {
947 pins = "sdc1_data";
948 bias-pull-up;
949 drive-strength = <8>;
950 };
951
952 sdc1_data_off: data-off {
953 pins = "sdc1_data";
954 bias-pull-up;
955 drive-strength = <2>;
956 };
957
958 sdc1_rclk_on: rclk-on {
959 pins = "sdc1_rclk";
960 bias-pull-down;
961 };
962
963 sdc1_rclk_off: rclk-off {
964 pins = "sdc1_rclk";
965 bias-pull-down;
966 };
f3d1939f
KD		 967
968 sdc2_clk_on: sdc2-clk-on {
969 pins = "sdc2_clk";
970 bias-disable;
971 drive-strength = <10>;
972 };
973
974 sdc2_clk_off: sdc2-clk-off {
975 pins = "sdc2_clk";
976 bias-disable;
977 drive-strength = <2>;
978 };
979
980 sdc2_cmd_on: sdc2-cmd-on {
981 pins = "sdc2_cmd";
982 bias-pull-up;
983 drive-strength = <10>;
984 };
985
986 sdc2_cmd_off: sdc2-cmd-off {
987 pins = "sdc2_cmd";
988 bias-pull-up;
989 drive-strength = <2>;
990 };
991
992 sdc2_data_on: sdc2-data-on {
993 pins = "sdc2_data";
994 bias-pull-up;
995 drive-strength = <10>;
996 };
997
998 sdc2_data_off: sdc2-data-off {
999 pins = "sdc2_data";
1000 bias-pull-up;
1001 drive-strength = <2>;
1002 };
feeaf56a
BK		 1003 };
1004 };
1005
1006 tcsr_mutex: hwlock {
1007 compatible = "qcom,tcsr-mutex";
1008 syscon = <&tcsr_mutex_regs 0 0x80>;
1009 #hwlock-cells = <1>;
1010 };
1011
7c865b09
KD		 1012 timer {
1013 compatible = "arm,armv8-timer";
1014 interrupts = <GIC_PPI 2 0xff08>,
1015 <GIC_PPI 3 0xff08>,
1016 <GIC_PPI 4 0xff08>,
1017 <GIC_PPI 1 0xff08>;
feeaf56a 1018 };
01104518 1019
53364cfc 1020 vph_pwr: vph-pwr-regulator {
01104518 1021 compatible = "regulator-fixed";
53364cfc 1022 regulator-name = "vph_pwr";
01104518
KD		 1023
1024 regulator-min-microvolt = <3600000>;
1025 regulator-max-microvolt = <3600000>;
1026
1027 regulator-always-on;
1028 };
feeaf56a
BK		 1029};
1030
Linux 6.x block layer and io_uring tree(s)