projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| feeaf56a | 2 | /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
| feeaf56a BK |
3 | */ |
| 4 | ||
| 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 6 | #include <dt-bindings/clock/qcom,gcc-msm8994.h> | |
| e9b0eb54 KD |
7 | #include <dt-bindings/clock/qcom,mmcc-msm8994.h> |
| 8 | #include <dt-bindings/clock/qcom,rpmcc.h> | |
| 0f7273c3 | 9 | #include <dt-bindings/power/qcom-rpmpd.h> |
| feeaf56a BK |
10 | |
| 11 | / { | |
| feeaf56a BK |
12 | interrupt-parent = <&intc>; |
| 13 | ||
| 14 | #address-cells = <2>; | |
| 15 | #size-cells = <2>; | |
| 16 | ||
| d8023f3a KD |
17 | aliases { |
| 18 | mmc1 = &sdhc1; | |
| 19 | mmc2 = &sdhc2; | |
| 20 | }; | |
| 21 | ||
| feeaf56a BK |
22 | chosen { }; |
| 23 | ||
| 7c865b09 | 24 | clocks { |
| 8c678bec | 25 | xo_board: xo-board { |
| 7c865b09 KD |
26 | compatible = "fixed-clock"; |
| 27 | #clock-cells = <0>; | |
| 28 | clock-frequency = <19200000>; | |
| 8c678bec | 29 | clock-output-names = "xo_board"; |
| 7c865b09 KD |
30 | }; |
| 31 | ||
| 8c678bec | 32 | sleep_clk: sleep-clk { |
| 7c865b09 KD |
33 | compatible = "fixed-clock"; |
| 34 | #clock-cells = <0>; | |
| 35 | clock-frequency = <32768>; | |
| 8c678bec | 36 | clock-output-names = "sleep_clk"; |
| 7c865b09 KD |
37 | }; |
| 38 | }; | |
| 39 | ||
| feeaf56a | 40 | cpus { |
| 02d8091b | 41 | #address-cells = <2>; |
| feeaf56a | 42 | #size-cells = <0>; |
| 02d8091b KD |
43 | |
| 44 | CPU0: cpu@0 { | |
| 45 | device_type = "cpu"; | |
| 46 | compatible = "arm,cortex-a53"; | |
| 47 | reg = <0x0 0x0>; | |
| 48 | enable-method = "psci"; | |
| 49 | next-level-cache = <&L2_0>; | |
| 50 | L2_0: l2-cache { | |
| 51 | compatible = "cache"; | |
| 52 | cache-level = <2>; | |
| 53 | }; | |
| 54 | }; | |
| 55 | ||
| 56 | CPU1: cpu@1 { | |
| 57 | device_type = "cpu"; | |
| 58 | compatible = "arm,cortex-a53"; | |
| 59 | reg = <0x0 0x1>; | |
| 60 | enable-method = "psci"; | |
| 61 | next-level-cache = <&L2_0>; | |
| 62 | }; | |
| 63 | ||
| 64 | CPU2: cpu@2 { | |
| 65 | device_type = "cpu"; | |
| 66 | compatible = "arm,cortex-a53"; | |
| 67 | reg = <0x0 0x2>; | |
| 68 | enable-method = "psci"; | |
| 69 | next-level-cache = <&L2_0>; | |
| 70 | }; | |
| 71 | ||
| 72 | CPU3: cpu@3 { | |
| 73 | device_type = "cpu"; | |
| 74 | compatible = "arm,cortex-a53"; | |
| 75 | reg = <0x0 0x3>; | |
| 76 | enable-method = "psci"; | |
| 77 | next-level-cache = <&L2_0>; | |
| 78 | }; | |
| 79 | ||
| 80 | CPU4: cpu@100 { | |
| 81 | device_type = "cpu"; | |
| 82 | compatible = "arm,cortex-a57"; | |
| 83 | reg = <0x0 0x100>; | |
| 84 | enable-method = "psci"; | |
| 85 | next-level-cache = <&L2_1>; | |
| 86 | L2_1: l2-cache { | |
| 87 | compatible = "cache"; | |
| 88 | cache-level = <2>; | |
| 89 | }; | |
| 90 | }; | |
| 91 | ||
| 92 | CPU5: cpu@101 { | |
| 93 | device_type = "cpu"; | |
| 94 | compatible = "arm,cortex-a57"; | |
| 95 | reg = <0x0 0x101>; | |
| 96 | enable-method = "psci"; | |
| 97 | next-level-cache = <&L2_1>; | |
| 98 | }; | |
| 99 | ||
| 100 | CPU6: cpu@102 { | |
| 101 | device_type = "cpu"; | |
| 102 | compatible = "arm,cortex-a57"; | |
| 103 | reg = <0x0 0x101>; | |
| 104 | enable-method = "psci"; | |
| 105 | next-level-cache = <&L2_1>; | |
| 106 | }; | |
| 107 | ||
| 108 | CPU7: cpu@103 { | |
| 109 | device_type = "cpu"; | |
| 110 | compatible = "arm,cortex-a57"; | |
| 111 | reg = <0x0 0x101>; | |
| 112 | enable-method = "psci"; | |
| 113 | next-level-cache = <&L2_1>; | |
| 114 | }; | |
| 115 | ||
| feeaf56a BK |
116 | cpu-map { |
| 117 | cluster0 { | |
| 118 | core0 { | |
| 119 | cpu = <&CPU0>; | |
| 120 | }; | |
| 02d8091b KD |
121 | |
| 122 | core1 { | |
| 123 | cpu = <&CPU1>; | |
| 124 | }; | |
| 125 | ||
| 126 | core2 { | |
| 127 | cpu = <&CPU2>; | |
| 128 | }; | |
| 129 | ||
| 130 | core3 { | |
| 131 | cpu = <&CPU3>; | |
| 132 | }; | |
| feeaf56a | 133 | }; |
| feeaf56a | 134 | |
| 02d8091b KD |
135 | cluster1 { |
| 136 | core0 { | |
| 137 | cpu = <&CPU4>; | |
| 138 | }; | |
| 139 | ||
| 140 | core1 { | |
| 141 | cpu = <&CPU5>; | |
| 142 | }; | |
| 143 | ||
| 976d321f | 144 | cpu6_map: core2 { |
| 02d8091b KD |
145 | cpu = <&CPU6>; |
| 146 | }; | |
| 147 | ||
| 976d321f | 148 | cpu7_map: core3 { |
| 02d8091b KD |
149 | cpu = <&CPU7>; |
| 150 | }; | |
| feeaf56a BK |
151 | }; |
| 152 | }; | |
| 153 | }; | |
| 154 | ||
| e4faf75d KD |
155 | firmware { |
| 156 | scm { | |
| 157 | compatible = "qcom,scm-msm8994", "qcom,scm"; | |
| 158 | }; | |
| 159 | }; | |
| 160 | ||
| c0dffc3f | 161 | memory@80000000 { |
| 7c865b09 KD |
162 | device_type = "memory"; |
| 163 | /* We expect the bootloader to fill in the reg */ | |
| c0dffc3f | 164 | reg = <0 0x80000000 0 0>; |
| 7c865b09 KD |
165 | }; |
| 166 | ||
| 76d0b35c KD |
167 | tcsr_mutex: hwlock { |
| 168 | compatible = "qcom,tcsr-mutex"; | |
| 169 | syscon = <&tcsr_mutex_regs 0 0x80>; | |
| 170 | #hwlock-cells = <1>; | |
| 171 | }; | |
| 172 | ||
| a1026ca2 KD |
173 | pmu { |
| 174 | compatible = "arm,cortex-a53-pmu"; | |
| 175 | interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; | |
| 176 | }; | |
| 177 | ||
| c21e7c06 KD |
178 | psci { |
| 179 | compatible = "arm,psci-0.2"; | |
| 180 | method = "hvc"; | |
| 181 | }; | |
| 182 | ||
| 7c865b09 KD |
183 | reserved-memory { |
| 184 | #address-cells = <2>; | |
| 185 | #size-cells = <2>; | |
| 186 | ranges; | |
| 187 | ||
| 74d6d0a1 KD |
188 | dfps_data_mem: dfps_data_mem@3400000 { |
| 189 | reg = <0 0x03400000 0 0x1000>; | |
| 190 | no-map; | |
| 191 | }; | |
| 192 | ||
| 049c46f3 KD |
193 | cont_splash_mem: memory@3401000 { |
| 194 | reg = <0 0x03401000 0 0x2200000>; | |
| 74d6d0a1 KD |
195 | no-map; |
| 196 | }; | |
| 197 | ||
| 7c865b09 | 198 | smem_mem: smem_region@6a00000 { |
| 74d6d0a1 KD |
199 | reg = <0 0x06a00000 0 0x200000>; |
| 200 | no-map; | |
| 201 | }; | |
| 202 | ||
| 203 | mpss_mem: memory@7000000 { | |
| 204 | reg = <0 0x07000000 0 0x5a00000>; | |
| 205 | no-map; | |
| 206 | }; | |
| 207 | ||
| 208 | peripheral_region: memory@ca00000 { | |
| 209 | reg = <0 0x0ca00000 0 0x1f00000>; | |
| 210 | no-map; | |
| 211 | }; | |
| 212 | ||
| 213 | rmtfs_mem: memory@c6400000 { | |
| 214 | compatible = "qcom,rmtfs-mem"; | |
| 215 | reg = <0 0xc6400000 0 0x180000>; | |
| 216 | no-map; | |
| 217 | ||
| 218 | qcom,client-id = <1>; | |
| 219 | }; | |
| 220 | ||
| 221 | mba_mem: memory@c6700000 { | |
| 222 | reg = <0 0xc6700000 0 0x100000>; | |
| 223 | no-map; | |
| 224 | }; | |
| 225 | ||
| 226 | audio_mem: memory@c7000000 { | |
| 227 | reg = <0 0xc7000000 0 0x800000>; | |
| 228 | no-map; | |
| 229 | }; | |
| 230 | ||
| 231 | adsp_mem: memory@c9400000 { | |
| 232 | reg = <0 0xc9400000 0 0x3f00000>; | |
| 7c865b09 KD |
233 | no-map; |
| 234 | }; | |
| 235 | }; | |
| 236 | ||
| 01104518 KD |
237 | smd { |
| 238 | compatible = "qcom,smd"; | |
| 239 | rpm { | |
| 240 | interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; | |
| 241 | qcom,ipc = <&apcs 8 0>; | |
| 242 | qcom,smd-edge = <15>; | |
| 01104518 KD |
243 | qcom,remote-pid = <6>; |
| 244 | ||
| 245 | rpm_requests: rpm-requests { | |
| 246 | compatible = "qcom,rpm-msm8994"; | |
| 247 | qcom,smd-channels = "rpm_requests"; | |
| 248 | ||
| 249 | rpmcc: rpmcc { | |
| 812b0b61 | 250 | compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; |
| 01104518 KD |
251 | #clock-cells = <1>; |
| 252 | }; | |
| 0f7273c3 KD |
253 | |
| 254 | rpmpd: power-controller { | |
| 255 | compatible = "qcom,msm8994-rpmpd"; | |
| 256 | #power-domain-cells = <1>; | |
| 257 | operating-points-v2 = <&rpmpd_opp_table>; | |
| 258 | ||
| 259 | rpmpd_opp_table: opp-table { | |
| 260 | compatible = "operating-points-v2"; | |
| 261 | ||
| 262 | rpmpd_opp_ret: opp1 { | |
| 263 | opp-level = <1>; | |
| 264 | }; | |
| 265 | rpmpd_opp_svs_krait: opp2 { | |
| 266 | opp-level = <2>; | |
| 267 | }; | |
| 268 | rpmpd_opp_svs_soc: opp3 { | |
| 269 | opp-level = <3>; | |
| 270 | }; | |
| 271 | rpmpd_opp_nom: opp4 { | |
| 272 | opp-level = <4>; | |
| 273 | }; | |
| 274 | rpmpd_opp_turbo: opp5 { | |
| 275 | opp-level = <5>; | |
| 276 | }; | |
| 277 | rpmpd_opp_super_turbo: opp6 { | |
| 278 | opp-level = <6>; | |
| 279 | }; | |
| 280 | }; | |
| 281 | }; | |
| 01104518 KD |
282 | }; |
| 283 | }; | |
| 284 | }; | |
| 285 | ||
| 7c865b09 KD |
286 | smem { |
| 287 | compatible = "qcom,smem"; | |
| 288 | memory-region = <&smem_mem>; | |
| 01104518 | 289 | qcom,rpm-msg-ram = <&rpm_msg_ram>; |
| 7c865b09 | 290 | hwlocks = <&tcsr_mutex 3>; |
| feeaf56a BK |
291 | }; |
| 292 | ||
| 886ddcfe KD |
293 | smp2p-lpass { |
| 294 | compatible = "qcom,smp2p"; | |
| 295 | qcom,smem = <443>, <429>; | |
| 296 | ||
| 297 | interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; | |
| 298 | ||
| 299 | qcom,ipc = <&apcs 8 10>; | |
| 300 | ||
| 301 | qcom,local-pid = <0>; | |
| 302 | qcom,remote-pid = <2>; | |
| 303 | ||
| 304 | adsp_smp2p_out: master-kernel { | |
| 305 | qcom,entry-name = "master-kernel"; | |
| 306 | #qcom,smem-state-cells = <1>; | |
| 307 | }; | |
| 308 | ||
| 309 | adsp_smp2p_in: slave-kernel { | |
| 310 | qcom,entry-name = "slave-kernel"; | |
| 311 | ||
| 312 | interrupt-controller; | |
| 313 | #interrupt-cells = <2>; | |
| 314 | }; | |
| 315 | }; | |
| 316 | ||
| 317 | smp2p-modem { | |
| 318 | compatible = "qcom,smp2p"; | |
| 319 | qcom,smem = <435>, <428>; | |
| 320 | ||
| 321 | interrupt-parent = <&intc>; | |
| 322 | interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; | |
| 323 | ||
| 324 | qcom,ipc = <&apcs 8 14>; | |
| 325 | ||
| 326 | qcom,local-pid = <0>; | |
| 327 | qcom,remote-pid = <1>; | |
| 328 | ||
| 329 | modem_smp2p_out: master-kernel { | |
| 330 | qcom,entry-name = "master-kernel"; | |
| 331 | #qcom,smem-state-cells = <1>; | |
| 332 | }; | |
| 333 | ||
| 334 | modem_smp2p_in: slave-kernel { | |
| 335 | qcom,entry-name = "slave-kernel"; | |
| 336 | ||
| 337 | interrupt-controller; | |
| 338 | #interrupt-cells = <2>; | |
| 339 | }; | |
| 340 | }; | |
| 341 | ||
| feeaf56a BK |
342 | soc: soc { |
| 343 | ||
| 344 | #address-cells = <1>; | |
| 345 | #size-cells = <1>; | |
| 346 | ranges = <0 0 0 0xffffffff>; | |
| 347 | compatible = "simple-bus"; | |
| 348 | ||
| 349 | intc: interrupt-controller@f9000000 { | |
| 350 | compatible = "qcom,msm-qgic2"; | |
| 351 | interrupt-controller; | |
| 352 | #interrupt-cells = <3>; | |
| 353 | reg = <0xf9000000 0x1000>, | |
| 7c865b09 | 354 | <0xf9002000 0x1000>; |
| feeaf56a BK |
355 | }; |
| 356 | ||
| 01104518 KD |
357 | apcs: mailbox@f900d000 { |
| 358 | compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; | |
| 359 | reg = <0xf900d000 0x2000>; | |
| 360 | #mbox-cells = <1>; | |
| 361 | }; | |
| 362 | ||
| e0be93fb KD |
363 | watchdog@f9017000 { |
| 364 | compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; | |
| 365 | reg = <0xf9017000 0x1000>; | |
| 366 | interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, | |
| 367 | <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; | |
| 368 | clocks = <&sleep_clk>; | |
| 369 | timeout-sec = <10>; | |
| 370 | }; | |
| 371 | ||
| feeaf56a BK |
372 | timer@f9020000 { |
| 373 | #address-cells = <1>; | |
| 374 | #size-cells = <1>; | |
| 375 | ranges; | |
| 376 | compatible = "arm,armv7-timer-mem"; | |
| 377 | reg = <0xf9020000 0x1000>; | |
| 378 | ||
| 379 | frame@f9021000 { | |
| 380 | frame-number = <0>; | |
| 381 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
| 382 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 383 | reg = <0xf9021000 0x1000>, | |
| 384 | <0xf9022000 0x1000>; | |
| 385 | }; | |
| 386 | ||
| 387 | frame@f9023000 { | |
| 388 | frame-number = <1>; | |
| 389 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 390 | reg = <0xf9023000 0x1000>; | |
| 391 | status = "disabled"; | |
| 392 | }; | |
| 393 | ||
| 394 | frame@f9024000 { | |
| 395 | frame-number = <2>; | |
| 396 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 397 | reg = <0xf9024000 0x1000>; | |
| 398 | status = "disabled"; | |
| 399 | }; | |
| 400 | ||
| 401 | frame@f9025000 { | |
| 402 | frame-number = <3>; | |
| 403 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 404 | reg = <0xf9025000 0x1000>; | |
| 405 | status = "disabled"; | |
| 406 | }; | |
| 407 | ||
| 408 | frame@f9026000 { | |
| 409 | frame-number = <4>; | |
| 410 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| 411 | reg = <0xf9026000 0x1000>; | |
| 412 | status = "disabled"; | |
| 413 | }; | |
| 414 | ||
| 415 | frame@f9027000 { | |
| 416 | frame-number = <5>; | |
| 417 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 418 | reg = <0xf9027000 0x1000>; | |
| 419 | status = "disabled"; | |
| 420 | }; | |
| 421 | ||
| 422 | frame@f9028000 { | |
| 423 | frame-number = <6>; | |
| 424 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
| 425 | reg = <0xf9028000 0x1000>; | |
| 426 | status = "disabled"; | |
| 427 | }; | |
| 428 | }; | |
| 429 | ||
| d9be0bc9 | 430 | usb3: usb@f92f8800 { |
| b7f1528e | 431 | compatible = "qcom,msm8994-dwc3", "qcom,dwc3"; |
| d9be0bc9 KD |
432 | reg = <0xf92f8800 0x400>; |
| 433 | #address-cells = <1>; | |
| 434 | #size-cells = <1>; | |
| 435 | ranges; | |
| 436 | ||
| 437 | clocks = <&gcc GCC_USB30_MASTER_CLK>, | |
| 438 | <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, | |
| 439 | <&gcc GCC_USB30_SLEEP_CLK>, | |
| 440 | <&gcc GCC_USB30_MOCK_UTMI_CLK>; | |
| 8d5fd4e4 KK |
441 | clock-names = "core", |
| 442 | "iface", | |
| 443 | "sleep", | |
| 444 | "mock_utmi"; | |
| d9be0bc9 KD |
445 | |
| 446 | assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, | |
| 447 | <&gcc GCC_USB30_MASTER_CLK>; | |
| 448 | assigned-clock-rates = <19200000>, <120000000>; | |
| 449 | ||
| 450 | power-domains = <&gcc USB30_GDSC>; | |
| 451 | qcom,select-utmi-as-pipe-clk; | |
| 452 | ||
| 2aa2b50d | 453 | usb@f9200000 { |
| d9be0bc9 KD |
454 | compatible = "snps,dwc3"; |
| 455 | reg = <0xf9200000 0xcc00>; | |
| 456 | interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; | |
| 457 | snps,dis_u2_susphy_quirk; | |
| 458 | snps,dis_enblslpm_quirk; | |
| 459 | maximum-speed = "high-speed"; | |
| 460 | dr_mode = "peripheral"; | |
| 461 | }; | |
| 462 | }; | |
| 463 | ||
| 448d9c22 | 464 | sdhc1: sdhci@f9824900 { |
| 4ec48ebf | 465 | compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; |
| 448d9c22 KD |
466 | reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; |
| 467 | reg-names = "hc_mem", "core_mem"; | |
| 468 | ||
| 469 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
| 470 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
| 471 | interrupt-names = "hc_irq", "pwr_irq"; | |
| 472 | ||
| 473 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, | |
| 474 | <&gcc GCC_SDCC1_AHB_CLK>, | |
| 475 | <&xo_board>; | |
| 476 | clock-names = "core", "iface", "xo"; | |
| 477 | ||
| 478 | pinctrl-names = "default", "sleep"; | |
| 479 | pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; | |
| 480 | pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; | |
| 481 | ||
| 482 | bus-width = <8>; | |
| 483 | non-removable; | |
| 484 | status = "disabled"; | |
| 485 | }; | |
| 486 | ||
| f3d1939f | 487 | sdhc2: sdhci@f98a4900 { |
| 4ec48ebf | 488 | compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; |
| f3d1939f KD |
489 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; |
| 490 | reg-names = "hc_mem", "core_mem"; | |
| 491 | ||
| 492 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
| 493 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
| 494 | interrupt-names = "hc_irq", "pwr_irq"; | |
| 495 | ||
| 496 | clocks = <&gcc GCC_SDCC2_APPS_CLK>, | |
| 497 | <&gcc GCC_SDCC2_AHB_CLK>, | |
| 498 | <&xo_board>; | |
| 499 | clock-names = "core", "iface", "xo"; | |
| 500 | ||
| 501 | pinctrl-names = "default", "sleep"; | |
| 502 | pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; | |
| 503 | pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; | |
| 504 | ||
| 505 | cd-gpios = <&tlmm 100 0>; | |
| 506 | bus-width = <4>; | |
| 507 | status = "disabled"; | |
| 508 | }; | |
| 509 | ||
| 828896c5 | 510 | blsp1_dma: dma-controller@f9904000 { |
| d3d071a0 KD |
511 | compatible = "qcom,bam-v1.7.0"; |
| 512 | reg = <0xf9904000 0x19000>; | |
| 513 | interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; | |
| 514 | clocks = <&gcc GCC_BLSP1_AHB_CLK>; | |
| 515 | clock-names = "bam_clk"; | |
| 516 | #dma-cells = <1>; | |
| 517 | qcom,ee = <0>; | |
| 518 | qcom,controlled-remotely; | |
| 1ae438d2 | 519 | num-channels = <24>; |
| d3d071a0 KD |
520 | qcom,num-ees = <4>; |
| 521 | }; | |
| 522 | ||
| 7c865b09 KD |
523 | blsp1_uart2: serial@f991e000 { |
| 524 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| 525 | reg = <0xf991e000 0x1000>; | |
| 526 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 7c865b09 KD |
527 | clock-names = "core", "iface"; |
| 528 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, | |
| 529 | <&gcc GCC_BLSP1_AHB_CLK>; | |
| d3d071a0 KD |
530 | pinctrl-names = "default", "sleep"; |
| 531 | pinctrl-0 = <&blsp1_uart2_default>; | |
| 532 | pinctrl-1 = <&blsp1_uart2_sleep>; | |
| 533 | status = "disabled"; | |
| 534 | }; | |
| 535 | ||
| e093d1a2 | 536 | blsp1_i2c1: i2c@f9923000 { |
| d3d071a0 KD |
537 | compatible = "qcom,i2c-qup-v2.2.1"; |
| 538 | reg = <0xf9923000 0x500>; | |
| 539 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
| 2374b99e KK |
540 | clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, |
| 541 | <&gcc GCC_BLSP1_AHB_CLK>; | |
| 542 | clock-names = "core", "iface"; | |
| d3d071a0 | 543 | clock-frequency = <400000>; |
| e093d1a2 GM |
544 | dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; |
| 545 | dma-names = "tx", "rx"; | |
| d3d071a0 KD |
546 | pinctrl-names = "default", "sleep"; |
| 547 | pinctrl-0 = <&i2c1_default>; | |
| 548 | pinctrl-1 = <&i2c1_sleep>; | |
| 549 | #address-cells = <1>; | |
| 550 | #size-cells = <0>; | |
| 551 | status = "disabled"; | |
| 552 | }; | |
| 553 | ||
| e093d1a2 | 554 | blsp1_spi1: spi@f9923000 { |
| d3d071a0 KD |
555 | compatible = "qcom,spi-qup-v2.2.1"; |
| 556 | reg = <0xf9923000 0x500>; | |
| 557 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
| 558 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, | |
| 559 | <&gcc GCC_BLSP1_AHB_CLK>; | |
| 560 | clock-names = "core", "iface"; | |
| 561 | spi-max-frequency = <19200000>; | |
| 562 | dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; | |
| 563 | dma-names = "tx", "rx"; | |
| 564 | pinctrl-names = "default", "sleep"; | |
| e093d1a2 GM |
565 | pinctrl-0 = <&blsp1_spi1_default>; |
| 566 | pinctrl-1 = <&blsp1_spi1_sleep>; | |
| d3d071a0 KD |
567 | #address-cells = <1>; |
| 568 | #size-cells = <0>; | |
| 569 | status = "disabled"; | |
| 570 | }; | |
| 571 | ||
| e093d1a2 | 572 | blsp1_i2c2: i2c@f9924000 { |
| d3d071a0 KD |
573 | compatible = "qcom,i2c-qup-v2.2.1"; |
| 574 | reg = <0xf9924000 0x500>; | |
| 575 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 2374b99e KK |
576 | clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, |
| 577 | <&gcc GCC_BLSP1_AHB_CLK>; | |
| 578 | clock-names = "core", "iface"; | |
| e093d1a2 | 579 | clock-frequency = <400000>; |
| d3d071a0 KD |
580 | dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; |
| 581 | dma-names = "tx", "rx"; | |
| 582 | pinctrl-names = "default", "sleep"; | |
| 583 | pinctrl-0 = <&i2c2_default>; | |
| 584 | pinctrl-1 = <&i2c2_sleep>; | |
| 585 | #address-cells = <1>; | |
| 586 | #size-cells = <0>; | |
| 587 | status = "disabled"; | |
| 588 | }; | |
| 589 | ||
| 590 | /* I2C3 doesn't exist */ | |
| 591 | ||
| e093d1a2 | 592 | blsp1_i2c4: i2c@f9926000 { |
| d3d071a0 KD |
593 | compatible = "qcom,i2c-qup-v2.2.1"; |
| 594 | reg = <0xf9926000 0x500>; | |
| 595 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| 2374b99e KK |
596 | clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, |
| 597 | <&gcc GCC_BLSP1_AHB_CLK>; | |
| 598 | clock-names = "core", "iface"; | |
| e093d1a2 GM |
599 | clock-frequency = <400000>; |
| 600 | dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; | |
| 601 | dma-names = "tx", "rx"; | |
| d3d071a0 KD |
602 | pinctrl-names = "default", "sleep"; |
| 603 | pinctrl-0 = <&i2c4_default>; | |
| 604 | pinctrl-1 = <&i2c4_sleep>; | |
| 605 | #address-cells = <1>; | |
| 606 | #size-cells = <0>; | |
| 607 | status = "disabled"; | |
| 608 | }; | |
| 609 | ||
| e093d1a2 GM |
610 | blsp1_i2c5: i2c@f9927000 { |
| 611 | compatible = "qcom,i2c-qup-v2.2.1"; | |
| 612 | reg = <0xf9927000 0x500>; | |
| 613 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
| 2374b99e KK |
614 | clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, |
| 615 | <&gcc GCC_BLSP1_AHB_CLK>; | |
| 616 | clock-names = "core", "iface"; | |
| e093d1a2 GM |
617 | clock-frequency = <400000>; |
| 618 | dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; | |
| 619 | dma-names = "tx", "rx"; | |
| 620 | pinctrl-names = "default", "sleep"; | |
| 621 | pinctrl-0 = <&i2c5_default>; | |
| 622 | pinctrl-1 = <&i2c5_sleep>; | |
| 623 | #address-cells = <1>; | |
| 624 | #size-cells = <0>; | |
| 625 | status = "disabled"; | |
| d3d071a0 KD |
626 | }; |
| 627 | ||
| e093d1a2 | 628 | blsp1_i2c6: i2c@f9928000 { |
| d3d071a0 KD |
629 | compatible = "qcom,i2c-qup-v2.2.1"; |
| 630 | reg = <0xf9928000 0x500>; | |
| 631 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
| 2374b99e KK |
632 | clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, |
| 633 | <&gcc GCC_BLSP1_AHB_CLK>; | |
| 634 | clock-names = "core", "iface"; | |
| e093d1a2 | 635 | clock-frequency = <400000>; |
| d3d071a0 KD |
636 | dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; |
| 637 | dma-names = "tx", "rx"; | |
| 638 | pinctrl-names = "default", "sleep"; | |
| 639 | pinctrl-0 = <&i2c6_default>; | |
| 640 | pinctrl-1 = <&i2c6_sleep>; | |
| 641 | #address-cells = <1>; | |
| 642 | #size-cells = <0>; | |
| 643 | status = "disabled"; | |
| 644 | }; | |
| 645 | ||
| e093d1a2 GM |
646 | blsp2_dma: dma-controller@f9944000 { |
| 647 | compatible = "qcom,bam-v1.7.0"; | |
| 648 | reg = <0xf9944000 0x19000>; | |
| 649 | interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; | |
| 650 | clocks = <&gcc GCC_BLSP2_AHB_CLK>; | |
| 651 | clock-names = "bam_clk"; | |
| 652 | #dma-cells = <1>; | |
| 653 | qcom,ee = <0>; | |
| 654 | qcom,controlled-remotely; | |
| 1ae438d2 | 655 | num-channels = <24>; |
| e093d1a2 GM |
656 | qcom,num-ees = <4>; |
| 657 | }; | |
| 658 | ||
| d3d071a0 KD |
659 | blsp2_uart2: serial@f995e000 { |
| 660 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| 661 | reg = <0xf995e000 0x1000>; | |
| a046032c | 662 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| d3d071a0 KD |
663 | clock-names = "core", "iface"; |
| 664 | clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, | |
| 665 | <&gcc GCC_BLSP2_AHB_CLK>; | |
| 666 | dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; | |
| 667 | dma-names = "tx", "rx"; | |
| 668 | pinctrl-names = "default", "sleep"; | |
| 669 | pinctrl-0 = <&blsp2_uart2_default>; | |
| 670 | pinctrl-1 = <&blsp2_uart2_sleep>; | |
| 671 | status = "disabled"; | |
| 672 | }; | |
| 673 | ||
| e093d1a2 GM |
674 | blsp2_i2c1: i2c@f9963000 { |
| 675 | compatible = "qcom,i2c-qup-v2.2.1"; | |
| 676 | reg = <0xf9963000 0x500>; | |
| 677 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 2374b99e KK |
678 | clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, |
| 679 | <&gcc GCC_BLSP2_AHB_CLK>; | |
| 680 | clock-names = "core", "iface"; | |
| e093d1a2 GM |
681 | clock-frequency = <400000>; |
| 682 | dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; | |
| 683 | dma-names = "tx", "rx"; | |
| 684 | pinctrl-names = "default", "sleep"; | |
| 685 | pinctrl-0 = <&i2c7_default>; | |
| 686 | pinctrl-1 = <&i2c7_sleep>; | |
| 687 | #address-cells = <1>; | |
| 688 | #size-cells = <0>; | |
| 689 | status = "disabled"; | |
| 690 | }; | |
| 691 | ||
| 692 | blsp2_spi4: spi@f9966000 { | |
| 693 | compatible = "qcom,spi-qup-v2.2.1"; | |
| 694 | reg = <0xf9966000 0x500>; | |
| 695 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
| 696 | clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, | |
| 697 | <&gcc GCC_BLSP2_AHB_CLK>; | |
| 698 | clock-names = "core", "iface"; | |
| 699 | spi-max-frequency = <19200000>; | |
| 700 | dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; | |
| 701 | dma-names = "tx", "rx"; | |
| 702 | pinctrl-names = "default", "sleep"; | |
| 703 | pinctrl-0 = <&blsp2_spi10_default>; | |
| 704 | pinctrl-1 = <&blsp2_spi10_sleep>; | |
| 705 | #address-cells = <1>; | |
| 706 | #size-cells = <0>; | |
| 707 | status = "disabled"; | |
| 708 | }; | |
| 709 | ||
| 710 | blsp2_i2c5: i2c@f9967000 { | |
| d3d071a0 KD |
711 | compatible = "qcom,i2c-qup-v2.2.1"; |
| 712 | reg = <0xf9967000 0x500>; | |
| 713 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
| 2374b99e KK |
714 | clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, |
| 715 | <&gcc GCC_BLSP2_AHB_CLK>; | |
| 716 | clock-names = "core", "iface"; | |
| d3d071a0 KD |
717 | clock-frequency = <355000>; |
| 718 | dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; | |
| 719 | dma-names = "tx", "rx"; | |
| 720 | pinctrl-names = "default", "sleep"; | |
| e093d1a2 GM |
721 | pinctrl-0 = <&i2c11_default>; |
| 722 | pinctrl-1 = <&i2c11_sleep>; | |
| d3d071a0 KD |
723 | #address-cells = <1>; |
| 724 | #size-cells = <0>; | |
| 725 | status = "disabled"; | |
| 7c865b09 KD |
726 | }; |
| 727 | ||
| 728 | gcc: clock-controller@fc400000 { | |
| 729 | compatible = "qcom,gcc-msm8994"; | |
| 730 | #clock-cells = <1>; | |
| 731 | #reset-cells = <1>; | |
| 732 | #power-domain-cells = <1>; | |
| 733 | reg = <0xfc400000 0x2000>; | |
| 4dd1ad61 | 734 | |
| 5827e283 | 735 | clock-names = "xo", "sleep"; |
| 4dd1ad61 | 736 | clocks = <&xo_board>, <&sleep_clk>; |
| 7c865b09 KD |
737 | }; |
| 738 | ||
| 179811be | 739 | rpm_msg_ram: sram@fc428000 { |
| 01104518 KD |
740 | compatible = "qcom,rpm-msg-ram"; |
| 741 | reg = <0xfc428000 0x4000>; | |
| 742 | }; | |
| 743 | ||
| feeaf56a BK |
744 | restart@fc4ab000 { |
| 745 | compatible = "qcom,pshold"; | |
| 746 | reg = <0xfc4ab000 0x4>; | |
| 747 | }; | |
| 748 | ||
| b0ad598f KD |
749 | spmi_bus: spmi@fc4c0000 { |
| 750 | compatible = "qcom,spmi-pmic-arb"; | |
| 751 | reg = <0xfc4cf000 0x1000>, | |
| 752 | <0xfc4cb000 0x1000>, | |
| 753 | <0xfc4ca000 0x1000>; | |
| 754 | reg-names = "core", "intr", "cnfg"; | |
| 755 | interrupt-names = "periph_irq"; | |
| 756 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | |
| 757 | qcom,ee = <0>; | |
| 758 | qcom,channel = <0>; | |
| 759 | #address-cells = <2>; | |
| 760 | #size-cells = <0>; | |
| 761 | interrupt-controller; | |
| 762 | #interrupt-cells = <4>; | |
| 763 | }; | |
| 764 | ||
| 7c865b09 KD |
765 | tcsr_mutex_regs: syscon@fd484000 { |
| 766 | compatible = "syscon"; | |
| 767 | reg = <0xfd484000 0x2000>; | |
| 768 | }; | |
| 769 | ||
| 770 | tlmm: pinctrl@fd510000 { | |
| feeaf56a BK |
771 | compatible = "qcom,msm8994-pinctrl"; |
| 772 | reg = <0xfd510000 0x4000>; | |
| 773 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
| 774 | gpio-controller; | |
| 7c865b09 | 775 | gpio-ranges = <&tlmm 0 0 146>; |
| feeaf56a BK |
776 | #gpio-cells = <2>; |
| 777 | interrupt-controller; | |
| 778 | #interrupt-cells = <2>; | |
| feeaf56a | 779 | |
| 7c865b09 KD |
780 | blsp1_uart2_default: blsp1-uart2-default { |
| 781 | function = "blsp_uart2"; | |
| 782 | pins = "gpio4", "gpio5"; | |
| 783 | drive-strength = <16>; | |
| 784 | bias-disable; | |
| 785 | }; | |
| feeaf56a | 786 | |
| 7c865b09 KD |
787 | blsp1_uart2_sleep: blsp1-uart2-sleep { |
| 788 | function = "gpio"; | |
| 789 | pins = "gpio4", "gpio5"; | |
| 790 | drive-strength = <2>; | |
| 791 | bias-pull-down; | |
| 792 | }; | |
| feeaf56a | 793 | |
| 7c865b09 KD |
794 | blsp2_uart2_default: blsp2-uart2-default { |
| 795 | function = "blsp_uart8"; | |
| a046032c KD |
796 | pins = "gpio45", "gpio46", |
| 797 | "gpio47", "gpio48"; | |
| 798 | drive-strength = <16>; | |
| 7c865b09 KD |
799 | bias-disable; |
| 800 | }; | |
| feeaf56a | 801 | |
| 7c865b09 KD |
802 | blsp2_uart2_sleep: blsp2-uart2-sleep { |
| 803 | function = "gpio"; | |
| a046032c KD |
804 | pins = "gpio45", "gpio46", |
| 805 | "gpio47", "gpio48"; | |
| 7c865b09 | 806 | drive-strength = <2>; |
| a046032c | 807 | bias-disable; |
| 7c865b09 | 808 | }; |
| feeaf56a | 809 | |
| 7c865b09 KD |
810 | i2c1_default: i2c1-default { |
| 811 | function = "blsp_i2c1"; | |
| 812 | pins = "gpio2", "gpio3"; | |
| 813 | drive-strength = <2>; | |
| 814 | bias-disable; | |
| 815 | }; | |
| feeaf56a | 816 | |
| 7c865b09 KD |
817 | i2c1_sleep: i2c1-sleep { |
| 818 | function = "gpio"; | |
| 819 | pins = "gpio2", "gpio3"; | |
| 820 | drive-strength = <2>; | |
| 821 | bias-disable; | |
| 822 | }; | |
| feeaf56a | 823 | |
| 7c865b09 KD |
824 | i2c2_default: i2c2-default { |
| 825 | function = "blsp_i2c2"; | |
| 826 | pins = "gpio6", "gpio7"; | |
| 827 | drive-strength = <2>; | |
| 828 | bias-disable; | |
| 829 | }; | |
| feeaf56a | 830 | |
| 7c865b09 KD |
831 | i2c2_sleep: i2c2-sleep { |
| 832 | function = "gpio"; | |
| 833 | pins = "gpio6", "gpio7"; | |
| 834 | drive-strength = <2>; | |
| 835 | bias-disable; | |
| 836 | }; | |
| 837 | ||
| 838 | i2c4_default: i2c4-default { | |
| 839 | function = "blsp_i2c4"; | |
| 840 | pins = "gpio19", "gpio20"; | |
| 841 | drive-strength = <2>; | |
| 842 | bias-disable; | |
| 843 | }; | |
| 844 | ||
| 845 | i2c4_sleep: i2c4-sleep { | |
| 846 | function = "gpio"; | |
| 847 | pins = "gpio19", "gpio20"; | |
| 848 | drive-strength = <2>; | |
| 849 | bias-pull-down; | |
| 850 | input-enable; | |
| 851 | }; | |
| 852 | ||
| 853 | i2c5_default: i2c5-default { | |
| 854 | function = "blsp_i2c5"; | |
| 855 | pins = "gpio23", "gpio24"; | |
| 856 | drive-strength = <2>; | |
| 857 | bias-disable; | |
| 858 | }; | |
| 859 | ||
| 860 | i2c5_sleep: i2c5-sleep { | |
| 861 | function = "gpio"; | |
| 862 | pins = "gpio23", "gpio24"; | |
| 863 | drive-strength = <2>; | |
| 864 | bias-disable; | |
| 865 | }; | |
| 866 | ||
| 867 | i2c6_default: i2c6-default { | |
| 868 | function = "blsp_i2c6"; | |
| 869 | pins = "gpio28", "gpio27"; | |
| 870 | drive-strength = <2>; | |
| 871 | bias-disable; | |
| 872 | }; | |
| 873 | ||
| 874 | i2c6_sleep: i2c6-sleep { | |
| 875 | function = "gpio"; | |
| 876 | pins = "gpio28", "gpio27"; | |
| 877 | drive-strength = <2>; | |
| 878 | bias-disable; | |
| 879 | }; | |
| 880 | ||
| e093d1a2 GM |
881 | i2c7_default: i2c7-default { |
| 882 | function = "blsp_i2c7"; | |
| 883 | pins = "gpio44", "gpio43"; | |
| 884 | drive-strength = <2>; | |
| 885 | bias-disable; | |
| 886 | }; | |
| 887 | ||
| 888 | i2c7_sleep: i2c7-sleep { | |
| 889 | function = "gpio"; | |
| 890 | pins = "gpio44", "gpio43"; | |
| 891 | drive-strength = <2>; | |
| 892 | bias-disable; | |
| 893 | }; | |
| 894 | ||
| 895 | blsp2_spi10_default: blsp2-spi10-default { | |
| 896 | default { | |
| 897 | function = "blsp_spi10"; | |
| 898 | pins = "gpio53", "gpio54", "gpio55"; | |
| 899 | drive-strength = <10>; | |
| 900 | bias-pull-down; | |
| 901 | }; | |
| 902 | cs { | |
| 903 | function = "gpio"; | |
| 904 | pins = "gpio55"; | |
| 905 | drive-strength = <2>; | |
| 906 | bias-disable; | |
| 907 | }; | |
| 908 | }; | |
| 909 | ||
| 910 | blsp2_spi10_sleep: blsp2-spi10-sleep { | |
| 911 | pins = "gpio53", "gpio54", "gpio55"; | |
| 912 | drive-strength = <2>; | |
| 913 | bias-disable; | |
| 914 | }; | |
| 915 | ||
| 916 | i2c11_default: i2c11-default { | |
| 917 | function = "blsp_i2c11"; | |
| 918 | pins = "gpio83", "gpio84"; | |
| 919 | drive-strength = <2>; | |
| 920 | bias-disable; | |
| 921 | }; | |
| 922 | ||
| 923 | i2c11_sleep: i2c11-sleep { | |
| 924 | function = "gpio"; | |
| 925 | pins = "gpio83", "gpio84"; | |
| 926 | drive-strength = <2>; | |
| 927 | bias-disable; | |
| 928 | }; | |
| 929 | ||
| 930 | blsp1_spi1_default: blsp1-spi1-default { | |
| 7c865b09 KD |
931 | default { |
| 932 | function = "blsp_spi1"; | |
| 933 | pins = "gpio0", "gpio1", "gpio3"; | |
| 934 | drive-strength = <10>; | |
| 935 | bias-pull-down; | |
| 936 | }; | |
| 937 | cs { | |
| 938 | function = "gpio"; | |
| 939 | pins = "gpio8"; | |
| 940 | drive-strength = <2>; | |
| 941 | bias-disable; | |
| 942 | }; | |
| 943 | }; | |
| 944 | ||
| e093d1a2 | 945 | blsp1_spi1_sleep: blsp1-spi1-sleep { |
| 7c865b09 KD |
946 | pins = "gpio0", "gpio1", "gpio3"; |
| 947 | drive-strength = <2>; | |
| 948 | bias-disable; | |
| 949 | }; | |
| 950 | ||
| 951 | sdc1_clk_on: clk-on { | |
| 952 | pins = "sdc1_clk"; | |
| 953 | bias-disable; | |
| 954 | drive-strength = <16>; | |
| 955 | }; | |
| 956 | ||
| 957 | sdc1_clk_off: clk-off { | |
| 958 | pins = "sdc1_clk"; | |
| 959 | bias-disable; | |
| 960 | drive-strength = <2>; | |
| 961 | }; | |
| 962 | ||
| 963 | sdc1_cmd_on: cmd-on { | |
| 964 | pins = "sdc1_cmd"; | |
| 965 | bias-pull-up; | |
| 966 | drive-strength = <8>; | |
| 967 | }; | |
| 968 | ||
| 969 | sdc1_cmd_off: cmd-off { | |
| 970 | pins = "sdc1_cmd"; | |
| 971 | bias-pull-up; | |
| 972 | drive-strength = <2>; | |
| 973 | }; | |
| 974 | ||
| 975 | sdc1_data_on: data-on { | |
| 976 | pins = "sdc1_data"; | |
| 977 | bias-pull-up; | |
| 978 | drive-strength = <8>; | |
| 979 | }; | |
| 980 | ||
| 981 | sdc1_data_off: data-off { | |
| 982 | pins = "sdc1_data"; | |
| 983 | bias-pull-up; | |
| 984 | drive-strength = <2>; | |
| 985 | }; | |
| 986 | ||
| 987 | sdc1_rclk_on: rclk-on { | |
| 988 | pins = "sdc1_rclk"; | |
| 989 | bias-pull-down; | |
| 990 | }; | |
| 991 | ||
| 992 | sdc1_rclk_off: rclk-off { | |
| 993 | pins = "sdc1_rclk"; | |
| 994 | bias-pull-down; | |
| 995 | }; | |
| f3d1939f KD |
996 | |
| 997 | sdc2_clk_on: sdc2-clk-on { | |
| 998 | pins = "sdc2_clk"; | |
| 999 | bias-disable; | |
| 1000 | drive-strength = <10>; | |
| 1001 | }; | |
| 1002 | ||
| 1003 | sdc2_clk_off: sdc2-clk-off { | |
| 1004 | pins = "sdc2_clk"; | |
| 1005 | bias-disable; | |
| 1006 | drive-strength = <2>; | |
| 1007 | }; | |
| 1008 | ||
| 1009 | sdc2_cmd_on: sdc2-cmd-on { | |
| 1010 | pins = "sdc2_cmd"; | |
| 1011 | bias-pull-up; | |
| 1012 | drive-strength = <10>; | |
| 1013 | }; | |
| 1014 | ||
| 1015 | sdc2_cmd_off: sdc2-cmd-off { | |
| 1016 | pins = "sdc2_cmd"; | |
| 1017 | bias-pull-up; | |
| 1018 | drive-strength = <2>; | |
| 1019 | }; | |
| 1020 | ||
| 1021 | sdc2_data_on: sdc2-data-on { | |
| 1022 | pins = "sdc2_data"; | |
| 1023 | bias-pull-up; | |
| 1024 | drive-strength = <10>; | |
| 1025 | }; | |
| 1026 | ||
| 1027 | sdc2_data_off: sdc2-data-off { | |
| 1028 | pins = "sdc2_data"; | |
| 1029 | bias-pull-up; | |
| 1030 | drive-strength = <2>; | |
| 1031 | }; | |
| feeaf56a | 1032 | }; |
| e9b0eb54 KD |
1033 | |
| 1034 | mmcc: clock-controller@fd8c0000 { | |
| 1035 | compatible = "qcom,mmcc-msm8994"; | |
| 1036 | reg = <0xfd8c0000 0x5200>; | |
| 1037 | #clock-cells = <1>; | |
| 1038 | #reset-cells = <1>; | |
| 1039 | #power-domain-cells = <1>; | |
| 1040 | ||
| 1041 | clock-names = "xo", | |
| 1042 | "gpll0", | |
| 1043 | "mmssnoc_ahb", | |
| 1044 | "oxili_gfx3d_clk_src", | |
| 1045 | "dsi0pll", | |
| 1046 | "dsi0pllbyte", | |
| 1047 | "dsi1pll", | |
| 1048 | "dsi1pllbyte", | |
| 1049 | "hdmipll"; | |
| 1050 | clocks = <&xo_board>, | |
| 1051 | <&gcc GPLL0_OUT_MMSSCC>, | |
| 1052 | <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, | |
| 1053 | <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, | |
| 1054 | <0>, | |
| 1055 | <0>, | |
| 1056 | <0>, | |
| 1057 | <0>, | |
| 1058 | <0>; | |
| 1059 | ||
| 1060 | assigned-clocks = <&mmcc MMPLL0_PLL>, | |
| 1061 | <&mmcc MMPLL1_PLL>, | |
| 1062 | <&mmcc MMPLL3_PLL>, | |
| 1063 | <&mmcc MMPLL4_PLL>, | |
| 1064 | <&mmcc MMPLL5_PLL>; | |
| 1065 | assigned-clock-rates = <800000000>, | |
| 1066 | <1167000000>, | |
| 1067 | <1020000000>, | |
| 1068 | <960000000>, | |
| 1069 | <600000000>; | |
| 1070 | }; | |
| 9d511d0a KD |
1071 | |
| 1072 | ocmem: ocmem@fdd00000 { | |
| 1073 | compatible = "qcom,msm8974-ocmem"; | |
| 1074 | reg = <0xfdd00000 0x2000>, | |
| 1075 | <0xfec00000 0x200000>; | |
| 1076 | reg-names = "ctrl", "mem"; | |
| 1077 | clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, | |
| 1078 | <&mmcc OCMEMCX_OCMEMNOC_CLK>; | |
| 1079 | clock-names = "core", "iface"; | |
| 1080 | ||
| 1081 | #address-cells = <1>; | |
| 1082 | #size-cells = <1>; | |
| 1083 | ||
| 1084 | gmu_sram: gmu-sram@0 { | |
| 1085 | reg = <0x0 0x180000>; | |
| 1086 | }; | |
| 1087 | }; | |
| feeaf56a BK |
1088 | }; |
| 1089 | ||
| 976d321f | 1090 | timer: timer { |
| 7c865b09 KD |
1091 | compatible = "arm,armv8-timer"; |
| 1092 | interrupts = <GIC_PPI 2 0xff08>, | |
| 1093 | <GIC_PPI 3 0xff08>, | |
| 1094 | <GIC_PPI 4 0xff08>, | |
| 1095 | <GIC_PPI 1 0xff08>; | |
| feeaf56a | 1096 | }; |
| 01104518 | 1097 | |
| 53364cfc | 1098 | vph_pwr: vph-pwr-regulator { |
| 01104518 | 1099 | compatible = "regulator-fixed"; |
| 53364cfc | 1100 | regulator-name = "vph_pwr"; |
| 01104518 KD |
1101 | |
| 1102 | regulator-min-microvolt = <3600000>; | |
| 1103 | regulator-max-microvolt = <3600000>; | |
| 1104 | ||
| 1105 | regulator-always-on; | |
| 1106 | }; | |
| feeaf56a BK |
1107 | }; |
| 1108 |