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Merge tag 'driver-core-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / arch / arm64 / boot / dts / qcom / ipq8074.dtsi
CommitLineData
97fb5e8d 1// SPDX-License-Identifier: GPL-2.0-only
41dac73e
VN		 2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
41dac73e
VN		 4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8
9/ {
10 model = "Qualcomm Technologies, Inc. IPQ8074";
11 compatible = "qcom,ipq8074";
12
e8a7fdc5
SM		 13 clocks {
14 sleep_clk: sleep_clk {
15 compatible = "fixed-clock";
f607dd76 16 clock-frequency = <32768>;
e8a7fdc5
SM		 17 #clock-cells = <0>;
18 };
19
20 xo: xo {
21 compatible = "fixed-clock";
22 clock-frequency = <19200000>;
23 #clock-cells = <0>;
24 };
25 };
26
27 cpus {
28 #address-cells = <0x1>;
29 #size-cells = <0x0>;
30
31 CPU0: cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a53";
34 reg = <0x0>;
35 next-level-cache = <&L2_0>;
36 enable-method = "psci";
37 };
38
39 CPU1: cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 reg = <0x1>;
44 next-level-cache = <&L2_0>;
45 };
46
47 CPU2: cpu@2 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 reg = <0x2>;
52 next-level-cache = <&L2_0>;
53 };
54
55 CPU3: cpu@3 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 reg = <0x3>;
60 next-level-cache = <&L2_0>;
61 };
62
63 L2_0: l2-cache {
64 compatible = "cache";
65 cache-level = <0x2>;
66 };
67 };
68
69 pmu {
292b1874 70 compatible = "arm,cortex-a53-pmu";
e8a7fdc5
SM		 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
72 };
73
74 psci {
75 compatible = "arm,psci-1.0";
76 method = "smc";
77 };
78
42124b94
RM		 79 reserved-memory {
80 #address-cells = <2>;
81 #size-cells = <2>;
82 ranges;
83
84 smem@4ab00000 {
85 compatible = "qcom,smem";
86 reg = <0x0 0x4ab00000 0x0 0x00100000>;
87 no-map;
88
89 hwlocks = <&tcsr_mutex 0>;
90 };
e4a4fdcf
K		 91
92 memory@4ac00000 {
93 no-map;
94 reg = <0x0 0x4ac00000 0x0 0x00400000>;
95 };
42124b94
RM		 96 };
97
6df9102f
GSP		 98 firmware {
99 scm {
100 compatible = "qcom,scm-ipq8074", "qcom,scm";
101 };
102 };
103
41dac73e
VN		 104 soc: soc {
105 #address-cells = <0x1>;
106 #size-cells = <0x1>;
107 ranges = <0 0 0 0xffffffff>;
108 compatible = "simple-bus";
109
5e09bc51
SM		 110 ssphy_1: phy@58000 {
111 compatible = "qcom,ipq8074-qmp-usb3-phy";
112 reg = <0x00058000 0x1c4>;
5e09bc51
SM		 113 #address-cells = <1>;
114 #size-cells = <1>;
115 ranges;
116
117 clocks = <&gcc GCC_USB1_AUX_CLK>,
118 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
119 <&xo>;
120 clock-names = "aux", "cfg_ahb", "ref";
121
122 resets = <&gcc GCC_USB1_PHY_BCR>,
123 <&gcc GCC_USB3PHY_1_PHY_BCR>;
124 reset-names = "phy","common";
125 status = "disabled";
126
1351512f 127 usb1_ssphy: phy@58200 {
5e09bc51
SM		 128 reg = <0x00058200 0x130>, /* Tx */
129 <0x00058400 0x200>, /* Rx */
130 <0x00058800 0x1f8>, /* PCS */
131 <0x00058600 0x044>; /* PCS misc*/
132 #phy-cells = <0>;
82d61e19 133 #clock-cells = <1>;
5e09bc51
SM		 134 clocks = <&gcc GCC_USB1_PIPE_CLK>;
135 clock-names = "pipe0";
136 clock-output-names = "gcc_usb1_pipe_clk_src";
137 };
138 };
139
140 qusb_phy_1: phy@59000 {
141 compatible = "qcom,ipq8074-qusb2-phy";
142 reg = <0x00059000 0x180>;
143 #phy-cells = <0>;
144
145 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
146 <&xo>;
147 clock-names = "cfg_ahb", "ref";
148
149 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
150 status = "disabled";
151 };
152
153 ssphy_0: phy@78000 {
154 compatible = "qcom,ipq8074-qmp-usb3-phy";
155 reg = <0x00078000 0x1c4>;
5e09bc51
SM		 156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges;
159
160 clocks = <&gcc GCC_USB0_AUX_CLK>,
161 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
162 <&xo>;
163 clock-names = "aux", "cfg_ahb", "ref";
164
165 resets = <&gcc GCC_USB0_PHY_BCR>,
166 <&gcc GCC_USB3PHY_0_PHY_BCR>;
167 reset-names = "phy","common";
168 status = "disabled";
169
1351512f 170 usb0_ssphy: phy@78200 {
5e09bc51
SM		 171 reg = <0x00078200 0x130>, /* Tx */
172 <0x00078400 0x200>, /* Rx */
173 <0x00078800 0x1f8>, /* PCS */
174 <0x00078600 0x044>; /* PCS misc*/
175 #phy-cells = <0>;
82d61e19 176 #clock-cells = <1>;
5e09bc51
SM		 177 clocks = <&gcc GCC_USB0_PIPE_CLK>;
178 clock-names = "pipe0";
179 clock-output-names = "gcc_usb0_pipe_clk_src";
180 };
181 };
182
183 qusb_phy_0: phy@79000 {
184 compatible = "qcom,ipq8074-qusb2-phy";
185 reg = <0x00079000 0x180>;
186 #phy-cells = <0>;
187
188 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
189 <&xo>;
190 clock-names = "cfg_ahb", "ref";
191
192 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
58b2785d 193 status = "disabled";
5e09bc51
SM		 194 };
195
942bcd33 196 pcie_qmp0: phy@86000 {
e8a7fdc5
SM		 197 compatible = "qcom,ipq8074-qmp-pcie-phy";
198 reg = <0x00086000 0x1000>;
942bcd33
SG		 199 #address-cells = <1>;
200 #size-cells = <1>;
201 ranges;
e8a7fdc5 202
942bcd33
SG		 203 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
204 <&gcc GCC_PCIE0_AHB_CLK>;
205 clock-names = "aux", "cfg_ahb";
e8a7fdc5
SM		 206 resets = <&gcc GCC_PCIE0_PHY_BCR>,
207 <&gcc GCC_PCIE0PHY_PHY_BCR>;
208 reset-names = "phy",
209 "common";
210 status = "disabled";
942bcd33
SG		 211
212 pcie_phy0: phy@86200 {
213 reg = <0x86200 0x16c>,
214 <0x86400 0x200>,
215 <0x86800 0x4f4>;
216 #phy-cells = <0>;
217 #clock-cells = <0>;
218 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
219 clock-names = "pipe0";
220 clock-output-names = "pcie_0_pipe_clk";
221 };
e8a7fdc5
SM		 222 };
223
942bcd33 224 pcie_qmp1: phy@8e000 {
e8a7fdc5
SM		 225 compatible = "qcom,ipq8074-qmp-pcie-phy";
226 reg = <0x0008e000 0x1000>;
942bcd33
SG		 227 #address-cells = <1>;
228 #size-cells = <1>;
229 ranges;
e8a7fdc5 230
942bcd33
SG		 231 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
232 <&gcc GCC_PCIE1_AHB_CLK>;
233 clock-names = "aux", "cfg_ahb";
e8a7fdc5
SM		 234 resets = <&gcc GCC_PCIE1_PHY_BCR>,
235 <&gcc GCC_PCIE1PHY_PHY_BCR>;
236 reset-names = "phy",
237 "common";
238 status = "disabled";
942bcd33
SG		 239
240 pcie_phy1: phy@8e200 {
241 reg = <0x8e200 0x16c>,
242 <0x8e400 0x200>,
243 <0x8e800 0x4f4>;
244 #phy-cells = <0>;
245 #clock-cells = <0>;
246 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
247 clock-names = "pipe0";
248 clock-output-names = "pcie_1_pipe_clk";
249 };
e8a7fdc5
SM		 250 };
251
d201f677
RM		 252 mdio: mdio@90000 {
253 compatible = "qcom,ipq4019-mdio";
254 reg = <0x00090000 0x64>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257
258 clocks = <&gcc GCC_MDIO_AHB_CLK>;
259 clock-names = "gcc_mdio_ahb_clk";
260
261 status = "disabled";
262 };
263
f26f6a5e
RM		 264 prng: rng@e3000 {
265 compatible = "qcom,prng-ee";
266 reg = <0x000e3000 0x1000>;
267 clocks = <&gcc GCC_PRNG_AHB_CLK>;
268 clock-names = "core";
269 status = "disabled";
270 };
271
bbef0142 272 cryptobam: dma-controller@704000 {
f9e2df82
RM		 273 compatible = "qcom,bam-v1.7.0";
274 reg = <0x00704000 0x20000>;
275 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
277 clock-names = "bam_clk";
278 #dma-cells = <1>;
279 qcom,ee = <1>;
8c97f0ac 280 qcom,controlled-remotely;
f9e2df82
RM		 281 status = "disabled";
282 };
283
284 crypto: crypto@73a000 {
285 compatible = "qcom,crypto-v5.1";
286 reg = <0x0073a000 0x6000>;
287 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
288 <&gcc GCC_CRYPTO_AXI_CLK>,
289 <&gcc GCC_CRYPTO_CLK>;
290 clock-names = "iface", "bus", "core";
291 dmas = <&cryptobam 2>, <&cryptobam 3>;
292 dma-names = "rx", "tx";
293 status = "disabled";
294 };
295
33057e16 296 tlmm: pinctrl@1000000 {
41dac73e 297 compatible = "qcom,ipq8074-pinctrl";
e8a7fdc5 298 reg = <0x01000000 0x300000>;
41dac73e
VN		 299 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
300 gpio-controller;
297177a4 301 gpio-ranges = <&tlmm 0 0 70>;
41dac73e
VN		 302 #gpio-cells = <0x2>;
303 interrupt-controller;
304 #interrupt-cells = <0x2>;
22592a22
S		 305
306 serial_4_pins: serial4-pinmux {
307 pins = "gpio23", "gpio24";
308 function = "blsp4_uart1";
309 drive-strength = <8>;
310 bias-disable;
311 };
312
313 i2c_0_pins: i2c-0-pinmux {
314 pins = "gpio42", "gpio43";
315 function = "blsp1_i2c";
316 drive-strength = <8>;
317 bias-disable;
318 };
319
320 spi_0_pins: spi-0-pins {
321 pins = "gpio38", "gpio39", "gpio40", "gpio41";
322 function = "blsp0_spi";
323 drive-strength = <8>;
324 bias-disable;
325 };
326
327 hsuart_pins: hsuart-pins {
328 pins = "gpio46", "gpio47", "gpio48", "gpio49";
329 function = "blsp2_uart";
330 drive-strength = <8>;
331 bias-disable;
332 };
333
334 qpic_pins: qpic-pins {
335 pins = "gpio1", "gpio3", "gpio4",
336 "gpio5", "gpio6", "gpio7",
337 "gpio8", "gpio10", "gpio11",
338 "gpio12", "gpio13", "gpio14",
339 "gpio15", "gpio16", "gpio17";
340 function = "qpic";
341 drive-strength = <8>;
342 bias-disable;
343 };
41dac73e
VN		 344 };
345
41dac73e
VN		 346 gcc: gcc@1800000 {
347 compatible = "qcom,gcc-ipq8074";
e8a7fdc5 348 reg = <0x01800000 0x80000>;
41dac73e
VN		 349 #clock-cells = <0x1>;
350 #reset-cells = <0x1>;
351 };
352
42124b94
RM		 353 tcsr_mutex: hwlock@1905000 {
354 compatible = "qcom,tcsr-mutex";
355 reg = <0x01905000 0x20000>;
356 #hwlock-cells = <1>;
357 };
358
63750607
RM		 359 spmi_bus: spmi@200f000 {
360 compatible = "qcom,spmi-pmic-arb";
361 reg = <0x0200f000 0x001000>,
362 <0x02400000 0x800000>,
363 <0x02c00000 0x800000>,
364 <0x03800000 0x200000>,
365 <0x0200a000 0x000700>;
366 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
367 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "periph_irq";
369 qcom,ee = <0>;
370 qcom,channel = <0>;
371 #address-cells = <2>;
372 #size-cells = <0>;
373 interrupt-controller;
374 #interrupt-cells = <4>;
375 cell-index = <0>;
376 };
377
cbc142c8
SM		 378 sdhc_1: sdhci@7824900 {
379 compatible = "qcom,sdhci-msm-v4";
380 reg = <0x7824900 0x500>, <0x7824000 0x800>;
381 reg-names = "hc_mem", "core_mem";
382
383 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
385 interrupt-names = "hc_irq", "pwr_irq";
386
387 clocks = <&xo>,
388 <&gcc GCC_SDCC1_AHB_CLK>,
389 <&gcc GCC_SDCC1_APPS_CLK>;
390 clock-names = "xo", "iface", "core";
391 max-frequency = <384000000>;
392 mmc-ddr-1_8v;
393 mmc-hs200-1_8v;
394 mmc-hs400-1_8v;
395 bus-width = <8>;
396
397 status = "disabled";
398 };
399
b7fbf46c 400 blsp_dma: dma-controller@7884000 {
22592a22 401 compatible = "qcom,bam-v1.7.0";
e8a7fdc5 402 reg = <0x07884000 0x2b000>;
22592a22
S		 403 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
405 clock-names = "bam_clk";
406 #dma-cells = <1>;
407 qcom,ee = <0>;
408 };
409
410 blsp1_uart1: serial@78af000 {
411 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
e8a7fdc5 412 reg = <0x078af000 0x200>;
22592a22
S		 413 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
415 <&gcc GCC_BLSP1_AHB_CLK>;
416 clock-names = "core", "iface";
417 status = "disabled";
418 };
419
420 blsp1_uart3: serial@78b1000 {
421 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
e8a7fdc5 422 reg = <0x078b1000 0x200>;
22592a22
S		 423 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
425 <&gcc GCC_BLSP1_AHB_CLK>;
426 clock-names = "core", "iface";
427 dmas = <&blsp_dma 4>,
428 <&blsp_dma 5>;
429 dma-names = "tx", "rx";
430 pinctrl-0 = <&hsuart_pins>;
431 pinctrl-names = "default";
432 status = "disabled";
433 };
434
e8a7fdc5
SM		 435 blsp1_uart5: serial@78b3000 {
436 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
437 reg = <0x078b3000 0x200>;
438 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
440 <&gcc GCC_BLSP1_AHB_CLK>;
441 clock-names = "core", "iface";
442 pinctrl-0 = <&serial_4_pins>;
443 pinctrl-names = "default";
444 status = "disabled";
445 };
446
22592a22
S		 447 blsp1_spi1: spi@78b5000 {
448 compatible = "qcom,spi-qup-v2.2.1";
449 #address-cells = <1>;
450 #size-cells = <0>;
e8a7fdc5 451 reg = <0x078b5000 0x600>;
22592a22
S		 452 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
453 spi-max-frequency = <50000000>;
454 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
455 <&gcc GCC_BLSP1_AHB_CLK>;
456 clock-names = "core", "iface";
457 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
458 dma-names = "tx", "rx";
459 pinctrl-0 = <&spi_0_pins>;
460 pinctrl-names = "default";
461 status = "disabled";
462 };
463
464 blsp1_i2c2: i2c@78b6000 {
465 compatible = "qcom,i2c-qup-v2.2.1";
466 #address-cells = <1>;
467 #size-cells = <0>;
e8a7fdc5 468 reg = <0x078b6000 0x600>;
22592a22 469 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2374b99e
KK		 470 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
471 <&gcc GCC_BLSP1_AHB_CLK>;
472 clock-names = "core", "iface";
22592a22 473 clock-frequency = <400000>;
0e1b27f4
KK		 474 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
475 dma-names = "tx", "rx";
22592a22
S		 476 pinctrl-0 = <&i2c_0_pins>;
477 pinctrl-names = "default";
478 status = "disabled";
479 };
480
481 blsp1_i2c3: i2c@78b7000 {
482 compatible = "qcom,i2c-qup-v2.2.1";
483 #address-cells = <1>;
484 #size-cells = <0>;
e8a7fdc5 485 reg = <0x078b7000 0x600>;
22592a22 486 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2374b99e
KK		 487 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
488 <&gcc GCC_BLSP1_AHB_CLK>;
489 clock-names = "core", "iface";
22592a22 490 clock-frequency = <100000>;
0e1b27f4
KK		 491 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
492 dma-names = "tx", "rx";
22592a22
S		 493 status = "disabled";
494 };
495
9c0bd8e5
CP		 496 blsp1_i2c5: i2c@78b9000 {
497 compatible = "qcom,i2c-qup-v2.2.1";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 reg = <0x78b9000 0x600>;
501 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
2374b99e
KK		 502 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
503 <&gcc GCC_BLSP1_AHB_CLK>;
504 clock-names = "core", "iface";
9c0bd8e5 505 clock-frequency = <400000>;
0e1b27f4
KK		 506 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
507 dma-names = "tx", "rx";
9c0bd8e5
CP		 508 status = "disabled";
509 };
510
abe66bb7
RM		 511 blsp1_i2c6: i2c@78ba000 {
512 compatible = "qcom,i2c-qup-v2.2.1";
513 #address-cells = <1>;
514 #size-cells = <0>;
515 reg = <0x078ba000 0x600>;
516 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2374b99e
KK		 517 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
518 <&gcc GCC_BLSP1_AHB_CLK>;
519 clock-names = "core", "iface";
abe66bb7 520 clock-frequency = <100000>;
0e1b27f4
KK		 521 dmas = <&blsp_dma 22>, <&blsp_dma 23>;
522 dma-names = "tx", "rx";
abe66bb7
RM		 523 status = "disabled";
524 };
525
b7fbf46c 526 qpic_bam: dma-controller@7984000 {
22592a22 527 compatible = "qcom,bam-v1.7.0";
e8a7fdc5 528 reg = <0x07984000 0x1a000>;
22592a22
S		 529 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&gcc GCC_QPIC_AHB_CLK>;
531 clock-names = "bam_clk";
532 #dma-cells = <1>;
533 qcom,ee = <0>;
534 status = "disabled";
535 };
536
537 qpic_nand: nand@79b0000 {
538 compatible = "qcom,ipq8074-nand";
e8a7fdc5 539 reg = <0x079b0000 0x10000>;
22592a22
S		 540 #address-cells = <1>;
541 #size-cells = <0>;
542 clocks = <&gcc GCC_QPIC_CLK>,
543 <&gcc GCC_QPIC_AHB_CLK>;
544 clock-names = "core", "aon";
545
546 dmas = <&qpic_bam 0>,
547 <&qpic_bam 1>,
548 <&qpic_bam 2>;
549 dma-names = "tx", "rx", "cmd";
550 pinctrl-0 = <&qpic_pins>;
551 pinctrl-names = "default";
41dac73e
VN		 552 status = "disabled";
553 };
33057e16 554
5e09bc51 555 usb_0: usb@8af8800 {
3a6b8bf1 556 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
5e09bc51
SM		 557 reg = <0x08af8800 0x400>;
558 #address-cells = <1>;
559 #size-cells = <1>;
560 ranges;
561
562 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
563 <&gcc GCC_USB0_MASTER_CLK>,
564 <&gcc GCC_USB0_SLEEP_CLK>,
565 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
8d5fd4e4
KK		 566 clock-names = "cfg_noc",
567 "core",
5e09bc51
SM		 568 "sleep",
569 "mock_utmi";
570
571 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
572 <&gcc GCC_USB0_MASTER_CLK>,
573 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
574 assigned-clock-rates = <133330000>,
575 <133330000>,
576 <19200000>;
577
578 resets = <&gcc GCC_USB0_BCR>;
579 status = "disabled";
580
b77a1c4d 581 dwc_0: usb@8a00000 {
5e09bc51
SM		 582 compatible = "snps,dwc3";
583 reg = <0x8a00000 0xcd00>;
584 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
585 phys = <&qusb_phy_0>, <&usb0_ssphy>;
586 phy-names = "usb2-phy", "usb3-phy";
5e09bc51
SM		 587 snps,is-utmi-l1-suspend;
588 snps,hird-threshold = /bits/ 8 <0x0>;
589 snps,dis_u2_susphy_quirk;
590 snps,dis_u3_susphy_quirk;
591 dr_mode = "host";
592 };
593 };
594
595 usb_1: usb@8cf8800 {
3a6b8bf1 596 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
5e09bc51
SM		 597 reg = <0x08cf8800 0x400>;
598 #address-cells = <1>;
599 #size-cells = <1>;
600 ranges;
601
602 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
603 <&gcc GCC_USB1_MASTER_CLK>,
604 <&gcc GCC_USB1_SLEEP_CLK>,
605 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
8d5fd4e4
KK		 606 clock-names = "cfg_noc",
607 "core",
5e09bc51
SM		 608 "sleep",
609 "mock_utmi";
610
611 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
612 <&gcc GCC_USB1_MASTER_CLK>,
613 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
614 assigned-clock-rates = <133330000>,
615 <133330000>,
616 <19200000>;
617
618 resets = <&gcc GCC_USB1_BCR>;
619 status = "disabled";
620
b77a1c4d 621 dwc_1: usb@8c00000 {
5e09bc51
SM		 622 compatible = "snps,dwc3";
623 reg = <0x8c00000 0xcd00>;
624 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
625 phys = <&qusb_phy_1>, <&usb1_ssphy>;
626 phy-names = "usb2-phy", "usb3-phy";
5e09bc51
SM		 627 snps,is-utmi-l1-suspend;
628 snps,hird-threshold = /bits/ 8 <0x0>;
629 snps,dis_u2_susphy_quirk;
630 snps,dis_u3_susphy_quirk;
631 dr_mode = "host";
632 };
633 };
634
e8a7fdc5
SM		 635 intc: interrupt-controller@b000000 {
636 compatible = "qcom,msm-qgic2";
59892de9
K		 637 #address-cells = <1>;
638 #size-cells = <1>;
e8a7fdc5
SM		 639 interrupt-controller;
640 #interrupt-cells = <0x3>;
641 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
59892de9
K		 642 ranges = <0 0xb00a000 0xffd>;
643
644 v2m@0 {
645 compatible = "arm,gic-v2m-frame";
646 msi-controller;
647 reg = <0x0 0xffd>;
648 };
e8a7fdc5 649 };
33057e16 650
e8a7fdc5
SM		 651 timer {
652 compatible = "arm,armv8-timer";
653 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
654 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
655 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
656 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
33057e16
S		 657 };
658
949766e0
K		 659 watchdog: watchdog@b017000 {
660 compatible = "qcom,kpss-wdt";
661 reg = <0xb017000 0x1000>;
662 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
663 clocks = <&sleep_clk>;
664 timeout-sec = <30>;
665 };
666
e8a7fdc5
SM		 667 timer@b120000 {
668 #address-cells = <1>;
669 #size-cells = <1>;
670 ranges;
671 compatible = "arm,armv7-timer-mem";
672 reg = <0x0b120000 0x1000>;
33057e16 673
e8a7fdc5
SM		 674 frame@b120000 {
675 frame-number = <0>;
676 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
678 reg = <0x0b121000 0x1000>,
679 <0x0b122000 0x1000>;
680 };
33057e16 681
e8a7fdc5
SM		 682 frame@b123000 {
683 frame-number = <1>;
684 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
685 reg = <0x0b123000 0x1000>;
686 status = "disabled";
687 };
33057e16 688
e8a7fdc5
SM		 689 frame@b124000 {
690 frame-number = <2>;
691 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
692 reg = <0x0b124000 0x1000>;
693 status = "disabled";
694 };
33057e16 695
e8a7fdc5
SM		 696 frame@b125000 {
697 frame-number = <3>;
698 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
699 reg = <0x0b125000 0x1000>;
700 status = "disabled";
701 };
33057e16 702
e8a7fdc5
SM		 703 frame@b126000 {
704 frame-number = <4>;
705 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
706 reg = <0x0b126000 0x1000>;
707 status = "disabled";
708 };
33057e16 709
e8a7fdc5
SM		 710 frame@b127000 {
711 frame-number = <5>;
712 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
713 reg = <0x0b127000 0x1000>;
714 status = "disabled";
715 };
33057e16 716
e8a7fdc5
SM		 717 frame@b128000 {
718 frame-number = <6>;
719 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
720 reg = <0x0b128000 0x1000>;
721 status = "disabled";
722 };
33057e16
S		 723 };
724
725 pcie1: pci@10000000 {
726 compatible = "qcom,pcie-ipq8074";
52c9887f
VK		 727 reg = <0x10000000 0xf1d>,
728 <0x10000f20 0xa8>,
729 <0x00088000 0x2000>,
730 <0x10100000 0x1000>;
33057e16
S		 731 reg-names = "dbi", "elbi", "parf", "config";
732 device_type = "pci";
733 linux,pci-domain = <1>;
734 bus-range = <0x00 0xff>;
735 num-lanes = <1>;
736 #address-cells = <3>;
737 #size-cells = <2>;
738
739 phys = <&pcie_phy1>;
740 phy-names = "pciephy";
741
742 ranges = <0x81000000 0 0x10200000 0x10200000
743 0 0x100000 /* downstream I/O */
744 0x82000000 0 0x10300000 0x10300000
745 0 0xd00000>; /* non-prefetchable memory */
746
747 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
748 interrupt-names = "msi";
749 #interrupt-cells = <1>;
750 interrupt-map-mask = <0 0 0 0x7>;
751 interrupt-map = <0 0 0 1 &intc 0 142
752 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
753 <0 0 0 2 &intc 0 143
754 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
755 <0 0 0 3 &intc 0 144
756 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
757 <0 0 0 4 &intc 0 145
758 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
759
760 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
761 <&gcc GCC_PCIE1_AXI_M_CLK>,
762 <&gcc GCC_PCIE1_AXI_S_CLK>,
763 <&gcc GCC_PCIE1_AHB_CLK>,
764 <&gcc GCC_PCIE1_AUX_CLK>;
765 clock-names = "iface",
766 "axi_m",
767 "axi_s",
768 "ahb",
769 "aux";
770 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
771 <&gcc GCC_PCIE1_SLEEP_ARES>,
772 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
773 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
774 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
775 <&gcc GCC_PCIE1_AHB_ARES>,
776 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
777 reset-names = "pipe",
778 "sleep",
779 "sticky",
780 "axi_m",
781 "axi_s",
782 "ahb",
783 "axi_m_sticky";
784 status = "disabled";
785 };
41dac73e 786
e8a7fdc5
SM		 787 pcie0: pci@20000000 {
788 compatible = "qcom,pcie-ipq8074";
52c9887f
VK		 789 reg = <0x20000000 0xf1d>,
790 <0x20000f20 0xa8>,
791 <0x00080000 0x2000>,
792 <0x20100000 0x1000>;
e8a7fdc5
SM		 793 reg-names = "dbi", "elbi", "parf", "config";
794 device_type = "pci";
795 linux,pci-domain = <0>;
796 bus-range = <0x00 0xff>;
797 num-lanes = <1>;
798 #address-cells = <3>;
799 #size-cells = <2>;
41dac73e 800
e8a7fdc5
SM		 801 phys = <&pcie_phy0>;
802 phy-names = "pciephy";
41dac73e 803
e8a7fdc5
SM		 804 ranges = <0x81000000 0 0x20200000 0x20200000
805 0 0x100000 /* downstream I/O */
806 0x82000000 0 0x20300000 0x20300000
807 0 0xd00000>; /* non-prefetchable memory */
41dac73e 808
e8a7fdc5
SM		 809 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
810 interrupt-names = "msi";
811 #interrupt-cells = <1>;
812 interrupt-map-mask = <0 0 0 0x7>;
813 interrupt-map = <0 0 0 1 &intc 0 75
814 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
815 <0 0 0 2 &intc 0 78
816 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
817 <0 0 0 3 &intc 0 79
818 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
819 <0 0 0 4 &intc 0 83
820 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
41dac73e 821
e8a7fdc5
SM		 822 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
823 <&gcc GCC_PCIE0_AXI_M_CLK>,
824 <&gcc GCC_PCIE0_AXI_S_CLK>,
825 <&gcc GCC_PCIE0_AHB_CLK>,
826 <&gcc GCC_PCIE0_AUX_CLK>;
41dac73e 827
e8a7fdc5
SM		 828 clock-names = "iface",
829 "axi_m",
830 "axi_s",
831 "ahb",
832 "aux";
833 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
834 <&gcc GCC_PCIE0_SLEEP_ARES>,
835 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
836 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
837 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
838 <&gcc GCC_PCIE0_AHB_ARES>,
839 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
840 reset-names = "pipe",
841 "sleep",
842 "sticky",
843 "axi_m",
844 "axi_s",
845 "ahb",
846 "axi_m_sticky";
847 status = "disabled";
41dac73e
VN		 848 };
849 };
850};
Linux 6.x block layer and io_uring tree(s)