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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[linux-block.git] / arch / arm64 / boot / dts / nvidia / tegra132.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
34b4f6d0
TR		 2#include <dt-bindings/clock/tegra124-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra124-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
0fa2bfcd 8#include <dt-bindings/thermal/tegra124-soctherm.h>
34b4f6d0
TR		 9
10/ {
11 compatible = "nvidia,tegra132", "nvidia,tegra124";
12 interrupt-parent = <&lic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
475d99fc 16 pcie@1003000 {
34b4f6d0
TR		 17 compatible = "nvidia,tegra124-pcie";
18 device_type = "pci";
19 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
20 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
21 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
22 reg-names = "pads", "afi", "cs";
23 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
24 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
25 interrupt-names = "intr", "msi";
26
27 #interrupt-cells = <1>;
28 interrupt-map-mask = <0 0 0 0>;
29 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
30
31 bus-range = <0x00 0xff>;
32 #address-cells = <3>;
33 #size-cells = <2>;
34
35 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
36 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
37 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
38 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
39 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
40
41 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
42 <&tegra_car TEGRA124_CLK_AFI>,
43 <&tegra_car TEGRA124_CLK_PLL_E>,
44 <&tegra_car TEGRA124_CLK_CML0>;
45 clock-names = "pex", "afi", "pll_e", "cml";
46 resets = <&tegra_car 70>,
47 <&tegra_car 72>,
48 <&tegra_car 74>;
49 reset-names = "pex", "afi", "pcie_x";
50 status = "disabled";
51
52 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
53 phy-names = "pcie";
54
55 pci@1,0 {
56 device_type = "pci";
57 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
58 reg = <0x000800 0 0 0 0>;
475d99fc 59 bus-range = <0x00 0xff>;
34b4f6d0
TR		 60 status = "disabled";
61
62 #address-cells = <3>;
63 #size-cells = <2>;
64 ranges;
65
66 nvidia,num-lanes = <2>;
67 };
68
69 pci@2,0 {
70 device_type = "pci";
71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
72 reg = <0x001000 0 0 0 0>;
475d99fc 73 bus-range = <0x00 0xff>;
34b4f6d0
TR		 74 status = "disabled";
75
76 #address-cells = <3>;
77 #size-cells = <2>;
78 ranges;
79
80 nvidia,num-lanes = <1>;
81 };
82 };
83
be70771d 84 host1x@50000000 {
34b4f6d0
TR		 85 compatible = "nvidia,tegra124-host1x", "simple-bus";
86 reg = <0x0 0x50000000 0x0 0x00034000>;
87 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
88 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
90 clock-names = "host1x";
91 resets = <&tegra_car 28>;
92 reset-names = "host1x";
93
94 #address-cells = <2>;
95 #size-cells = <2>;
96
97 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
98
be70771d 99 dc@54200000 {
34b4f6d0
TR		 100 compatible = "nvidia,tegra124-dc";
101 reg = <0x0 0x54200000 0x0 0x00040000>;
102 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
104 <&tegra_car TEGRA124_CLK_PLL_P>;
105 clock-names = "dc", "parent";
106 resets = <&tegra_car 27>;
107 reset-names = "dc";
108
109 iommus = <&mc TEGRA_SWGROUP_DC>;
110
111 nvidia,head = <0>;
112 };
113
be70771d 114 dc@54240000 {
34b4f6d0
TR		 115 compatible = "nvidia,tegra124-dc";
116 reg = <0x0 0x54240000 0x0 0x00040000>;
117 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
119 <&tegra_car TEGRA124_CLK_PLL_P>;
120 clock-names = "dc", "parent";
121 resets = <&tegra_car 26>;
122 reset-names = "dc";
123
124 iommus = <&mc TEGRA_SWGROUP_DCB>;
125
126 nvidia,head = <1>;
127 };
128
be70771d 129 hdmi@54280000 {
34b4f6d0
TR		 130 compatible = "nvidia,tegra124-hdmi";
131 reg = <0x0 0x54280000 0x0 0x00040000>;
132 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
134 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
135 clock-names = "hdmi", "parent";
136 resets = <&tegra_car 51>;
137 reset-names = "hdmi";
138 status = "disabled";
139 };
140
be70771d 141 sor@54540000 {
34b4f6d0
TR		 142 compatible = "nvidia,tegra124-sor";
143 reg = <0x0 0x54540000 0x0 0x00040000>;
144 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
146 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
147 <&tegra_car TEGRA124_CLK_PLL_DP>,
148 <&tegra_car TEGRA124_CLK_CLK_M>;
149 clock-names = "sor", "parent", "dp", "safe";
150 resets = <&tegra_car 182>;
151 reset-names = "sor";
152 status = "disabled";
153 };
154
be70771d 155 dpaux: dpaux@545c0000 {
34b4f6d0
TR		 156 compatible = "nvidia,tegra124-dpaux";
157 reg = <0x0 0x545c0000 0x0 0x00040000>;
158 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
160 <&tegra_car TEGRA124_CLK_PLL_DP>;
161 clock-names = "dpaux", "parent";
162 resets = <&tegra_car 181>;
163 reset-names = "dpaux";
164 status = "disabled";
165 };
166 };
167
be70771d 168 gic: interrupt-controller@50041000 {
34b4f6d0
TR		 169 compatible = "arm,cortex-a15-gic";
170 #interrupt-cells = <3>;
171 interrupt-controller;
172 reg = <0x0 0x50041000 0x0 0x1000>,
173 <0x0 0x50042000 0x0 0x2000>,
174 <0x0 0x50044000 0x0 0x2000>,
175 <0x0 0x50046000 0x0 0x2000>;
176 interrupts = <GIC_PPI 9
177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
178 interrupt-parent = <&gic>;
179 };
180
be70771d 181 gpu@57000000 {
34b4f6d0
TR		 182 compatible = "nvidia,gk20a";
183 reg = <0x0 0x57000000 0x0 0x01000000>,
184 <0x0 0x58000000 0x0 0x01000000>;
185 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "stall", "nonstall";
188 clocks = <&tegra_car TEGRA124_CLK_GPU>,
189 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
190 clock-names = "gpu", "pwr";
191 resets = <&tegra_car 184>;
192 reset-names = "gpu";
193 status = "disabled";
194 };
195
196 lic: interrupt-controller@60004000 {
197 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
198 reg = <0x0 0x60004000 0x0 0x100>,
199 <0x0 0x60004100 0x0 0x100>,
200 <0x0 0x60004200 0x0 0x100>,
201 <0x0 0x60004300 0x0 0x100>,
202 <0x0 0x60004400 0x0 0x100>;
203 interrupt-controller;
204 #interrupt-cells = <3>;
205 interrupt-parent = <&gic>;
206 };
207
be70771d 208 timer@60005000 {
34b4f6d0
TR		 209 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
210 reg = <0x0 0x60005000 0x0 0x400>;
211 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
218 clock-names = "timer";
219 };
220
be70771d 221 tegra_car: clock@60006000 {
34b4f6d0
TR		 222 compatible = "nvidia,tegra132-car";
223 reg = <0x0 0x60006000 0x0 0x1000>;
224 #clock-cells = <1>;
225 #reset-cells = <1>;
226 nvidia,external-memory-controller = <&emc>;
227 };
228
be70771d 229 flow-controller@60007000 {
18236a14 230 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
34b4f6d0
TR		 231 reg = <0x0 0x60007000 0x0 0x1000>;
232 };
233
be70771d 234 actmon@6000c800 {
34b4f6d0
TR		 235 compatible = "nvidia,tegra124-actmon";
236 reg = <0x0 0x6000c800 0x0 0x400>;
237 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
239 <&tegra_car TEGRA124_CLK_EMC>;
240 clock-names = "actmon", "emc";
241 resets = <&tegra_car 119>;
242 reset-names = "actmon";
243 };
244
be70771d 245 gpio: gpio@6000d000 {
34b4f6d0
TR		 246 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
247 reg = <0x0 0x6000d000 0x0 0x1000>;
248 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
256 #gpio-cells = <2>;
257 gpio-controller;
258 #interrupt-cells = <2>;
259 interrupt-controller;
260 };
261
be70771d 262 apbdma: dma@60020000 {
34b4f6d0
TR		 263 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
264 reg = <0x0 0x60020000 0x0 0x1400>;
265 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
298 clock-names = "dma";
299 resets = <&tegra_car 34>;
300 reset-names = "dma";
301 #dma-cells = <1>;
302 };
303
be70771d 304 apbmisc@70000800 {
34b4f6d0
TR		 305 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
306 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
307 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
308 };
309
be70771d 310 pinmux: pinmux@70000868 {
34b4f6d0
TR		 311 compatible = "nvidia,tegra124-pinmux";
312 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
313 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
314 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
315 };
316
317 /*
318 * There are two serial driver i.e. 8250 based simple serial
319 * driver and APB DMA based serial driver for higher baudrate
ef769e32 320 * and performance. To enable the 8250 based driver, the compatible
34b4f6d0 321 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
68cd8b2e 322 * the APB DMA based serial driver, the compatible is
34b4f6d0
TR		 323 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
324 */
be70771d 325 uarta: serial@70006000 {
34b4f6d0
TR		 326 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
327 reg = <0x0 0x70006000 0x0 0x40>;
328 reg-shift = <2>;
329 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
331 clock-names = "serial";
332 resets = <&tegra_car 6>;
333 reset-names = "serial";
334 dmas = <&apbdma 8>, <&apbdma 8>;
335 dma-names = "rx", "tx";
336 status = "disabled";
337 };
338
be70771d 339 uartb: serial@70006040 {
34b4f6d0
TR		 340 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
341 reg = <0x0 0x70006040 0x0 0x40>;
342 reg-shift = <2>;
343 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
345 clock-names = "serial";
346 resets = <&tegra_car 7>;
347 reset-names = "serial";
348 dmas = <&apbdma 9>, <&apbdma 9>;
349 dma-names = "rx", "tx";
350 status = "disabled";
351 };
352
be70771d 353 uartc: serial@70006200 {
34b4f6d0
TR		 354 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
355 reg = <0x0 0x70006200 0x0 0x40>;
356 reg-shift = <2>;
357 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
359 clock-names = "serial";
360 resets = <&tegra_car 55>;
361 reset-names = "serial";
362 dmas = <&apbdma 10>, <&apbdma 10>;
363 dma-names = "rx", "tx";
364 status = "disabled";
365 };
366
be70771d 367 uartd: serial@70006300 {
34b4f6d0
TR		 368 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
369 reg = <0x0 0x70006300 0x0 0x40>;
370 reg-shift = <2>;
371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
373 clock-names = "serial";
374 resets = <&tegra_car 65>;
375 reset-names = "serial";
376 dmas = <&apbdma 19>, <&apbdma 19>;
377 dma-names = "rx", "tx";
378 status = "disabled";
379 };
380
be70771d 381 pwm: pwm@7000a000 {
34b4f6d0
TR		 382 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
383 reg = <0x0 0x7000a000 0x0 0x100>;
384 #pwm-cells = <2>;
385 clocks = <&tegra_car TEGRA124_CLK_PWM>;
386 clock-names = "pwm";
387 resets = <&tegra_car 17>;
388 reset-names = "pwm";
389 status = "disabled";
390 };
391
be70771d 392 i2c@7000c000 {
34b4f6d0
TR		 393 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
394 reg = <0x0 0x7000c000 0x0 0x100>;
395 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
396 #address-cells = <1>;
397 #size-cells = <0>;
398 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
399 clock-names = "div-clk";
400 resets = <&tegra_car 12>;
401 reset-names = "i2c";
402 dmas = <&apbdma 21>, <&apbdma 21>;
403 dma-names = "rx", "tx";
404 status = "disabled";
405 };
406
be70771d 407 i2c@7000c400 {
34b4f6d0
TR		 408 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
409 reg = <0x0 0x7000c400 0x0 0x100>;
410 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
411 #address-cells = <1>;
412 #size-cells = <0>;
413 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
414 clock-names = "div-clk";
415 resets = <&tegra_car 54>;
416 reset-names = "i2c";
417 dmas = <&apbdma 22>, <&apbdma 22>;
418 dma-names = "rx", "tx";
419 status = "disabled";
420 };
421
be70771d 422 i2c@7000c500 {
34b4f6d0
TR		 423 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
424 reg = <0x0 0x7000c500 0x0 0x100>;
425 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
429 clock-names = "div-clk";
430 resets = <&tegra_car 67>;
431 reset-names = "i2c";
432 dmas = <&apbdma 23>, <&apbdma 23>;
433 dma-names = "rx", "tx";
434 status = "disabled";
435 };
436
be70771d 437 i2c@7000c700 {
34b4f6d0
TR		 438 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
439 reg = <0x0 0x7000c700 0x0 0x100>;
440 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
444 clock-names = "div-clk";
445 resets = <&tegra_car 103>;
446 reset-names = "i2c";
447 dmas = <&apbdma 26>, <&apbdma 26>;
448 dma-names = "rx", "tx";
449 status = "disabled";
450 };
451
be70771d 452 i2c@7000d000 {
34b4f6d0
TR		 453 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
454 reg = <0x0 0x7000d000 0x0 0x100>;
455 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
459 clock-names = "div-clk";
460 resets = <&tegra_car 47>;
461 reset-names = "i2c";
462 dmas = <&apbdma 24>, <&apbdma 24>;
463 dma-names = "rx", "tx";
464 status = "disabled";
465 };
466
be70771d 467 i2c@7000d100 {
34b4f6d0
TR		 468 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
469 reg = <0x0 0x7000d100 0x0 0x100>;
470 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
474 clock-names = "div-clk";
475 resets = <&tegra_car 166>;
476 reset-names = "i2c";
477 dmas = <&apbdma 30>, <&apbdma 30>;
478 dma-names = "rx", "tx";
479 status = "disabled";
480 };
481
be70771d 482 spi@7000d400 {
34b4f6d0
TR		 483 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
484 reg = <0x0 0x7000d400 0x0 0x200>;
485 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
487 #size-cells = <0>;
488 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
489 clock-names = "spi";
490 resets = <&tegra_car 41>;
491 reset-names = "spi";
492 dmas = <&apbdma 15>, <&apbdma 15>;
493 dma-names = "rx", "tx";
494 status = "disabled";
495 };
496
be70771d 497 spi@7000d600 {
34b4f6d0
TR		 498 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
499 reg = <0x0 0x7000d600 0x0 0x200>;
500 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
504 clock-names = "spi";
505 resets = <&tegra_car 44>;
506 reset-names = "spi";
507 dmas = <&apbdma 16>, <&apbdma 16>;
508 dma-names = "rx", "tx";
509 status = "disabled";
510 };
511
be70771d 512 spi@7000d800 {
34b4f6d0
TR		 513 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
514 reg = <0x0 0x7000d800 0x0 0x200>;
515 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
519 clock-names = "spi";
520 resets = <&tegra_car 46>;
521 reset-names = "spi";
522 dmas = <&apbdma 17>, <&apbdma 17>;
523 dma-names = "rx", "tx";
524 status = "disabled";
525 };
526
be70771d 527 spi@7000da00 {
34b4f6d0
TR		 528 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
529 reg = <0x0 0x7000da00 0x0 0x200>;
530 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
534 clock-names = "spi";
535 resets = <&tegra_car 68>;
536 reset-names = "spi";
537 dmas = <&apbdma 18>, <&apbdma 18>;
538 dma-names = "rx", "tx";
539 status = "disabled";
540 };
541
be70771d 542 spi@7000dc00 {
34b4f6d0
TR		 543 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
544 reg = <0x0 0x7000dc00 0x0 0x200>;
545 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
547 #size-cells = <0>;
548 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
549 clock-names = "spi";
550 resets = <&tegra_car 104>;
551 reset-names = "spi";
552 dmas = <&apbdma 27>, <&apbdma 27>;
553 dma-names = "rx", "tx";
554 status = "disabled";
555 };
556
be70771d 557 spi@7000de00 {
34b4f6d0
TR		 558 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
559 reg = <0x0 0x7000de00 0x0 0x200>;
560 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
561 #address-cells = <1>;
562 #size-cells = <0>;
563 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
564 clock-names = "spi";
565 resets = <&tegra_car 105>;
566 reset-names = "spi";
567 dmas = <&apbdma 28>, <&apbdma 28>;
568 dma-names = "rx", "tx";
569 status = "disabled";
570 };
571
be70771d 572 rtc@7000e000 {
34b4f6d0
TR		 573 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
574 reg = <0x0 0x7000e000 0x0 0x100>;
575 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&tegra_car TEGRA124_CLK_RTC>;
577 clock-names = "rtc";
578 };
579
be70771d 580 pmc@7000e400 {
34b4f6d0
TR		 581 compatible = "nvidia,tegra124-pmc";
582 reg = <0x0 0x7000e400 0x0 0x400>;
583 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
584 clock-names = "pclk", "clk32k_in";
585 };
586
be70771d 587 fuse@7000f800 {
34b4f6d0
TR		 588 compatible = "nvidia,tegra124-efuse";
589 reg = <0x0 0x7000f800 0x0 0x400>;
590 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
591 clock-names = "fuse";
592 resets = <&tegra_car 39>;
593 reset-names = "fuse";
594 };
595
be70771d 596 mc: memory-controller@70019000 {
34b4f6d0
TR		 597 compatible = "nvidia,tegra132-mc";
598 reg = <0x0 0x70019000 0x0 0x1000>;
599 clocks = <&tegra_car TEGRA124_CLK_MC>;
600 clock-names = "mc";
601
602 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
603
604 #iommu-cells = <1>;
605 };
606
be70771d 607 emc: emc@7001b000 {
34b4f6d0
TR		 608 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
609 reg = <0x0 0x7001b000 0x0 0x1000>;
610
611 nvidia,memory-controller = <&mc>;
612 };
613
be70771d 614 sata@70020000 {
34b4f6d0
TR		 615 compatible = "nvidia,tegra124-ahci";
616 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
617 <0x0 0x70020000 0x0 0x7000>; /* SATA */
618 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&tegra_car TEGRA124_CLK_SATA>,
620 <&tegra_car TEGRA124_CLK_SATA_OOB>,
621 <&tegra_car TEGRA124_CLK_CML1>,
622 <&tegra_car TEGRA124_CLK_PLL_E>;
623 clock-names = "sata", "sata-oob", "cml1", "pll_e";
624 resets = <&tegra_car 124>,
625 <&tegra_car 123>,
626 <&tegra_car 129>;
627 reset-names = "sata", "sata-oob", "sata-cold";
628 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
629 phy-names = "sata-phy";
630 status = "disabled";
631 };
632
be70771d 633 hda@70030000 {
34b4f6d0
TR		 634 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
635 "nvidia,tegra30-hda";
636 reg = <0x0 0x70030000 0x0 0x10000>;
637 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&tegra_car TEGRA124_CLK_HDA>,
639 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
640 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
641 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
642 resets = <&tegra_car 125>, /* hda */
643 <&tegra_car 128>, /* hda2hdmi */
644 <&tegra_car 111>; /* hda2codec_2x */
645 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
646 status = "disabled";
647 };
648
be70771d 649 padctl: padctl@7009f000 {
34b4f6d0
TR		 650 compatible = "nvidia,tegra132-xusb-padctl",
651 "nvidia,tegra124-xusb-padctl";
652 reg = <0x0 0x7009f000 0x0 0x1000>;
653 resets = <&tegra_car 142>;
654 reset-names = "padctl";
655
656 #phy-cells = <1>;
657
658 phys {
659 pcie-0 {
660 status = "disabled";
661 };
662
663 sata-0 {
664 status = "disabled";
665 };
666
667 usb3-0 {
668 status = "disabled";
669 };
670
671 usb3-1 {
672 status = "disabled";
673 };
674
675 utmi-0 {
676 status = "disabled";
677 };
678
679 utmi-1 {
680 status = "disabled";
681 };
682
683 utmi-2 {
684 status = "disabled";
685 };
686 };
687 };
688
be70771d 689 sdhci@700b0000 {
34b4f6d0
TR		 690 compatible = "nvidia,tegra124-sdhci";
691 reg = <0x0 0x700b0000 0x0 0x200>;
692 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
694 clock-names = "sdhci";
695 resets = <&tegra_car 14>;
696 reset-names = "sdhci";
697 status = "disabled";
698 };
699
be70771d 700 sdhci@700b0200 {
34b4f6d0
TR		 701 compatible = "nvidia,tegra124-sdhci";
702 reg = <0x0 0x700b0200 0x0 0x200>;
703 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
705 clock-names = "sdhci";
706 resets = <&tegra_car 9>;
707 reset-names = "sdhci";
708 status = "disabled";
709 };
710
be70771d 711 sdhci@700b0400 {
34b4f6d0
TR		 712 compatible = "nvidia,tegra124-sdhci";
713 reg = <0x0 0x700b0400 0x0 0x200>;
714 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
716 clock-names = "sdhci";
717 resets = <&tegra_car 69>;
718 reset-names = "sdhci";
719 status = "disabled";
720 };
721
be70771d 722 sdhci@700b0600 {
34b4f6d0
TR		 723 compatible = "nvidia,tegra124-sdhci";
724 reg = <0x0 0x700b0600 0x0 0x200>;
725 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
727 clock-names = "sdhci";
728 resets = <&tegra_car 15>;
729 reset-names = "sdhci";
730 status = "disabled";
731 };
732
be70771d 733 soctherm: thermal-sensor@700e2000 {
0fa2bfcd 734 compatible = "nvidia,tegra132-soctherm";
f4357938
WN		 735 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */
736 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
737 reg-names = "soctherm-reg", "ccroc-reg";
34b4f6d0
TR		 738 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
740 <&tegra_car TEGRA124_CLK_SOC_THERM>;
741 clock-names = "tsensor", "soctherm";
742 resets = <&tegra_car 78>;
743 reset-names = "soctherm";
744 #thermal-sensor-cells = <1>;
f4357938
WN		 745
746 throttle-cfgs {
747 throttle_heavy: heavy {
748 nvidia,priority = <100>;
749 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
750
751 #cooling-cells = <2>;
752 };
753 };
34b4f6d0
TR		 754 };
755
0fa2bfcd
WN		 756 thermal-zones {
757 cpu {
758 polling-delay-passive = <1000>;
759 polling-delay = <0>;
760
761 thermal-sensors =
762 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
a6ebde25
WN		 763
764 trips {
765 cpu_shutdown_trip {
766 temperature = <105000>;
767 hysteresis = <1000>;
768 type = "critical";
769 };
f4357938
WN		 770
771 cpu_throttle_trip: throttle-trip {
772 temperature = <102000>;
773 hysteresis = <1000>;
774 type = "hot";
775 };
a6ebde25
WN		 776 };
777
778 cooling-maps {
f4357938
WN		 779 map0 {
780 trip = <&cpu_throttle_trip>;
781 cooling-device = <&throttle_heavy 1 1>;
782 };
a6ebde25 783 };
0fa2bfcd
WN		 784 };
785 mem {
786 polling-delay-passive = <0>;
787 polling-delay = <0>;
788
789 thermal-sensors =
790 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
a6ebde25
WN		 791
792 trips {
793 mem_shutdown_trip {
794 temperature = <101000>;
795 hysteresis = <1000>;
796 type = "critical";
797 };
798 };
799
800 cooling-maps {
801 /*
802 * There are currently no cooling maps,
803 * because there are no cooling devices.
804 */
805 };
0fa2bfcd
WN		 806 };
807 gpu {
808 polling-delay-passive = <1000>;
809 polling-delay = <0>;
810
811 thermal-sensors =
812 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
a6ebde25
WN		 813
814 trips {
815 gpu_shutdown_trip {
816 temperature = <101000>;
817 hysteresis = <1000>;
818 type = "critical";
819 };
f4357938
WN		 820
821 gpu_throttle_trip: throttle-trip {
822 temperature = <99000>;
823 hysteresis = <1000>;
824 type = "hot";
825 };
a6ebde25
WN		 826 };
827
828 cooling-maps {
f4357938
WN		 829 map0 {
830 trip = <&gpu_throttle_trip>;
831 cooling-device = <&throttle_heavy 1 1>;
832 };
a6ebde25 833 };
0fa2bfcd
WN		 834 };
835 pllx {
836 polling-delay-passive = <0>;
837 polling-delay = <0>;
838
839 thermal-sensors =
840 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
a6ebde25
WN		 841
842 trips {
843 pllx_shutdown_trip {
844 temperature = <105000>;
845 hysteresis = <1000>;
846 type = "critical";
847 };
848 };
849
850 cooling-maps {
851 /*
852 * There are currently no cooling maps,
853 * because there are no cooling devices.
854 */
855 };
0fa2bfcd
WN		 856 };
857 };
858
be70771d 859 ahub@70300000 {
34b4f6d0
TR		 860 compatible = "nvidia,tegra124-ahub";
861 reg = <0x0 0x70300000 0x0 0x200>,
862 <0x0 0x70300800 0x0 0x800>,
863 <0x0 0x70300200 0x0 0x600>;
864 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
866 <&tegra_car TEGRA124_CLK_APBIF>;
867 clock-names = "d_audio", "apbif";
868 resets = <&tegra_car 106>, /* d_audio */
869 <&tegra_car 107>, /* apbif */
870 <&tegra_car 30>, /* i2s0 */
871 <&tegra_car 11>, /* i2s1 */
872 <&tegra_car 18>, /* i2s2 */
873 <&tegra_car 101>, /* i2s3 */
874 <&tegra_car 102>, /* i2s4 */
875 <&tegra_car 108>, /* dam0 */
876 <&tegra_car 109>, /* dam1 */
877 <&tegra_car 110>, /* dam2 */
878 <&tegra_car 10>, /* spdif */
879 <&tegra_car 153>, /* amx */
880 <&tegra_car 185>, /* amx1 */
881 <&tegra_car 154>, /* adx */
882 <&tegra_car 180>, /* adx1 */
883 <&tegra_car 186>, /* afc0 */
884 <&tegra_car 187>, /* afc1 */
885 <&tegra_car 188>, /* afc2 */
886 <&tegra_car 189>, /* afc3 */
887 <&tegra_car 190>, /* afc4 */
888 <&tegra_car 191>; /* afc5 */
889 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
890 "i2s3", "i2s4", "dam0", "dam1", "dam2",
891 "spdif", "amx", "amx1", "adx", "adx1",
892 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
893 dmas = <&apbdma 1>, <&apbdma 1>,
894 <&apbdma 2>, <&apbdma 2>,
895 <&apbdma 3>, <&apbdma 3>,
896 <&apbdma 4>, <&apbdma 4>,
897 <&apbdma 6>, <&apbdma 6>,
898 <&apbdma 7>, <&apbdma 7>,
899 <&apbdma 12>, <&apbdma 12>,
900 <&apbdma 13>, <&apbdma 13>,
901 <&apbdma 14>, <&apbdma 14>,
902 <&apbdma 29>, <&apbdma 29>;
903 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
904 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
905 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
906 "rx9", "tx9";
907 ranges;
908 #address-cells = <2>;
909 #size-cells = <2>;
910
be70771d 911 tegra_i2s0: i2s@70301000 {
34b4f6d0
TR		 912 compatible = "nvidia,tegra124-i2s";
913 reg = <0x0 0x70301000 0x0 0x100>;
914 nvidia,ahub-cif-ids = <4 4>;
915 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
916 clock-names = "i2s";
917 resets = <&tegra_car 30>;
918 reset-names = "i2s";
919 status = "disabled";
920 };
921
be70771d 922 tegra_i2s1: i2s@70301100 {
34b4f6d0
TR		 923 compatible = "nvidia,tegra124-i2s";
924 reg = <0x0 0x70301100 0x0 0x100>;
925 nvidia,ahub-cif-ids = <5 5>;
926 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
927 clock-names = "i2s";
928 resets = <&tegra_car 11>;
929 reset-names = "i2s";
930 status = "disabled";
931 };
932
be70771d 933 tegra_i2s2: i2s@70301200 {
34b4f6d0
TR		 934 compatible = "nvidia,tegra124-i2s";
935 reg = <0x0 0x70301200 0x0 0x100>;
936 nvidia,ahub-cif-ids = <6 6>;
937 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
938 clock-names = "i2s";
939 resets = <&tegra_car 18>;
940 reset-names = "i2s";
941 status = "disabled";
942 };
943
be70771d 944 tegra_i2s3: i2s@70301300 {
34b4f6d0
TR		 945 compatible = "nvidia,tegra124-i2s";
946 reg = <0x0 0x70301300 0x0 0x100>;
947 nvidia,ahub-cif-ids = <7 7>;
948 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
949 clock-names = "i2s";
950 resets = <&tegra_car 101>;
951 reset-names = "i2s";
952 status = "disabled";
953 };
954
be70771d 955 tegra_i2s4: i2s@70301400 {
34b4f6d0
TR		 956 compatible = "nvidia,tegra124-i2s";
957 reg = <0x0 0x70301400 0x0 0x100>;
958 nvidia,ahub-cif-ids = <8 8>;
959 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
960 clock-names = "i2s";
961 resets = <&tegra_car 102>;
962 reset-names = "i2s";
963 status = "disabled";
964 };
965 };
966
be70771d 967 usb@7d000000 {
34b4f6d0
TR		 968 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
969 reg = <0x0 0x7d000000 0x0 0x4000>;
970 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
971 phy_type = "utmi";
972 clocks = <&tegra_car TEGRA124_CLK_USBD>;
973 clock-names = "usb";
974 resets = <&tegra_car 22>;
975 reset-names = "usb";
976 nvidia,phy = <&phy1>;
977 status = "disabled";
978 };
979
be70771d 980 phy1: usb-phy@7d000000 {
34b4f6d0
TR		 981 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
982 reg = <0x0 0x7d000000 0x0 0x4000>,
983 <0x0 0x7d000000 0x0 0x4000>;
984 phy_type = "utmi";
985 clocks = <&tegra_car TEGRA124_CLK_USBD>,
986 <&tegra_car TEGRA124_CLK_PLL_U>,
987 <&tegra_car TEGRA124_CLK_USBD>;
988 clock-names = "reg", "pll_u", "utmi-pads";
989 resets = <&tegra_car 22>, <&tegra_car 22>;
990 reset-names = "usb", "utmi-pads";
991 nvidia,hssync-start-delay = <0>;
992 nvidia,idle-wait-delay = <17>;
993 nvidia,elastic-limit = <16>;
994 nvidia,term-range-adj = <6>;
995 nvidia,xcvr-setup = <9>;
996 nvidia,xcvr-lsfslew = <0>;
997 nvidia,xcvr-lsrslew = <3>;
998 nvidia,hssquelch-level = <2>;
999 nvidia,hsdiscon-level = <5>;
1000 nvidia,xcvr-hsslew = <12>;
1001 nvidia,has-utmi-pad-registers;
1002 status = "disabled";
1003 };
1004
be70771d 1005 usb@7d004000 {
34b4f6d0
TR		 1006 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1007 reg = <0x0 0x7d004000 0x0 0x4000>;
1008 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1009 phy_type = "utmi";
1010 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1011 clock-names = "usb";
1012 resets = <&tegra_car 58>;
1013 reset-names = "usb";
1014 nvidia,phy = <&phy2>;
1015 status = "disabled";
1016 };
1017
be70771d 1018 phy2: usb-phy@7d004000 {
34b4f6d0
TR		 1019 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1020 reg = <0x0 0x7d004000 0x0 0x4000>,
1021 <0x0 0x7d000000 0x0 0x4000>;
1022 phy_type = "utmi";
1023 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1024 <&tegra_car TEGRA124_CLK_PLL_U>,
1025 <&tegra_car TEGRA124_CLK_USBD>;
1026 clock-names = "reg", "pll_u", "utmi-pads";
1027 resets = <&tegra_car 58>, <&tegra_car 22>;
1028 reset-names = "usb", "utmi-pads";
1029 nvidia,hssync-start-delay = <0>;
1030 nvidia,idle-wait-delay = <17>;
1031 nvidia,elastic-limit = <16>;
1032 nvidia,term-range-adj = <6>;
1033 nvidia,xcvr-setup = <9>;
1034 nvidia,xcvr-lsfslew = <0>;
1035 nvidia,xcvr-lsrslew = <3>;
1036 nvidia,hssquelch-level = <2>;
1037 nvidia,hsdiscon-level = <5>;
1038 nvidia,xcvr-hsslew = <12>;
1039 status = "disabled";
1040 };
1041
be70771d 1042 usb@7d008000 {
34b4f6d0
TR		 1043 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1044 reg = <0x0 0x7d008000 0x0 0x4000>;
1045 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1046 phy_type = "utmi";
1047 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1048 clock-names = "usb";
1049 resets = <&tegra_car 59>;
1050 reset-names = "usb";
1051 nvidia,phy = <&phy3>;
1052 status = "disabled";
1053 };
1054
be70771d 1055 phy3: usb-phy@7d008000 {
34b4f6d0
TR		 1056 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1057 reg = <0x0 0x7d008000 0x0 0x4000>,
1058 <0x0 0x7d000000 0x0 0x4000>;
1059 phy_type = "utmi";
1060 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1061 <&tegra_car TEGRA124_CLK_PLL_U>,
1062 <&tegra_car TEGRA124_CLK_USBD>;
1063 clock-names = "reg", "pll_u", "utmi-pads";
1064 resets = <&tegra_car 59>, <&tegra_car 22>;
1065 reset-names = "usb", "utmi-pads";
1066 nvidia,hssync-start-delay = <0>;
1067 nvidia,idle-wait-delay = <17>;
1068 nvidia,elastic-limit = <16>;
1069 nvidia,term-range-adj = <6>;
1070 nvidia,xcvr-setup = <9>;
1071 nvidia,xcvr-lsfslew = <0>;
1072 nvidia,xcvr-lsrslew = <3>;
1073 nvidia,hssquelch-level = <2>;
1074 nvidia,hsdiscon-level = <5>;
1075 nvidia,xcvr-hsslew = <12>;
1076 status = "disabled";
1077 };
1078
1079 cpus {
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082
1083 cpu@0 {
1084 device_type = "cpu";
1085 compatible = "nvidia,denver", "arm,armv8";
1086 reg = <0>;
1087 };
1088
1089 cpu@1 {
1090 device_type = "cpu";
1091 compatible = "nvidia,denver", "arm,armv8";
1092 reg = <1>;
1093 };
1094 };
1095
1096 timer {
1097 compatible = "arm,armv7-timer";
1098 interrupts = <GIC_PPI 13
1099 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1100 <GIC_PPI 14
1101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1102 <GIC_PPI 11
1103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1104 <GIC_PPI 10
1105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1106 interrupt-parent = <&gic>;
1107 };
1108};
Linux 6.x block layer and io_uring tree(s)