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arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zones
[linux-2.6-block.git] / arch / arm64 / boot / dts / nvidia / tegra132.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
34b4f6d0
TR		 2#include <dt-bindings/clock/tegra124-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra124-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
0fa2bfcd 8#include <dt-bindings/thermal/tegra124-soctherm.h>
359ae651 9#include <dt-bindings/soc/tegra-pmc.h>
34b4f6d0
TR		 10
11/ {
12 compatible = "nvidia,tegra132", "nvidia,tegra124";
13 interrupt-parent = <&lic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
475d99fc 17 pcie@1003000 {
34b4f6d0
TR		 18 compatible = "nvidia,tegra124-pcie";
19 device_type = "pci";
644c569d
TR		 20 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
21 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
22 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
34b4f6d0
TR		 23 reg-names = "pads", "afi", "cs";
24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26 interrupt-names = "intr", "msi";
27
28 #interrupt-cells = <1>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
31
32 bus-range = <0x00 0xff>;
33 #address-cells = <3>;
34 #size-cells = <2>;
35
644c569d
TR		 36 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
37 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
38 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
39 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
40 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
34b4f6d0
TR		 41
42 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
43 <&tegra_car TEGRA124_CLK_AFI>,
44 <&tegra_car TEGRA124_CLK_PLL_E>,
45 <&tegra_car TEGRA124_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
48 <&tegra_car 72>,
49 <&tegra_car 74>;
50 reset-names = "pex", "afi", "pcie_x";
51 status = "disabled";
52
34b4f6d0
TR		 53 pci@1,0 {
54 device_type = "pci";
55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
475d99fc 57 bus-range = <0x00 0xff>;
34b4f6d0
TR		 58 status = "disabled";
59
60 #address-cells = <3>;
61 #size-cells = <2>;
62 ranges;
63
64 nvidia,num-lanes = <2>;
65 };
66
67 pci@2,0 {
68 device_type = "pci";
69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70 reg = <0x001000 0 0 0 0>;
475d99fc 71 bus-range = <0x00 0xff>;
34b4f6d0
TR		 72 status = "disabled";
73
74 #address-cells = <3>;
75 #size-cells = <2>;
76 ranges;
77
78 nvidia,num-lanes = <1>;
79 };
80 };
81
be70771d 82 host1x@50000000 {
01a9d523 83 compatible = "nvidia,tegra132-host1x",
ef126bc4 84 "nvidia,tegra124-host1x";
34b4f6d0
TR		 85 reg = <0x0 0x50000000 0x0 0x00034000>;
86 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
87 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
052d3f65 88 interrupt-names = "syncpt", "host1x";
34b4f6d0
TR		 89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
90 clock-names = "host1x";
91 resets = <&tegra_car 28>;
92 reset-names = "host1x";
93
94 #address-cells = <2>;
95 #size-cells = <2>;
96
97 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
98
be70771d 99 dc@54200000 {
34b4f6d0
TR		 100 compatible = "nvidia,tegra124-dc";
101 reg = <0x0 0x54200000 0x0 0x00040000>;
102 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
352092b0
TR		 103 clocks = <&tegra_car TEGRA124_CLK_DISP1>;
104 clock-names = "dc";
34b4f6d0
TR		 105 resets = <&tegra_car 27>;
106 reset-names = "dc";
107
108 iommus = <&mc TEGRA_SWGROUP_DC>;
109
110 nvidia,head = <0>;
111 };
112
be70771d 113 dc@54240000 {
34b4f6d0
TR		 114 compatible = "nvidia,tegra124-dc";
115 reg = <0x0 0x54240000 0x0 0x00040000>;
116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
352092b0
TR		 117 clocks = <&tegra_car TEGRA124_CLK_DISP2>;
118 clock-names = "dc";
34b4f6d0
TR		 119 resets = <&tegra_car 26>;
120 reset-names = "dc";
121
122 iommus = <&mc TEGRA_SWGROUP_DCB>;
123
124 nvidia,head = <1>;
125 };
126
be70771d 127 hdmi@54280000 {
34b4f6d0
TR		 128 compatible = "nvidia,tegra124-hdmi";
129 reg = <0x0 0x54280000 0x0 0x00040000>;
130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
132 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
133 clock-names = "hdmi", "parent";
134 resets = <&tegra_car 51>;
135 reset-names = "hdmi";
136 status = "disabled";
137 };
138
be70771d 139 sor@54540000 {
34b4f6d0
TR		 140 compatible = "nvidia,tegra124-sor";
141 reg = <0x0 0x54540000 0x0 0x00040000>;
142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
abc9c8a5 144 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
34b4f6d0
TR		 145 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
146 <&tegra_car TEGRA124_CLK_PLL_DP>,
147 <&tegra_car TEGRA124_CLK_CLK_M>;
abc9c8a5 148 clock-names = "sor", "out", "parent", "dp", "safe";
34b4f6d0
TR		 149 resets = <&tegra_car 182>;
150 reset-names = "sor";
151 status = "disabled";
152 };
153
be70771d 154 dpaux: dpaux@545c0000 {
34b4f6d0
TR		 155 compatible = "nvidia,tegra124-dpaux";
156 reg = <0x0 0x545c0000 0x0 0x00040000>;
157 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
159 <&tegra_car TEGRA124_CLK_PLL_DP>;
160 clock-names = "dpaux", "parent";
161 resets = <&tegra_car 181>;
162 reset-names = "dpaux";
163 status = "disabled";
997a3b73
TR		 164
165 i2c-bus {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 };
34b4f6d0
TR		 169 };
170 };
171
be70771d 172 gic: interrupt-controller@50041000 {
34b4f6d0
TR		 173 compatible = "arm,cortex-a15-gic";
174 #interrupt-cells = <3>;
175 interrupt-controller;
176 reg = <0x0 0x50041000 0x0 0x1000>,
177 <0x0 0x50042000 0x0 0x2000>,
178 <0x0 0x50044000 0x0 0x2000>,
179 <0x0 0x50046000 0x0 0x2000>;
180 interrupts = <GIC_PPI 9
181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
182 interrupt-parent = <&gic>;
183 };
184
be70771d 185 gpu@57000000 {
34b4f6d0
TR		 186 compatible = "nvidia,gk20a";
187 reg = <0x0 0x57000000 0x0 0x01000000>,
188 <0x0 0x58000000 0x0 0x01000000>;
189 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-names = "stall", "nonstall";
192 clocks = <&tegra_car TEGRA124_CLK_GPU>,
193 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
194 clock-names = "gpu", "pwr";
195 resets = <&tegra_car 184>;
196 reset-names = "gpu";
197 status = "disabled";
198 };
199
200 lic: interrupt-controller@60004000 {
201 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
202 reg = <0x0 0x60004000 0x0 0x100>,
203 <0x0 0x60004100 0x0 0x100>,
204 <0x0 0x60004200 0x0 0x100>,
205 <0x0 0x60004300 0x0 0x100>,
206 <0x0 0x60004400 0x0 0x100>;
207 interrupt-controller;
208 #interrupt-cells = <3>;
209 interrupt-parent = <&gic>;
210 };
211
be70771d 212 timer@60005000 {
34b4f6d0
TR		 213 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
214 reg = <0x0 0x60005000 0x0 0x400>;
215 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
222 clock-names = "timer";
223 };
224
be70771d 225 tegra_car: clock@60006000 {
34b4f6d0
TR		 226 compatible = "nvidia,tegra132-car";
227 reg = <0x0 0x60006000 0x0 0x1000>;
228 #clock-cells = <1>;
229 #reset-cells = <1>;
230 nvidia,external-memory-controller = <&emc>;
231 };
232
be70771d 233 flow-controller@60007000 {
18236a14 234 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
34b4f6d0
TR		 235 reg = <0x0 0x60007000 0x0 0x1000>;
236 };
237
be70771d 238 actmon@6000c800 {
34b4f6d0
TR		 239 compatible = "nvidia,tegra124-actmon";
240 reg = <0x0 0x6000c800 0x0 0x400>;
241 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
243 <&tegra_car TEGRA124_CLK_EMC>;
244 clock-names = "actmon", "emc";
245 resets = <&tegra_car 119>;
246 reset-names = "actmon";
247 };
248
be70771d 249 gpio: gpio@6000d000 {
34b4f6d0
TR		 250 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
251 reg = <0x0 0x6000d000 0x0 0x1000>;
252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
260 #gpio-cells = <2>;
261 gpio-controller;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 };
265
be70771d 266 apbdma: dma@60020000 {
34b4f6d0
TR		 267 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
268 reg = <0x0 0x60020000 0x0 0x1400>;
269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
302 clock-names = "dma";
303 resets = <&tegra_car 34>;
304 reset-names = "dma";
305 #dma-cells = <1>;
306 };
307
be70771d 308 apbmisc@70000800 {
34b4f6d0
TR		 309 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
310 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
311 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
312 };
313
be70771d 314 pinmux: pinmux@70000868 {
34b4f6d0
TR		 315 compatible = "nvidia,tegra124-pinmux";
316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
317 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
318 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
319 };
320
321 /*
322 * There are two serial driver i.e. 8250 based simple serial
323 * driver and APB DMA based serial driver for higher baudrate
ef769e32 324 * and performance. To enable the 8250 based driver, the compatible
34b4f6d0 325 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
68cd8b2e 326 * the APB DMA based serial driver, the compatible is
34b4f6d0
TR		 327 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
328 */
be70771d 329 uarta: serial@70006000 {
34b4f6d0
TR		 330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
331 reg = <0x0 0x70006000 0x0 0x40>;
332 reg-shift = <2>;
333 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
335 clock-names = "serial";
336 resets = <&tegra_car 6>;
337 reset-names = "serial";
338 dmas = <&apbdma 8>, <&apbdma 8>;
339 dma-names = "rx", "tx";
340 status = "disabled";
341 };
342
be70771d 343 uartb: serial@70006040 {
34b4f6d0
TR		 344 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
345 reg = <0x0 0x70006040 0x0 0x40>;
346 reg-shift = <2>;
347 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
349 clock-names = "serial";
350 resets = <&tegra_car 7>;
351 reset-names = "serial";
352 dmas = <&apbdma 9>, <&apbdma 9>;
353 dma-names = "rx", "tx";
354 status = "disabled";
355 };
356
be70771d 357 uartc: serial@70006200 {
34b4f6d0
TR		 358 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
359 reg = <0x0 0x70006200 0x0 0x40>;
360 reg-shift = <2>;
361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
363 clock-names = "serial";
364 resets = <&tegra_car 55>;
365 reset-names = "serial";
366 dmas = <&apbdma 10>, <&apbdma 10>;
367 dma-names = "rx", "tx";
368 status = "disabled";
369 };
370
be70771d 371 uartd: serial@70006300 {
34b4f6d0
TR		 372 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
373 reg = <0x0 0x70006300 0x0 0x40>;
374 reg-shift = <2>;
375 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
377 clock-names = "serial";
378 resets = <&tegra_car 65>;
379 reset-names = "serial";
380 dmas = <&apbdma 19>, <&apbdma 19>;
381 dma-names = "rx", "tx";
382 status = "disabled";
383 };
384
be70771d 385 pwm: pwm@7000a000 {
34b4f6d0
TR		 386 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
387 reg = <0x0 0x7000a000 0x0 0x100>;
388 #pwm-cells = <2>;
389 clocks = <&tegra_car TEGRA124_CLK_PWM>;
390 clock-names = "pwm";
391 resets = <&tegra_car 17>;
392 reset-names = "pwm";
393 status = "disabled";
394 };
395
be70771d 396 i2c@7000c000 {
34b4f6d0
TR		 397 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
398 reg = <0x0 0x7000c000 0x0 0x100>;
399 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
400 #address-cells = <1>;
401 #size-cells = <0>;
402 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
403 clock-names = "div-clk";
404 resets = <&tegra_car 12>;
405 reset-names = "i2c";
406 dmas = <&apbdma 21>, <&apbdma 21>;
407 dma-names = "rx", "tx";
408 status = "disabled";
409 };
410
be70771d 411 i2c@7000c400 {
34b4f6d0
TR		 412 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
413 reg = <0x0 0x7000c400 0x0 0x100>;
414 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
416 #size-cells = <0>;
417 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
418 clock-names = "div-clk";
419 resets = <&tegra_car 54>;
420 reset-names = "i2c";
421 dmas = <&apbdma 22>, <&apbdma 22>;
422 dma-names = "rx", "tx";
423 status = "disabled";
424 };
425
be70771d 426 i2c@7000c500 {
34b4f6d0
TR		 427 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
428 reg = <0x0 0x7000c500 0x0 0x100>;
429 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
433 clock-names = "div-clk";
434 resets = <&tegra_car 67>;
435 reset-names = "i2c";
436 dmas = <&apbdma 23>, <&apbdma 23>;
437 dma-names = "rx", "tx";
438 status = "disabled";
439 };
440
be70771d 441 i2c@7000c700 {
34b4f6d0
TR		 442 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
443 reg = <0x0 0x7000c700 0x0 0x100>;
444 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
445 #address-cells = <1>;
446 #size-cells = <0>;
447 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
448 clock-names = "div-clk";
449 resets = <&tegra_car 103>;
450 reset-names = "i2c";
451 dmas = <&apbdma 26>, <&apbdma 26>;
452 dma-names = "rx", "tx";
453 status = "disabled";
454 };
455
be70771d 456 i2c@7000d000 {
34b4f6d0
TR		 457 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
458 reg = <0x0 0x7000d000 0x0 0x100>;
459 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>;
461 #size-cells = <0>;
462 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
463 clock-names = "div-clk";
464 resets = <&tegra_car 47>;
465 reset-names = "i2c";
466 dmas = <&apbdma 24>, <&apbdma 24>;
467 dma-names = "rx", "tx";
468 status = "disabled";
469 };
470
be70771d 471 i2c@7000d100 {
34b4f6d0
TR		 472 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
473 reg = <0x0 0x7000d100 0x0 0x100>;
474 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
478 clock-names = "div-clk";
479 resets = <&tegra_car 166>;
480 reset-names = "i2c";
481 dmas = <&apbdma 30>, <&apbdma 30>;
482 dma-names = "rx", "tx";
483 status = "disabled";
484 };
485
be70771d 486 spi@7000d400 {
34b4f6d0
TR		 487 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
488 reg = <0x0 0x7000d400 0x0 0x200>;
489 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
493 clock-names = "spi";
494 resets = <&tegra_car 41>;
495 reset-names = "spi";
496 dmas = <&apbdma 15>, <&apbdma 15>;
497 dma-names = "rx", "tx";
498 status = "disabled";
499 };
500
be70771d 501 spi@7000d600 {
34b4f6d0
TR		 502 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
503 reg = <0x0 0x7000d600 0x0 0x200>;
504 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
508 clock-names = "spi";
509 resets = <&tegra_car 44>;
510 reset-names = "spi";
511 dmas = <&apbdma 16>, <&apbdma 16>;
512 dma-names = "rx", "tx";
513 status = "disabled";
514 };
515
be70771d 516 spi@7000d800 {
34b4f6d0
TR		 517 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
518 reg = <0x0 0x7000d800 0x0 0x200>;
519 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
523 clock-names = "spi";
524 resets = <&tegra_car 46>;
525 reset-names = "spi";
526 dmas = <&apbdma 17>, <&apbdma 17>;
527 dma-names = "rx", "tx";
528 status = "disabled";
529 };
530
be70771d 531 spi@7000da00 {
34b4f6d0
TR		 532 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
533 reg = <0x0 0x7000da00 0x0 0x200>;
534 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
538 clock-names = "spi";
539 resets = <&tegra_car 68>;
540 reset-names = "spi";
541 dmas = <&apbdma 18>, <&apbdma 18>;
542 dma-names = "rx", "tx";
543 status = "disabled";
544 };
545
be70771d 546 spi@7000dc00 {
34b4f6d0
TR		 547 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
548 reg = <0x0 0x7000dc00 0x0 0x200>;
549 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
553 clock-names = "spi";
554 resets = <&tegra_car 104>;
555 reset-names = "spi";
556 dmas = <&apbdma 27>, <&apbdma 27>;
557 dma-names = "rx", "tx";
558 status = "disabled";
559 };
560
be70771d 561 spi@7000de00 {
34b4f6d0
TR		 562 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
563 reg = <0x0 0x7000de00 0x0 0x200>;
564 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
565 #address-cells = <1>;
566 #size-cells = <0>;
567 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
568 clock-names = "spi";
569 resets = <&tegra_car 105>;
570 reset-names = "spi";
571 dmas = <&apbdma 28>, <&apbdma 28>;
572 dma-names = "rx", "tx";
573 status = "disabled";
574 };
575
be70771d 576 rtc@7000e000 {
34b4f6d0
TR		 577 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
578 reg = <0x0 0x7000e000 0x0 0x100>;
579 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&tegra_car TEGRA124_CLK_RTC>;
581 clock-names = "rtc";
582 };
583
359ae651 584 tegra_pmc: pmc@7000e400 {
34b4f6d0
TR		 585 compatible = "nvidia,tegra124-pmc";
586 reg = <0x0 0x7000e400 0x0 0x400>;
587 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
588 clock-names = "pclk", "clk32k_in";
359ae651 589 #clock-cells = <1>;
34b4f6d0
TR		 590 };
591
be70771d 592 fuse@7000f800 {
34b4f6d0
TR		 593 compatible = "nvidia,tegra124-efuse";
594 reg = <0x0 0x7000f800 0x0 0x400>;
595 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
596 clock-names = "fuse";
597 resets = <&tegra_car 39>;
598 reset-names = "fuse";
599 };
600
be70771d 601 mc: memory-controller@70019000 {
34b4f6d0
TR		 602 compatible = "nvidia,tegra132-mc";
603 reg = <0x0 0x70019000 0x0 0x1000>;
604 clocks = <&tegra_car TEGRA124_CLK_MC>;
605 clock-names = "mc";
606
607 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
608
609 #iommu-cells = <1>;
610 };
611
47cd385e 612 emc: external-memory-controller@7001b000 {
4473b1e8 613 compatible = "nvidia,tegra132-emc";
34b4f6d0 614 reg = <0x0 0x7001b000 0x0 0x1000>;
0bab86ab
TR		 615 clocks = <&tegra_car TEGRA124_CLK_EMC>;
616 clock-names = "emc";
34b4f6d0
TR		 617
618 nvidia,memory-controller = <&mc>;
619 };
620
be70771d 621 sata@70020000 {
34b4f6d0
TR		 622 compatible = "nvidia,tegra124-ahci";
623 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
624 <0x0 0x70020000 0x0 0x7000>; /* SATA */
625 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&tegra_car TEGRA124_CLK_SATA>,
627 <&tegra_car TEGRA124_CLK_SATA_OOB>,
628 <&tegra_car TEGRA124_CLK_CML1>,
629 <&tegra_car TEGRA124_CLK_PLL_E>;
630 clock-names = "sata", "sata-oob", "cml1", "pll_e";
631 resets = <&tegra_car 124>,
632 <&tegra_car 123>,
633 <&tegra_car 129>;
634 reset-names = "sata", "sata-oob", "sata-cold";
34b4f6d0
TR		 635 status = "disabled";
636 };
637
be70771d 638 hda@70030000 {
34b4f6d0
TR		 639 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
640 "nvidia,tegra30-hda";
641 reg = <0x0 0x70030000 0x0 0x10000>;
642 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&tegra_car TEGRA124_CLK_HDA>,
644 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
645 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
646 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
647 resets = <&tegra_car 125>, /* hda */
648 <&tegra_car 128>, /* hda2hdmi */
649 <&tegra_car 111>; /* hda2codec_2x */
650 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
651 status = "disabled";
652 };
653
574d9cff
TR		 654 usb@70090000 {
655 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb";
656 reg = <0x0 0x70090000 0x0 0x8000>,
657 <0x0 0x70098000 0x0 0x1000>,
658 <0x0 0x70099000 0x0 0x1000>;
659 reg-names = "hcd", "fpci", "ipfs";
660
661 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
663
664 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
665 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
666 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
667 <&tegra_car TEGRA124_CLK_XUSB_SS>,
668 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
669 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
670 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
671 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
672 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
673 <&tegra_car TEGRA124_CLK_CLK_M>,
674 <&tegra_car TEGRA124_CLK_PLL_E>;
675 clock-names = "xusb_host", "xusb_host_src",
676 "xusb_falcon_src", "xusb_ss",
677 "xusb_ss_src", "xusb_ss_div2",
678 "xusb_hs_src", "xusb_fs_src",
679 "pll_u_480m", "clk_m", "pll_e";
680 resets = <&tegra_car 89>, <&tegra_car 156>,
681 <&tegra_car 143>;
682 reset-names = "xusb_host", "xusb_ss", "xusb_src";
683
684 nvidia,xusb-padctl = <&padctl>;
685
686 status = "disabled";
687 };
688
be70771d 689 padctl: padctl@7009f000 {
34b4f6d0
TR		 690 compatible = "nvidia,tegra132-xusb-padctl",
691 "nvidia,tegra124-xusb-padctl";
692 reg = <0x0 0x7009f000 0x0 0x1000>;
693 resets = <&tegra_car 142>;
694 reset-names = "padctl";
695
574d9cff
TR		 696 pads {
697 usb2 {
698 status = "disabled";
699
700 lanes {
701 usb2-0 {
702 status = "disabled";
703 #phy-cells = <0>;
704 };
705
706 usb2-1 {
707 status = "disabled";
708 #phy-cells = <0>;
709 };
710
711 usb2-2 {
712 status = "disabled";
713 #phy-cells = <0>;
714 };
715 };
716 };
34b4f6d0 717
574d9cff 718 ulpi {
34b4f6d0 719 status = "disabled";
574d9cff
TR		 720
721 lanes {
722 ulpi-0 {
723 status = "disabled";
724 #phy-cells = <0>;
725 };
726 };
34b4f6d0
TR		 727 };
728
574d9cff 729 hsic {
34b4f6d0 730 status = "disabled";
574d9cff
TR		 731
732 lanes {
733 hsic-0 {
734 status = "disabled";
735 #phy-cells = <0>;
736 };
737
738 hsic-1 {
739 status = "disabled";
740 #phy-cells = <0>;
741 };
742 };
34b4f6d0
TR		 743 };
744
574d9cff 745 pcie {
34b4f6d0 746 status = "disabled";
574d9cff
TR		 747
748 lanes {
749 pcie-0 {
750 status = "disabled";
751 #phy-cells = <0>;
752 };
753
754 pcie-1 {
755 status = "disabled";
756 #phy-cells = <0>;
757 };
758
759 pcie-2 {
760 status = "disabled";
761 #phy-cells = <0>;
762 };
763
764 pcie-3 {
765 status = "disabled";
766 #phy-cells = <0>;
767 };
768
769 pcie-4 {
770 status = "disabled";
771 #phy-cells = <0>;
772 };
773 };
34b4f6d0
TR		 774 };
775
574d9cff
TR		 776 sata {
777 status = "disabled";
778
779 lanes {
780 sata-0 {
781 status = "disabled";
782 #phy-cells = <0>;
783 };
784 };
785 };
786 };
787
788 ports {
789 usb2-0 {
34b4f6d0
TR		 790 status = "disabled";
791 };
792
574d9cff 793 usb2-1 {
34b4f6d0
TR		 794 status = "disabled";
795 };
796
574d9cff 797 usb2-2 {
34b4f6d0
TR		 798 status = "disabled";
799 };
800
574d9cff
TR		 801 hsic-0 {
802 status = "disabled";
803 };
804
805 hsic-1 {
806 status = "disabled";
807 };
808
809 usb3-0 {
810 status = "disabled";
811 };
812
813 usb3-1 {
34b4f6d0
TR		 814 status = "disabled";
815 };
816 };
817 };
818
67bb17f6 819 mmc@700b0000 {
34b4f6d0
TR		 820 compatible = "nvidia,tegra124-sdhci";
821 reg = <0x0 0x700b0000 0x0 0x200>;
822 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
824 clock-names = "sdhci";
825 resets = <&tegra_car 14>;
826 reset-names = "sdhci";
827 status = "disabled";
828 };
829
67bb17f6 830 mmc@700b0200 {
34b4f6d0
TR		 831 compatible = "nvidia,tegra124-sdhci";
832 reg = <0x0 0x700b0200 0x0 0x200>;
833 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
835 clock-names = "sdhci";
836 resets = <&tegra_car 9>;
837 reset-names = "sdhci";
838 status = "disabled";
839 };
840
67bb17f6 841 mmc@700b0400 {
34b4f6d0
TR		 842 compatible = "nvidia,tegra124-sdhci";
843 reg = <0x0 0x700b0400 0x0 0x200>;
844 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
846 clock-names = "sdhci";
847 resets = <&tegra_car 69>;
848 reset-names = "sdhci";
849 status = "disabled";
850 };
851
67bb17f6 852 mmc@700b0600 {
34b4f6d0
TR		 853 compatible = "nvidia,tegra124-sdhci";
854 reg = <0x0 0x700b0600 0x0 0x200>;
855 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
857 clock-names = "sdhci";
858 resets = <&tegra_car 15>;
859 reset-names = "sdhci";
860 status = "disabled";
861 };
862
be70771d 863 soctherm: thermal-sensor@700e2000 {
0fa2bfcd 864 compatible = "nvidia,tegra132-soctherm";
644c569d
TR		 865 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
866 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
f4357938 867 reg-names = "soctherm-reg", "ccroc-reg";
34b4f6d0
TR		 868 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
4b32eb1c 870 <&tegra_car TEGRA124_CLK_SOC_THERM>;
34b4f6d0
TR		 871 clock-names = "tsensor", "soctherm";
872 resets = <&tegra_car 78>;
873 reset-names = "soctherm";
874 #thermal-sensor-cells = <1>;
f4357938
WN		 875
876 throttle-cfgs {
877 throttle_heavy: heavy {
878 nvidia,priority = <100>;
879 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
880
881 #cooling-cells = <2>;
882 };
883 };
34b4f6d0
TR		 884 };
885
0fa2bfcd
WN		 886 thermal-zones {
887 cpu {
888 polling-delay-passive = <1000>;
889 polling-delay = <0>;
890
891 thermal-sensors =
892 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
a6ebde25
WN		 893
894 trips {
895 cpu_shutdown_trip {
896 temperature = <105000>;
897 hysteresis = <1000>;
898 type = "critical";
899 };
f4357938
WN		 900
901 cpu_throttle_trip: throttle-trip {
902 temperature = <102000>;
903 hysteresis = <1000>;
904 type = "hot";
905 };
a6ebde25
WN		 906 };
907
908 cooling-maps {
f4357938
WN		 909 map0 {
910 trip = <&cpu_throttle_trip>;
911 cooling-device = <&throttle_heavy 1 1>;
912 };
a6ebde25 913 };
0fa2bfcd
WN		 914 };
915 mem {
916 polling-delay-passive = <0>;
917 polling-delay = <0>;
918
919 thermal-sensors =
920 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
a6ebde25
WN		 921
922 trips {
923 mem_shutdown_trip {
924 temperature = <101000>;
925 hysteresis = <1000>;
926 type = "critical";
927 };
5aaa0de9
NC		 928 mem_throttle_trip {
929 temperature = <99000>;
930 hysteresis = <1000>;
931 type = "hot";
932 };
a6ebde25
WN		 933 };
934
935 cooling-maps {
936 /*
937 * There are currently no cooling maps,
938 * because there are no cooling devices.
939 */
940 };
0fa2bfcd
WN		 941 };
942 gpu {
943 polling-delay-passive = <1000>;
944 polling-delay = <0>;
945
946 thermal-sensors =
947 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
a6ebde25
WN		 948
949 trips {
950 gpu_shutdown_trip {
951 temperature = <101000>;
952 hysteresis = <1000>;
953 type = "critical";
954 };
f4357938
WN		 955
956 gpu_throttle_trip: throttle-trip {
957 temperature = <99000>;
958 hysteresis = <1000>;
959 type = "hot";
960 };
a6ebde25
WN		 961 };
962
963 cooling-maps {
f4357938
WN		 964 map0 {
965 trip = <&gpu_throttle_trip>;
966 cooling-device = <&throttle_heavy 1 1>;
967 };
a6ebde25 968 };
0fa2bfcd
WN		 969 };
970 pllx {
971 polling-delay-passive = <0>;
972 polling-delay = <0>;
973
974 thermal-sensors =
975 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
a6ebde25
WN		 976
977 trips {
978 pllx_shutdown_trip {
979 temperature = <105000>;
980 hysteresis = <1000>;
981 type = "critical";
982 };
5aaa0de9
NC		 983 pllx_throttle_trip {
984 temperature = <99000>;
985 hysteresis = <1000>;
986 type = "hot";
987 };
a6ebde25
WN		 988 };
989
990 cooling-maps {
991 /*
992 * There are currently no cooling maps,
993 * because there are no cooling devices.
994 */
995 };
0fa2bfcd
WN		 996 };
997 };
998
be70771d 999 ahub@70300000 {
34b4f6d0
TR		 1000 compatible = "nvidia,tegra124-ahub";
1001 reg = <0x0 0x70300000 0x0 0x200>,
1002 <0x0 0x70300800 0x0 0x800>,
1003 <0x0 0x70300200 0x0 0x600>;
1004 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
1006 <&tegra_car TEGRA124_CLK_APBIF>;
1007 clock-names = "d_audio", "apbif";
1008 resets = <&tegra_car 106>, /* d_audio */
1009 <&tegra_car 107>, /* apbif */
1010 <&tegra_car 30>, /* i2s0 */
1011 <&tegra_car 11>, /* i2s1 */
1012 <&tegra_car 18>, /* i2s2 */
1013 <&tegra_car 101>, /* i2s3 */
1014 <&tegra_car 102>, /* i2s4 */
1015 <&tegra_car 108>, /* dam0 */
1016 <&tegra_car 109>, /* dam1 */
1017 <&tegra_car 110>, /* dam2 */
1018 <&tegra_car 10>, /* spdif */
1019 <&tegra_car 153>, /* amx */
1020 <&tegra_car 185>, /* amx1 */
1021 <&tegra_car 154>, /* adx */
1022 <&tegra_car 180>, /* adx1 */
1023 <&tegra_car 186>, /* afc0 */
1024 <&tegra_car 187>, /* afc1 */
1025 <&tegra_car 188>, /* afc2 */
1026 <&tegra_car 189>, /* afc3 */
1027 <&tegra_car 190>, /* afc4 */
1028 <&tegra_car 191>; /* afc5 */
1029 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1030 "i2s3", "i2s4", "dam0", "dam1", "dam2",
1031 "spdif", "amx", "amx1", "adx", "adx1",
1032 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
1033 dmas = <&apbdma 1>, <&apbdma 1>,
1034 <&apbdma 2>, <&apbdma 2>,
1035 <&apbdma 3>, <&apbdma 3>,
1036 <&apbdma 4>, <&apbdma 4>,
1037 <&apbdma 6>, <&apbdma 6>,
1038 <&apbdma 7>, <&apbdma 7>,
1039 <&apbdma 12>, <&apbdma 12>,
1040 <&apbdma 13>, <&apbdma 13>,
1041 <&apbdma 14>, <&apbdma 14>,
1042 <&apbdma 29>, <&apbdma 29>;
1043 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1044 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
1045 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
1046 "rx9", "tx9";
1047 ranges;
1048 #address-cells = <2>;
1049 #size-cells = <2>;
1050
be70771d 1051 tegra_i2s0: i2s@70301000 {
34b4f6d0
TR		 1052 compatible = "nvidia,tegra124-i2s";
1053 reg = <0x0 0x70301000 0x0 0x100>;
1054 nvidia,ahub-cif-ids = <4 4>;
1055 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
1056 clock-names = "i2s";
1057 resets = <&tegra_car 30>;
1058 reset-names = "i2s";
1059 status = "disabled";
1060 };
1061
be70771d 1062 tegra_i2s1: i2s@70301100 {
34b4f6d0
TR		 1063 compatible = "nvidia,tegra124-i2s";
1064 reg = <0x0 0x70301100 0x0 0x100>;
1065 nvidia,ahub-cif-ids = <5 5>;
1066 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1067 clock-names = "i2s";
1068 resets = <&tegra_car 11>;
1069 reset-names = "i2s";
1070 status = "disabled";
1071 };
1072
be70771d 1073 tegra_i2s2: i2s@70301200 {
34b4f6d0
TR		 1074 compatible = "nvidia,tegra124-i2s";
1075 reg = <0x0 0x70301200 0x0 0x100>;
1076 nvidia,ahub-cif-ids = <6 6>;
1077 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1078 clock-names = "i2s";
1079 resets = <&tegra_car 18>;
1080 reset-names = "i2s";
1081 status = "disabled";
1082 };
1083
be70771d 1084 tegra_i2s3: i2s@70301300 {
34b4f6d0
TR		 1085 compatible = "nvidia,tegra124-i2s";
1086 reg = <0x0 0x70301300 0x0 0x100>;
1087 nvidia,ahub-cif-ids = <7 7>;
1088 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1089 clock-names = "i2s";
1090 resets = <&tegra_car 101>;
1091 reset-names = "i2s";
1092 status = "disabled";
1093 };
1094
be70771d 1095 tegra_i2s4: i2s@70301400 {
34b4f6d0
TR		 1096 compatible = "nvidia,tegra124-i2s";
1097 reg = <0x0 0x70301400 0x0 0x100>;
1098 nvidia,ahub-cif-ids = <8 8>;
1099 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1100 clock-names = "i2s";
1101 resets = <&tegra_car 102>;
1102 reset-names = "i2s";
1103 status = "disabled";
1104 };
1105 };
1106
be70771d 1107 usb@7d000000 {
34b4f6d0
TR		 1108 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1109 reg = <0x0 0x7d000000 0x0 0x4000>;
1110 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1111 phy_type = "utmi";
1112 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1113 clock-names = "usb";
1114 resets = <&tegra_car 22>;
1115 reset-names = "usb";
1116 nvidia,phy = <&phy1>;
1117 status = "disabled";
1118 };
1119
be70771d 1120 phy1: usb-phy@7d000000 {
34b4f6d0
TR		 1121 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1122 reg = <0x0 0x7d000000 0x0 0x4000>,
1123 <0x0 0x7d000000 0x0 0x4000>;
1124 phy_type = "utmi";
1125 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1126 <&tegra_car TEGRA124_CLK_PLL_U>,
1127 <&tegra_car TEGRA124_CLK_USBD>;
1128 clock-names = "reg", "pll_u", "utmi-pads";
1129 resets = <&tegra_car 22>, <&tegra_car 22>;
1130 reset-names = "usb", "utmi-pads";
27e2c657 1131 #phy-cells = <0>;
34b4f6d0
TR		 1132 nvidia,hssync-start-delay = <0>;
1133 nvidia,idle-wait-delay = <17>;
1134 nvidia,elastic-limit = <16>;
1135 nvidia,term-range-adj = <6>;
1136 nvidia,xcvr-setup = <9>;
1137 nvidia,xcvr-lsfslew = <0>;
1138 nvidia,xcvr-lsrslew = <3>;
1139 nvidia,hssquelch-level = <2>;
1140 nvidia,hsdiscon-level = <5>;
1141 nvidia,xcvr-hsslew = <12>;
1142 nvidia,has-utmi-pad-registers;
1143 status = "disabled";
1144 };
1145
be70771d 1146 usb@7d004000 {
34b4f6d0
TR		 1147 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1148 reg = <0x0 0x7d004000 0x0 0x4000>;
1149 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1150 phy_type = "utmi";
1151 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1152 clock-names = "usb";
1153 resets = <&tegra_car 58>;
1154 reset-names = "usb";
1155 nvidia,phy = <&phy2>;
1156 status = "disabled";
1157 };
1158
be70771d 1159 phy2: usb-phy@7d004000 {
34b4f6d0
TR		 1160 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1161 reg = <0x0 0x7d004000 0x0 0x4000>,
1162 <0x0 0x7d000000 0x0 0x4000>;
1163 phy_type = "utmi";
1164 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1165 <&tegra_car TEGRA124_CLK_PLL_U>,
1166 <&tegra_car TEGRA124_CLK_USBD>;
1167 clock-names = "reg", "pll_u", "utmi-pads";
1168 resets = <&tegra_car 58>, <&tegra_car 22>;
1169 reset-names = "usb", "utmi-pads";
27e2c657 1170 #phy-cells = <0>;
34b4f6d0
TR		 1171 nvidia,hssync-start-delay = <0>;
1172 nvidia,idle-wait-delay = <17>;
1173 nvidia,elastic-limit = <16>;
1174 nvidia,term-range-adj = <6>;
1175 nvidia,xcvr-setup = <9>;
1176 nvidia,xcvr-lsfslew = <0>;
1177 nvidia,xcvr-lsrslew = <3>;
1178 nvidia,hssquelch-level = <2>;
1179 nvidia,hsdiscon-level = <5>;
1180 nvidia,xcvr-hsslew = <12>;
1181 status = "disabled";
1182 };
1183
be70771d 1184 usb@7d008000 {
34b4f6d0
TR		 1185 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1186 reg = <0x0 0x7d008000 0x0 0x4000>;
1187 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1188 phy_type = "utmi";
1189 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1190 clock-names = "usb";
1191 resets = <&tegra_car 59>;
1192 reset-names = "usb";
1193 nvidia,phy = <&phy3>;
1194 status = "disabled";
1195 };
1196
be70771d 1197 phy3: usb-phy@7d008000 {
34b4f6d0
TR		 1198 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1199 reg = <0x0 0x7d008000 0x0 0x4000>,
1200 <0x0 0x7d000000 0x0 0x4000>;
1201 phy_type = "utmi";
1202 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1203 <&tegra_car TEGRA124_CLK_PLL_U>,
1204 <&tegra_car TEGRA124_CLK_USBD>;
1205 clock-names = "reg", "pll_u", "utmi-pads";
1206 resets = <&tegra_car 59>, <&tegra_car 22>;
1207 reset-names = "usb", "utmi-pads";
27e2c657 1208 #phy-cells = <0>;
34b4f6d0
TR		 1209 nvidia,hssync-start-delay = <0>;
1210 nvidia,idle-wait-delay = <17>;
1211 nvidia,elastic-limit = <16>;
1212 nvidia,term-range-adj = <6>;
1213 nvidia,xcvr-setup = <9>;
1214 nvidia,xcvr-lsfslew = <0>;
1215 nvidia,xcvr-lsrslew = <3>;
1216 nvidia,hssquelch-level = <2>;
1217 nvidia,hsdiscon-level = <5>;
1218 nvidia,xcvr-hsslew = <12>;
1219 status = "disabled";
1220 };
1221
1222 cpus {
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1225
1226 cpu@0 {
1227 device_type = "cpu";
31af04cd 1228 compatible = "nvidia,denver";
34b4f6d0
TR		 1229 reg = <0>;
1230 };
1231
1232 cpu@1 {
1233 device_type = "cpu";
31af04cd 1234 compatible = "nvidia,denver";
34b4f6d0
TR		 1235 reg = <1>;
1236 };
1237 };
1238
1239 timer {
1240 compatible = "arm,armv7-timer";
1241 interrupts = <GIC_PPI 13
1242 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1243 <GIC_PPI 14
1244 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1245 <GIC_PPI 11
1246 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1247 <GIC_PPI 10
1248 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1249 interrupt-parent = <&gic>;
1250 };
1251};
Linux 6.x block layer and io_uring tree(s)