[linux-2.6-block.git] / arch / arm64 / boot / dts / mediatek / mt7622-bananapi-bpi-r64.dts

/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Ryder Lee <ryder.lee@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

#include "mt7622.dtsi"
#include "mt6380.dtsi"

/ {
	model = "Bananapi BPI-R64";
	compatible = "bananapi,bpi-r64", "mediatek,mt7622";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
	};

	cpus {
		cpu@0 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};

		cpu@1 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		factory {
			label = "factory";
			linux,code = <BTN_0>;
			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
		};

		wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
		};
	};

	leds {
		compatible = "gpio-leds";

		green {
			label = "bpi-r64:pio:green";
			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		red {
			label = "bpi-r64:pio:red";
			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	memory {
		reg = <0 0x40000000 0 0x40000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_5v: regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&bch {
	status = "disabled";
};

&btif {
	status = "okay";
};

&cir {
	pinctrl-names = "default";
	pinctrl-0 = <&irrx_pins>;
	status = "okay";
};

&eth {
	pinctrl-names = "default";
	pinctrl-0 = <&eth_pins>;
	status = "okay";

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-handle = <&phy5>;
	};

	mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		phy5: ethernet-phy@5 {
			reg = <5>;
			phy-mode = "sgmii";
		};
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
};

&mmc0 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&emmc_pins_default>;
	pinctrl-1 = <&emmc_pins_uhs>;
	status = "okay";
	bus-width = <8>;
	max-frequency = <50000000>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
	non-removable;
};

&mmc1 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&sd0_pins_default>;
	pinctrl-1 = <&sd0_pins_uhs>;
	status = "okay";
	bus-width = <4>;
	max-frequency = <50000000>;
	cap-sd-highspeed;
	r_smpl = <1>;
	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_3p3v>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};

&nandc {
	pinctrl-names = "default";
	pinctrl-0 = <&parallel_nand_pins>;
	status = "disabled";
};

&nor_flash {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_nor_pins>;
	status = "disabled";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
	status = "okay";

	pcie@0,0 {
		status = "okay";
	};

	pcie@1,0 {
		status = "okay";
	};
};

&pio {
	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
	 */
	asm_sel {
		gpio-hog;
		gpios = <90 GPIO_ACTIVE_HIGH>;
		output-high;
	};

	/* eMMC is shared pin with parallel NAND */
	emmc_pins_default: emmc-pins-default {
		mux {
			function = "emmc", "emmc_rst";
			groups = "emmc";
		};

		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
		 */
		conf-cmd-dat {
			pins = "NDL0", "NDL1", "NDL2",
			       "NDL3", "NDL4", "NDL5",
			       "NDL6", "NDL7", "NRB";
			input-enable;
			bias-pull-up;
		};

		conf-clk {
			pins = "NCLE";
			bias-pull-down;
		};
	};

	emmc_pins_uhs: emmc-pins-uhs {
		mux {
			function = "emmc";
			groups = "emmc";
		};

		conf-cmd-dat {
			pins = "NDL0", "NDL1", "NDL2",
			       "NDL3", "NDL4", "NDL5",
			       "NDL6", "NDL7", "NRB";
			input-enable;
			drive-strength = <4>;
			bias-pull-up;
		};

		conf-clk {
			pins = "NCLE";
			drive-strength = <4>;
			bias-pull-down;
		};
	};

	eth_pins: eth-pins {
		mux {
			function = "eth";
			groups = "mdc_mdio", "rgmii_via_gmac2";
		};
	};

	i2c1_pins: i2c1-pins {
		mux {
			function = "i2c";
			groups =  "i2c1_0";
		};
	};

	i2c2_pins: i2c2-pins {
		mux {
			function = "i2c";
			groups =  "i2c2_0";
		};
	};

	i2s1_pins: i2s1-pins {
		mux {
			function = "i2s";
			groups =  "i2s_out_mclk_bclk_ws",
				  "i2s1_in_data",
				  "i2s1_out_data";
		};

		conf {
			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
			       "I2S_WS", "I2S_MCLK";
			drive-strength = <12>;
			bias-pull-down;
		};
	};

	irrx_pins: irrx-pins {
		mux {
			function = "ir";
			groups =  "ir_1_rx";
		};
	};

	irtx_pins: irtx-pins {
		mux {
			function = "ir";
			groups =  "ir_1_tx";
		};
	};

	/* Parallel nand is shared pin with eMMC */
	parallel_nand_pins: parallel-nand-pins {
		mux {
			function = "flash";
			groups = "par_nand";
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie0_pad_perst",
				 "pcie0_1_waken",
				 "pcie0_1_clkreq";
		};
	};

	pcie1_pins: pcie1-pins {
		mux {
			function = "pcie";
			groups = "pcie1_pad_perst",
				 "pcie1_0_waken",
				 "pcie1_0_clkreq";
		};
	};

	pmic_bus_pins: pmic-bus-pins {
		mux {
			function = "pmic";
			groups = "pmic_bus";
		};
	};

	pwm7_pins: pwm1-2-pins {
		mux {
			function = "pwm";
			groups = "pwm_ch7_2";
		};
	};

	wled_pins: wled-pins {
		mux {
			function = "led";
			groups = "wled";
		};
	};

	sd0_pins_default: sd0-pins-default {
		mux {
			function = "sd";
			groups = "sd_0";
		};

		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
		 *  DAT2, DAT3, CMD, CLK for SD respectively.
		 */
		conf-cmd-data {
			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
			       "I2S2_IN","I2S4_OUT";
			input-enable;
			drive-strength = <8>;
			bias-pull-up;
		};
		conf-clk {
			pins = "I2S3_OUT";
			drive-strength = <12>;
			bias-pull-down;
		};
		conf-cd {
			pins = "TXD3";
			bias-pull-up;
		};
	};

	sd0_pins_uhs: sd0-pins-uhs {
		mux {
			function = "sd";
			groups = "sd_0";
		};

		conf-cmd-data {
			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
			       "I2S2_IN","I2S4_OUT";
			input-enable;
			bias-pull-up;
		};

		conf-clk {
			pins = "I2S3_OUT";
			bias-pull-down;
		};
	};

	/* Serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	spic0_pins: spic0-pins {
		mux {
			function = "spi";
			groups = "spic0_0";
		};
	};

	spic1_pins: spic1-pins {
		mux {
			function = "spi";
			groups = "spic1_0";
		};
	};

	/* SPI-NOR is shared pin with serial NAND */
	spi_nor_pins: spi-nor-pins {
		mux {
			function = "flash";
			groups = "spi_nor";
		};
	};

	/* serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	uart0_pins: uart0-pins {
		mux {
			function = "uart";
			groups = "uart0_0_tx_rx" ;
		};
	};

	uart2_pins: uart2-pins {
		mux {
			function = "uart";
			groups = "uart2_1_tx_rx" ;
		};
	};

	watchdog_pins: watchdog-pins {
		mux {
			function = "watchdog";
			groups = "watchdog";
		};
	};
};

&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm7_pins>;
	status = "okay";
};

&pwrap {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_bus_pins>;

	status = "okay";
};

&sata {
	status = "disable";
};

&sata_phy {
	status = "disable";
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic0_pins>;
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic1_pins>;
	status = "okay";
};

&ssusb {
	vusb33-supply = <&reg_3p3v>;
	vbus-supply = <&reg_5v>;
	status = "okay";
};

&u3phy {
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

&watchdog {
	pinctrl-names = "default";
	pinctrl-0 = <&watchdog_pins>;
	status = "okay";
};
Commit	Line	Data
0b6286dd RL	1	/*
	2	* Copyright (c) 2018 MediaTek Inc.
	3	* Author: Ryder Lee <ryder.lee@mediatek.com>
	4	*
	5	* SPDX-License-Identifier: (GPL-2.0 OR MIT)
	6	*/
	7
	8	/dts-v1/;
	9	#include <dt-bindings/input/input.h>
	10	#include <dt-bindings/gpio/gpio.h>
	11
	12	#include "mt7622.dtsi"
	13	#include "mt6380.dtsi"
	14
	15	/ {
	16	model = "Bananapi BPI-R64";
	17	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
	18
396defa8 RL	19	aliases {
	20	serial0 = &uart0;
	21	};
	22
0b6286dd	23	chosen {
396defa8 RL	24	stdout-path = "serial0:115200n8";
396defa8 RL	25	bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
0b6286dd RL	26	};
	27
	28	cpus {
	29	cpu@0 {
	30	proc-supply = <&mt6380_vcpu_reg>;
	31	sram-supply = <&mt6380_vm_reg>;
	32	};
	33
	34	cpu@1 {
	35	proc-supply = <&mt6380_vcpu_reg>;
	36	sram-supply = <&mt6380_vm_reg>;
	37	};
	38	};
	39
	40	gpio-keys {
	41	compatible = "gpio-keys";
	42
	43	factory {
	44	label = "factory";
	45	linux,code = <BTN_0>;
	46	gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
	47	};
	48
	49	wps {
	50	label = "wps";
	51	linux,code = <KEY_WPS_BUTTON>;
	52	gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
	53	};
	54	};
	55
	56	leds {
	57	compatible = "gpio-leds";
	58
	59	green {
	60	label = "bpi-r64:pio:green";
	61	gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
	62	default-state = "off";
	63	};
	64
	65	red {
	66	label = "bpi-r64:pio:red";
	67	gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
	68	default-state = "off";
	69	};
	70	};
	71
	72	memory {
	73	reg = <0 0x40000000 0 0x40000000>;
	74	};
	75
	76	reg_1p8v: regulator-1p8v {
	77	compatible = "regulator-fixed";
	78	regulator-name = "fixed-1.8V";
	79	regulator-min-microvolt = <1800000>;
	80	regulator-max-microvolt = <1800000>;
	81	regulator-always-on;
	82	};
	83
	84	reg_3p3v: regulator-3p3v {
	85	compatible = "regulator-fixed";
	86	regulator-name = "fixed-3.3V";
	87	regulator-min-microvolt = <3300000>;
	88	regulator-max-microvolt = <3300000>;
	89	regulator-boot-on;
90	regulator-always-on;
91	};
92
93	reg_5v: regulator-5v {
94	compatible = "regulator-fixed";
95	regulator-name = "fixed-5V";
96	regulator-min-microvolt = <5000000>;
97	regulator-max-microvolt = <5000000>;
98	regulator-boot-on;
99	regulator-always-on;
100	};
101	};
102
103	&bch {
104	status = "disabled";
105	};
106
107	&btif {
108	status = "okay";
109	};
110
111	&cir {
112	pinctrl-names = "default";
113	pinctrl-0 = <&irrx_pins>;
114	status = "okay";
115	};
116
117	&eth {
118	pinctrl-names = "default";
119	pinctrl-0 = <&eth_pins>;
120	status = "okay";
121
122	gmac1: mac@1 {
123	compatible = "mediatek,eth-mac";
124	reg = <1>;
125	phy-handle = <&phy5>;
126	};
127
128	mdio-bus {
129	#address-cells = <1>;
130	#size-cells = <0>;
131
132	phy5: ethernet-phy@5 {
133	reg = <5>;
134	phy-mode = "sgmii";
135	};
136	};
137	};
138
139	&i2c1 {
140	pinctrl-names = "default";
141	pinctrl-0 = <&i2c1_pins>;
142	status = "okay";
143	};
144
145	&i2c2 {
146	pinctrl-names = "default";
147	pinctrl-0 = <&i2c2_pins>;
148	status = "okay";
149	};
150
151	&mmc0 {
152	pinctrl-names = "default", "state_uhs";
153	pinctrl-0 = <&emmc_pins_default>;
154	pinctrl-1 = <&emmc_pins_uhs>;
155	status = "okay";
156	bus-width = <8>;
157	max-frequency = <50000000>;
158	cap-mmc-highspeed;
159	mmc-hs200-1_8v;
160	vmmc-supply = <&reg_3p3v>;
161	vqmmc-supply = <&reg_1p8v>;
162	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
163	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
164	non-removable;
165	};
166
167	&mmc1 {
168	pinctrl-names = "default", "state_uhs";
169	pinctrl-0 = <&sd0_pins_default>;
170	pinctrl-1 = <&sd0_pins_uhs>;
171	status = "okay";
172	bus-width = <4>;
173	max-frequency = <50000000>;
174	cap-sd-highspeed;
175	r_smpl = <1>;
176	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
177	vmmc-supply = <&reg_3p3v>;
178	vqmmc-supply = <&reg_3p3v>;
179	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
180	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
181	};
182
183	&nandc {
184	pinctrl-names = "default";
185	pinctrl-0 = <&parallel_nand_pins>;
186	status = "disabled";
187	};
188
189	&nor_flash {
190	pinctrl-names = "default";
191	pinctrl-0 = <&spi_nor_pins>;
192	status = "disabled";
193
194	flash@0 {
195	compatible = "jedec,spi-nor";
196	reg = <0>;
197	};
198	};
199
200	&pcie {
201	pinctrl-names = "default";
202	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
203	status = "okay";
204
205	pcie@0,0 {
206	status = "okay";
207	};
208
209	pcie@1,0 {
210	status = "okay";
211	};
212	};
213
214	&pio {
215	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
216	* SATA functions. i.e. output-high: PCIe, output-low: SATA
217	*/
218	asm_sel {
219	gpio-hog;
220	gpios = <90 GPIO_ACTIVE_HIGH>;
221	output-high;
222	};
223
224	/* eMMC is shared pin with parallel NAND */
225	emmc_pins_default: emmc-pins-default {
226	mux {
227	function = "emmc", "emmc_rst";
228	groups = "emmc";
229	};
230
231	/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
232	* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
233	* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
234	*/
235	conf-cmd-dat {
236	pins = "NDL0", "NDL1", "NDL2",
237	"NDL3", "NDL4", "NDL5",
238	"NDL6", "NDL7", "NRB";
239	input-enable;
240	bias-pull-up;
241	};
242
243	conf-clk {
244	pins = "NCLE";
245	bias-pull-down;
246	};
247	};
248
249	emmc_pins_uhs: emmc-pins-uhs {
250	mux {
251	function = "emmc";
252	groups = "emmc";
253	};
254
255	conf-cmd-dat {
256	pins = "NDL0", "NDL1", "NDL2",
257	"NDL3", "NDL4", "NDL5",
258	"NDL6", "NDL7", "NRB";
259	input-enable;
260	drive-strength = <4>;
261	bias-pull-up;
262	};
263
264	conf-clk {
265	pins = "NCLE";
266	drive-strength = <4>;
267	bias-pull-down;
268	};
269	};
270
271	eth_pins: eth-pins {
272	mux {
273	function = "eth";
274	groups = "mdc_mdio", "rgmii_via_gmac2";
275	};
276	};
277
278	i2c1_pins: i2c1-pins {
279	mux {
280	function = "i2c";
281	groups = "i2c1_0";
282	};
283	};
284
285	i2c2_pins: i2c2-pins {
286	mux {
287	function = "i2c";
288	groups = "i2c2_0";
289	};
290	};
291
292	i2s1_pins: i2s1-pins {
293	mux {
294	function = "i2s";
295	groups = "i2s_out_mclk_bclk_ws",
296	"i2s1_in_data",
297	"i2s1_out_data";
298	};
299
300	conf {
301	pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
302	"I2S_WS", "I2S_MCLK";
303	drive-strength = <12>;
304	bias-pull-down;
305	};
306	};
307
308	irrx_pins: irrx-pins {
309	mux {
310	function = "ir";
311	groups = "ir_1_rx";
312	};
313	};
314
315	irtx_pins: irtx-pins {
316	mux {
317	function = "ir";
318	groups = "ir_1_tx";
319	};
320	};
321
322	/* Parallel nand is shared pin with eMMC */
323	parallel_nand_pins: parallel-nand-pins {
324	mux {
325	function = "flash";
326	groups = "par_nand";
327	};
328	};
329
330	pcie0_pins: pcie0-pins {
331	mux {
332	function = "pcie";
333	groups = "pcie0_pad_perst",
334	"pcie0_1_waken",
335	"pcie0_1_clkreq";
336	};
337	};
338
339	pcie1_pins: pcie1-pins {
340	mux {
341	function = "pcie";
342	groups = "pcie1_pad_perst",
343	"pcie1_0_waken",
344	"pcie1_0_clkreq";
345	};
346	};
347
348	pmic_bus_pins: pmic-bus-pins {
349	mux {
350	function = "pmic";
351	groups = "pmic_bus";
352	};
353	};
354
355	pwm7_pins: pwm1-2-pins {
356	mux {
357	function = "pwm";
358	groups = "pwm_ch7_2";
359	};
360	};
361
362	wled_pins: wled-pins {
363	mux {
364	function = "led";
365	groups = "wled";
366	};
367	};
368
369	sd0_pins_default: sd0-pins-default {
370	mux {
371	function = "sd";
372	groups = "sd_0";
373	};
374
375	/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
376	* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
377	* DAT2, DAT3, CMD, CLK for SD respectively.
378	*/
379	conf-cmd-data {
380	pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
381	"I2S2_IN","I2S4_OUT";
382	input-enable;
383	drive-strength = <8>;
384	bias-pull-up;
385	};
386	conf-clk {
387	pins = "I2S3_OUT";
388	drive-strength = <12>;
389	bias-pull-down;
390	};
391	conf-cd {
392	pins = "TXD3";
393	bias-pull-up;
394	};
395	};
396
397	sd0_pins_uhs: sd0-pins-uhs {
398	mux {
399	function = "sd";
400	groups = "sd_0";
401	};
402
403	conf-cmd-data {
404	pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
405	"I2S2_IN","I2S4_OUT";
406	input-enable;
407	bias-pull-up;
408	};
409
410	conf-clk {
411	pins = "I2S3_OUT";
412	bias-pull-down;
413	};
414	};
415
416	/* Serial NAND is shared pin with SPI-NOR */
417	serial_nand_pins: serial-nand-pins {
418	mux {
419	function = "flash";
420	groups = "snfi";
421	};
422	};
423
424	spic0_pins: spic0-pins {
425	mux {
426	function = "spi";
427	groups = "spic0_0";
428	};
429	};
430
431	spic1_pins: spic1-pins {
432	mux {
433	function = "spi";
434	groups = "spic1_0";
435	};
436	};
437
438	/* SPI-NOR is shared pin with serial NAND */
439	spi_nor_pins: spi-nor-pins {
440	mux {
441	function = "flash";
442	groups = "spi_nor";
443	};
444	};
445
446	/* serial NAND is shared pin with SPI-NOR */
447	serial_nand_pins: serial-nand-pins {
448	mux {
449	function = "flash";
450	groups = "snfi";
451	};
452	};
453
454	uart0_pins: uart0-pins {
455	mux {
456	function = "uart";
457	groups = "uart0_0_tx_rx" ;
458	};
459	};
460
461	uart2_pins: uart2-pins {
462	mux {
463	function = "uart";
464	groups = "uart2_1_tx_rx" ;
465	};
466	};
467
468	watchdog_pins: watchdog-pins {
469	mux {
470	function = "watchdog";
471	groups = "watchdog";
472	};
473	};
474	};
475
476	&pwm {
477	pinctrl-names = "default";
478	pinctrl-0 = <&pwm7_pins>;
479	status = "okay";
480	};
481
482	&pwrap {
483	pinctrl-names = "default";
484	pinctrl-0 = <&pmic_bus_pins>;
485
486	status = "okay";
487	};
488
489	&sata {
490	status = "disable";
491	};
492
493	&sata_phy {
494	status = "disable";
495	};
496
497	&spi0 {
498	pinctrl-names = "default";
499	pinctrl-0 = <&spic0_pins>;
500	status = "okay";
501	};
502
503	&spi1 {
504	pinctrl-names = "default";
505	pinctrl-0 = <&spic1_pins>;
506	status = "okay";
507	};
508
509	&ssusb {
510	vusb33-supply = <&reg_3p3v>;
511	vbus-supply = <&reg_5v>;
512	status = "okay";
513	};
514
515	&u3phy {
516	status = "okay";
517	};
518
519	&uart0 {
520	pinctrl-names = "default";
521	pinctrl-0 = <&uart0_pins>;
522	status = "okay";
523	};
524
525	&uart2 {
526	pinctrl-names = "default";
527	pinctrl-0 = <&uart2_pins>;
528	status = "okay";
529	};
530
531	&watchdog {
532	pinctrl-names = "default";
533	pinctrl-0 = <&watchdog_pins>;
534	status = "okay";
535	};