[linux-block.git] / arch / arm64 / boot / dts / mediatek / mt7622-bananapi-bpi-r64.dts

/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Ryder Lee <ryder.lee@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

#include "mt7622.dtsi"
#include "mt6380.dtsi"

/ {
	model = "Bananapi BPI-R64";
	chassis-type = "embedded";
	compatible = "bananapi,bpi-r64", "mediatek,mt7622";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
	};

	cpus {
		cpu@0 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};

		cpu@1 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		factory-key {
			label = "factory";
			linux,code = <BTN_0>;
			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
		};

		wps-key {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led-0 {
			label = "bpi-r64:pio:green";
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-1 {
			label = "bpi-r64:pio:red";
			color = <LED_COLOR_ID_RED>;
			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	memory@40000000 {
		reg = <0 0x40000000 0 0x40000000>;
		device_type = "memory";
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_5v: regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&bch {
	status = "disabled";
};

&btif {
	status = "okay";
};

&cir {
	pinctrl-names = "default";
	pinctrl-0 = <&irrx_pins>;
	status = "okay";
};

&eth {
	status = "okay";
	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "rgmii";

		fixed-link {
			speed = <1000>;
			full-duplex;
			pause;
		};
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch@0 {
			compatible = "mediatek,mt7531";
			reg = <0>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
			reset-gpios = <&pio 54 0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "wan";
				};

				port@1 {
					reg = <1>;
					label = "lan0";
				};

				port@2 {
					reg = <2>;
					label = "lan1";
				};

				port@3 {
					reg = <3>;
					label = "lan2";
				};

				port@4 {
					reg = <4>;
					label = "lan3";
				};

				port@5 {
					reg = <5>;
					ethernet = <&gmac1>;
					phy-mode = "rgmii";

					fixed-link {
						speed = <1000>;
						full-duplex;
						pause;
					};
				};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};
		};

	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
};

&mmc0 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&emmc_pins_default>;
	pinctrl-1 = <&emmc_pins_uhs>;
	status = "okay";
	bus-width = <8>;
	max-frequency = <50000000>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
	non-removable;
};

&mmc1 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&sd0_pins_default>;
	pinctrl-1 = <&sd0_pins_uhs>;
	status = "okay";
	bus-width = <4>;
	max-frequency = <50000000>;
	cap-sd-highspeed;
	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_3p3v>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};

&nandc {
	pinctrl-names = "default";
	pinctrl-0 = <&parallel_nand_pins>;
	status = "disabled";
};

&bch {
	status = "okay";
};

&snfi {
	pinctrl-names = "default";
	pinctrl-0 = <&serial_nand_pins>;
	status = "okay";
	flash@0 {
		compatible = "spi-nand";
		reg = <0>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		nand-ecc-engine = <&snfi>;
		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bl2";
				reg = <0x0 0x80000>;
				read-only;
			};

			partition@80000 {
				label = "fip";
				reg = <0x80000 0x200000>;
				read-only;
			};

			ubi: partition@280000 {
				label = "ubi";
				reg = <0x280000 0x7d80000>;
			};
		};
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
	status = "okay";
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie1_pins>;
	status = "okay";
};

&pio {
	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
	 */
	asm_sel {
		gpio-hog;
		gpios = <90 GPIO_ACTIVE_HIGH>;
		output-high;
	};

	/* eMMC is shared pin with parallel NAND */
	emmc_pins_default: emmc-pins-default {
		mux {
			function = "emmc", "emmc_rst";
			groups = "emmc";
		};

		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
		 */
		conf-cmd-dat {
			pins = "NDL0", "NDL1", "NDL2",
			       "NDL3", "NDL4", "NDL5",
			       "NDL6", "NDL7", "NRB";
			input-enable;
			bias-pull-up;
		};

		conf-clk {
			pins = "NCLE";
			bias-pull-down;
		};
	};

	emmc_pins_uhs: emmc-pins-uhs {
		mux {
			function = "emmc";
			groups = "emmc";
		};

		conf-cmd-dat {
			pins = "NDL0", "NDL1", "NDL2",
			       "NDL3", "NDL4", "NDL5",
			       "NDL6", "NDL7", "NRB";
			input-enable;
			drive-strength = <4>;
			bias-pull-up;
		};

		conf-clk {
			pins = "NCLE";
			drive-strength = <4>;
			bias-pull-down;
		};
	};

	eth_pins: eth-pins {
		mux {
			function = "eth";
			groups = "mdc_mdio", "rgmii_via_gmac2";
		};
	};

	i2c1_pins: i2c1-pins {
		mux {
			function = "i2c";
			groups = "i2c1_0";
		};
	};

	i2c2_pins: i2c2-pins {
		mux {
			function = "i2c";
			groups = "i2c2_0";
		};
	};

	i2s1_pins: i2s1-pins {
		mux {
			function = "i2s";
			groups = "i2s_out_mclk_bclk_ws",
				 "i2s1_in_data",
				 "i2s1_out_data";
		};

		conf {
			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
			       "I2S_WS", "I2S_MCLK";
			drive-strength = <12>;
			bias-pull-down;
		};
	};

	irrx_pins: irrx-pins {
		mux {
			function = "ir";
			groups = "ir_1_rx";
		};
	};

	irtx_pins: irtx-pins {
		mux {
			function = "ir";
			groups = "ir_1_tx";
		};
	};

	/* Parallel nand is shared pin with eMMC */
	parallel_nand_pins: parallel-nand-pins {
		mux {
			function = "flash";
			groups = "par_nand";
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie0_pad_perst",
				 "pcie0_1_waken",
				 "pcie0_1_clkreq";
		};
	};

	pcie1_pins: pcie1-pins {
		mux {
			function = "pcie";
			groups = "pcie1_pad_perst",
				 "pcie1_0_waken",
				 "pcie1_0_clkreq";
		};
	};

	pmic_bus_pins: pmic-bus-pins {
		mux {
			function = "pmic";
			groups = "pmic_bus";
		};
	};

	pwm_pins: pwm-pins {
		mux {
			function = "pwm";
			groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
				 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
				 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
				 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
				 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
				 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
		};
	};

	wled_pins: wled-pins {
		mux {
			function = "led";
			groups = "wled";
		};
	};

	sd0_pins_default: sd0-pins-default {
		mux {
			function = "sd";
			groups = "sd_0";
		};

		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
		 *  DAT2, DAT3, CMD, CLK for SD respectively.
		 */
		conf-cmd-data {
			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
			       "I2S2_IN","I2S4_OUT";
			input-enable;
			drive-strength = <8>;
			bias-pull-up;
		};
		conf-clk {
			pins = "I2S3_OUT";
			drive-strength = <12>;
			bias-pull-down;
		};
		conf-cd {
			pins = "TXD3";
			bias-pull-up;
		};
	};

	sd0_pins_uhs: sd0-pins-uhs {
		mux {
			function = "sd";
			groups = "sd_0";
		};

		conf-cmd-data {
			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
			       "I2S2_IN","I2S4_OUT";
			input-enable;
			bias-pull-up;
		};

		conf-clk {
			pins = "I2S3_OUT";
			bias-pull-down;
		};
	};

	/* Serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	spic0_pins: spic0-pins {
		mux {
			function = "spi";
			groups = "spic0_0";
		};
	};

	spic1_pins: spic1-pins {
		mux {
			function = "spi";
			groups = "spic1_0";
		};
	};

	/* SPI-NOR is shared pin with serial NAND */
	spi_nor_pins: spi-nor-pins {
		mux {
			function = "flash";
			groups = "spi_nor";
		};
	};

	/* serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	uart0_pins: uart0-pins {
		mux {
			function = "uart";
			groups = "uart0_0_tx_rx" ;
		};
	};

	uart2_pins: uart2-pins {
		mux {
			function = "uart";
			groups = "uart2_1_tx_rx" ;
		};
	};

	watchdog_pins: watchdog-pins {
		mux {
			function = "watchdog";
			groups = "watchdog";
		};
	};
};

&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm_pins>;
	status = "okay";
};

&pwrap {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_bus_pins>;

	status = "okay";
};

&sata {
	status = "disabled";
};

&sata_phy {
	status = "disabled";
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic0_pins>;
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic1_pins>;
};

&ssusb {
	vusb33-supply = <&reg_3p3v>;
	vbus-supply = <&reg_5v>;
	status = "okay";
};

&u3phy {
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
};

&watchdog {
	pinctrl-names = "default";
	pinctrl-0 = <&watchdog_pins>;
	status = "okay";
};

&wmac {
	status = "okay";
};
Commit	Line	Data
0b6286dd RL	1	/*
	2	* Copyright (c) 2018 MediaTek Inc.
	3	* Author: Ryder Lee <ryder.lee@mediatek.com>
	4	*
	5	* SPDX-License-Identifier: (GPL-2.0 OR MIT)
	6	*/
	7
	8	/dts-v1/;
	9	#include <dt-bindings/input/input.h>
	10	#include <dt-bindings/gpio/gpio.h>
7db5dfd3	11	#include <dt-bindings/leds/common.h>
0b6286dd RL	12
	13	#include "mt7622.dtsi"
	14	#include "mt6380.dtsi"
	15
	16	/ {
	17	model = "Bananapi BPI-R64";
380d18fb	18	chassis-type = "embedded";
0b6286dd RL	19	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
0b6286dd RL	20
396defa8 RL	21	aliases {
	22	serial0 = &uart0;
	23	};
	24
0b6286dd	25	chosen {
396defa8 RL	26	stdout-path = "serial0:115200n8";
396defa8 RL	27	bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
0b6286dd RL	28	};
	29
	30	cpus {
	31	cpu@0 {
	32	proc-supply = <&mt6380_vcpu_reg>;
	33	sram-supply = <&mt6380_vm_reg>;
	34	};
	35
	36	cpu@1 {
	37	proc-supply = <&mt6380_vcpu_reg>;
	38	sram-supply = <&mt6380_vm_reg>;
	39	};
	40	};
	41
	42	gpio-keys {
	43	compatible = "gpio-keys";
	44
335d1603	45	factory-key {
0b6286dd RL	46	label = "factory";
	47	linux,code = <BTN_0>;
	48	gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
	49	};
	50
335d1603	51	wps-key {
0b6286dd RL	52	label = "wps";
0b6286dd RL	53	linux,code = <KEY_WPS_BUTTON>;
c98e6e68	54	gpios = <&pio 102 GPIO_ACTIVE_LOW>;
0b6286dd RL	55	};
	56	};
	57
	58	leds {
	59	compatible = "gpio-leds";
	60
7db5dfd3	61	led-0 {
0b6286dd	62	label = "bpi-r64:pio:green";
7db5dfd3	63	color = <LED_COLOR_ID_GREEN>;
0b6286dd RL	64	gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
	65	default-state = "off";
	66	};
	67
7db5dfd3	68	led-1 {
0b6286dd	69	label = "bpi-r64:pio:red";
7db5dfd3	70	color = <LED_COLOR_ID_RED>;
0b6286dd RL	71	gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
	72	default-state = "off";
	73	};
	74	};
	75
8e6ecbfd	76	memory@40000000 {
0b6286dd	77	reg = <0 0x40000000 0 0x40000000>;
99d100e0	78	device_type = "memory";
0b6286dd RL	79	};
	80
	81	reg_1p8v: regulator-1p8v {
	82	compatible = "regulator-fixed";
	83	regulator-name = "fixed-1.8V";
	84	regulator-min-microvolt = <1800000>;
	85	regulator-max-microvolt = <1800000>;
	86	regulator-always-on;
	87	};
	88
	89	reg_3p3v: regulator-3p3v {
	90	compatible = "regulator-fixed";
	91	regulator-name = "fixed-3.3V";
	92	regulator-min-microvolt = <3300000>;
	93	regulator-max-microvolt = <3300000>;
	94	regulator-boot-on;
	95	regulator-always-on;
	96	};
	97
	98	reg_5v: regulator-5v {
	99	compatible = "regulator-fixed";
	100	regulator-name = "fixed-5V";
	101	regulator-min-microvolt = <5000000>;
	102	regulator-max-microvolt = <5000000>;
	103	regulator-boot-on;
	104	regulator-always-on;
	105	};
	106	};
	107
	108	&bch {
	109	status = "disabled";
	110	};
	111
	112	&btif {
	113	status = "okay";
	114	};
	115
	116	&cir {
	117	pinctrl-names = "default";
	118	pinctrl-0 = <&irrx_pins>;
	119	status = "okay";
	120	};
	121
	122	&eth {
0b6286dd	123	status = "okay";
bd69baaa RD	124	gmac0: mac@0 {
	125	compatible = "mediatek,eth-mac";
	126	reg = <0>;
	127	phy-mode = "2500base-x";
	128
	129	fixed-link {
	130	speed = <2500>;
	131	full-duplex;
	132	pause;
	133	};
	134	};
0b6286dd RL	135
	136	gmac1: mac@1 {
	137	compatible = "mediatek,eth-mac";
	138	reg = <1>;
bd69baaa RD	139	phy-mode = "rgmii";
	140
	141	fixed-link {
	142	speed = <1000>;
	143	full-duplex;
	144	pause;
	145	};
0b6286dd RL	146	};
0b6286dd RL	147
bd69baaa	148	mdio: mdio-bus {
0b6286dd RL	149	#address-cells = <1>;
0b6286dd RL	150	#size-cells = <0>;
79a675e6 LC	151
	152	switch@0 {
	153	compatible = "mediatek,mt7531";
	154	reg = <0>;
983f37ee DG	155	interrupt-controller;
983f37ee DG	156	#interrupt-cells = <1>;
de7e42e9	157	interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
79a675e6 LC	158	reset-gpios = <&pio 54 0>;
	159
	160	ports {
	161	#address-cells = <1>;
	162	#size-cells = <0>;
	163
	164	port@0 {
	165	reg = <0>;
	166	label = "wan";
	167	};
	168
	169	port@1 {
	170	reg = <1>;
	171	label = "lan0";
	172	};
	173
	174	port@2 {
	175	reg = <2>;
	176	label = "lan1";
	177	};
	178
	179	port@3 {
	180	reg = <3>;
	181	label = "lan2";
	182	};
	183
	184	port@4 {
	185	reg = <4>;
	186	label = "lan3";
	187	};
	188
7b8cc130 AÜ	189	port@5 {
	190	reg = <5>;
	191	ethernet = <&gmac1>;
	192	phy-mode = "rgmii";
	193
	194	fixed-link {
	195	speed = <1000>;
	196	full-duplex;
	197	pause;
	198	};
	199	};
	200
79a675e6 LC	201	port@6 {
	202	reg = <6>;
	203	label = "cpu";
	204	ethernet = <&gmac0>;
	205	phy-mode = "2500base-x";
	206
	207	fixed-link {
	208	speed = <2500>;
	209	full-duplex;
	210	pause;
	211	};
	212	};
	213	};
	214	};
	215
0b6286dd RL	216	};
	217	};
	218
	219	&i2c1 {
	220	pinctrl-names = "default";
	221	pinctrl-0 = <&i2c1_pins>;
	222	status = "okay";
	223	};
	224
	225	&i2c2 {
	226	pinctrl-names = "default";
	227	pinctrl-0 = <&i2c2_pins>;
	228	status = "okay";
	229	};
	230
	231	&mmc0 {
	232	pinctrl-names = "default", "state_uhs";
	233	pinctrl-0 = <&emmc_pins_default>;
	234	pinctrl-1 = <&emmc_pins_uhs>;
	235	status = "okay";
	236	bus-width = <8>;
	237	max-frequency = <50000000>;
	238	cap-mmc-highspeed;
	239	mmc-hs200-1_8v;
	240	vmmc-supply = <&reg_3p3v>;
	241	vqmmc-supply = <&reg_1p8v>;
	242	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
	243	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
	244	non-removable;
	245	};
	246
	247	&mmc1 {
	248	pinctrl-names = "default", "state_uhs";
	249	pinctrl-0 = <&sd0_pins_default>;
	250	pinctrl-1 = <&sd0_pins_uhs>;
	251	status = "okay";
	252	bus-width = <4>;
	253	max-frequency = <50000000>;
	254	cap-sd-highspeed;
0b6286dd RL	255	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
	256	vmmc-supply = <&reg_3p3v>;
	257	vqmmc-supply = <&reg_3p3v>;
	258	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
	259	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
	260	};
	261
	262	&nandc {
	263	pinctrl-names = "default";
	264	pinctrl-0 = <&parallel_nand_pins>;
	265	status = "disabled";
	266	};
	267
d278f43f DG	268	&bch {
	269	status = "okay";
	270	};
0b6286dd	271
d278f43f DG	272	&snfi {
	273	pinctrl-names = "default";
	274	pinctrl-0 = <&serial_nand_pins>;
	275	status = "okay";
0b6286dd	276	flash@0 {
d278f43f	277	compatible = "spi-nand";
0b6286dd	278	reg = <0>;
d278f43f DG	279	spi-tx-bus-width = <4>;
	280	spi-rx-bus-width = <4>;
	281	nand-ecc-engine = <&snfi>;
	282	partitions {
	283	compatible = "fixed-partitions";
	284	#address-cells = <1>;
	285	#size-cells = <1>;
	286
	287	partition@0 {
	288	label = "bl2";
	289	reg = <0x0 0x80000>;
	290	read-only;
	291	};
	292
	293	partition@80000 {
	294	label = "fip";
	295	reg = <0x80000 0x200000>;
	296	read-only;
	297	};
	298
	299	ubi: partition@280000 {
	300	label = "ubi";
	301	reg = <0x280000 0x7d80000>;
	302	};
	303	};
0b6286dd RL	304	};
	305	};
	306
c99c4733	307	&pcie0 {
0b6286dd	308	pinctrl-names = "default";
c99c4733	309	pinctrl-0 = <&pcie0_pins>;
0b6286dd	310	status = "okay";
c99c4733	311	};
0b6286dd	312
c99c4733 CL	313	&pcie1 {
	314	pinctrl-names = "default";
	315	pinctrl-0 = <&pcie1_pins>;
	316	status = "okay";
0b6286dd RL	317	};
	318
	319	&pio {
	320	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
	321	* SATA functions. i.e. output-high: PCIe, output-low: SATA
	322	*/
	323	asm_sel {
	324	gpio-hog;
	325	gpios = <90 GPIO_ACTIVE_HIGH>;
	326	output-high;
	327	};
	328
	329	/* eMMC is shared pin with parallel NAND */
	330	emmc_pins_default: emmc-pins-default {
	331	mux {
	332	function = "emmc", "emmc_rst";
	333	groups = "emmc";
	334	};
	335
	336	/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
	337	* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
	338	* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
	339	*/
	340	conf-cmd-dat {
	341	pins = "NDL0", "NDL1", "NDL2",
	342	"NDL3", "NDL4", "NDL5",
	343	"NDL6", "NDL7", "NRB";
	344	input-enable;
	345	bias-pull-up;
	346	};
	347
	348	conf-clk {
	349	pins = "NCLE";
	350	bias-pull-down;
	351	};
	352	};
	353
	354	emmc_pins_uhs: emmc-pins-uhs {
	355	mux {
	356	function = "emmc";
	357	groups = "emmc";
	358	};
	359
	360	conf-cmd-dat {
	361	pins = "NDL0", "NDL1", "NDL2",
	362	"NDL3", "NDL4", "NDL5",
	363	"NDL6", "NDL7", "NRB";
	364	input-enable;
	365	drive-strength = <4>;
	366	bias-pull-up;
	367	};
	368
	369	conf-clk {
	370	pins = "NCLE";
	371	drive-strength = <4>;
	372	bias-pull-down;
	373	};
	374	};
	375
	376	eth_pins: eth-pins {
	377	mux {
	378	function = "eth";
	379	groups = "mdc_mdio", "rgmii_via_gmac2";
	380	};
381	};
382
383	i2c1_pins: i2c1-pins {
384	mux {
385	function = "i2c";
2e9cf554	386	groups = "i2c1_0";
0b6286dd RL	387	};
	388	};
	389
	390	i2c2_pins: i2c2-pins {
	391	mux {
	392	function = "i2c";
2e9cf554	393	groups = "i2c2_0";
0b6286dd RL	394	};
	395	};
	396
	397	i2s1_pins: i2s1-pins {
	398	mux {
	399	function = "i2s";
aee69e45 KK	400	groups = "i2s_out_mclk_bclk_ws",
	401	"i2s1_in_data",
	402	"i2s1_out_data";
0b6286dd RL	403	};
	404
	405	conf {
	406	pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
	407	"I2S_WS", "I2S_MCLK";
	408	drive-strength = <12>;
	409	bias-pull-down;
	410	};
	411	};
	412
	413	irrx_pins: irrx-pins {
	414	mux {
	415	function = "ir";
2e9cf554	416	groups = "ir_1_rx";
0b6286dd RL	417	};
	418	};
	419
	420	irtx_pins: irtx-pins {
	421	mux {
	422	function = "ir";
2e9cf554	423	groups = "ir_1_tx";
0b6286dd RL	424	};
	425	};
	426
	427	/* Parallel nand is shared pin with eMMC */
	428	parallel_nand_pins: parallel-nand-pins {
	429	mux {
	430	function = "flash";
	431	groups = "par_nand";
	432	};
	433	};
	434
	435	pcie0_pins: pcie0-pins {
	436	mux {
	437	function = "pcie";
	438	groups = "pcie0_pad_perst",
	439	"pcie0_1_waken",
	440	"pcie0_1_clkreq";
	441	};
	442	};
	443
	444	pcie1_pins: pcie1-pins {
	445	mux {
	446	function = "pcie";
	447	groups = "pcie1_pad_perst",
	448	"pcie1_0_waken",
	449	"pcie1_0_clkreq";
	450	};
	451	};
	452
	453	pmic_bus_pins: pmic-bus-pins {
	454	mux {
	455	function = "pmic";
	456	groups = "pmic_bus";
	457	};
	458	};
	459
3f071671	460	pwm_pins: pwm-pins {
0b6286dd RL	461	mux {
0b6286dd RL	462	function = "pwm";
3f071671 FW	463	groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
	464	"pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
	465	"pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
	466	"pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
	467	"pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
	468	"pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
0b6286dd RL	469	};
	470	};
	471
	472	wled_pins: wled-pins {
	473	mux {
	474	function = "led";
	475	groups = "wled";
	476	};
	477	};
	478
	479	sd0_pins_default: sd0-pins-default {
	480	mux {
	481	function = "sd";
	482	groups = "sd_0";
	483	};
	484
	485	/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
	486	* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
	487	* DAT2, DAT3, CMD, CLK for SD respectively.
	488	*/
	489	conf-cmd-data {
	490	pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
	491	"I2S2_IN","I2S4_OUT";
	492	input-enable;
	493	drive-strength = <8>;
	494	bias-pull-up;
	495	};
	496	conf-clk {
	497	pins = "I2S3_OUT";
	498	drive-strength = <12>;
	499	bias-pull-down;
	500	};
	501	conf-cd {
	502	pins = "TXD3";
	503	bias-pull-up;
	504	};
	505	};
	506
	507	sd0_pins_uhs: sd0-pins-uhs {
	508	mux {
	509	function = "sd";
	510	groups = "sd_0";
	511	};
	512
	513	conf-cmd-data {
	514	pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
	515	"I2S2_IN","I2S4_OUT";
	516	input-enable;
	517	bias-pull-up;
	518	};
	519
	520	conf-clk {
	521	pins = "I2S3_OUT";
	522	bias-pull-down;
	523	};
	524	};
	525
	526	/* Serial NAND is shared pin with SPI-NOR */
	527	serial_nand_pins: serial-nand-pins {
	528	mux {
	529	function = "flash";
	530	groups = "snfi";
	531	};
	532	};
533
534	spic0_pins: spic0-pins {
535	mux {
536	function = "spi";
537	groups = "spic0_0";
538	};
539	};
540
541	spic1_pins: spic1-pins {
542	mux {
543	function = "spi";
544	groups = "spic1_0";
545	};
546	};
547
548	/* SPI-NOR is shared pin with serial NAND */
549	spi_nor_pins: spi-nor-pins {
550	mux {
551	function = "flash";
552	groups = "spi_nor";
553	};
554	};
555
556	/* serial NAND is shared pin with SPI-NOR */
557	serial_nand_pins: serial-nand-pins {
558	mux {
559	function = "flash";
560	groups = "snfi";
561	};
562	};
563
564	uart0_pins: uart0-pins {
565	mux {
566	function = "uart";
567	groups = "uart0_0_tx_rx" ;
568	};
569	};
570
571	uart2_pins: uart2-pins {
572	mux {
573	function = "uart";
574	groups = "uart2_1_tx_rx" ;
575	};
576	};
577
578	watchdog_pins: watchdog-pins {
579	mux {
580	function = "watchdog";
581	groups = "watchdog";
582	};
583	};
584	};
585
586	&pwm {
587	pinctrl-names = "default";
3f071671	588	pinctrl-0 = <&pwm_pins>;
0b6286dd RL	589	status = "okay";
	590	};
	591
	592	&pwrap {
	593	pinctrl-names = "default";
	594	pinctrl-0 = <&pmic_bus_pins>;
	595
	596	status = "okay";
	597	};
	598
	599	&sata {
c718f36c	600	status = "disabled";
0b6286dd RL	601	};
	602
	603	&sata_phy {
c718f36c	604	status = "disabled";
0b6286dd RL	605	};
	606
	607	&spi0 {
	608	pinctrl-names = "default";
	609	pinctrl-0 = <&spic0_pins>;
	610	status = "okay";
	611	};
	612
	613	&spi1 {
	614	pinctrl-names = "default";
	615	pinctrl-0 = <&spic1_pins>;
0b6286dd RL	616	};
	617
	618	&ssusb {
	619	vusb33-supply = <&reg_3p3v>;
	620	vbus-supply = <&reg_5v>;
	621	status = "okay";
	622	};
	623
	624	&u3phy {
	625	status = "okay";
	626	};
	627
	628	&uart0 {
	629	pinctrl-names = "default";
	630	pinctrl-0 = <&uart0_pins>;
	631	status = "okay";
	632	};
	633
	634	&uart2 {
	635	pinctrl-names = "default";
	636	pinctrl-0 = <&uart2_pins>;
0b6286dd RL	637	};
	638
	639	&watchdog {
	640	pinctrl-names = "default";
	641	pinctrl-0 = <&watchdog_pins>;
	642	status = "okay";
	643	};
1ba2ed77 RL	644
	645	&wmac {
	646	status = "okay";
	647	};