[linux-2.6-block.git] / arch / arm64 / boot / dts / marvell / armada-ap806.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP806.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/dts-v1/;

/ {
	model = "Marvell Armada AP806";
	compatible = "marvell,armada-ap806";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		gpio0 = &ap_gpio;
		spi0 = &spi0;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		idle_states {
			entry_method = "arm,pcsi";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <80>;
				exit-latency-us  = <160>;
				min-residency-us = <320>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <500>;
				exit-latency-us = <1000>;
				min-residency-us = <2500>;
			};
		};
	};

	ap806 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		config-space@f0000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0x0 0xf0000000 0x1000000>;

			gic: interrupt-controller@210000 {
				compatible = "arm,gic-400";
				#interrupt-cells = <3>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				interrupt-controller;
				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				reg = <0x210000 0x10000>,
				      <0x220000 0x20000>,
				      <0x240000 0x20000>,
				      <0x260000 0x20000>;

				gic_v2m0: v2m@280000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x280000 0x1000>;
					arm,msi-base-spi = <160>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m1: v2m@290000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x290000 0x1000>;
					arm,msi-base-spi = <192>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m2: v2m@2a0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2a0000 0x1000>;
					arm,msi-base-spi = <224>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m3: v2m@2b0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2b0000 0x1000>;
					arm,msi-base-spi = <256>;
					arm,msi-num-spis = <32>;
				};
			};

			timer {
				compatible = "arm,armv8-timer";
				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
			};

			pmu {
				compatible = "arm,cortex-a72-pmu";
				interrupt-parent = <&pic>;
				interrupts = <17>;
			};

			odmi: odmi@300000 {
				compatible = "marvell,odmi-controller";
				interrupt-controller;
				msi-controller;
				marvell,odmi-frames = <4>;
				reg = <0x300000 0x4000>,
				      <0x304000 0x4000>,
				      <0x308000 0x4000>,
				      <0x30C000 0x4000>;
				marvell,spi-base = <128>, <136>, <144>, <152>;
			};

			gicp: gicp@3f0040 {
				compatible = "marvell,ap806-gicp";
				reg = <0x3f0040 0x10>;
				marvell,spi-ranges = <64 64>, <288 64>;
				msi-controller;
			};

			pic: interrupt-controller@3f0100 {
				compatible = "marvell,armada-8k-pic";
				reg = <0x3f0100 0x10>;
				#interrupt-cells = <1>;
				interrupt-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			sei: interrupt-controller@3f0200 {
				compatible = "marvell,ap806-sei";
				reg = <0x3f0200 0x40>;
				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				interrupt-controller;
				msi-controller;
			};

			xor@400000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x400000 0x1000>,
				      <0x410000 0x1000>;
				msi-parent = <&gic_v2m0>;
				clocks = <&ap_clk 3>;
				dma-coherent;
			};

			xor@420000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x420000 0x1000>,
				      <0x430000 0x1000>;
				msi-parent = <&gic_v2m0>;
				clocks = <&ap_clk 3>;
				dma-coherent;
			};

			xor@440000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x440000 0x1000>,
				      <0x450000 0x1000>;
				msi-parent = <&gic_v2m0>;
				clocks = <&ap_clk 3>;
				dma-coherent;
			};

			xor@460000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x460000 0x1000>,
				      <0x470000 0x1000>;
				msi-parent = <&gic_v2m0>;
				clocks = <&ap_clk 3>;
				dma-coherent;
			};

			spi0: spi@510600 {
				compatible = "marvell,armada-380-spi";
				reg = <0x510600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ap_clk 3>;
				status = "disabled";
			};

			i2c0: i2c@511000 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x511000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&ap_clk 3>;
				status = "disabled";
			};

			uart0: serial@512000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ap_clk 3>;
				status = "disabled";
			};

			uart1: serial@512100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ap_clk 3>;
				status = "disabled";

			};

			watchdog: watchdog@610000 {
				compatible = "arm,sbsa-gwdt";
				reg = <0x610000 0x1000>, <0x600000 0x1000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			};

			ap_sdhci0: sdhci@6e0000 {
				compatible = "marvell,armada-ap806-sdhci";
				reg = <0x6e0000 0x300>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "core";
				clocks = <&ap_clk 4>;
				dma-coherent;
				marvell,xenon-phy-slow-mode;
				status = "disabled";
			};

			ap_syscon: system-controller@6f4000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x6f4000 0x2000>;

				ap_clk: clock {
					compatible = "marvell,ap806-clock";
					#clock-cells = <1>;
				};

				ap_pinctrl: pinctrl {
					compatible = "marvell,ap806-pinctrl";

					uart0_pins: uart0-pins {
						marvell,pins = "mpp11", "mpp19";
						marvell,function = "uart0";
					};
				};

				ap_gpio: gpio@1040 {
					compatible = "marvell,armada-8k-gpio";
					offset = <0x1040>;
					ngpios = <20>;
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&ap_pinctrl 0 0 20>;
				};
			};

			ap_syscon1: system-controller@6f8000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x6f8000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;

				ap_thermal: thermal-sensor@80 {
					compatible = "marvell,armada-ap806-thermal";
					reg = <0x80 0x10>;
					#thermal-sensor-cells = <1>;
				};
			};
		};
	};

	/*
	 * The thermal IP features one internal sensor plus, if applicable, one
	 * remote channel wired to one sensor per CPU.
	 *
	 * The cooling maps are always empty as there are no cooling devices.
	 */
	thermal-zones {
		ap_thermal_ic: ap-thermal-ic {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 0>;

			trips {	};
			cooling-maps { };
		};

		ap_thermal_cpu1: ap-thermal-cpu1 {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 1>;

			trips { };
			cooling-maps { };
		};

		ap_thermal_cpu2: ap-thermal-cpu2 {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 2>;

			trips { };
			cooling-maps { };
		};

		ap_thermal_cpu3: ap-thermal-cpu3 {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 3>;

			trips { };
			cooling-maps { };
		};

		ap_thermal_cpu4: ap-thermal-cpu4 {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 4>;

			trips { };
			cooling-maps { };
		};
	};
};
Commit	Line	Data
292816a6	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
ec7e5a56 TP	2	/*
	3	* Copyright (C) 2016 Marvell Technology Group Ltd.
	4	*
ec7e5a56 TP	5	* Device Tree file for Marvell Armada AP806.
	6	*/
	7
	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
3be14851	9	#include <dt-bindings/thermal/thermal.h>
ec7e5a56 TP	10
	11	/dts-v1/;
	12
	13	/ {
	14	model = "Marvell Armada AP806";
	15	compatible = "marvell,armada-ap806";
	16	#address-cells = <2>;
	17	#size-cells = <2>;
	18
bf151162 TP	19	aliases {
	20	serial0 = &uart0;
	21	serial1 = &uart1;
63dac0f4	22	gpio0 = &ap_gpio;
e2a393c6	23	spi0 = &spi0;
bf151162 TP	24	};
bf151162 TP	25
ec7e5a56 TP	26	psci {
	27	compatible = "arm,psci-0.2";
	28	method = "smc";
	29	};
	30
8ed46368	31	cpus {
	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
	35	idle_states {
	36	entry_method = "arm,pcsi";
	37
	38	CPU_SLEEP_0: cpu-sleep-0 {
	39	compatible = "arm,idle-state";
	40	local-timer-stop;
	41	arm,psci-suspend-param = <0x0010000>;
	42	entry-latency-us = <80>;
	43	exit-latency-us = <160>;
	44	min-residency-us = <320>;
	45	};
	46
	47	CLUSTER_SLEEP_0: cluster-sleep-0 {
	48	compatible = "arm,idle-state";
	49	local-timer-stop;
	50	arm,psci-suspend-param = <0x1010000>;
	51	entry-latency-us = <500>;
	52	exit-latency-us = <1000>;
	53	min-residency-us = <2500>;
	54	};
	55	};
	56	};
	57
ec7e5a56 TP	58	ap806 {
	59	#address-cells = <2>;
	60	#size-cells = <2>;
	61	compatible = "simple-bus";
	62	interrupt-parent = <&gic>;
	63	ranges;
	64
70347888	65	config-space@f0000000 {
ec7e5a56 TP	66	#address-cells = <1>;
	67	#size-cells = <1>;
	68	compatible = "simple-bus";
	69	ranges = <0x0 0x0 0xf0000000 0x1000000>;
	70
	71	gic: interrupt-controller@210000 {
	72	compatible = "arm,gic-400";
	73	#interrupt-cells = <3>;
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	ranges;
	77	interrupt-controller;
	78	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	79	reg = <0x210000 0x10000>,
	80	<0x220000 0x20000>,
	81	<0x240000 0x20000>,
	82	<0x260000 0x20000>;
	83
	84	gic_v2m0: v2m@280000 {
	85	compatible = "arm,gic-v2m-frame";
	86	msi-controller;
	87	reg = <0x280000 0x1000>;
	88	arm,msi-base-spi = <160>;
	89	arm,msi-num-spis = <32>;
	90	};
	91	gic_v2m1: v2m@290000 {
	92	compatible = "arm,gic-v2m-frame";
	93	msi-controller;
	94	reg = <0x290000 0x1000>;
	95	arm,msi-base-spi = <192>;
	96	arm,msi-num-spis = <32>;
	97	};
	98	gic_v2m2: v2m@2a0000 {
	99	compatible = "arm,gic-v2m-frame";
	100	msi-controller;
	101	reg = <0x2a0000 0x1000>;
	102	arm,msi-base-spi = <224>;
	103	arm,msi-num-spis = <32>;
	104	};
	105	gic_v2m3: v2m@2b0000 {
	106	compatible = "arm,gic-v2m-frame";
	107	msi-controller;
	108	reg = <0x2b0000 0x1000>;
	109	arm,msi-base-spi = <256>;
	110	arm,msi-num-spis = <32>;
	111	};
	112	};
	113
	114	timer {
	115	compatible = "arm,armv8-timer";
f2a89d3b MZ	116	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	117	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	118	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	119	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
ec7e5a56 TP	120	};
ec7e5a56 TP	121
98e45c16 TP	122	pmu {
	123	compatible = "arm,cortex-a72-pmu";
	124	interrupt-parent = <&pic>;
	125	interrupts = <17>;
	126	};
	127
ec7e5a56 TP	128	odmi: odmi@300000 {
	129	compatible = "marvell,odmi-controller";
	130	interrupt-controller;
	131	msi-controller;
	132	marvell,odmi-frames = <4>;
	133	reg = <0x300000 0x4000>,
	134	<0x304000 0x4000>,
	135	<0x308000 0x4000>,
	136	<0x30C000 0x4000>;
	137	marvell,spi-base = <128>, <136>, <144>, <152>;
	138	};
	139
6ef84a82 TP	140	gicp: gicp@3f0040 {
	141	compatible = "marvell,ap806-gicp";
	142	reg = <0x3f0040 0x10>;
	143	marvell,spi-ranges = <64 64>, <288 64>;
	144	msi-controller;
	145	};
	146
98e45c16 TP	147	pic: interrupt-controller@3f0100 {
	148	compatible = "marvell,armada-8k-pic";
	149	reg = <0x3f0100 0x10>;
	150	#interrupt-cells = <1>;
	151	interrupt-controller;
	152	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
	153	};
	154
b9a5950f MR	155	sei: interrupt-controller@3f0200 {
	156	compatible = "marvell,ap806-sei";
	157	reg = <0x3f0200 0x40>;
	158	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	159	#interrupt-cells = <1>;
	160	interrupt-controller;
	161	msi-controller;
	162	};
	163
1093e5f6	164	xor@400000 {
7eec6594	165	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
b5ebfad8 TP	166	reg = <0x400000 0x1000>,
	167	<0x410000 0x1000>;
	168	msi-parent = <&gic_v2m0>;
a6d8bd91	169	clocks = <&ap_clk 3>;
b5ebfad8 TP	170	dma-coherent;
	171	};
	172
1093e5f6	173	xor@420000 {
7eec6594	174	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
b5ebfad8 TP	175	reg = <0x420000 0x1000>,
	176	<0x430000 0x1000>;
	177	msi-parent = <&gic_v2m0>;
a6d8bd91	178	clocks = <&ap_clk 3>;
b5ebfad8 TP	179	dma-coherent;
	180	};
	181
1093e5f6	182	xor@440000 {
7eec6594	183	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
b5ebfad8 TP	184	reg = <0x440000 0x1000>,
	185	<0x450000 0x1000>;
	186	msi-parent = <&gic_v2m0>;
a6d8bd91	187	clocks = <&ap_clk 3>;
b5ebfad8 TP	188	dma-coherent;
	189	};
	190
1093e5f6	191	xor@460000 {
7eec6594	192	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
b5ebfad8 TP	193	reg = <0x460000 0x1000>,
	194	<0x470000 0x1000>;
	195	msi-parent = <&gic_v2m0>;
a6d8bd91	196	clocks = <&ap_clk 3>;
b5ebfad8 TP	197	dma-coherent;
	198	};
	199
ec7e5a56 TP	200	spi0: spi@510600 {
	201	compatible = "marvell,armada-380-spi";
	202	reg = <0x510600 0x50>;
	203	#address-cells = <1>;
	204	#size-cells = <0>;
ec7e5a56	205	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
3675fb59	206	clocks = <&ap_clk 3>;
ec7e5a56 TP	207	status = "disabled";
	208	};
	209
	210	i2c0: i2c@511000 {
d8b330a3	211	compatible = "marvell,mv78230-i2c";
ec7e5a56 TP	212	reg = <0x511000 0x20>;
	213	#address-cells = <1>;
	214	#size-cells = <0>;
	215	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	216	timeout-ms = <1000>;
3675fb59	217	clocks = <&ap_clk 3>;
ec7e5a56 TP	218	status = "disabled";
	219	};
	220
037ad463	221	uart0: serial@512000 {
ec7e5a56 TP	222	compatible = "snps,dw-apb-uart";
	223	reg = <0x512000 0x100>;
	224	reg-shift = <2>;
	225	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	226	reg-io-width = <1>;
3675fb59	227	clocks = <&ap_clk 3>;
ec7e5a56 TP	228	status = "disabled";
	229	};
	230
037ad463	231	uart1: serial@512100 {
ec7e5a56 TP	232	compatible = "snps,dw-apb-uart";
	233	reg = <0x512100 0x100>;
	234	reg-shift = <2>;
	235	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	236	reg-io-width = <1>;
3675fb59	237	clocks = <&ap_clk 3>;
ec7e5a56 TP	238	status = "disabled";
	239
	240	};
	241
d3ce06b4	242	watchdog: watchdog@610000 {
e34ffe32 BS	243	compatible = "arm,sbsa-gwdt";
	244	reg = <0x610000 0x1000>, <0x600000 0x1000>;
	245	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	246	};
	247
910b4c5c GC	248	ap_sdhci0: sdhci@6e0000 {
	249	compatible = "marvell,armada-ap806-sdhci";
	250	reg = <0x6e0000 0x300>;
	251	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	252	clock-names = "core";
3675fb59	253	clocks = <&ap_clk 4>;
910b4c5c GC	254	dma-coherent;
	255	marvell,xenon-phy-slow-mode;
	256	status = "disabled";
	257	};
	258
bb233a93	259	ap_syscon: system-controller@6f4000 {
3675fb59	260	compatible = "syscon", "simple-mfd";
9e7460fc	261	reg = <0x6f4000 0x2000>;
3675fb59 GC	262
	263	ap_clk: clock {
	264	compatible = "marvell,ap806-clock";
	265	#clock-cells = <1>;
	266	};
ae701b60 GC	267
	268	ap_pinctrl: pinctrl {
	269	compatible = "marvell,ap806-pinctrl";
9e83bbdb TP	270
	271	uart0_pins: uart0-pins {
	272	marvell,pins = "mpp11", "mpp19";
	273	marvell,function = "uart0";
	274	};
ae701b60	275	};
63dac0f4	276
9e7460fc	277	ap_gpio: gpio@1040 {
63dac0f4 GC	278	compatible = "marvell,armada-8k-gpio";
63dac0f4 GC	279	offset = <0x1040>;
a0ac89b5	280	ngpios = <20>;
63dac0f4 GC	281	gpio-controller;
63dac0f4 GC	282	#gpio-cells = <2>;
a0ac89b5	283	gpio-ranges = <&ap_pinctrl 0 0 20>;
63dac0f4	284	};
d2b78fb6	285	};
4cada038	286
0863e01c MR	287	ap_syscon1: system-controller@6f8000 {
	288	compatible = "syscon", "simple-mfd";
	289	reg = <0x6f8000 0x1000>;
	290	#address-cells = <1>;
	291	#size-cells = <1>;
	292
	293	ap_thermal: thermal-sensor@80 {
	294	compatible = "marvell,armada-ap806-thermal";
	295	reg = <0x80 0x10>;
3be14851	296	#thermal-sensor-cells = <1>;
0863e01c	297	};
4cada038	298	};
ec7e5a56 TP	299	};
ec7e5a56 TP	300	};
3be14851 MR	301
	302	/*
	303	* The thermal IP features one internal sensor plus, if applicable, one
	304	* remote channel wired to one sensor per CPU.
	305	*
	306	* The cooling maps are always empty as there are no cooling devices.
	307	*/
	308	thermal-zones {
	309	ap_thermal_ic: ap-thermal-ic {
	310	polling-delay-passive = <1000>;
	311	polling-delay = <1000>;
	312
	313	thermal-sensors = <&ap_thermal 0>;
	314
	315	trips { };
	316	cooling-maps { };
	317	};
	318
	319	ap_thermal_cpu1: ap-thermal-cpu1 {
	320	polling-delay-passive = <1000>;
	321	polling-delay = <1000>;
	322
	323	thermal-sensors = <&ap_thermal 1>;
	324
	325	trips { };
	326	cooling-maps { };
	327	};
	328
	329	ap_thermal_cpu2: ap-thermal-cpu2 {
	330	polling-delay-passive = <1000>;
	331	polling-delay = <1000>;
	332
	333	thermal-sensors = <&ap_thermal 2>;
	334
	335	trips { };
	336	cooling-maps { };
	337	};
	338
	339	ap_thermal_cpu3: ap-thermal-cpu3 {
	340	polling-delay-passive = <1000>;
	341	polling-delay = <1000>;
	342
	343	thermal-sensors = <&ap_thermal 3>;
	344
	345	trips { };
	346	cooling-maps { };
	347	};
	348
	349	ap_thermal_cpu4: ap-thermal-cpu4 {
	350	polling-delay-passive = <1000>;
	351	polling-delay = <1000>;
	352
	353	thermal-sensors = <&ap_thermal 4>;
	354
	355	trips { };
	356	cooling-maps { };
	357	};
	358	};
ec7e5a56	359	};