projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1d0ea069 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 4f357f94 KW |
2 | /** |
| 3 | * dts file for Hisilicon D05 Development Board | |
| 4 | * | |
| 5 | * Copyright (C) 2016 Hisilicon Ltd. | |
| 4f357f94 KW |
6 | */ |
| 7 | ||
| 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 9 | ||
| 10 | / { | |
| 11 | compatible = "hisilicon,hip07-d05"; | |
| 12 | interrupt-parent = <&gic>; | |
| 13 | #address-cells = <2>; | |
| 14 | #size-cells = <2>; | |
| 15 | ||
| 16 | psci { | |
| 17 | compatible = "arm,psci-0.2"; | |
| 18 | method = "smc"; | |
| 19 | }; | |
| 20 | ||
| 21 | cpus { | |
| 22 | #address-cells = <1>; | |
| 23 | #size-cells = <0>; | |
| 24 | ||
| 25 | cpu-map { | |
| 26 | cluster0 { | |
| 27 | core0 { | |
| 28 | cpu = <&cpu0>; | |
| 29 | }; | |
| 30 | core1 { | |
| 31 | cpu = <&cpu1>; | |
| 32 | }; | |
| 33 | core2 { | |
| 34 | cpu = <&cpu2>; | |
| 35 | }; | |
| 36 | core3 { | |
| 37 | cpu = <&cpu3>; | |
| 38 | }; | |
| 39 | }; | |
| 40 | ||
| 41 | cluster1 { | |
| 42 | core0 { | |
| 43 | cpu = <&cpu4>; | |
| 44 | }; | |
| 45 | core1 { | |
| 46 | cpu = <&cpu5>; | |
| 47 | }; | |
| 48 | core2 { | |
| 49 | cpu = <&cpu6>; | |
| 50 | }; | |
| 51 | core3 { | |
| 52 | cpu = <&cpu7>; | |
| 53 | }; | |
| 54 | }; | |
| 55 | ||
| 56 | cluster2 { | |
| 57 | core0 { | |
| 58 | cpu = <&cpu8>; | |
| 59 | }; | |
| 60 | core1 { | |
| 61 | cpu = <&cpu9>; | |
| 62 | }; | |
| 63 | core2 { | |
| 64 | cpu = <&cpu10>; | |
| 65 | }; | |
| 66 | core3 { | |
| 67 | cpu = <&cpu11>; | |
| 68 | }; | |
| 69 | }; | |
| 70 | ||
| 71 | cluster3 { | |
| 72 | core0 { | |
| 73 | cpu = <&cpu12>; | |
| 74 | }; | |
| 75 | core1 { | |
| 76 | cpu = <&cpu13>; | |
| 77 | }; | |
| 78 | core2 { | |
| 79 | cpu = <&cpu14>; | |
| 80 | }; | |
| 81 | core3 { | |
| 82 | cpu = <&cpu15>; | |
| 83 | }; | |
| 84 | }; | |
| 85 | ||
| 86 | cluster4 { | |
| 87 | core0 { | |
| 88 | cpu = <&cpu16>; | |
| 89 | }; | |
| 90 | core1 { | |
| 91 | cpu = <&cpu17>; | |
| 92 | }; | |
| 93 | core2 { | |
| 94 | cpu = <&cpu18>; | |
| 95 | }; | |
| 96 | core3 { | |
| 97 | cpu = <&cpu19>; | |
| 98 | }; | |
| 99 | }; | |
| 100 | ||
| 101 | cluster5 { | |
| 102 | core0 { | |
| 103 | cpu = <&cpu20>; | |
| 104 | }; | |
| 105 | core1 { | |
| 106 | cpu = <&cpu21>; | |
| 107 | }; | |
| 108 | core2 { | |
| 109 | cpu = <&cpu22>; | |
| 110 | }; | |
| 111 | core3 { | |
| 112 | cpu = <&cpu23>; | |
| 113 | }; | |
| 114 | }; | |
| 115 | ||
| 116 | cluster6 { | |
| 117 | core0 { | |
| 118 | cpu = <&cpu24>; | |
| 119 | }; | |
| 120 | core1 { | |
| 121 | cpu = <&cpu25>; | |
| 122 | }; | |
| 123 | core2 { | |
| 124 | cpu = <&cpu26>; | |
| 125 | }; | |
| 126 | core3 { | |
| 127 | cpu = <&cpu27>; | |
| 128 | }; | |
| 129 | }; | |
| 130 | ||
| 131 | cluster7 { | |
| 132 | core0 { | |
| 133 | cpu = <&cpu28>; | |
| 134 | }; | |
| 135 | core1 { | |
| 136 | cpu = <&cpu29>; | |
| 137 | }; | |
| 138 | core2 { | |
| 139 | cpu = <&cpu30>; | |
| 140 | }; | |
| 141 | core3 { | |
| 142 | cpu = <&cpu31>; | |
| 143 | }; | |
| 144 | }; | |
| 145 | ||
| 146 | cluster8 { | |
| 147 | core0 { | |
| 148 | cpu = <&cpu32>; | |
| 149 | }; | |
| 150 | core1 { | |
| 151 | cpu = <&cpu33>; | |
| 152 | }; | |
| 153 | core2 { | |
| 154 | cpu = <&cpu34>; | |
| 155 | }; | |
| 156 | core3 { | |
| 157 | cpu = <&cpu35>; | |
| 158 | }; | |
| 159 | }; | |
| 160 | ||
| 161 | cluster9 { | |
| 162 | core0 { | |
| 163 | cpu = <&cpu36>; | |
| 164 | }; | |
| 165 | core1 { | |
| 166 | cpu = <&cpu37>; | |
| 167 | }; | |
| 168 | core2 { | |
| 169 | cpu = <&cpu38>; | |
| 170 | }; | |
| 171 | core3 { | |
| 172 | cpu = <&cpu39>; | |
| 173 | }; | |
| 174 | }; | |
| 175 | ||
| 176 | cluster10 { | |
| 177 | core0 { | |
| 178 | cpu = <&cpu40>; | |
| 179 | }; | |
| 180 | core1 { | |
| 181 | cpu = <&cpu41>; | |
| 182 | }; | |
| 183 | core2 { | |
| 184 | cpu = <&cpu42>; | |
| 185 | }; | |
| 186 | core3 { | |
| 187 | cpu = <&cpu43>; | |
| 188 | }; | |
| 189 | }; | |
| 190 | ||
| 191 | cluster11 { | |
| 192 | core0 { | |
| 193 | cpu = <&cpu44>; | |
| 194 | }; | |
| 195 | core1 { | |
| 196 | cpu = <&cpu45>; | |
| 197 | }; | |
| 198 | core2 { | |
| 199 | cpu = <&cpu46>; | |
| 200 | }; | |
| 201 | core3 { | |
| 202 | cpu = <&cpu47>; | |
| 203 | }; | |
| 204 | }; | |
| 205 | ||
| 206 | cluster12 { | |
| 207 | core0 { | |
| 208 | cpu = <&cpu48>; | |
| 209 | }; | |
| 210 | core1 { | |
| 211 | cpu = <&cpu49>; | |
| 212 | }; | |
| 213 | core2 { | |
| 214 | cpu = <&cpu50>; | |
| 215 | }; | |
| 216 | core3 { | |
| 217 | cpu = <&cpu51>; | |
| 218 | }; | |
| 219 | }; | |
| 220 | ||
| 221 | cluster13 { | |
| 222 | core0 { | |
| 223 | cpu = <&cpu52>; | |
| 224 | }; | |
| 225 | core1 { | |
| 226 | cpu = <&cpu53>; | |
| 227 | }; | |
| 228 | core2 { | |
| 229 | cpu = <&cpu54>; | |
| 230 | }; | |
| 231 | core3 { | |
| 232 | cpu = <&cpu55>; | |
| 233 | }; | |
| 234 | }; | |
| 235 | ||
| 236 | cluster14 { | |
| 237 | core0 { | |
| 238 | cpu = <&cpu56>; | |
| 239 | }; | |
| 240 | core1 { | |
| 241 | cpu = <&cpu57>; | |
| 242 | }; | |
| 243 | core2 { | |
| 244 | cpu = <&cpu58>; | |
| 245 | }; | |
| 246 | core3 { | |
| 247 | cpu = <&cpu59>; | |
| 248 | }; | |
| 249 | }; | |
| 250 | ||
| 251 | cluster15 { | |
| 252 | core0 { | |
| 253 | cpu = <&cpu60>; | |
| 254 | }; | |
| 255 | core1 { | |
| 256 | cpu = <&cpu61>; | |
| 257 | }; | |
| 258 | core2 { | |
| 259 | cpu = <&cpu62>; | |
| 260 | }; | |
| 261 | core3 { | |
| 262 | cpu = <&cpu63>; | |
| 263 | }; | |
| 264 | }; | |
| 265 | }; | |
| 266 | ||
| 267 | cpu0: cpu@10000 { | |
| 268 | device_type = "cpu"; | |
| 31af04cd | 269 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
270 | reg = <0x10000>; |
| 271 | enable-method = "psci"; | |
| 272 | next-level-cache = <&cluster0_l2>; | |
| 273 | numa-node-id = <0>; | |
| 274 | }; | |
| 275 | ||
| 276 | cpu1: cpu@10001 { | |
| 277 | device_type = "cpu"; | |
| 31af04cd | 278 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
279 | reg = <0x10001>; |
| 280 | enable-method = "psci"; | |
| 281 | next-level-cache = <&cluster0_l2>; | |
| 282 | numa-node-id = <0>; | |
| 283 | }; | |
| 284 | ||
| 285 | cpu2: cpu@10002 { | |
| 286 | device_type = "cpu"; | |
| 31af04cd | 287 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
288 | reg = <0x10002>; |
| 289 | enable-method = "psci"; | |
| 290 | next-level-cache = <&cluster0_l2>; | |
| 291 | numa-node-id = <0>; | |
| 292 | }; | |
| 293 | ||
| 294 | cpu3: cpu@10003 { | |
| 295 | device_type = "cpu"; | |
| 31af04cd | 296 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
297 | reg = <0x10003>; |
| 298 | enable-method = "psci"; | |
| 299 | next-level-cache = <&cluster0_l2>; | |
| 300 | numa-node-id = <0>; | |
| 301 | }; | |
| 302 | ||
| 303 | cpu4: cpu@10100 { | |
| 304 | device_type = "cpu"; | |
| 31af04cd | 305 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
306 | reg = <0x10100>; |
| 307 | enable-method = "psci"; | |
| 308 | next-level-cache = <&cluster1_l2>; | |
| 309 | numa-node-id = <0>; | |
| 310 | }; | |
| 311 | ||
| 312 | cpu5: cpu@10101 { | |
| 313 | device_type = "cpu"; | |
| 31af04cd | 314 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
315 | reg = <0x10101>; |
| 316 | enable-method = "psci"; | |
| 317 | next-level-cache = <&cluster1_l2>; | |
| 318 | numa-node-id = <0>; | |
| 319 | }; | |
| 320 | ||
| 321 | cpu6: cpu@10102 { | |
| 322 | device_type = "cpu"; | |
| 31af04cd | 323 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
324 | reg = <0x10102>; |
| 325 | enable-method = "psci"; | |
| 326 | next-level-cache = <&cluster1_l2>; | |
| 327 | numa-node-id = <0>; | |
| 328 | }; | |
| 329 | ||
| 330 | cpu7: cpu@10103 { | |
| 331 | device_type = "cpu"; | |
| 31af04cd | 332 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
333 | reg = <0x10103>; |
| 334 | enable-method = "psci"; | |
| 335 | next-level-cache = <&cluster1_l2>; | |
| 336 | numa-node-id = <0>; | |
| 337 | }; | |
| 338 | ||
| 339 | cpu8: cpu@10200 { | |
| 340 | device_type = "cpu"; | |
| 31af04cd | 341 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
342 | reg = <0x10200>; |
| 343 | enable-method = "psci"; | |
| 344 | next-level-cache = <&cluster2_l2>; | |
| 345 | numa-node-id = <0>; | |
| 346 | }; | |
| 347 | ||
| 348 | cpu9: cpu@10201 { | |
| 349 | device_type = "cpu"; | |
| 31af04cd | 350 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
351 | reg = <0x10201>; |
| 352 | enable-method = "psci"; | |
| 353 | next-level-cache = <&cluster2_l2>; | |
| 354 | numa-node-id = <0>; | |
| 355 | }; | |
| 356 | ||
| 357 | cpu10: cpu@10202 { | |
| 358 | device_type = "cpu"; | |
| 31af04cd | 359 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
360 | reg = <0x10202>; |
| 361 | enable-method = "psci"; | |
| 362 | next-level-cache = <&cluster2_l2>; | |
| 363 | numa-node-id = <0>; | |
| 364 | }; | |
| 365 | ||
| 366 | cpu11: cpu@10203 { | |
| 367 | device_type = "cpu"; | |
| 31af04cd | 368 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
369 | reg = <0x10203>; |
| 370 | enable-method = "psci"; | |
| 371 | next-level-cache = <&cluster2_l2>; | |
| 372 | numa-node-id = <0>; | |
| 373 | }; | |
| 374 | ||
| 375 | cpu12: cpu@10300 { | |
| 376 | device_type = "cpu"; | |
| 31af04cd | 377 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
378 | reg = <0x10300>; |
| 379 | enable-method = "psci"; | |
| 380 | next-level-cache = <&cluster3_l2>; | |
| 381 | numa-node-id = <0>; | |
| 382 | }; | |
| 383 | ||
| 384 | cpu13: cpu@10301 { | |
| 385 | device_type = "cpu"; | |
| 31af04cd | 386 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
387 | reg = <0x10301>; |
| 388 | enable-method = "psci"; | |
| 389 | next-level-cache = <&cluster3_l2>; | |
| 390 | numa-node-id = <0>; | |
| 391 | }; | |
| 392 | ||
| 393 | cpu14: cpu@10302 { | |
| 394 | device_type = "cpu"; | |
| 31af04cd | 395 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
396 | reg = <0x10302>; |
| 397 | enable-method = "psci"; | |
| 398 | next-level-cache = <&cluster3_l2>; | |
| 399 | numa-node-id = <0>; | |
| 400 | }; | |
| 401 | ||
| 402 | cpu15: cpu@10303 { | |
| 403 | device_type = "cpu"; | |
| 31af04cd | 404 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
405 | reg = <0x10303>; |
| 406 | enable-method = "psci"; | |
| 407 | next-level-cache = <&cluster3_l2>; | |
| 408 | numa-node-id = <0>; | |
| 409 | }; | |
| 410 | ||
| 411 | cpu16: cpu@30000 { | |
| 412 | device_type = "cpu"; | |
| 31af04cd | 413 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
414 | reg = <0x30000>; |
| 415 | enable-method = "psci"; | |
| 416 | next-level-cache = <&cluster4_l2>; | |
| 417 | numa-node-id = <1>; | |
| 418 | }; | |
| 419 | ||
| 420 | cpu17: cpu@30001 { | |
| 421 | device_type = "cpu"; | |
| 31af04cd | 422 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
423 | reg = <0x30001>; |
| 424 | enable-method = "psci"; | |
| 425 | next-level-cache = <&cluster4_l2>; | |
| 426 | numa-node-id = <1>; | |
| 427 | }; | |
| 428 | ||
| 429 | cpu18: cpu@30002 { | |
| 430 | device_type = "cpu"; | |
| 31af04cd | 431 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
432 | reg = <0x30002>; |
| 433 | enable-method = "psci"; | |
| 434 | next-level-cache = <&cluster4_l2>; | |
| 435 | numa-node-id = <1>; | |
| 436 | }; | |
| 437 | ||
| 438 | cpu19: cpu@30003 { | |
| 439 | device_type = "cpu"; | |
| 31af04cd | 440 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
441 | reg = <0x30003>; |
| 442 | enable-method = "psci"; | |
| 443 | next-level-cache = <&cluster4_l2>; | |
| 444 | numa-node-id = <1>; | |
| 445 | }; | |
| 446 | ||
| 447 | cpu20: cpu@30100 { | |
| 448 | device_type = "cpu"; | |
| 31af04cd | 449 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
450 | reg = <0x30100>; |
| 451 | enable-method = "psci"; | |
| 452 | next-level-cache = <&cluster5_l2>; | |
| 453 | numa-node-id = <1>; | |
| 454 | }; | |
| 455 | ||
| 456 | cpu21: cpu@30101 { | |
| 457 | device_type = "cpu"; | |
| 31af04cd | 458 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
459 | reg = <0x30101>; |
| 460 | enable-method = "psci"; | |
| 461 | next-level-cache = <&cluster5_l2>; | |
| 462 | numa-node-id = <1>; | |
| 463 | }; | |
| 464 | ||
| 465 | cpu22: cpu@30102 { | |
| 466 | device_type = "cpu"; | |
| 31af04cd | 467 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
468 | reg = <0x30102>; |
| 469 | enable-method = "psci"; | |
| 470 | next-level-cache = <&cluster5_l2>; | |
| 471 | numa-node-id = <1>; | |
| 472 | }; | |
| 473 | ||
| 474 | cpu23: cpu@30103 { | |
| 475 | device_type = "cpu"; | |
| 31af04cd | 476 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
477 | reg = <0x30103>; |
| 478 | enable-method = "psci"; | |
| 479 | next-level-cache = <&cluster5_l2>; | |
| 480 | numa-node-id = <1>; | |
| 481 | }; | |
| 482 | ||
| 483 | cpu24: cpu@30200 { | |
| 484 | device_type = "cpu"; | |
| 31af04cd | 485 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
486 | reg = <0x30200>; |
| 487 | enable-method = "psci"; | |
| 488 | next-level-cache = <&cluster6_l2>; | |
| 489 | numa-node-id = <1>; | |
| 490 | }; | |
| 491 | ||
| 492 | cpu25: cpu@30201 { | |
| 493 | device_type = "cpu"; | |
| 31af04cd | 494 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
495 | reg = <0x30201>; |
| 496 | enable-method = "psci"; | |
| 497 | next-level-cache = <&cluster6_l2>; | |
| 498 | numa-node-id = <1>; | |
| 499 | }; | |
| 500 | ||
| 501 | cpu26: cpu@30202 { | |
| 502 | device_type = "cpu"; | |
| 31af04cd | 503 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
504 | reg = <0x30202>; |
| 505 | enable-method = "psci"; | |
| 506 | next-level-cache = <&cluster6_l2>; | |
| 507 | numa-node-id = <1>; | |
| 508 | }; | |
| 509 | ||
| 510 | cpu27: cpu@30203 { | |
| 511 | device_type = "cpu"; | |
| 31af04cd | 512 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
513 | reg = <0x30203>; |
| 514 | enable-method = "psci"; | |
| 515 | next-level-cache = <&cluster6_l2>; | |
| 516 | numa-node-id = <1>; | |
| 517 | }; | |
| 518 | ||
| 519 | cpu28: cpu@30300 { | |
| 520 | device_type = "cpu"; | |
| 31af04cd | 521 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
522 | reg = <0x30300>; |
| 523 | enable-method = "psci"; | |
| 524 | next-level-cache = <&cluster7_l2>; | |
| 525 | numa-node-id = <1>; | |
| 526 | }; | |
| 527 | ||
| 528 | cpu29: cpu@30301 { | |
| 529 | device_type = "cpu"; | |
| 31af04cd | 530 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
531 | reg = <0x30301>; |
| 532 | enable-method = "psci"; | |
| 533 | next-level-cache = <&cluster7_l2>; | |
| 534 | numa-node-id = <1>; | |
| 535 | }; | |
| 536 | ||
| 537 | cpu30: cpu@30302 { | |
| 538 | device_type = "cpu"; | |
| 31af04cd | 539 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
540 | reg = <0x30302>; |
| 541 | enable-method = "psci"; | |
| 542 | next-level-cache = <&cluster7_l2>; | |
| 543 | numa-node-id = <1>; | |
| 544 | }; | |
| 545 | ||
| 546 | cpu31: cpu@30303 { | |
| 547 | device_type = "cpu"; | |
| 31af04cd | 548 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
549 | reg = <0x30303>; |
| 550 | enable-method = "psci"; | |
| 551 | next-level-cache = <&cluster7_l2>; | |
| 552 | numa-node-id = <1>; | |
| 553 | }; | |
| 554 | ||
| 555 | cpu32: cpu@50000 { | |
| 556 | device_type = "cpu"; | |
| 31af04cd | 557 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
558 | reg = <0x50000>; |
| 559 | enable-method = "psci"; | |
| 560 | next-level-cache = <&cluster8_l2>; | |
| 561 | numa-node-id = <2>; | |
| 562 | }; | |
| 563 | ||
| 564 | cpu33: cpu@50001 { | |
| 565 | device_type = "cpu"; | |
| 31af04cd | 566 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
567 | reg = <0x50001>; |
| 568 | enable-method = "psci"; | |
| 569 | next-level-cache = <&cluster8_l2>; | |
| 570 | numa-node-id = <2>; | |
| 571 | }; | |
| 572 | ||
| 573 | cpu34: cpu@50002 { | |
| 574 | device_type = "cpu"; | |
| 31af04cd | 575 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
576 | reg = <0x50002>; |
| 577 | enable-method = "psci"; | |
| 578 | next-level-cache = <&cluster8_l2>; | |
| 579 | numa-node-id = <2>; | |
| 580 | }; | |
| 581 | ||
| 582 | cpu35: cpu@50003 { | |
| 583 | device_type = "cpu"; | |
| 31af04cd | 584 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
585 | reg = <0x50003>; |
| 586 | enable-method = "psci"; | |
| 587 | next-level-cache = <&cluster8_l2>; | |
| 588 | numa-node-id = <2>; | |
| 589 | }; | |
| 590 | ||
| 591 | cpu36: cpu@50100 { | |
| 592 | device_type = "cpu"; | |
| 31af04cd | 593 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
594 | reg = <0x50100>; |
| 595 | enable-method = "psci"; | |
| 596 | next-level-cache = <&cluster9_l2>; | |
| 597 | numa-node-id = <2>; | |
| 598 | }; | |
| 599 | ||
| 600 | cpu37: cpu@50101 { | |
| 601 | device_type = "cpu"; | |
| 31af04cd | 602 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
603 | reg = <0x50101>; |
| 604 | enable-method = "psci"; | |
| 605 | next-level-cache = <&cluster9_l2>; | |
| 606 | numa-node-id = <2>; | |
| 607 | }; | |
| 608 | ||
| 609 | cpu38: cpu@50102 { | |
| 610 | device_type = "cpu"; | |
| 31af04cd | 611 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
612 | reg = <0x50102>; |
| 613 | enable-method = "psci"; | |
| 614 | next-level-cache = <&cluster9_l2>; | |
| 615 | numa-node-id = <2>; | |
| 616 | }; | |
| 617 | ||
| 618 | cpu39: cpu@50103 { | |
| 619 | device_type = "cpu"; | |
| 31af04cd | 620 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
621 | reg = <0x50103>; |
| 622 | enable-method = "psci"; | |
| 623 | next-level-cache = <&cluster9_l2>; | |
| 624 | numa-node-id = <2>; | |
| 625 | }; | |
| 626 | ||
| 627 | cpu40: cpu@50200 { | |
| 628 | device_type = "cpu"; | |
| 31af04cd | 629 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
630 | reg = <0x50200>; |
| 631 | enable-method = "psci"; | |
| 632 | next-level-cache = <&cluster10_l2>; | |
| 633 | numa-node-id = <2>; | |
| 634 | }; | |
| 635 | ||
| 636 | cpu41: cpu@50201 { | |
| 637 | device_type = "cpu"; | |
| 31af04cd | 638 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
639 | reg = <0x50201>; |
| 640 | enable-method = "psci"; | |
| 641 | next-level-cache = <&cluster10_l2>; | |
| 642 | numa-node-id = <2>; | |
| 643 | }; | |
| 644 | ||
| 645 | cpu42: cpu@50202 { | |
| 646 | device_type = "cpu"; | |
| 31af04cd | 647 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
648 | reg = <0x50202>; |
| 649 | enable-method = "psci"; | |
| 650 | next-level-cache = <&cluster10_l2>; | |
| 651 | numa-node-id = <2>; | |
| 652 | }; | |
| 653 | ||
| 654 | cpu43: cpu@50203 { | |
| 655 | device_type = "cpu"; | |
| 31af04cd | 656 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
657 | reg = <0x50203>; |
| 658 | enable-method = "psci"; | |
| 659 | next-level-cache = <&cluster10_l2>; | |
| 660 | numa-node-id = <2>; | |
| 661 | }; | |
| 662 | ||
| 663 | cpu44: cpu@50300 { | |
| 664 | device_type = "cpu"; | |
| 31af04cd | 665 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
666 | reg = <0x50300>; |
| 667 | enable-method = "psci"; | |
| 668 | next-level-cache = <&cluster11_l2>; | |
| 669 | numa-node-id = <2>; | |
| 670 | }; | |
| 671 | ||
| 672 | cpu45: cpu@50301 { | |
| 673 | device_type = "cpu"; | |
| 31af04cd | 674 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
675 | reg = <0x50301>; |
| 676 | enable-method = "psci"; | |
| 677 | next-level-cache = <&cluster11_l2>; | |
| 678 | numa-node-id = <2>; | |
| 679 | }; | |
| 680 | ||
| 681 | cpu46: cpu@50302 { | |
| 682 | device_type = "cpu"; | |
| 31af04cd | 683 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
684 | reg = <0x50302>; |
| 685 | enable-method = "psci"; | |
| 686 | next-level-cache = <&cluster11_l2>; | |
| 687 | numa-node-id = <2>; | |
| 688 | }; | |
| 689 | ||
| 690 | cpu47: cpu@50303 { | |
| 691 | device_type = "cpu"; | |
| 31af04cd | 692 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
693 | reg = <0x50303>; |
| 694 | enable-method = "psci"; | |
| 695 | next-level-cache = <&cluster11_l2>; | |
| 696 | numa-node-id = <2>; | |
| 697 | }; | |
| 698 | ||
| 699 | cpu48: cpu@70000 { | |
| 700 | device_type = "cpu"; | |
| 31af04cd | 701 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
702 | reg = <0x70000>; |
| 703 | enable-method = "psci"; | |
| 704 | next-level-cache = <&cluster12_l2>; | |
| 705 | numa-node-id = <3>; | |
| 706 | }; | |
| 707 | ||
| 708 | cpu49: cpu@70001 { | |
| 709 | device_type = "cpu"; | |
| 31af04cd | 710 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
711 | reg = <0x70001>; |
| 712 | enable-method = "psci"; | |
| 713 | next-level-cache = <&cluster12_l2>; | |
| 714 | numa-node-id = <3>; | |
| 715 | }; | |
| 716 | ||
| 717 | cpu50: cpu@70002 { | |
| 718 | device_type = "cpu"; | |
| 31af04cd | 719 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
720 | reg = <0x70002>; |
| 721 | enable-method = "psci"; | |
| 722 | next-level-cache = <&cluster12_l2>; | |
| 723 | numa-node-id = <3>; | |
| 724 | }; | |
| 725 | ||
| 726 | cpu51: cpu@70003 { | |
| 727 | device_type = "cpu"; | |
| 31af04cd | 728 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
729 | reg = <0x70003>; |
| 730 | enable-method = "psci"; | |
| 731 | next-level-cache = <&cluster12_l2>; | |
| 732 | numa-node-id = <3>; | |
| 733 | }; | |
| 734 | ||
| 735 | cpu52: cpu@70100 { | |
| 736 | device_type = "cpu"; | |
| 31af04cd | 737 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
738 | reg = <0x70100>; |
| 739 | enable-method = "psci"; | |
| 740 | next-level-cache = <&cluster13_l2>; | |
| 741 | numa-node-id = <3>; | |
| 742 | }; | |
| 743 | ||
| 744 | cpu53: cpu@70101 { | |
| 745 | device_type = "cpu"; | |
| 31af04cd | 746 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
747 | reg = <0x70101>; |
| 748 | enable-method = "psci"; | |
| 749 | next-level-cache = <&cluster13_l2>; | |
| 750 | numa-node-id = <3>; | |
| 751 | }; | |
| 752 | ||
| 753 | cpu54: cpu@70102 { | |
| 754 | device_type = "cpu"; | |
| 31af04cd | 755 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
756 | reg = <0x70102>; |
| 757 | enable-method = "psci"; | |
| 758 | next-level-cache = <&cluster13_l2>; | |
| 759 | numa-node-id = <3>; | |
| 760 | }; | |
| 761 | ||
| 762 | cpu55: cpu@70103 { | |
| 763 | device_type = "cpu"; | |
| 31af04cd | 764 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
765 | reg = <0x70103>; |
| 766 | enable-method = "psci"; | |
| 767 | next-level-cache = <&cluster13_l2>; | |
| 768 | numa-node-id = <3>; | |
| 769 | }; | |
| 770 | ||
| 771 | cpu56: cpu@70200 { | |
| 772 | device_type = "cpu"; | |
| 31af04cd | 773 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
774 | reg = <0x70200>; |
| 775 | enable-method = "psci"; | |
| 776 | next-level-cache = <&cluster14_l2>; | |
| 777 | numa-node-id = <3>; | |
| 778 | }; | |
| 779 | ||
| 780 | cpu57: cpu@70201 { | |
| 781 | device_type = "cpu"; | |
| 31af04cd | 782 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
783 | reg = <0x70201>; |
| 784 | enable-method = "psci"; | |
| 785 | next-level-cache = <&cluster14_l2>; | |
| 786 | numa-node-id = <3>; | |
| 787 | }; | |
| 788 | ||
| 789 | cpu58: cpu@70202 { | |
| 790 | device_type = "cpu"; | |
| 31af04cd | 791 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
792 | reg = <0x70202>; |
| 793 | enable-method = "psci"; | |
| 794 | next-level-cache = <&cluster14_l2>; | |
| 795 | numa-node-id = <3>; | |
| 796 | }; | |
| 797 | ||
| 798 | cpu59: cpu@70203 { | |
| 799 | device_type = "cpu"; | |
| 31af04cd | 800 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
801 | reg = <0x70203>; |
| 802 | enable-method = "psci"; | |
| 803 | next-level-cache = <&cluster14_l2>; | |
| 804 | numa-node-id = <3>; | |
| 805 | }; | |
| 806 | ||
| 807 | cpu60: cpu@70300 { | |
| 808 | device_type = "cpu"; | |
| 31af04cd | 809 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
810 | reg = <0x70300>; |
| 811 | enable-method = "psci"; | |
| 812 | next-level-cache = <&cluster15_l2>; | |
| 813 | numa-node-id = <3>; | |
| 814 | }; | |
| 815 | ||
| 816 | cpu61: cpu@70301 { | |
| 817 | device_type = "cpu"; | |
| 31af04cd | 818 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
819 | reg = <0x70301>; |
| 820 | enable-method = "psci"; | |
| 821 | next-level-cache = <&cluster15_l2>; | |
| 822 | numa-node-id = <3>; | |
| 823 | }; | |
| 824 | ||
| 825 | cpu62: cpu@70302 { | |
| 826 | device_type = "cpu"; | |
| 31af04cd | 827 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
828 | reg = <0x70302>; |
| 829 | enable-method = "psci"; | |
| 830 | next-level-cache = <&cluster15_l2>; | |
| 831 | numa-node-id = <3>; | |
| 832 | }; | |
| 833 | ||
| 834 | cpu63: cpu@70303 { | |
| 835 | device_type = "cpu"; | |
| 31af04cd | 836 | compatible = "arm,cortex-a72"; |
| 4f357f94 KW |
837 | reg = <0x70303>; |
| 838 | enable-method = "psci"; | |
| 839 | next-level-cache = <&cluster15_l2>; | |
| 840 | numa-node-id = <3>; | |
| 841 | }; | |
| 842 | ||
| 843 | cluster0_l2: l2-cache0 { | |
| 844 | compatible = "cache"; | |
| 845 | }; | |
| 846 | ||
| 847 | cluster1_l2: l2-cache1 { | |
| 848 | compatible = "cache"; | |
| 849 | }; | |
| 850 | ||
| 851 | cluster2_l2: l2-cache2 { | |
| 852 | compatible = "cache"; | |
| 853 | }; | |
| 854 | ||
| 855 | cluster3_l2: l2-cache3 { | |
| 856 | compatible = "cache"; | |
| 857 | }; | |
| 858 | ||
| 859 | cluster4_l2: l2-cache4 { | |
| 860 | compatible = "cache"; | |
| 861 | }; | |
| 862 | ||
| 863 | cluster5_l2: l2-cache5 { | |
| 864 | compatible = "cache"; | |
| 865 | }; | |
| 866 | ||
| 867 | cluster6_l2: l2-cache6 { | |
| 868 | compatible = "cache"; | |
| 869 | }; | |
| 870 | ||
| 871 | cluster7_l2: l2-cache7 { | |
| 872 | compatible = "cache"; | |
| 873 | }; | |
| 874 | ||
| 875 | cluster8_l2: l2-cache8 { | |
| 876 | compatible = "cache"; | |
| 877 | }; | |
| 878 | ||
| 879 | cluster9_l2: l2-cache9 { | |
| 880 | compatible = "cache"; | |
| 881 | }; | |
| 882 | ||
| 883 | cluster10_l2: l2-cache10 { | |
| 884 | compatible = "cache"; | |
| 885 | }; | |
| 886 | ||
| 887 | cluster11_l2: l2-cache11 { | |
| 888 | compatible = "cache"; | |
| 889 | }; | |
| 890 | ||
| 891 | cluster12_l2: l2-cache12 { | |
| 892 | compatible = "cache"; | |
| 893 | }; | |
| 894 | ||
| 895 | cluster13_l2: l2-cache13 { | |
| 896 | compatible = "cache"; | |
| 897 | }; | |
| 898 | ||
| 899 | cluster14_l2: l2-cache14 { | |
| 900 | compatible = "cache"; | |
| 901 | }; | |
| 902 | ||
| 903 | cluster15_l2: l2-cache15 { | |
| 904 | compatible = "cache"; | |
| 905 | }; | |
| 906 | }; | |
| 907 | ||
| 908 | gic: interrupt-controller@4d000000 { | |
| 909 | compatible = "arm,gic-v3"; | |
| 910 | #interrupt-cells = <3>; | |
| 911 | #address-cells = <2>; | |
| 912 | #size-cells = <2>; | |
| 913 | ranges; | |
| 914 | interrupt-controller; | |
| 915 | #redistributor-regions = <4>; | |
| 916 | redistributor-stride = <0x0 0x40000>; | |
| 917 | reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */ | |
| 918 | <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */ | |
| 919 | <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */ | |
| 920 | <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */ | |
| 921 | <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */ | |
| 922 | <0x0 0xfe000000 0x0 0x10000>, /* GICC */ | |
| 923 | <0x0 0xfe010000 0x0 0x10000>, /* GICH */ | |
| 924 | <0x0 0xfe020000 0x0 0x10000>; /* GICV */ | |
| 925 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 926 | ||
| 927 | p0_its_peri_a: interrupt-controller@4c000000 { | |
| 928 | compatible = "arm,gic-v3-its"; | |
| 929 | msi-controller; | |
| 930 | #msi-cells = <1>; | |
| 931 | reg = <0x0 0x4c000000 0x0 0x40000>; | |
| 932 | }; | |
| 933 | ||
| 934 | p0_its_peri_b: interrupt-controller@6c000000 { | |
| 935 | compatible = "arm,gic-v3-its"; | |
| 936 | msi-controller; | |
| 937 | #msi-cells = <1>; | |
| 938 | reg = <0x0 0x6c000000 0x0 0x40000>; | |
| 939 | }; | |
| 940 | ||
| 941 | p0_its_dsa_a: interrupt-controller@c6000000 { | |
| 942 | compatible = "arm,gic-v3-its"; | |
| 943 | msi-controller; | |
| 944 | #msi-cells = <1>; | |
| 945 | reg = <0x0 0xc6000000 0x0 0x40000>; | |
| 946 | }; | |
| 947 | ||
| 948 | p0_its_dsa_b: interrupt-controller@8,c6000000 { | |
| 949 | compatible = "arm,gic-v3-its"; | |
| 950 | msi-controller; | |
| 951 | #msi-cells = <1>; | |
| 952 | reg = <0x8 0xc6000000 0x0 0x40000>; | |
| 953 | }; | |
| 954 | ||
| 955 | p1_its_peri_a: interrupt-controller@400,4c000000 { | |
| 956 | compatible = "arm,gic-v3-its"; | |
| 957 | msi-controller; | |
| 958 | #msi-cells = <1>; | |
| 959 | reg = <0x400 0x4c000000 0x0 0x40000>; | |
| 960 | }; | |
| 961 | ||
| 962 | p1_its_peri_b: interrupt-controller@400,6c000000 { | |
| 963 | compatible = "arm,gic-v3-its"; | |
| 964 | msi-controller; | |
| 965 | #msi-cells = <1>; | |
| 966 | reg = <0x400 0x6c000000 0x0 0x40000>; | |
| 967 | }; | |
| 968 | ||
| 969 | p1_its_dsa_a: interrupt-controller@400,c6000000 { | |
| 970 | compatible = "arm,gic-v3-its"; | |
| 971 | msi-controller; | |
| 972 | #msi-cells = <1>; | |
| 973 | reg = <0x400 0xc6000000 0x0 0x40000>; | |
| 974 | }; | |
| 975 | ||
| 976 | p1_its_dsa_b: interrupt-controller@408,c6000000 { | |
| 977 | compatible = "arm,gic-v3-its"; | |
| 978 | msi-controller; | |
| 979 | #msi-cells = <1>; | |
| 980 | reg = <0x408 0xc6000000 0x0 0x40000>; | |
| 981 | }; | |
| 982 | }; | |
| 983 | ||
| 984 | timer { | |
| 985 | compatible = "arm,armv8-timer"; | |
| 986 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, | |
| 987 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, | |
| 988 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, | |
| 989 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; | |
| 990 | }; | |
| 991 | ||
| 992 | pmu { | |
| 993 | compatible = "arm,cortex-a72-pmu"; | |
| 994 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 995 | }; | |
| 996 | ||
| 997 | p0_mbigen_peri_b: interrupt-controller@60080000 { | |
| 998 | compatible = "hisilicon,mbigen-v2"; | |
| 999 | reg = <0x0 0x60080000 0x0 0x10000>; | |
| 1000 | ||
| 1001 | mbigen_uart: uart_intc { | |
| 1002 | msi-parent = <&p0_its_peri_b 0x120c7>; | |
| 1003 | interrupt-controller; | |
| 1004 | #interrupt-cells = <2>; | |
| 1005 | num-pins = <1>; | |
| 1006 | }; | |
| 1007 | }; | |
| 1008 | ||
| 1009 | p0_mbigen_pcie_a: interrupt-controller@a0080000 { | |
| 1010 | compatible = "hisilicon,mbigen-v2"; | |
| 1011 | reg = <0x0 0xa0080000 0x0 0x10000>; | |
| 1012 | ||
| bbeca45f WX |
1013 | mbigen_pcie2_a: intc_pcie2_a { |
| 1014 | msi-parent = <&p0_its_dsa_a 0x40087>; | |
| 1015 | interrupt-controller; | |
| 1016 | #interrupt-cells = <2>; | |
| 1017 | num-pins = <10>; | |
| 1018 | }; | |
| 1019 | ||
| 1020 | mbigen_sas1: intc_sas1 { | |
| 1021 | msi-parent = <&p0_its_dsa_a 0x40000>; | |
| 1022 | interrupt-controller; | |
| 1023 | #interrupt-cells = <2>; | |
| 1024 | num-pins = <128>; | |
| 1025 | }; | |
| 1026 | ||
| 1027 | mbigen_sas2: intc_sas2 { | |
| 1028 | msi-parent = <&p0_its_dsa_a 0x40040>; | |
| 1029 | interrupt-controller; | |
| 1030 | #interrupt-cells = <2>; | |
| 1031 | num-pins = <128>; | |
| 1032 | }; | |
| 1033 | ||
| 1034 | mbigen_smmu_pcie: intc_smmu_pcie { | |
| 1035 | msi-parent = <&p0_its_dsa_a 0x40b0c>; | |
| 1036 | interrupt-controller; | |
| 1037 | #interrupt-cells = <2>; | |
| 1038 | num-pins = <3>; | |
| 1039 | }; | |
| 1040 | ||
| 4f357f94 KW |
1041 | mbigen_usb: intc_usb { |
| 1042 | msi-parent = <&p0_its_dsa_a 0x40080>; | |
| 1043 | interrupt-controller; | |
| 1044 | #interrupt-cells = <2>; | |
| 1045 | num-pins = <2>; | |
| 1046 | }; | |
| 1047 | }; | |
| e4a1f785 JC |
1048 | p0_mbigen_alg_a:interrupt-controller@d0080000 { |
| 1049 | compatible = "hisilicon,mbigen-v2"; | |
| 1050 | reg = <0x0 0xd0080000 0x0 0x10000>; | |
| 4f357f94 | 1051 | |
| e4a1f785 JC |
1052 | p0_mbigen_sec_a: intc_sec { |
| 1053 | msi-parent = <&p0_its_dsa_a 0x40400>; | |
| 1054 | interrupt-controller; | |
| 1055 | #interrupt-cells = <2>; | |
| 1056 | num-pins = <33>; | |
| 1057 | }; | |
| 1058 | p0_mbigen_smmu_alg_a: intc_smmu_alg { | |
| 1059 | msi-parent = <&p0_its_dsa_a 0x40b1b>; | |
| 1060 | interrupt-controller; | |
| 1061 | #interrupt-cells = <2>; | |
| 1062 | num-pins = <3>; | |
| 1063 | }; | |
| 1064 | }; | |
| 1065 | p0_mbigen_alg_b:interrupt-controller@8,d0080000 { | |
| 1066 | compatible = "hisilicon,mbigen-v2"; | |
| 1067 | reg = <0x8 0xd0080000 0x0 0x10000>; | |
| 1068 | ||
| 1069 | p0_mbigen_sec_b: intc_sec { | |
| 1070 | msi-parent = <&p0_its_dsa_b 0x42400>; | |
| 1071 | interrupt-controller; | |
| 1072 | #interrupt-cells = <2>; | |
| 1073 | num-pins = <33>; | |
| 1074 | }; | |
| 1075 | p0_mbigen_smmu_alg_b: intc_smmu_alg { | |
| 1076 | msi-parent = <&p0_its_dsa_b 0x42b1b>; | |
| 1077 | interrupt-controller; | |
| 1078 | #interrupt-cells = <2>; | |
| 1079 | num-pins = <3>; | |
| 1080 | }; | |
| 1081 | }; | |
| 1082 | p1_mbigen_alg_a:interrupt-controller@400,d0080000 { | |
| 1083 | compatible = "hisilicon,mbigen-v2"; | |
| 1084 | reg = <0x400 0xd0080000 0x0 0x10000>; | |
| 1085 | ||
| 1086 | p1_mbigen_sec_a: intc_sec { | |
| 1087 | msi-parent = <&p1_its_dsa_a 0x44400>; | |
| 1088 | interrupt-controller; | |
| 1089 | #interrupt-cells = <2>; | |
| 1090 | num-pins = <33>; | |
| 1091 | }; | |
| 1092 | p1_mbigen_smmu_alg_a: intc_smmu_alg { | |
| 1093 | msi-parent = <&p1_its_dsa_a 0x44b1b>; | |
| 1094 | interrupt-controller; | |
| 1095 | #interrupt-cells = <2>; | |
| 1096 | num-pins = <3>; | |
| 1097 | }; | |
| 1098 | }; | |
| 1099 | p1_mbigen_alg_b:interrupt-controller@408,d0080000 { | |
| 1100 | compatible = "hisilicon,mbigen-v2"; | |
| 1101 | reg = <0x408 0xd0080000 0x0 0x10000>; | |
| 1102 | ||
| 1103 | p1_mbigen_sec_b: intc_sec { | |
| 1104 | msi-parent = <&p1_its_dsa_b 0x46400>; | |
| 1105 | interrupt-controller; | |
| 1106 | #interrupt-cells = <2>; | |
| 1107 | num-pins = <33>; | |
| 1108 | }; | |
| 1109 | p1_mbigen_smmu_alg_b: intc_smmu_alg { | |
| 1110 | msi-parent = <&p1_its_dsa_b 0x46b1b>; | |
| 1111 | interrupt-controller; | |
| 1112 | #interrupt-cells = <2>; | |
| 1113 | num-pins = <3>; | |
| 1114 | }; | |
| 1115 | }; | |
| bbeca45f WX |
1116 | p0_mbigen_dsa_a: interrupt-controller@c0080000 { |
| 1117 | compatible = "hisilicon,mbigen-v2"; | |
| 1118 | reg = <0x0 0xc0080000 0x0 0x10000>; | |
| 1119 | ||
| 1120 | mbigen_dsaf0: intc_dsaf0 { | |
| 1121 | msi-parent = <&p0_its_dsa_a 0x40800>; | |
| 1122 | interrupt-controller; | |
| 1123 | #interrupt-cells = <2>; | |
| 1124 | num-pins = <409>; | |
| 1125 | }; | |
| 1126 | ||
| 1127 | mbigen_dsa_roce: intc-roce { | |
| 1128 | msi-parent = <&p0_its_dsa_a 0x40B1E>; | |
| 1129 | interrupt-controller; | |
| 1130 | #interrupt-cells = <2>; | |
| 1131 | num-pins = <34>; | |
| 1132 | }; | |
| 1133 | ||
| 1134 | mbigen_sas0: intc-sas0 { | |
| 1135 | msi-parent = <&p0_its_dsa_a 0x40900>; | |
| 1136 | interrupt-controller; | |
| 1137 | #interrupt-cells = <2>; | |
| 1138 | num-pins = <128>; | |
| 1139 | }; | |
| 1140 | ||
| 1141 | mbigen_smmu_dsa: intc_smmu_dsa { | |
| 1142 | msi-parent = <&p0_its_dsa_a 0x40b20>; | |
| 1143 | interrupt-controller; | |
| 1144 | #interrupt-cells = <2>; | |
| 1145 | num-pins = <3>; | |
| 1146 | }; | |
| 1147 | }; | |
| 1148 | ||
| 17f21343 SKT |
1149 | /** |
| 1150 | * HiSilicon erratum 161010801: This describes the limitation | |
| 1151 | * of HiSilicon platforms hip06/hip07 to support the SMMUv3 | |
| 1152 | * mappings for PCIe MSI transactions. | |
| 1153 | * PCIe controller on these platforms has to differentiate the | |
| 1154 | * MSI payload against other DMA payload and has to modify the | |
| 1155 | * MSI payload. This makes it difficult for these platforms to | |
| 1156 | * have a SMMU translation for MSI. In order to workaround this, | |
| 1157 | * ARM SMMUv3 driver requires a quirk to treat the MSI regions | |
| 1158 | * separately. Such a quirk is currently missing for DT based | |
| 1159 | * systems. Hence please make sure that the smmu pcie node on | |
| 1160 | * hip07 is disabled as this will break the PCIe functionality | |
| 1161 | * when iommu-map entry is used along with the PCIe node. | |
| 1162 | * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html | |
| 1163 | */ | |
| 1164 | smmu0: smmu_pcie { | |
| 1165 | compatible = "arm,smmu-v3"; | |
| 1166 | reg = <0x0 0xa0040000 0x0 0x20000>; | |
| 1167 | #iommu-cells = <1>; | |
| 1168 | dma-coherent; | |
| 1169 | smmu-cb-memtype = <0x0 0x1>; | |
| 1170 | hisilicon,broken-prefetch-cmd; | |
| 1171 | status = "disabled"; | |
| 1172 | }; | |
| e4a1f785 JC |
1173 | p0_smmu_alg_a: smmu_alg@d0040000 { |
| 1174 | compatible = "arm,smmu-v3"; | |
| 1175 | reg = <0x0 0xd0040000 0x0 0x20000>; | |
| 1176 | interrupt-parent = <&p0_mbigen_smmu_alg_a>; | |
| 1177 | interrupts = <733 1>, | |
| 1178 | <734 1>, | |
| 1179 | <735 1>; | |
| 1180 | interrupt-names = "eventq", "gerror", "priq"; | |
| 1181 | #iommu-cells = <1>; | |
| 1182 | dma-coherent; | |
| 1183 | hisilicon,broken-prefetch-cmd; | |
| 1184 | /* smmu-cb-memtype = <0x0 0x1>;*/ | |
| 1185 | }; | |
| 1186 | p0_smmu_alg_b: smmu_alg@8,d0040000 { | |
| 1187 | compatible = "arm,smmu-v3"; | |
| 1188 | reg = <0x8 0xd0040000 0x0 0x20000>; | |
| 1189 | interrupt-parent = <&p0_mbigen_smmu_alg_b>; | |
| 1190 | interrupts = <733 1>, | |
| 1191 | <734 1>, | |
| 1192 | <735 1>; | |
| 1193 | interrupt-names = "eventq", "gerror", "priq"; | |
| 1194 | #iommu-cells = <1>; | |
| 1195 | dma-coherent; | |
| 1196 | hisilicon,broken-prefetch-cmd; | |
| 1197 | /* smmu-cb-memtype = <0x0 0x1>;*/ | |
| 1198 | }; | |
| 1199 | p1_smmu_alg_a: smmu_alg@400,d0040000 { | |
| 1200 | compatible = "arm,smmu-v3"; | |
| 1201 | reg = <0x400 0xd0040000 0x0 0x20000>; | |
| 1202 | interrupt-parent = <&p1_mbigen_smmu_alg_a>; | |
| 1203 | interrupts = <733 1>, | |
| 1204 | <734 1>, | |
| 1205 | <735 1>; | |
| 1206 | interrupt-names = "eventq", "gerror", "priq"; | |
| 1207 | #iommu-cells = <1>; | |
| 1208 | dma-coherent; | |
| 1209 | hisilicon,broken-prefetch-cmd; | |
| 1210 | /* smmu-cb-memtype = <0x0 0x1>;*/ | |
| 1211 | }; | |
| 1212 | p1_smmu_alg_b: smmu_alg@408,d0040000 { | |
| 1213 | compatible = "arm,smmu-v3"; | |
| 1214 | reg = <0x408 0xd0040000 0x0 0x20000>; | |
| 1215 | interrupt-parent = <&p1_mbigen_smmu_alg_b>; | |
| 1216 | interrupts = <733 1>, | |
| 1217 | <734 1>, | |
| 1218 | <735 1>; | |
| 1219 | interrupt-names = "eventq", "gerror", "priq"; | |
| 1220 | #iommu-cells = <1>; | |
| 1221 | dma-coherent; | |
| 1222 | hisilicon,broken-prefetch-cmd; | |
| 1223 | /* smmu-cb-memtype = <0x0 0x1>;*/ | |
| 1224 | }; | |
| 17f21343 | 1225 | |
| 4f357f94 KW |
1226 | soc { |
| 1227 | compatible = "simple-bus"; | |
| 1228 | #address-cells = <2>; | |
| 1229 | #size-cells = <2>; | |
| 1230 | ranges; | |
| 1231 | ||
| d2a1606c JG |
1232 | isa@a01b0000 { |
| 1233 | compatible = "hisilicon,hip07-lpc"; | |
| 1234 | #size-cells = <1>; | |
| 1235 | #address-cells = <2>; | |
| 1236 | reg = <0x0 0xa01b0000 0x0 0x1000>; | |
| 1237 | ||
| 1238 | ipmi0: bt@e4 { | |
| 1239 | compatible = "ipmi-bt"; | |
| 1240 | device_type = "ipmi"; | |
| 1241 | reg = <0x01 0xe4 0x04>; | |
| 1242 | status = "disabled"; | |
| 1243 | }; | |
| 1244 | }; | |
| 1245 | ||
| 4f357f94 KW |
1246 | uart0: uart@602b0000 { |
| 1247 | compatible = "arm,sbsa-uart"; | |
| 1248 | reg = <0x0 0x602b0000 0x0 0x1000>; | |
| 1249 | interrupt-parent = <&mbigen_uart>; | |
| 1250 | interrupts = <807 4>; | |
| 1251 | current-speed = <115200>; | |
| 1252 | reg-io-width = <4>; | |
| 1253 | status = "disabled"; | |
| 1254 | }; | |
| 1255 | ||
| 1256 | usb_ohci: ohci@a7030000 { | |
| 1257 | compatible = "generic-ohci"; | |
| 1258 | reg = <0x0 0xa7030000 0x0 0x10000>; | |
| 1259 | interrupt-parent = <&mbigen_usb>; | |
| 1260 | interrupts = <640 4>; | |
| 1261 | dma-coherent; | |
| 1262 | status = "disabled"; | |
| 1263 | }; | |
| 1264 | ||
| 1265 | usb_ehci: ehci@a7020000 { | |
| 1266 | compatible = "generic-ehci"; | |
| 1267 | reg = <0x0 0xa7020000 0x0 0x10000>; | |
| 1268 | interrupt-parent = <&mbigen_usb>; | |
| 1269 | interrupts = <641 4>; | |
| 1270 | dma-coherent; | |
| 1271 | status = "disabled"; | |
| 1272 | }; | |
| 38de5b56 WX |
1273 | |
| 1274 | peri_c_subctrl: sub_ctrl_c@60000000 { | |
| 1275 | compatible = "hisilicon,peri-subctrl","syscon"; | |
| 1276 | reg = <0 0x60000000 0x0 0x10000>; | |
| 1277 | }; | |
| 1278 | ||
| 1279 | dsa_subctrl: dsa_subctrl@c0000000 { | |
| 1280 | compatible = "hisilicon,dsa-subctrl", "syscon"; | |
| 1281 | reg = <0x0 0xc0000000 0x0 0x10000>; | |
| 1282 | }; | |
| 1283 | ||
| 45cc842d HT |
1284 | dsa_cpld: dsa_cpld@78000010 { |
| 1285 | compatible = "syscon"; | |
| 1286 | reg = <0x0 0x78000010 0x0 0x100>; | |
| 1287 | reg-io-width = <2>; | |
| 1288 | }; | |
| 1289 | ||
| 86d67897 WX |
1290 | pcie_subctl: pcie_subctl@a0000000 { |
| 1291 | compatible = "hisilicon,pcie-sas-subctrl", "syscon"; | |
| 1292 | reg = <0x0 0xa0000000 0x0 0x10000>; | |
| 1293 | }; | |
| 1294 | ||
| 38de5b56 WX |
1295 | serdes_ctrl: sds_ctrl@c2200000 { |
| 1296 | compatible = "syscon"; | |
| 1297 | reg = <0 0xc2200000 0x0 0x80000>; | |
| 1298 | }; | |
| 1299 | ||
| 1300 | mdio@603c0000 { | |
| 1301 | compatible = "hisilicon,hns-mdio"; | |
| 1302 | reg = <0x0 0x603c0000 0x0 0x1000>; | |
| 1303 | subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 | |
| 1304 | 0x531c 0x5a1c>; | |
| 1305 | #address-cells = <1>; | |
| 1306 | #size-cells = <0>; | |
| 1307 | ||
| 1308 | phy0: ethernet-phy@0 { | |
| 1309 | compatible = "ethernet-phy-ieee802.3-c22"; | |
| 1310 | reg = <0>; | |
| 1311 | }; | |
| 1312 | ||
| 1313 | phy1: ethernet-phy@1 { | |
| 1314 | compatible = "ethernet-phy-ieee802.3-c22"; | |
| 1315 | reg = <1>; | |
| 1316 | }; | |
| 1317 | }; | |
| 1318 | ||
| 1319 | dsaf0: dsa@c7000000 { | |
| 1320 | #address-cells = <1>; | |
| 1321 | #size-cells = <0>; | |
| 1322 | compatible = "hisilicon,hns-dsaf-v2"; | |
| 1323 | mode = "6port-16rss"; | |
| 1324 | reg = <0x0 0xc5000000 0x0 0x890000 | |
| 1325 | 0x0 0xc7000000 0x0 0x600000>; | |
| 1326 | reg-names = "ppe-base", "dsaf-base"; | |
| 1327 | interrupt-parent = <&mbigen_dsaf0>; | |
| 1328 | subctrl-syscon = <&dsa_subctrl>; | |
| 1329 | reset-field-offset = <0>; | |
| 1330 | interrupts = | |
| 1331 | <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, | |
| 1332 | <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, | |
| 1333 | <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, | |
| 1334 | <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, | |
| 1335 | <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, | |
| 1336 | <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, | |
| 1337 | <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, | |
| 1338 | <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, | |
| 1339 | <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, | |
| 1340 | <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, | |
| 1341 | <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, | |
| 1342 | <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, | |
| 1343 | <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, | |
| 1344 | <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, | |
| 1345 | <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, | |
| 1346 | <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, | |
| 1347 | <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, | |
| 1348 | <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, | |
| 1349 | <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, | |
| 1350 | <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, | |
| 1351 | <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, | |
| 1352 | <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, | |
| 1353 | <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, | |
| 1354 | <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, | |
| 1355 | <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, | |
| 1356 | <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, | |
| 1357 | <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, | |
| 1358 | <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, | |
| 1359 | <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, | |
| 1360 | <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, | |
| 1361 | <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, | |
| 1362 | <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, | |
| 1363 | <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, | |
| 1364 | <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, | |
| 1365 | <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, | |
| 1366 | <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, | |
| 1367 | <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, | |
| 1368 | <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, | |
| 1369 | <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, | |
| 1370 | <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, | |
| 1371 | <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, | |
| 1372 | <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, | |
| 1373 | <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, | |
| 1374 | <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, | |
| 1375 | <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, | |
| 1376 | <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, | |
| 1377 | <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, | |
| 1378 | <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, | |
| 1379 | <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, | |
| 1380 | <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, | |
| 1381 | <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, | |
| 1382 | <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, | |
| 1383 | <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, | |
| 1384 | <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, | |
| 1385 | <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, | |
| 1386 | <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, | |
| 1387 | <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, | |
| 1388 | <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, | |
| 1389 | <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, | |
| 1390 | <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, | |
| 1391 | <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, | |
| 1392 | <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, | |
| 1393 | <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, | |
| 1394 | <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, | |
| 1395 | <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, | |
| 1396 | <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, | |
| 1397 | <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, | |
| 1398 | <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, | |
| 1399 | <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, | |
| 1400 | <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, | |
| 1401 | <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, | |
| 1402 | <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, | |
| 1403 | <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, | |
| 1404 | <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, | |
| 1405 | <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, | |
| 1406 | <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, | |
| 1407 | <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, | |
| 1408 | <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, | |
| 1409 | <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, | |
| 1410 | <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, | |
| 1411 | <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, | |
| 1412 | <1340 1>, <1341 1>, <1342 1>, <1343 1>; | |
| 1413 | ||
| 1414 | desc-num = <0x400>; | |
| 1415 | buf-size = <0x1000>; | |
| 1416 | dma-coherent; | |
| 1417 | ||
| 1418 | port@0 { | |
| 1419 | reg = <0>; | |
| 1420 | serdes-syscon = <&serdes_ctrl>; | |
| 45cc842d | 1421 | cpld-syscon = <&dsa_cpld 0x0>; |
| 38de5b56 WX |
1422 | port-rst-offset = <0>; |
| 1423 | port-mode-offset = <0>; | |
| 1424 | mc-mac-mask = [ff f0 00 00 00 00]; | |
| 1425 | media-type = "fiber"; | |
| 1426 | }; | |
| 1427 | ||
| 1428 | port@1 { | |
| 1429 | reg = <1>; | |
| 1430 | serdes-syscon= <&serdes_ctrl>; | |
| 45cc842d | 1431 | cpld-syscon = <&dsa_cpld 0x4>; |
| 38de5b56 WX |
1432 | port-rst-offset = <1>; |
| 1433 | port-mode-offset = <1>; | |
| 1434 | mc-mac-mask = [ff f0 00 00 00 00]; | |
| 1435 | media-type = "fiber"; | |
| 1436 | }; | |
| 1437 | ||
| 1438 | port@4 { | |
| 1439 | reg = <4>; | |
| 1440 | phy-handle = <&phy0>; | |
| 1441 | serdes-syscon= <&serdes_ctrl>; | |
| 1442 | port-rst-offset = <4>; | |
| 1443 | port-mode-offset = <2>; | |
| 1444 | mc-mac-mask = [ff f0 00 00 00 00]; | |
| 1445 | media-type = "copper"; | |
| 1446 | }; | |
| 1447 | ||
| 1448 | port@5 { | |
| 1449 | reg = <5>; | |
| 1450 | phy-handle = <&phy1>; | |
| 1451 | serdes-syscon= <&serdes_ctrl>; | |
| 1452 | port-rst-offset = <5>; | |
| 1453 | port-mode-offset = <3>; | |
| 1454 | mc-mac-mask = [ff f0 00 00 00 00]; | |
| 1455 | media-type = "copper"; | |
| 1456 | }; | |
| 1457 | }; | |
| 1458 | ||
| 1459 | eth0: ethernet@4{ | |
| 1460 | compatible = "hisilicon,hns-nic-v2"; | |
| 1461 | ae-handle = <&dsaf0>; | |
| 1462 | port-idx-in-ae = <4>; | |
| 1463 | local-mac-address = [00 00 00 00 00 00]; | |
| 1464 | status = "disabled"; | |
| 1465 | dma-coherent; | |
| 1466 | }; | |
| 1467 | ||
| 1468 | eth1: ethernet@5{ | |
| 1469 | compatible = "hisilicon,hns-nic-v2"; | |
| 1470 | ae-handle = <&dsaf0>; | |
| 1471 | port-idx-in-ae = <5>; | |
| 1472 | local-mac-address = [00 00 00 00 00 00]; | |
| 1473 | status = "disabled"; | |
| 1474 | dma-coherent; | |
| 1475 | }; | |
| 1476 | ||
| 1477 | eth2: ethernet@0{ | |
| 1478 | compatible = "hisilicon,hns-nic-v2"; | |
| 1479 | ae-handle = <&dsaf0>; | |
| 1480 | port-idx-in-ae = <0>; | |
| 1481 | local-mac-address = [00 00 00 00 00 00]; | |
| 1482 | status = "disabled"; | |
| 1483 | dma-coherent; | |
| 1484 | }; | |
| 1485 | ||
| 1486 | eth3: ethernet@1{ | |
| 1487 | compatible = "hisilicon,hns-nic-v2"; | |
| 1488 | ae-handle = <&dsaf0>; | |
| 1489 | port-idx-in-ae = <1>; | |
| 1490 | local-mac-address = [00 00 00 00 00 00]; | |
| 1491 | status = "disabled"; | |
| 1492 | dma-coherent; | |
| 1493 | }; | |
| 0f57c6c9 WX |
1494 | |
| 1495 | infiniband@c4000000 { | |
| 1496 | compatible = "hisilicon,hns-roce-v1"; | |
| 1497 | reg = <0x0 0xc4000000 0x0 0x100000>; | |
| 1498 | dma-coherent; | |
| 1499 | eth-handle = <ð2 ð3 0 0 ð0 ð1>; | |
| 1500 | dsaf-handle = <&dsaf0>; | |
| 1501 | node-guid = [00 9A CD 00 00 01 02 03]; | |
| 1502 | #address-cells = <2>; | |
| 1503 | #size-cells = <2>; | |
| 1504 | interrupt-parent = <&mbigen_dsa_roce>; | |
| 1505 | interrupts = <722 1>, | |
| 1506 | <723 1>, | |
| 1507 | <724 1>, | |
| 1508 | <725 1>, | |
| 1509 | <726 1>, | |
| 1510 | <727 1>, | |
| 1511 | <728 1>, | |
| 1512 | <729 1>, | |
| 1513 | <730 1>, | |
| 1514 | <731 1>, | |
| 1515 | <732 1>, | |
| 1516 | <733 1>, | |
| 1517 | <734 1>, | |
| 1518 | <735 1>, | |
| 1519 | <736 1>, | |
| 1520 | <737 1>, | |
| 1521 | <738 1>, | |
| 1522 | <739 1>, | |
| 1523 | <740 1>, | |
| 1524 | <741 1>, | |
| 1525 | <742 1>, | |
| 1526 | <743 1>, | |
| 1527 | <744 1>, | |
| 1528 | <745 1>, | |
| 1529 | <746 1>, | |
| 1530 | <747 1>, | |
| 1531 | <748 1>, | |
| 1532 | <749 1>, | |
| 1533 | <750 1>, | |
| 1534 | <751 1>, | |
| 1535 | <752 1>, | |
| 1536 | <753 1>, | |
| 1537 | <785 1>, | |
| 1538 | <754 4>; | |
| 1539 | ||
| 1540 | interrupt-names = "hns-roce-comp-0", | |
| 1541 | "hns-roce-comp-1", | |
| 1542 | "hns-roce-comp-2", | |
| 1543 | "hns-roce-comp-3", | |
| 1544 | "hns-roce-comp-4", | |
| 1545 | "hns-roce-comp-5", | |
| 1546 | "hns-roce-comp-6", | |
| 1547 | "hns-roce-comp-7", | |
| 1548 | "hns-roce-comp-8", | |
| 1549 | "hns-roce-comp-9", | |
| 1550 | "hns-roce-comp-10", | |
| 1551 | "hns-roce-comp-11", | |
| 1552 | "hns-roce-comp-12", | |
| 1553 | "hns-roce-comp-13", | |
| 1554 | "hns-roce-comp-14", | |
| 1555 | "hns-roce-comp-15", | |
| 1556 | "hns-roce-comp-16", | |
| 1557 | "hns-roce-comp-17", | |
| 1558 | "hns-roce-comp-18", | |
| 1559 | "hns-roce-comp-19", | |
| 1560 | "hns-roce-comp-20", | |
| 1561 | "hns-roce-comp-21", | |
| 1562 | "hns-roce-comp-22", | |
| 1563 | "hns-roce-comp-23", | |
| 1564 | "hns-roce-comp-24", | |
| 1565 | "hns-roce-comp-25", | |
| 1566 | "hns-roce-comp-26", | |
| 1567 | "hns-roce-comp-27", | |
| 1568 | "hns-roce-comp-28", | |
| 1569 | "hns-roce-comp-29", | |
| 1570 | "hns-roce-comp-30", | |
| 1571 | "hns-roce-comp-31", | |
| 1572 | "hns-roce-async", | |
| 1573 | "hns-roce-common"; | |
| 1574 | }; | |
| 86d67897 WX |
1575 | |
| 1576 | sas0: sas@c3000000 { | |
| 1577 | compatible = "hisilicon,hip07-sas-v2"; | |
| 1578 | reg = <0 0xc3000000 0 0x10000>; | |
| 1579 | sas-addr = [50 01 88 20 16 00 00 00]; | |
| 1580 | hisilicon,sas-syscon = <&dsa_subctrl>; | |
| 1581 | ctrl-reset-reg = <0xa60>; | |
| 1582 | ctrl-reset-sts-reg = <0x5a30>; | |
| 1583 | ctrl-clock-ena-reg = <0x338>; | |
| 1584 | queue-count = <16>; | |
| 1585 | phy-count = <8>; | |
| 1586 | dma-coherent; | |
| 1587 | interrupt-parent = <&mbigen_sas0>; | |
| 1588 | interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, | |
| 1589 | <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, | |
| 1590 | <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, | |
| 1591 | <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, | |
| 1592 | <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, | |
| 1593 | <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, | |
| 1594 | <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, | |
| 1595 | <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, | |
| 1596 | <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, | |
| 1597 | <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, | |
| 1598 | <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, | |
| 1599 | <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, | |
| 1600 | <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, | |
| 1601 | <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, | |
| 1602 | <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, | |
| 1603 | <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, | |
| 1604 | <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, | |
| 1605 | <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, | |
| 1606 | <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, | |
| 1607 | <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, | |
| 1608 | <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, | |
| 1609 | <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, | |
| 1610 | <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, | |
| 1611 | <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, | |
| 1612 | <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, | |
| 1613 | <630 1>,<631 1>,<632 1>; | |
| 1614 | status = "disabled"; | |
| 1615 | }; | |
| 1616 | ||
| 1617 | sas1: sas@a2000000 { | |
| 1618 | compatible = "hisilicon,hip07-sas-v2"; | |
| 1619 | reg = <0 0xa2000000 0 0x10000>; | |
| 1620 | sas-addr = [50 01 88 20 16 00 00 00]; | |
| 1621 | hisilicon,sas-syscon = <&pcie_subctl>; | |
| 1622 | hip06-sas-v2-quirk-amt; | |
| 1623 | ctrl-reset-reg = <0xa18>; | |
| 1624 | ctrl-reset-sts-reg = <0x5a0c>; | |
| 1625 | ctrl-clock-ena-reg = <0x318>; | |
| 1626 | queue-count = <16>; | |
| 1627 | phy-count = <8>; | |
| 1628 | dma-coherent; | |
| 1629 | interrupt-parent = <&mbigen_sas1>; | |
| 1630 | interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, | |
| 1631 | <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, | |
| 1632 | <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, | |
| 1633 | <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, | |
| 1634 | <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, | |
| 1635 | <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, | |
| 1636 | <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, | |
| 1637 | <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, | |
| 1638 | <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, | |
| 1639 | <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, | |
| 1640 | <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, | |
| 1641 | <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, | |
| 1642 | <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, | |
| 1643 | <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, | |
| 1644 | <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, | |
| 1645 | <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, | |
| 1646 | <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, | |
| 1647 | <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, | |
| 1648 | <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, | |
| 1649 | <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, | |
| 1650 | <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, | |
| 1651 | <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, | |
| 1652 | <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, | |
| 1653 | <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, | |
| 1654 | <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, | |
| 1655 | <605 1>,<606 1>,<607 1>; | |
| 1656 | status = "disabled"; | |
| 1657 | }; | |
| 1658 | ||
| 1659 | sas2: sas@a3000000 { | |
| 1660 | compatible = "hisilicon,hip07-sas-v2"; | |
| 1661 | reg = <0 0xa3000000 0 0x10000>; | |
| 1662 | sas-addr = [50 01 88 20 16 00 00 00]; | |
| 1663 | hisilicon,sas-syscon = <&pcie_subctl>; | |
| 1664 | ctrl-reset-reg = <0xae0>; | |
| 1665 | ctrl-reset-sts-reg = <0x5a70>; | |
| 1666 | ctrl-clock-ena-reg = <0x3a8>; | |
| 1667 | queue-count = <16>; | |
| 1668 | phy-count = <9>; | |
| 1669 | dma-coherent; | |
| 1670 | interrupt-parent = <&mbigen_sas2>; | |
| 1671 | interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, | |
| 1672 | <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, | |
| 1673 | <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, | |
| 1674 | <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, | |
| 1675 | <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, | |
| 1676 | <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, | |
| 1677 | <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, | |
| 1678 | <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, | |
| 1679 | <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, | |
| 1680 | <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, | |
| 1681 | <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, | |
| 1682 | <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, | |
| 1683 | <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, | |
| 1684 | <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, | |
| 1685 | <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, | |
| 1686 | <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, | |
| 1687 | <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, | |
| 1688 | <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, | |
| 1689 | <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, | |
| 1690 | <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, | |
| 1691 | <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, | |
| 1692 | <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, | |
| 1693 | <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, | |
| 1694 | <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, | |
| 1695 | <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, | |
| 1696 | <637 1>,<638 1>,<639 1>; | |
| 1697 | status = "disabled"; | |
| 1698 | }; | |
| 9f5ce88d ZW |
1699 | |
| 1700 | p0_pcie2_a: pcie@a00a0000 { | |
| 1701 | compatible = "hisilicon,hip07-pcie-ecam"; | |
| 1702 | reg = <0 0xaf800000 0 0x800000>, | |
| 1703 | <0 0xa00a0000 0 0x10000>; | |
| 1704 | bus-range = <0xf8 0xff>; | |
| 1705 | msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; | |
| 1706 | msi-map-mask = <0xffff>; | |
| 1707 | #address-cells = <3>; | |
| 1708 | #size-cells = <2>; | |
| 1709 | device_type = "pci"; | |
| 1710 | dma-coherent; | |
| 1711 | ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000 | |
| 1712 | 0x01000000 0 0 0 0xaf7f0000 0 0x10000>; | |
| 1713 | #interrupt-cells = <1>; | |
| 1714 | interrupt-map-mask = <0xf800 0 0 7>; | |
| 1715 | interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 | |
| 1716 | 0x0 0 0 2 &mbigen_pcie2_a 671 4 | |
| 1717 | 0x0 0 0 3 &mbigen_pcie2_a 671 4 | |
| 1718 | 0x0 0 0 4 &mbigen_pcie2_a 671 4>; | |
| 1719 | status = "disabled"; | |
| 1720 | }; | |
| e4a1f785 JC |
1721 | p0_sec_a: crypto@d2000000 { |
| 1722 | compatible = "hisilicon,hip07-sec"; | |
| 1723 | reg = <0x0 0xd0000000 0x0 0x10000 | |
| 1724 | 0x0 0xd2000000 0x0 0x10000 | |
| 1725 | 0x0 0xd2010000 0x0 0x10000 | |
| 1726 | 0x0 0xd2020000 0x0 0x10000 | |
| 1727 | 0x0 0xd2030000 0x0 0x10000 | |
| 1728 | 0x0 0xd2040000 0x0 0x10000 | |
| 1729 | 0x0 0xd2050000 0x0 0x10000 | |
| 1730 | 0x0 0xd2060000 0x0 0x10000 | |
| 1731 | 0x0 0xd2070000 0x0 0x10000 | |
| 1732 | 0x0 0xd2080000 0x0 0x10000 | |
| 1733 | 0x0 0xd2090000 0x0 0x10000 | |
| 1734 | 0x0 0xd20a0000 0x0 0x10000 | |
| 1735 | 0x0 0xd20b0000 0x0 0x10000 | |
| 1736 | 0x0 0xd20c0000 0x0 0x10000 | |
| 1737 | 0x0 0xd20d0000 0x0 0x10000 | |
| 1738 | 0x0 0xd20e0000 0x0 0x10000 | |
| 1739 | 0x0 0xd20f0000 0x0 0x10000 | |
| 1740 | 0x0 0xd2100000 0x0 0x10000>; | |
| 1741 | interrupt-parent = <&p0_mbigen_sec_a>; | |
| 1742 | iommus = <&p0_smmu_alg_a 0x600>; | |
| 1743 | dma-coherent; | |
| 1744 | interrupts = <576 4>, | |
| 1745 | <577 1>, <578 4>, | |
| 1746 | <579 1>, <580 4>, | |
| 1747 | <581 1>, <582 4>, | |
| 1748 | <583 1>, <584 4>, | |
| 1749 | <585 1>, <586 4>, | |
| 1750 | <587 1>, <588 4>, | |
| 1751 | <589 1>, <590 4>, | |
| 1752 | <591 1>, <592 4>, | |
| 1753 | <593 1>, <594 4>, | |
| 1754 | <595 1>, <596 4>, | |
| 1755 | <597 1>, <598 4>, | |
| 1756 | <599 1>, <600 4>, | |
| 1757 | <601 1>, <602 4>, | |
| 1758 | <603 1>, <604 4>, | |
| 1759 | <605 1>, <606 4>, | |
| 1760 | <607 1>, <608 4>; | |
| 1761 | }; | |
| 1762 | p0_sec_b: crypto@8,d2000000 { | |
| 1763 | compatible = "hisilicon,hip07-sec"; | |
| 1764 | reg = <0x8 0xd0000000 0x0 0x10000 | |
| 1765 | 0x8 0xd2000000 0x0 0x10000 | |
| 1766 | 0x8 0xd2010000 0x0 0x10000 | |
| 1767 | 0x8 0xd2020000 0x0 0x10000 | |
| 1768 | 0x8 0xd2030000 0x0 0x10000 | |
| 1769 | 0x8 0xd2040000 0x0 0x10000 | |
| 1770 | 0x8 0xd2050000 0x0 0x10000 | |
| 1771 | 0x8 0xd2060000 0x0 0x10000 | |
| 1772 | 0x8 0xd2070000 0x0 0x10000 | |
| 1773 | 0x8 0xd2080000 0x0 0x10000 | |
| 1774 | 0x8 0xd2090000 0x0 0x10000 | |
| 1775 | 0x8 0xd20a0000 0x0 0x10000 | |
| 1776 | 0x8 0xd20b0000 0x0 0x10000 | |
| 1777 | 0x8 0xd20c0000 0x0 0x10000 | |
| 1778 | 0x8 0xd20d0000 0x0 0x10000 | |
| 1779 | 0x8 0xd20e0000 0x0 0x10000 | |
| 1780 | 0x8 0xd20f0000 0x0 0x10000 | |
| 1781 | 0x8 0xd2100000 0x0 0x10000>; | |
| 1782 | interrupt-parent = <&p0_mbigen_sec_b>; | |
| 1783 | iommus = <&p0_smmu_alg_b 0x600>; | |
| 1784 | dma-coherent; | |
| 1785 | interrupts = <576 4>, | |
| 1786 | <577 1>, <578 4>, | |
| 1787 | <579 1>, <580 4>, | |
| 1788 | <581 1>, <582 4>, | |
| 1789 | <583 1>, <584 4>, | |
| 1790 | <585 1>, <586 4>, | |
| 1791 | <587 1>, <588 4>, | |
| 1792 | <589 1>, <590 4>, | |
| 1793 | <591 1>, <592 4>, | |
| 1794 | <593 1>, <594 4>, | |
| 1795 | <595 1>, <596 4>, | |
| 1796 | <597 1>, <598 4>, | |
| 1797 | <599 1>, <600 4>, | |
| 1798 | <601 1>, <602 4>, | |
| 1799 | <603 1>, <604 4>, | |
| 1800 | <605 1>, <606 4>, | |
| 1801 | <607 1>, <608 4>; | |
| 1802 | }; | |
| 1803 | p1_sec_a: crypto@400,d2000000 { | |
| 1804 | compatible = "hisilicon,hip07-sec"; | |
| 1805 | reg = <0x400 0xd0000000 0x0 0x10000 | |
| 1806 | 0x400 0xd2000000 0x0 0x10000 | |
| 1807 | 0x400 0xd2010000 0x0 0x10000 | |
| 1808 | 0x400 0xd2020000 0x0 0x10000 | |
| 1809 | 0x400 0xd2030000 0x0 0x10000 | |
| 1810 | 0x400 0xd2040000 0x0 0x10000 | |
| 1811 | 0x400 0xd2050000 0x0 0x10000 | |
| 1812 | 0x400 0xd2060000 0x0 0x10000 | |
| 1813 | 0x400 0xd2070000 0x0 0x10000 | |
| 1814 | 0x400 0xd2080000 0x0 0x10000 | |
| 1815 | 0x400 0xd2090000 0x0 0x10000 | |
| 1816 | 0x400 0xd20a0000 0x0 0x10000 | |
| 1817 | 0x400 0xd20b0000 0x0 0x10000 | |
| 1818 | 0x400 0xd20c0000 0x0 0x10000 | |
| 1819 | 0x400 0xd20d0000 0x0 0x10000 | |
| 1820 | 0x400 0xd20e0000 0x0 0x10000 | |
| 1821 | 0x400 0xd20f0000 0x0 0x10000 | |
| 1822 | 0x400 0xd2100000 0x0 0x10000>; | |
| 1823 | interrupt-parent = <&p1_mbigen_sec_a>; | |
| 1824 | iommus = <&p1_smmu_alg_a 0x600>; | |
| 1825 | dma-coherent; | |
| 1826 | interrupts = <576 4>, | |
| 1827 | <577 1>, <578 4>, | |
| 1828 | <579 1>, <580 4>, | |
| 1829 | <581 1>, <582 4>, | |
| 1830 | <583 1>, <584 4>, | |
| 1831 | <585 1>, <586 4>, | |
| 1832 | <587 1>, <588 4>, | |
| 1833 | <589 1>, <590 4>, | |
| 1834 | <591 1>, <592 4>, | |
| 1835 | <593 1>, <594 4>, | |
| 1836 | <595 1>, <596 4>, | |
| 1837 | <597 1>, <598 4>, | |
| 1838 | <599 1>, <600 4>, | |
| 1839 | <601 1>, <602 4>, | |
| 1840 | <603 1>, <604 4>, | |
| 1841 | <605 1>, <606 4>, | |
| 1842 | <607 1>, <608 4>; | |
| 1843 | }; | |
| 1844 | p1_sec_b: crypto@408,d2000000 { | |
| 1845 | compatible = "hisilicon,hip07-sec"; | |
| 1846 | reg = <0x408 0xd0000000 0x0 0x10000 | |
| 1847 | 0x408 0xd2000000 0x0 0x10000 | |
| 1848 | 0x408 0xd2010000 0x0 0x10000 | |
| 1849 | 0x408 0xd2020000 0x0 0x10000 | |
| 1850 | 0x408 0xd2030000 0x0 0x10000 | |
| 1851 | 0x408 0xd2040000 0x0 0x10000 | |
| 1852 | 0x408 0xd2050000 0x0 0x10000 | |
| 1853 | 0x408 0xd2060000 0x0 0x10000 | |
| 1854 | 0x408 0xd2070000 0x0 0x10000 | |
| 1855 | 0x408 0xd2080000 0x0 0x10000 | |
| 1856 | 0x408 0xd2090000 0x0 0x10000 | |
| 1857 | 0x408 0xd20a0000 0x0 0x10000 | |
| 1858 | 0x408 0xd20b0000 0x0 0x10000 | |
| 1859 | 0x408 0xd20c0000 0x0 0x10000 | |
| 1860 | 0x408 0xd20d0000 0x0 0x10000 | |
| 1861 | 0x408 0xd20e0000 0x0 0x10000 | |
| 1862 | 0x408 0xd20f0000 0x0 0x10000 | |
| 1863 | 0x408 0xd2100000 0x0 0x10000>; | |
| 1864 | interrupt-parent = <&p1_mbigen_sec_b>; | |
| 1865 | iommus = <&p1_smmu_alg_b 0x600>; | |
| 1866 | dma-coherent; | |
| 1867 | interrupts = <576 4>, | |
| 1868 | <577 1>, <578 4>, | |
| 1869 | <579 1>, <580 4>, | |
| 1870 | <581 1>, <582 4>, | |
| 1871 | <583 1>, <584 4>, | |
| 1872 | <585 1>, <586 4>, | |
| 1873 | <587 1>, <588 4>, | |
| 1874 | <589 1>, <590 4>, | |
| 1875 | <591 1>, <592 4>, | |
| 1876 | <593 1>, <594 4>, | |
| 1877 | <595 1>, <596 4>, | |
| 1878 | <597 1>, <598 4>, | |
| 1879 | <599 1>, <600 4>, | |
| 1880 | <601 1>, <602 4>, | |
| 1881 | <603 1>, <604 4>, | |
| 1882 | <605 1>, <606 4>, | |
| 1883 | <607 1>, <608 4>; | |
| 1884 | }; | |
| 1885 | ||
| 4f357f94 KW |
1886 | }; |
| 1887 | }; |