[linux-2.6-block.git] / arch / arm64 / boot / dts / hisilicon / hip05.dtsi

/**
 * dts file for Hisilicon D02 Development Board
 *
 * Copyright (C) 2014,2015 Hisilicon Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "hisilicon,hip05-d02";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&cpu8>;
				};
				core1 {
					cpu = <&cpu9>;
				};
				core2 {
					cpu = <&cpu10>;
				};
				core3 {
					cpu = <&cpu11>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&cpu12>;
				};
				core1 {
					cpu = <&cpu13>;
				};
				core2 {
					cpu = <&cpu14>;
				};
				core3 {
					cpu = <&cpu15>;
				};
			};
		};

		cpu0: cpu@20000 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20000>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu1: cpu@20001 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20001>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu2: cpu@20002 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20002>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu3: cpu@20003 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20003>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu4: cpu@20100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20100>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu5: cpu@20101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20101>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu6: cpu@20102 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20102>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu7: cpu@20103 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20103>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu8: cpu@20200 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20200>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu9: cpu@20201 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20201>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu10: cpu@20202 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20202>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu11: cpu@20203 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20203>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu12: cpu@20300 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20300>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu13: cpu@20301 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20301>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu14: cpu@20302 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20302>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu15: cpu@20303 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x20303>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
		};

		cluster1_l2: l2-cache1 {
			compatible = "cache";
		};

		cluster2_l2: l2-cache2 {
			compatible = "cache";
		};

		cluster3_l2: l2-cache3 {
			compatible = "cache";
		};
	};

	gic: interrupt-controller@8d000000 {
		compatible = "arm,gic-v3";
                #interrupt-cells = <3>;
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
                interrupt-controller;
                #redistributor-regions = <1>;
                redistributor-stride = <0x0 0x30000>;
		reg = <0x0 0x8d000000 0 0x10000>,	/* GICD */
		      <0x0 0x8d100000 0 0x300000>,	/* GICR */
		      <0x0 0xfe000000 0 0x10000>,	/* GICC */
		      <0x0 0xfe010000 0 0x10000>,       /* GICH */
		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		its_peri: interrupt-controller@8c000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0x8c000000 0x0 0x40000>;
		};

		its_m3: interrupt-controller@a3000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xa3000000 0x0 0x40000>;
		};

		its_pcie: interrupt-controller@b7000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xb7000000 0x0 0x40000>;
		};

		its_dsa: interrupt-controller@c6000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xc6000000 0x0 0x40000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		refclk200mhz: refclk200mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};

		uart0: uart@80300000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x80300000 0x0 0x10000>;
			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&refclk200mhz>;
			clock-names = "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart1: uart@80310000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x80310000 0x0 0x10000>;
			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&refclk200mhz>;
			clock-names = "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		lbc: localbus@80380000 {
			compatible = "hisilicon,hisi-localbus", "simple-bus";
			reg = <0x0 0x80380000 0x0 0x10000>;
			status = "disabled";
		};

		peri_gpio0: gpio@802e0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x802e0000 0x0 0x10000>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		peri_gpio1: gpio@802f0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x802f0000 0x0 0x10000>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
fcab303c DT	1	/**
	2	* dts file for Hisilicon D02 Development Board
	3	*
	4	* Copyright (C) 2014,2015 Hisilicon Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* publishhed by the Free Software Foundation.
	9	*
	10	*/
	11
	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
	13
	14	/ {
	15	compatible = "hisilicon,hip05-d02";
	16	interrupt-parent = <&gic>;
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19
	20	psci {
	21	compatible = "arm,psci-0.2";
	22	method = "smc";
	23	};
	24
	25	cpus {
	26	#address-cells = <1>;
	27	#size-cells = <0>;
	28
	29	cpu-map {
	30	cluster0 {
	31	core0 {
	32	cpu = <&cpu0>;
	33	};
	34	core1 {
	35	cpu = <&cpu1>;
	36	};
	37	core2 {
	38	cpu = <&cpu2>;
	39	};
	40	core3 {
	41	cpu = <&cpu3>;
	42	};
	43	};
	44	cluster1 {
	45	core0 {
	46	cpu = <&cpu4>;
	47	};
	48	core1 {
	49	cpu = <&cpu5>;
	50	};
	51	core2 {
	52	cpu = <&cpu6>;
	53	};
	54	core3 {
	55	cpu = <&cpu7>;
	56	};
	57	};
	58	cluster2 {
	59	core0 {
	60	cpu = <&cpu8>;
	61	};
	62	core1 {
	63	cpu = <&cpu9>;
	64	};
65	core2 {
66	cpu = <&cpu10>;
67	};
68	core3 {
69	cpu = <&cpu11>;
70	};
71	};
72	cluster3 {
73	core0 {
74	cpu = <&cpu12>;
75	};
76	core1 {
77	cpu = <&cpu13>;
78	};
79	core2 {
80	cpu = <&cpu14>;
81	};
82	core3 {
83	cpu = <&cpu15>;
84	};
85	};
86	};
87
88	cpu0: cpu@20000 {
89	device_type = "cpu";
90	compatible = "arm,cortex-a57", "arm,armv8";
91	reg = <0x20000>;
92	enable-method = "psci";
dbb58d0f	93	next-level-cache = <&cluster0_l2>;
fcab303c DT	94	};
	95
	96	cpu1: cpu@20001 {
	97	device_type = "cpu";
	98	compatible = "arm,cortex-a57", "arm,armv8";
	99	reg = <0x20001>;
	100	enable-method = "psci";
dbb58d0f	101	next-level-cache = <&cluster0_l2>;
fcab303c DT	102	};
	103
	104	cpu2: cpu@20002 {
	105	device_type = "cpu";
	106	compatible = "arm,cortex-a57", "arm,armv8";
	107	reg = <0x20002>;
	108	enable-method = "psci";
dbb58d0f	109	next-level-cache = <&cluster0_l2>;
fcab303c DT	110	};
	111
	112	cpu3: cpu@20003 {
	113	device_type = "cpu";
	114	compatible = "arm,cortex-a57", "arm,armv8";
	115	reg = <0x20003>;
	116	enable-method = "psci";
dbb58d0f	117	next-level-cache = <&cluster0_l2>;
fcab303c DT	118	};
	119
	120	cpu4: cpu@20100 {
	121	device_type = "cpu";
	122	compatible = "arm,cortex-a57", "arm,armv8";
	123	reg = <0x20100>;
	124	enable-method = "psci";
dbb58d0f	125	next-level-cache = <&cluster1_l2>;
fcab303c DT	126	};
	127
	128	cpu5: cpu@20101 {
	129	device_type = "cpu";
	130	compatible = "arm,cortex-a57", "arm,armv8";
	131	reg = <0x20101>;
	132	enable-method = "psci";
dbb58d0f	133	next-level-cache = <&cluster1_l2>;
fcab303c DT	134	};
	135
	136	cpu6: cpu@20102 {
	137	device_type = "cpu";
	138	compatible = "arm,cortex-a57", "arm,armv8";
	139	reg = <0x20102>;
	140	enable-method = "psci";
dbb58d0f	141	next-level-cache = <&cluster1_l2>;
fcab303c DT	142	};
	143
	144	cpu7: cpu@20103 {
	145	device_type = "cpu";
	146	compatible = "arm,cortex-a57", "arm,armv8";
	147	reg = <0x20103>;
	148	enable-method = "psci";
dbb58d0f	149	next-level-cache = <&cluster1_l2>;
fcab303c DT	150	};
	151
	152	cpu8: cpu@20200 {
	153	device_type = "cpu";
	154	compatible = "arm,cortex-a57", "arm,armv8";
	155	reg = <0x20200>;
	156	enable-method = "psci";
dbb58d0f	157	next-level-cache = <&cluster2_l2>;
fcab303c DT	158	};
	159
	160	cpu9: cpu@20201 {
	161	device_type = "cpu";
	162	compatible = "arm,cortex-a57", "arm,armv8";
	163	reg = <0x20201>;
	164	enable-method = "psci";
dbb58d0f	165	next-level-cache = <&cluster2_l2>;
fcab303c DT	166	};
	167
	168	cpu10: cpu@20202 {
	169	device_type = "cpu";
	170	compatible = "arm,cortex-a57", "arm,armv8";
	171	reg = <0x20202>;
	172	enable-method = "psci";
dbb58d0f	173	next-level-cache = <&cluster2_l2>;
fcab303c DT	174	};
	175
	176	cpu11: cpu@20203 {
	177	device_type = "cpu";
	178	compatible = "arm,cortex-a57", "arm,armv8";
	179	reg = <0x20203>;
	180	enable-method = "psci";
dbb58d0f	181	next-level-cache = <&cluster2_l2>;
fcab303c DT	182	};
	183
	184	cpu12: cpu@20300 {
	185	device_type = "cpu";
	186	compatible = "arm,cortex-a57", "arm,armv8";
	187	reg = <0x20300>;
	188	enable-method = "psci";
dbb58d0f	189	next-level-cache = <&cluster3_l2>;
fcab303c DT	190	};
	191
	192	cpu13: cpu@20301 {
	193	device_type = "cpu";
	194	compatible = "arm,cortex-a57", "arm,armv8";
	195	reg = <0x20301>;
	196	enable-method = "psci";
dbb58d0f	197	next-level-cache = <&cluster3_l2>;
fcab303c DT	198	};
	199
	200	cpu14: cpu@20302 {
	201	device_type = "cpu";
	202	compatible = "arm,cortex-a57", "arm,armv8";
	203	reg = <0x20302>;
	204	enable-method = "psci";
dbb58d0f	205	next-level-cache = <&cluster3_l2>;
fcab303c DT	206	};
	207
	208	cpu15: cpu@20303 {
	209	device_type = "cpu";
	210	compatible = "arm,cortex-a57", "arm,armv8";
	211	reg = <0x20303>;
	212	enable-method = "psci";
dbb58d0f KW	213	next-level-cache = <&cluster3_l2>;
	214	};
	215
	216	cluster0_l2: l2-cache0 {
	217	compatible = "cache";
	218	};
	219
	220	cluster1_l2: l2-cache1 {
	221	compatible = "cache";
	222	};
	223
	224	cluster2_l2: l2-cache2 {
	225	compatible = "cache";
	226	};
	227
	228	cluster3_l2: l2-cache3 {
	229	compatible = "cache";
fcab303c DT	230	};
	231	};
	232
	233	gic: interrupt-controller@8d000000 {
	234	compatible = "arm,gic-v3";
	235	#interrupt-cells = <3>;
	236	#address-cells = <2>;
	237	#size-cells = <2>;
	238	ranges;
	239	interrupt-controller;
	240	#redistributor-regions = <1>;
	241	redistributor-stride = <0x0 0x30000>;
	242	reg = <0x0 0x8d000000 0 0x10000>, /* GICD */
	243	<0x0 0x8d100000 0 0x300000>, /* GICR */
	244	<0x0 0xfe000000 0 0x10000>, /* GICC */
	245	<0x0 0xfe010000 0 0x10000>, /* GICH */
	246	<0x0 0xfe020000 0 0x10000>; /* GICV */
	247	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	248
abf9c25d	249	its_peri: interrupt-controller@8c000000 {
fcab303c DT	250	compatible = "arm,gic-v3-its";
fcab303c DT	251	msi-controller;
70896650	252	#msi-cells = <1>;
fcab303c DT	253	reg = <0x0 0x8c000000 0x0 0x40000>;
fcab303c DT	254	};
abf9c25d KW	255
	256	its_m3: interrupt-controller@a3000000 {
	257	compatible = "arm,gic-v3-its";
	258	msi-controller;
70896650	259	#msi-cells = <1>;
abf9c25d KW	260	reg = <0x0 0xa3000000 0x0 0x40000>;
	261	};
	262
	263	its_pcie: interrupt-controller@b7000000 {
	264	compatible = "arm,gic-v3-its";
	265	msi-controller;
70896650	266	#msi-cells = <1>;
abf9c25d KW	267	reg = <0x0 0xb7000000 0x0 0x40000>;
	268	};
	269
	270	its_dsa: interrupt-controller@c6000000 {
	271	compatible = "arm,gic-v3-its";
	272	msi-controller;
70896650	273	#msi-cells = <1>;
abf9c25d KW	274	reg = <0x0 0xc6000000 0x0 0x40000>;
abf9c25d KW	275	};
fcab303c DT	276	};
	277
	278	timer {
	279	compatible = "arm,armv8-timer";
	280	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	281	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	282	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	283	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	284	};
	285
	286	pmu {
6897db62	287	compatible = "arm,cortex-a57-pmu";
fcab303c DT	288	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	289	};
	290
	291	soc {
	292	compatible = "simple-bus";
	293	#address-cells = <2>;
	294	#size-cells = <2>;
	295	ranges;
	296
	297	refclk200mhz: refclk200mhz {
	298	compatible = "fixed-clock";
	299	#clock-cells = <0>;
	300	clock-frequency = <200000000>;
	301	};
	302
	303	uart0: uart@80300000 {
	304	compatible = "snps,dw-apb-uart";
	305	reg = <0x0 0x80300000 0x0 0x10000>;
	306	interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
	307	clocks = <&refclk200mhz>;
	308	clock-names = "apb_pclk";
	309	reg-shift = <2>;
	310	reg-io-width = <4>;
	311	status = "disabled";
	312	};
	313
	314	uart1: uart@80310000 {
	315	compatible = "snps,dw-apb-uart";
	316	reg = <0x0 0x80310000 0x0 0x10000>;
	317	interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	318	clocks = <&refclk200mhz>;
	319	clock-names = "apb_pclk";
	320	reg-shift = <2>;
	321	reg-io-width = <4>;
	322	status = "disabled";
	323	};
8f41d122	324
162d23bf KW	325	lbc: localbus@80380000 {
	326	compatible = "hisilicon,hisi-localbus", "simple-bus";
	327	reg = <0x0 0x80380000 0x0 0x10000>;
	328	status = "disabled";
	329	};
	330
8f41d122 KW	331	peri_gpio0: gpio@802e0000 {
	332	#address-cells = <1>;
	333	#size-cells = <0>;
	334	compatible = "snps,dw-apb-gpio";
	335	reg = <0x0 0x802e0000 0x0 0x10000>;
	336	status = "disabled";
	337
	338	porta: gpio-controller@0 {
	339	compatible = "snps,dw-apb-gpio-port";
	340	gpio-controller;
	341	#gpio-cells = <2>;
	342	snps,nr-gpios = <32>;
	343	reg = <0>;
	344	interrupt-controller;
	345	#interrupt-cells = <2>;
	346	interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
	347	};
	348	};
	349
	350	peri_gpio1: gpio@802f0000 {
	351	#address-cells = <1>;
	352	#size-cells = <0>;
	353	compatible = "snps,dw-apb-gpio";
	354	reg = <0x0 0x802f0000 0x0 0x10000>;
	355	status = "disabled";
	356
	357	portb: gpio-controller@0 {
	358	compatible = "snps,dw-apb-gpio-port";
	359	gpio-controller;
	360	#gpio-cells = <2>;
	361	snps,nr-gpios = <32>;
	362	reg = <0>;
	363	interrupt-controller;
	364	#interrupt-cells = <2>;
	365	interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
	366	};
	367	};
fcab303c DT	368	};
fcab303c DT	369	};