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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-2.6-block.git] / arch / arm64 / boot / dts / hisilicon / hi6220.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
86e8f528
BW		 2/*
3 * dts file for Hisilicon Hi6220 SoC
4 *
5 * Copyright (C) 2015, Hisilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
339d00cb 9#include <dt-bindings/reset/hisi,hi6220-resets.h>
a362ec8f 10#include <dt-bindings/clock/hi6220-clock.h>
379e9bf5 11#include <dt-bindings/pinctrl/hisi.h>
cd0b69ec 12#include <dt-bindings/thermal/thermal.h>
86e8f528
BW		 13
14/ {
15 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24
25 cpus {
26 #address-cells = <2>;
27 #size-cells = <0>;
28
29 cpu-map {
30 cluster0 {
31 core0 {
32 cpu = <&cpu0>;
33 };
34 core1 {
35 cpu = <&cpu1>;
36 };
37 core2 {
38 cpu = <&cpu2>;
39 };
40 core3 {
41 cpu = <&cpu3>;
42 };
43 };
44 cluster1 {
45 core0 {
46 cpu = <&cpu4>;
47 };
48 core1 {
49 cpu = <&cpu5>;
50 };
51 core2 {
52 cpu = <&cpu6>;
53 };
54 core3 {
55 cpu = <&cpu7>;
56 };
57 };
58 };
59
58fa29bf
LY		 60 idle-states {
61 entry-method = "psci";
62
63 CPU_SLEEP: cpu-sleep {
64 compatible = "arm,idle-state";
65 local-timer-stop;
66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency-us = <700>;
68 exit-latency-us = <250>;
69 min-residency-us = <1000>;
70 };
71
72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = "arm,idle-state";
74 local-timer-stop;
75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency-us = <1000>;
77 exit-latency-us = <700>;
78 min-residency-us = <2700>;
79 wakeup-latency-us = <1500>;
80 };
81 };
82
86e8f528
BW		 83 cpu0: cpu@0 {
84 compatible = "arm,cortex-a53", "arm,armv8";
85 device_type = "cpu";
86 reg = <0x0 0x0>;
87 enable-method = "psci";
64851603 88 next-level-cache = <&CLUSTER0_L2>;
99860540
LY		 89 clocks = <&stub_clock 0>;
90 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
4d4585c2 92 #cooling-cells = <2>; /* min followed by max */
cd0b69ec 93 dynamic-power-coefficient = <311>;
86e8f528
BW		 94 };
95
96 cpu1: cpu@1 {
97 compatible = "arm,cortex-a53", "arm,armv8";
98 device_type = "cpu";
99 reg = <0x0 0x1>;
100 enable-method = "psci";
64851603 101 next-level-cache = <&CLUSTER0_L2>;
b27dedf5 102 clocks = <&stub_clock 0>;
99860540 103 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
4d4585c2
VK		 105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coefficient = <311>;
86e8f528
BW		 107 };
108
109 cpu2: cpu@2 {
110 compatible = "arm,cortex-a53", "arm,armv8";
111 device_type = "cpu";
112 reg = <0x0 0x2>;
113 enable-method = "psci";
64851603 114 next-level-cache = <&CLUSTER0_L2>;
b27dedf5 115 clocks = <&stub_clock 0>;
99860540 116 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
4d4585c2
VK		 118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <311>;
86e8f528
BW		 120 };
121
122 cpu3: cpu@3 {
123 compatible = "arm,cortex-a53", "arm,armv8";
124 device_type = "cpu";
125 reg = <0x0 0x3>;
126 enable-method = "psci";
64851603 127 next-level-cache = <&CLUSTER0_L2>;
b27dedf5 128 clocks = <&stub_clock 0>;
99860540 129 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
4d4585c2
VK		 131 #cooling-cells = <2>; /* min followed by max */
132 dynamic-power-coefficient = <311>;
86e8f528
BW		 133 };
134
135 cpu4: cpu@100 {
136 compatible = "arm,cortex-a53", "arm,armv8";
137 device_type = "cpu";
138 reg = <0x0 0x100>;
139 enable-method = "psci";
64851603 140 next-level-cache = <&CLUSTER1_L2>;
b27dedf5 141 clocks = <&stub_clock 0>;
99860540 142 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
4d4585c2
VK		 144 #cooling-cells = <2>; /* min followed by max */
145 dynamic-power-coefficient = <311>;
86e8f528
BW		 146 };
147
148 cpu5: cpu@101 {
149 compatible = "arm,cortex-a53", "arm,armv8";
150 device_type = "cpu";
151 reg = <0x0 0x101>;
152 enable-method = "psci";
64851603 153 next-level-cache = <&CLUSTER1_L2>;
b27dedf5 154 clocks = <&stub_clock 0>;
99860540 155 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
4d4585c2
VK		 157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coefficient = <311>;
86e8f528
BW		 159 };
160
161 cpu6: cpu@102 {
162 compatible = "arm,cortex-a53", "arm,armv8";
163 device_type = "cpu";
164 reg = <0x0 0x102>;
165 enable-method = "psci";
64851603 166 next-level-cache = <&CLUSTER1_L2>;
b27dedf5 167 clocks = <&stub_clock 0>;
99860540 168 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
4d4585c2
VK		 170 #cooling-cells = <2>; /* min followed by max */
171 dynamic-power-coefficient = <311>;
86e8f528
BW		 172 };
173
174 cpu7: cpu@103 {
175 compatible = "arm,cortex-a53", "arm,armv8";
176 device_type = "cpu";
177 reg = <0x0 0x103>;
178 enable-method = "psci";
64851603 179 next-level-cache = <&CLUSTER1_L2>;
b27dedf5 180 clocks = <&stub_clock 0>;
99860540 181 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
4d4585c2
VK		 183 #cooling-cells = <2>; /* min followed by max */
184 dynamic-power-coefficient = <311>;
86e8f528 185 };
64851603
LY		 186
187 CLUSTER0_L2: l2-cache0 {
188 compatible = "cache";
189 };
190
191 CLUSTER1_L2: l2-cache1 {
192 compatible = "cache";
193 };
86e8f528
BW		 194 };
195
99860540
LY		 196 cpu_opp_table: cpu_opp_table {
197 compatible = "operating-points-v2";
198 opp-shared;
199
200 opp00 {
201 opp-hz = /bits/ 64 <208000000>;
202 opp-microvolt = <1040000>;
203 clock-latency-ns = <500000>;
204 };
205 opp01 {
206 opp-hz = /bits/ 64 <432000000>;
207 opp-microvolt = <1040000>;
208 clock-latency-ns = <500000>;
209 };
210 opp02 {
211 opp-hz = /bits/ 64 <729000000>;
212 opp-microvolt = <1090000>;
213 clock-latency-ns = <500000>;
214 };
215 opp03 {
216 opp-hz = /bits/ 64 <960000000>;
217 opp-microvolt = <1180000>;
218 clock-latency-ns = <500000>;
219 };
220 opp04 {
221 opp-hz = /bits/ 64 <1200000000>;
222 opp-microvolt = <1330000>;
223 clock-latency-ns = <500000>;
224 };
225 };
226
86e8f528
BW		 227 gic: interrupt-controller@f6801000 {
228 compatible = "arm,gic-400";
229 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
230 <0x0 0xf6802000 0 0x2000>, /* GICC */
231 <0x0 0xf6804000 0 0x2000>, /* GICH */
232 <0x0 0xf6806000 0 0x2000>; /* GICV */
233 #address-cells = <0>;
234 #interrupt-cells = <3>;
235 interrupt-controller;
236 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
237 };
238
239 timer {
240 compatible = "arm,armv8-timer";
241 interrupt-parent = <&gic>;
242 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
243 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
244 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
245 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
246 };
247
248 soc {
249 compatible = "simple-bus";
250 #address-cells = <2>;
251 #size-cells = <2>;
252 ranges;
253
99860540
LY		 254 sram: sram@fff80000 {
255 compatible = "hisilicon,hi6220-sramctrl", "syscon";
256 reg = <0x0 0xfff80000 0x0 0x12000>;
257 };
258
86e8f528
BW		 259 ao_ctrl: ao_ctrl@f7800000 {
260 compatible = "hisilicon,hi6220-aoctrl", "syscon";
261 reg = <0x0 0xf7800000 0x0 0x2000>;
262 #clock-cells = <1>;
263 };
264
265 sys_ctrl: sys_ctrl@f7030000 {
266 compatible = "hisilicon,hi6220-sysctrl", "syscon";
267 reg = <0x0 0xf7030000 0x0 0x2000>;
268 #clock-cells = <1>;
3e14cd4c 269 #reset-cells = <1>;
86e8f528
BW		 270 };
271
272 media_ctrl: media_ctrl@f4410000 {
273 compatible = "hisilicon,hi6220-mediactrl", "syscon";
274 reg = <0x0 0xf4410000 0x0 0x1000>;
275 #clock-cells = <1>;
339d00cb 276 #reset-cells = <1>;
86e8f528
BW		 277 };
278
279 pm_ctrl: pm_ctrl@f7032000 {
280 compatible = "hisilicon,hi6220-pmctrl", "syscon";
281 reg = <0x0 0xf7032000 0x0 0x1000>;
282 #clock-cells = <1>;
283 };
284
94d2d94b
ZG		 285 acpu_sctrl: acpu_sctrl@f6504000 {
286 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
287 reg = <0x0 0xf6504000 0x0 0x1000>;
288 #clock-cells = <1>;
289 };
290
3814b61b
XL		 291 medianoc_ade: medianoc_ade@f4520000 {
292 compatible = "syscon";
293 reg = <0x0 0xf4520000 0x0 0x4000>;
294 };
295
99860540
LY		 296 stub_clock: stub_clock {
297 compatible = "hisilicon,hi6220-stub-clk";
298 hisilicon,hi6220-clk-sram = <&sram>;
299 #clock-cells = <1>;
300 mbox-names = "mbox-tx";
301 mboxes = <&mailbox 1 0 11>;
302 };
303
86e8f528
BW		 304 uart0: uart@f8015000 { /* console */
305 compatible = "arm,pl011", "arm,primecell";
306 reg = <0x0 0xf8015000 0x0 0x1000>;
307 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
a362ec8f
TB		 308 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
309 <&ao_ctrl HI6220_UART0_PCLK>;
86e8f528
BW		 310 clock-names = "uartclk", "apb_pclk";
311 };
a362ec8f
TB		 312
313 uart1: uart@f7111000 {
314 compatible = "arm,pl011", "arm,primecell";
315 reg = <0x0 0xf7111000 0x0 0x1000>;
316 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
318 <&sys_ctrl HI6220_UART1_PCLK>;
319 clock-names = "uartclk", "apb_pclk";
c2aad932
GX		 320 pinctrl-names = "default";
321 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
a362ec8f
TB		 322 status = "disabled";
323 };
324
325 uart2: uart@f7112000 {
326 compatible = "arm,pl011", "arm,primecell";
327 reg = <0x0 0xf7112000 0x0 0x1000>;
328 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
330 <&sys_ctrl HI6220_UART2_PCLK>;
331 clock-names = "uartclk", "apb_pclk";
c2aad932
GX		 332 pinctrl-names = "default";
333 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
a362ec8f
TB		 334 status = "disabled";
335 };
336
337 uart3: uart@f7113000 {
338 compatible = "arm,pl011", "arm,primecell";
339 reg = <0x0 0xf7113000 0x0 0x1000>;
340 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
342 <&sys_ctrl HI6220_UART3_PCLK>;
343 clock-names = "uartclk", "apb_pclk";
c2aad932
GX		 344 pinctrl-names = "default";
345 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
346 status = "disabled";
a362ec8f
TB		 347 };
348
349 uart4: uart@f7114000 {
350 compatible = "arm,pl011", "arm,primecell";
351 reg = <0x0 0xf7114000 0x0 0x1000>;
352 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
354 <&sys_ctrl HI6220_UART4_PCLK>;
355 clock-names = "uartclk", "apb_pclk";
c2aad932
GX		 356 pinctrl-names = "default";
357 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
a362ec8f
TB		 358 status = "disabled";
359 };
9e927031 360
0cf6a8e2
JS		 361 dma0: dma@f7370000 {
362 compatible = "hisilicon,k3-dma-1.0";
363 reg = <0x0 0xf7370000 0x0 0x1000>;
364 #dma-cells = <1>;
365 dma-channels = <15>;
366 dma-requests = <32>;
367 interrupts = <0 84 4>;
368 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
369 dma-no-cci;
370 dma-type = "hi6220_dma";
371 status = "ok";
372 };
373
9e927031
LY		 374 dual_timer0: timer@f8008000 {
375 compatible = "arm,sp804", "arm,primecell";
376 reg = <0x0 0xf8008000 0x0 0x1000>;
377 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
380 <&ao_ctrl HI6220_TIMER0_PCLK>,
381 <&ao_ctrl HI6220_TIMER0_PCLK>;
382 clock-names = "timer1", "timer2", "apb_pclk";
383 };
f2bfacf9 384
810bd15f
ZG		 385 rtc0: rtc@f8003000 {
386 compatible = "arm,pl031", "arm,primecell";
387 reg = <0x0 0xf8003000 0x0 0x1000>;
388 interrupts = <0 12 4>;
389 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
390 clock-names = "apb_pclk";
391 };
392
393 rtc1: rtc@f8004000 {
394 compatible = "arm,pl031", "arm,primecell";
395 reg = <0x0 0xf8004000 0x0 0x1000>;
396 interrupts = <0 8 4>;
397 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
398 clock-names = "apb_pclk";
399 };
400
379e9bf5
ZK		 401 pmx0: pinmux@f7010000 {
402 compatible = "pinctrl-single";
403 reg = <0x0 0xf7010000 0x0 0x27c>;
404 #address-cells = <1>;
405 #size-cells = <1>;
be76fd31 406 #pinctrl-cells = <1>;
379e9bf5
ZK		 407 #gpio-range-cells = <3>;
408 pinctrl-single,register-width = <32>;
409 pinctrl-single,function-mask = <7>;
410 pinctrl-single,gpio-range = <
411 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
412 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
413 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
414 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
415 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
416 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
417 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
418 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
419 &range 0 1 MUX_M1 /* gpio 10: [0] */
420 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
421 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
422 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
423 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
424 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
425 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
426 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
427 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
428 &range 122 1 MUX_M1 /* gpio 15: [6] */
429 &range 126 1 MUX_M1 /* gpio 15: [7] */
430 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
431 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
432 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
433 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
434 >;
435 range: gpio-range {
436 #pinctrl-single,gpio-range-cells = <3>;
437 };
438 };
439
440 pmx1: pinmux@f7010800 {
441 compatible = "pinconf-single";
442 reg = <0x0 0xf7010800 0x0 0x28c>;
443 #address-cells = <1>;
444 #size-cells = <1>;
be76fd31 445 #pinctrl-cells = <1>;
379e9bf5
ZK		 446 pinctrl-single,register-width = <32>;
447 };
448
449 pmx2: pinmux@f8001800 {
450 compatible = "pinconf-single";
451 reg = <0x0 0xf8001800 0x0 0x78>;
452 #address-cells = <1>;
453 #size-cells = <1>;
be76fd31 454 #pinctrl-cells = <1>;
379e9bf5
ZK		 455 pinctrl-single,register-width = <32>;
456 };
457
f2bfacf9
ZK		 458 gpio0: gpio@f8011000 {
459 compatible = "arm,pl061", "arm,primecell";
460 reg = <0x0 0xf8011000 0x0 0x1000>;
461 interrupts = <0 52 0x4>;
462 gpio-controller;
463 #gpio-cells = <2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 clocks = <&ao_ctrl 2>;
467 clock-names = "apb_pclk";
468 };
469
470 gpio1: gpio@f8012000 {
471 compatible = "arm,pl061", "arm,primecell";
472 reg = <0x0 0xf8012000 0x0 0x1000>;
473 interrupts = <0 53 0x4>;
474 gpio-controller;
475 #gpio-cells = <2>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 clocks = <&ao_ctrl 2>;
479 clock-names = "apb_pclk";
480 };
481
482 gpio2: gpio@f8013000 {
483 compatible = "arm,pl061", "arm,primecell";
484 reg = <0x0 0xf8013000 0x0 0x1000>;
485 interrupts = <0 54 0x4>;
486 gpio-controller;
487 #gpio-cells = <2>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 clocks = <&ao_ctrl 2>;
491 clock-names = "apb_pclk";
492 };
493
494 gpio3: gpio@f8014000 {
495 compatible = "arm,pl061", "arm,primecell";
496 reg = <0x0 0xf8014000 0x0 0x1000>;
497 interrupts = <0 55 0x4>;
498 gpio-controller;
499 #gpio-cells = <2>;
379e9bf5 500 gpio-ranges = <&pmx0 0 80 8>;
f2bfacf9
ZK		 501 interrupt-controller;
502 #interrupt-cells = <2>;
503 clocks = <&ao_ctrl 2>;
504 clock-names = "apb_pclk";
505 };
506
507 gpio4: gpio@f7020000 {
508 compatible = "arm,pl061", "arm,primecell";
509 reg = <0x0 0xf7020000 0x0 0x1000>;
510 interrupts = <0 56 0x4>;
511 gpio-controller;
512 #gpio-cells = <2>;
379e9bf5 513 gpio-ranges = <&pmx0 0 88 8>;
f2bfacf9
ZK		 514 interrupt-controller;
515 #interrupt-cells = <2>;
516 clocks = <&ao_ctrl 2>;
517 clock-names = "apb_pclk";
518 };
519
520 gpio5: gpio@f7021000 {
521 compatible = "arm,pl061", "arm,primecell";
522 reg = <0x0 0xf7021000 0x0 0x1000>;
523 interrupts = <0 57 0x4>;
524 gpio-controller;
525 #gpio-cells = <2>;
379e9bf5 526 gpio-ranges = <&pmx0 0 96 8>;
f2bfacf9
ZK		 527 interrupt-controller;
528 #interrupt-cells = <2>;
529 clocks = <&ao_ctrl 2>;
530 clock-names = "apb_pclk";
531 };
532
533 gpio6: gpio@f7022000 {
534 compatible = "arm,pl061", "arm,primecell";
535 reg = <0x0 0xf7022000 0x0 0x1000>;
536 interrupts = <0 58 0x4>;
537 gpio-controller;
538 #gpio-cells = <2>;
379e9bf5 539 gpio-ranges = <&pmx0 0 104 8>;
f2bfacf9
ZK		 540 interrupt-controller;
541 #interrupt-cells = <2>;
542 clocks = <&ao_ctrl 2>;
543 clock-names = "apb_pclk";
544 };
545
546 gpio7: gpio@f7023000 {
547 compatible = "arm,pl061", "arm,primecell";
548 reg = <0x0 0xf7023000 0x0 0x1000>;
549 interrupts = <0 59 0x4>;
550 gpio-controller;
551 #gpio-cells = <2>;
379e9bf5 552 gpio-ranges = <&pmx0 0 112 8>;
f2bfacf9
ZK		 553 interrupt-controller;
554 #interrupt-cells = <2>;
555 clocks = <&ao_ctrl 2>;
556 clock-names = "apb_pclk";
557 };
558
559 gpio8: gpio@f7024000 {
560 compatible = "arm,pl061", "arm,primecell";
561 reg = <0x0 0xf7024000 0x0 0x1000>;
562 interrupts = <0 60 0x4>;
563 gpio-controller;
564 #gpio-cells = <2>;
379e9bf5 565 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
f2bfacf9
ZK		 566 interrupt-controller;
567 #interrupt-cells = <2>;
568 clocks = <&ao_ctrl 2>;
569 clock-names = "apb_pclk";
570 };
571
572 gpio9: gpio@f7025000 {
573 compatible = "arm,pl061", "arm,primecell";
574 reg = <0x0 0xf7025000 0x0 0x1000>;
575 interrupts = <0 61 0x4>;
576 gpio-controller;
577 #gpio-cells = <2>;
379e9bf5 578 gpio-ranges = <&pmx0 0 8 8>;
f2bfacf9
ZK		 579 interrupt-controller;
580 #interrupt-cells = <2>;
581 clocks = <&ao_ctrl 2>;
582 clock-names = "apb_pclk";
583 };
584
585 gpio10: gpio@f7026000 {
586 compatible = "arm,pl061", "arm,primecell";
587 reg = <0x0 0xf7026000 0x0 0x1000>;
588 interrupts = <0 62 0x4>;
589 gpio-controller;
590 #gpio-cells = <2>;
379e9bf5 591 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
f2bfacf9
ZK		 592 interrupt-controller;
593 #interrupt-cells = <2>;
594 clocks = <&ao_ctrl 2>;
595 clock-names = "apb_pclk";
596 };
597
598 gpio11: gpio@f7027000 {
599 compatible = "arm,pl061", "arm,primecell";
600 reg = <0x0 0xf7027000 0x0 0x1000>;
601 interrupts = <0 63 0x4>;
602 gpio-controller;
603 #gpio-cells = <2>;
379e9bf5 604 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
f2bfacf9
ZK		 605 interrupt-controller;
606 #interrupt-cells = <2>;
607 clocks = <&ao_ctrl 2>;
608 clock-names = "apb_pclk";
609 };
610
611 gpio12: gpio@f7028000 {
612 compatible = "arm,pl061", "arm,primecell";
613 reg = <0x0 0xf7028000 0x0 0x1000>;
614 interrupts = <0 64 0x4>;
615 gpio-controller;
616 #gpio-cells = <2>;
379e9bf5 617 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
f2bfacf9
ZK		 618 interrupt-controller;
619 #interrupt-cells = <2>;
620 clocks = <&ao_ctrl 2>;
621 clock-names = "apb_pclk";
622 };
623
624 gpio13: gpio@f7029000 {
625 compatible = "arm,pl061", "arm,primecell";
626 reg = <0x0 0xf7029000 0x0 0x1000>;
627 interrupts = <0 65 0x4>;
628 gpio-controller;
379e9bf5
ZK		 629 #gpio-cells = <2>;
630 gpio-ranges = <&pmx0 0 48 8>;
f2bfacf9
ZK		 631 interrupt-controller;
632 #interrupt-cells = <2>;
633 clocks = <&ao_ctrl 2>;
634 clock-names = "apb_pclk";
635 };
636
637 gpio14: gpio@f702a000 {
638 compatible = "arm,pl061", "arm,primecell";
639 reg = <0x0 0xf702a000 0x0 0x1000>;
640 interrupts = <0 66 0x4>;
641 gpio-controller;
642 #gpio-cells = <2>;
379e9bf5 643 gpio-ranges = <&pmx0 0 56 8>;
f2bfacf9
ZK		 644 interrupt-controller;
645 #interrupt-cells = <2>;
646 clocks = <&ao_ctrl 2>;
647 clock-names = "apb_pclk";
648 };
649
650 gpio15: gpio@f702b000 {
651 compatible = "arm,pl061", "arm,primecell";
652 reg = <0x0 0xf702b000 0x0 0x1000>;
653 interrupts = <0 67 0x4>;
654 gpio-controller;
655 #gpio-cells = <2>;
379e9bf5
ZK		 656 gpio-ranges = <
657 &pmx0 0 74 6
658 &pmx0 6 122 1
659 &pmx0 7 126 1
660 >;
f2bfacf9
ZK		 661 interrupt-controller;
662 #interrupt-cells = <2>;
663 clocks = <&ao_ctrl 2>;
664 clock-names = "apb_pclk";
665 };
666
667 gpio16: gpio@f702c000 {
668 compatible = "arm,pl061", "arm,primecell";
669 reg = <0x0 0xf702c000 0x0 0x1000>;
670 interrupts = <0 68 0x4>;
671 gpio-controller;
672 #gpio-cells = <2>;
379e9bf5 673 gpio-ranges = <&pmx0 0 127 8>;
f2bfacf9
ZK		 674 interrupt-controller;
675 #interrupt-cells = <2>;
676 clocks = <&ao_ctrl 2>;
677 clock-names = "apb_pclk";
678 };
679
680 gpio17: gpio@f702d000 {
681 compatible = "arm,pl061", "arm,primecell";
682 reg = <0x0 0xf702d000 0x0 0x1000>;
683 interrupts = <0 69 0x4>;
684 gpio-controller;
685 #gpio-cells = <2>;
379e9bf5 686 gpio-ranges = <&pmx0 0 135 8>;
f2bfacf9
ZK		 687 interrupt-controller;
688 #interrupt-cells = <2>;
689 clocks = <&ao_ctrl 2>;
690 clock-names = "apb_pclk";
691 };
692
693 gpio18: gpio@f702e000 {
694 compatible = "arm,pl061", "arm,primecell";
695 reg = <0x0 0xf702e000 0x0 0x1000>;
696 interrupts = <0 70 0x4>;
697 gpio-controller;
698 #gpio-cells = <2>;
379e9bf5 699 gpio-ranges = <&pmx0 0 143 8>;
f2bfacf9
ZK		 700 interrupt-controller;
701 #interrupt-cells = <2>;
702 clocks = <&ao_ctrl 2>;
703 clock-names = "apb_pclk";
704 };
705
706 gpio19: gpio@f702f000 {
707 compatible = "arm,pl061", "arm,primecell";
708 reg = <0x0 0xf702f000 0x0 0x1000>;
709 interrupts = <0 71 0x4>;
710 gpio-controller;
711 #gpio-cells = <2>;
379e9bf5 712 gpio-ranges = <&pmx0 0 151 8>;
f2bfacf9
ZK		 713 interrupt-controller;
714 #interrupt-cells = <2>;
715 clocks = <&ao_ctrl 2>;
716 clock-names = "apb_pclk";
717 };
60dac1b1
ZK		 718
719 spi0: spi@f7106000 {
720 compatible = "arm,pl022", "arm,primecell";
721 reg = <0x0 0xf7106000 0x0 0x1000>;
722 interrupts = <0 50 4>;
723 bus-id = <0>;
724 enable-dma = <0>;
725 clocks = <&sys_ctrl HI6220_SPI_CLK>;
726 clock-names = "apb_pclk";
727 pinctrl-names = "default";
728 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
729 num-cs = <1>;
730 cs-gpios = <&gpio6 2 0>;
731 status = "disabled";
732 };
5ff3a4dd
XK		 733
734 i2c0: i2c@f7100000 {
735 compatible = "snps,designware-i2c";
736 reg = <0x0 0xf7100000 0x0 0x1000>;
737 interrupts = <0 44 4>;
738 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
739 i2c-sda-hold-time-ns = <300>;
740 pinctrl-names = "default";
741 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
742 status = "disabled";
743 };
744
745 i2c1: i2c@f7101000 {
746 compatible = "snps,designware-i2c";
747 reg = <0x0 0xf7101000 0x0 0x1000>;
748 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
749 interrupts = <0 45 4>;
750 i2c-sda-hold-time-ns = <300>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
753 status = "disabled";
754 };
755
756 i2c2: i2c@f7102000 {
757 compatible = "snps,designware-i2c";
758 reg = <0x0 0xf7102000 0x0 0x1000>;
759 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
760 interrupts = <0 46 4>;
761 i2c-sda-hold-time-ns = <300>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
764 status = "disabled";
765 };
b4b31a7c 766
b4b31a7c
ZG		 767 usb_phy: usbphy {
768 compatible = "hisilicon,hi6220-usb-phy";
769 #phy-cells = <0>;
1b32a5ff 770 phy-supply = <&reg_5v_hub>;
b4b31a7c
ZG		 771 hisilicon,peripheral-syscon = <&sys_ctrl>;
772 };
773
774 usb: usb@f72c0000 {
775 compatible = "hisilicon,hi6220-usb";
776 reg = <0x0 0xf72c0000 0x0 0x40000>;
777 phys = <&usb_phy>;
778 phy-names = "usb2-phy";
779 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
780 clock-names = "otg";
781 dr_mode = "otg";
b4b31a7c
ZG		 782 g-rx-fifo-size = <512>;
783 g-np-tx-fifo-size = <128>;
341b26b7
SG		 784 g-tx-fifo-size = <128 128 128 128 128 128 128 128
785 16 16 16 16 16 16 16>;
b4b31a7c
ZG		 786 interrupts = <0 77 0x4>;
787 };
86073570
LY		 788
789 mailbox: mailbox@f7510000 {
790 compatible = "hisilicon,hi6220-mbox";
791 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
792 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
793 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
794 #mbox-cells = <3>;
795 };
d6b259d4
XK		 796
797 dwmmc_0: dwmmc0@f723d000 {
798 compatible = "hisilicon,hi6220-dw-mshc";
d6b259d4
XK		 799 reg = <0x0 0xf723d000 0x0 0x1000>;
800 interrupts = <0x0 0x48 0x4>;
801 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
802 clock-names = "ciu", "biu";
94914fc8 803 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
0fbdf995 804 reset-names = "reset";
d6b259d4
XK		 805 pinctrl-names = "default";
806 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
807 &emmc_cfg_func &emmc_rst_cfg_func>;
808 };
809
810 dwmmc_1: dwmmc1@f723e000 {
811 compatible = "hisilicon,hi6220-dw-mshc";
d6b259d4 812 hisilicon,peripheral-syscon = <&ao_ctrl>;
d6b259d4
XK		 813 reg = <0x0 0xf723e000 0x0 0x1000>;
814 interrupts = <0x0 0x49 0x4>;
815 #address-cells = <0x1>;
816 #size-cells = <0x0>;
817 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
818 clock-names = "ciu", "biu";
94914fc8 819 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
0fbdf995 820 reset-names = "reset";
d6b259d4
XK		 821 pinctrl-names = "default", "idle";
822 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
823 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
824 };
825
826 dwmmc_2: dwmmc2@f723f000 {
827 compatible = "hisilicon,hi6220-dw-mshc";
d6b259d4
XK		 828 reg = <0x0 0xf723f000 0x0 0x1000>;
829 interrupts = <0x0 0x4a 0x4>;
830 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
831 clock-names = "ciu", "biu";
94914fc8 832 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
0fbdf995 833 reset-names = "reset";
d6b259d4
XK		 834 pinctrl-names = "default", "idle";
835 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
836 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
837 };
2158ab08 838
6bbec98e
DS		 839 watchdog0: watchdog@f8005000 {
840 compatible = "arm,sp805-wdt", "arm,primecell";
841 reg = <0x0 0xf8005000 0x0 0x1000>;
842 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
844 clock-names = "apb_pclk";
845 };
846
2158ab08
LY		 847 tsensor: tsensor@0,f7030700 {
848 compatible = "hisilicon,tsensor";
849 reg = <0x0 0xf7030700 0x0 0x1000>;
850 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&sys_ctrl 22>;
852 clock-names = "thermal_clk";
853 #thermal-sensor-cells = <1>;
854 };
cd0b69ec 855
0cf6a8e2
JS		 856 i2s0: i2s@f7118000{
857 compatible = "hisilicon,hi6210-i2s";
858 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
859 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
860 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
861 <&sys_ctrl HI6220_BBPPLL0_DIV>;
862 clock-names = "dacodec", "i2s-base";
863 dmas = <&dma0 15 &dma0 14>;
864 dma-names = "rx", "tx";
865 hisilicon,sysctrl-syscon = <&sys_ctrl>;
866 #sound-dai-cells = <1>;
867 };
868
cd0b69ec
LY		 869 thermal-zones {
870
871 cls0: cls0 {
872 polling-delay = <1000>;
873 polling-delay-passive = <100>;
874 sustainable-power = <3326>;
875
876 /* sensor ID */
877 thermal-sensors = <&tsensor 2>;
878
879 trips {
880 threshold: trip-point@0 {
881 temperature = <65000>;
882 hysteresis = <0>;
883 type = "passive";
884 };
885
886 target: trip-point@1 {
887 temperature = <75000>;
888 hysteresis = <0>;
889 type = "passive";
890 };
891 };
892
893 cooling-maps {
894 map0 {
895 trip = <&target>;
6ad5506e
VK		 896 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
897 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
898 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
899 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
900 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
901 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
902 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
903 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cd0b69ec
LY		 904 };
905 };
906 };
907 };
3814b61b
XL		 908
909 ade: ade@f4100000 {
910 compatible = "hisilicon,hi6220-ade";
911 reg = <0x0 0xf4100000 0x0 0x7800>;
912 reg-names = "ade_base";
913 hisilicon,noc-syscon = <&medianoc_ade>;
914 resets = <&media_ctrl MEDIA_ADE>;
915 interrupts = <0 115 4>; /* ldi interrupt */
916
917 clocks = <&media_ctrl HI6220_ADE_CORE>,
918 <&media_ctrl HI6220_CODEC_JPEG>,
919 <&media_ctrl HI6220_ADE_PIX_SRC>;
920 /*clock name*/
921 clock-names = "clk_ade_core",
922 "clk_codec_jpeg",
923 "clk_ade_pix";
924
925 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
926 <&media_ctrl HI6220_CODEC_JPEG>;
927 assigned-clock-rates = <360000000>, <288000000>;
928 dma-coherent;
929 status = "disabled";
930
931 port {
932 ade_out: endpoint {
933 remote-endpoint = <&dsi_in>;
934 };
935 };
936 };
937
938 dsi: dsi@f4107800 {
939 compatible = "hisilicon,hi6220-dsi";
940 reg = <0x0 0xf4107800 0x0 0x100>;
941 clocks = <&media_ctrl HI6220_DSI_PCLK>;
942 clock-names = "pclk";
943 status = "disabled";
944
945 ports {
946 #address-cells = <1>;
947 #size-cells = <0>;
948
949 /* 0 for input port */
950 port@0 {
951 reg = <0>;
952 dsi_in: endpoint {
953 remote-endpoint = <&ade_out>;
954 };
955 };
956 };
957 };
4fcf9a62
LY		 958
959 debug@f6590000 {
960 compatible = "arm,coresight-cpu-debug","arm,primecell";
961 reg = <0 0xf6590000 0 0x1000>;
962 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
963 clock-names = "apb_pclk";
964 cpu = <&cpu0>;
965 };
966
967 debug@f6592000 {
968 compatible = "arm,coresight-cpu-debug","arm,primecell";
969 reg = <0 0xf6592000 0 0x1000>;
970 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
971 clock-names = "apb_pclk";
972 cpu = <&cpu1>;
973 };
974
975 debug@f6594000 {
976 compatible = "arm,coresight-cpu-debug","arm,primecell";
977 reg = <0 0xf6594000 0 0x1000>;
978 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
979 clock-names = "apb_pclk";
980 cpu = <&cpu2>;
981 };
982
983 debug@f6596000 {
984 compatible = "arm,coresight-cpu-debug","arm,primecell";
985 reg = <0 0xf6596000 0 0x1000>;
986 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
987 clock-names = "apb_pclk";
988 cpu = <&cpu3>;
989 };
990
991 debug@f65d0000 {
992 compatible = "arm,coresight-cpu-debug","arm,primecell";
993 reg = <0 0xf65d0000 0 0x1000>;
994 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
995 clock-names = "apb_pclk";
996 cpu = <&cpu4>;
997 };
998
999 debug@f65d2000 {
1000 compatible = "arm,coresight-cpu-debug","arm,primecell";
1001 reg = <0 0xf65d2000 0 0x1000>;
1002 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1003 clock-names = "apb_pclk";
1004 cpu = <&cpu5>;
1005 };
1006
1007 debug@f65d4000 {
1008 compatible = "arm,coresight-cpu-debug","arm,primecell";
1009 reg = <0 0xf65d4000 0 0x1000>;
1010 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1011 clock-names = "apb_pclk";
1012 cpu = <&cpu6>;
1013 };
1014
1015 debug@f65d6000 {
1016 compatible = "arm,coresight-cpu-debug","arm,primecell";
1017 reg = <0 0xf65d6000 0 0x1000>;
1018 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1019 clock-names = "apb_pclk";
1020 cpu = <&cpu7>;
1021 };
86e8f528
BW		 1022 };
1023};
0b798427
LP		 1024
1025#include "hi6220-coresight.dtsi"
Linux 6.x block layer and io_uring tree(s)