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Merge tag 'usb-5.16-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
[linux-block.git] / arch / arm64 / boot / dts / freescale / imx8mq.dtsi
CommitLineData
748f908c
LS		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
fdbcc04d 8#include <dt-bindings/power/imx8mq-power.h>
fc26e600 9#include <dt-bindings/reset/imx8mq-reset.h>
748f908c 10#include <dt-bindings/gpio/gpio.h>
a01194d7 11#include "dt-bindings/input/input.h"
748f908c 12#include <dt-bindings/interrupt-controller/arm-gic.h>
e464fd2b 13#include <dt-bindings/thermal/thermal.h>
ad1abc8a 14#include <dt-bindings/interconnect/imx8mq.h>
748f908c
LS		 15#include "imx8mq-pinfunc.h"
16
17/ {
c412123f 18 interrupt-parent = <&gpc>;
748f908c
LS		 19
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
614d8846 24 ethernet0 = &fec1;
1f370972
AH		 25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
748f908c
LS		 30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 i2c3 = &i2c4;
e9a8d996
PF		 34 mmc0 = &usdhc1;
35 mmc1 = &usdhc2;
748f908c
LS		 36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
85761f45
FE		 40 spi0 = &ecspi1;
41 spi1 = &ecspi2;
42 spi2 = &ecspi3;
748f908c
LS		 43 };
44
45 ckil: clock-ckil {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
49 clock-output-names = "ckil";
50 };
51
52 osc_25m: clock-osc-25m {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 clock-output-names = "osc_25m";
57 };
58
59 osc_27m: clock-osc-27m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <27000000>;
63 clock-output-names = "osc_27m";
64 };
65
66 clk_ext1: clock-ext1 {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <133000000>;
70 clock-output-names = "clk_ext1";
71 };
72
73 clk_ext2: clock-ext2 {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <133000000>;
77 clock-output-names = "clk_ext2";
78 };
79
80 clk_ext3: clock-ext3 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <133000000>;
84 clock-output-names = "clk_ext3";
85 };
86
87 clk_ext4: clock-ext4 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency= <133000000>;
91 clock-output-names = "clk_ext4";
92 };
93
94 cpus {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 A53_0: cpu@0 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53";
101 reg = <0x0>;
b810641a
AV		 102 clock-latency = <61036>; /* two CLK32 periods */
103 clocks = <&clk IMX8MQ_CLK_ARM>;
748f908c
LS		 104 enable-method = "psci";
105 next-level-cache = <&A53_L2>;
64d26f8c 106 operating-points-v2 = <&a53_opp_table>;
e464fd2b 107 #cooling-cells = <2>;
12629c5c
LC		 108 nvmem-cells = <&cpu_speed_grade>;
109 nvmem-cell-names = "speed_grade";
748f908c
LS		 110 };
111
112 A53_1: cpu@1 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a53";
115 reg = <0x1>;
b810641a
AV		 116 clock-latency = <61036>; /* two CLK32 periods */
117 clocks = <&clk IMX8MQ_CLK_ARM>;
748f908c
LS		 118 enable-method = "psci";
119 next-level-cache = <&A53_L2>;
64d26f8c 120 operating-points-v2 = <&a53_opp_table>;
e464fd2b 121 #cooling-cells = <2>;
748f908c
LS		 122 };
123
124 A53_2: cpu@2 {
125 device_type = "cpu";
126 compatible = "arm,cortex-a53";
127 reg = <0x2>;
b810641a
AV		 128 clock-latency = <61036>; /* two CLK32 periods */
129 clocks = <&clk IMX8MQ_CLK_ARM>;
748f908c
LS		 130 enable-method = "psci";
131 next-level-cache = <&A53_L2>;
64d26f8c 132 operating-points-v2 = <&a53_opp_table>;
e464fd2b 133 #cooling-cells = <2>;
748f908c
LS		 134 };
135
136 A53_3: cpu@3 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a53";
139 reg = <0x3>;
b810641a
AV		 140 clock-latency = <61036>; /* two CLK32 periods */
141 clocks = <&clk IMX8MQ_CLK_ARM>;
748f908c
LS		 142 enable-method = "psci";
143 next-level-cache = <&A53_L2>;
64d26f8c 144 operating-points-v2 = <&a53_opp_table>;
e464fd2b 145 #cooling-cells = <2>;
748f908c
LS		 146 };
147
148 A53_L2: l2-cache0 {
149 compatible = "cache";
150 };
151 };
152
dbde7ec3
FE		 153 a53_opp_table: opp-table {
154 compatible = "operating-points-v2";
155 opp-shared;
156
157 opp-800000000 {
158 opp-hz = /bits/ 64 <800000000>;
159 opp-microvolt = <900000>;
12629c5c
LC		 160 /* Industrial only */
161 opp-supported-hw = <0xf>, <0x4>;
162 clock-latency-ns = <150000>;
db4cfe2f 163 opp-suspend;
12629c5c
LC		 164 };
165
166 opp-1000000000 {
167 opp-hz = /bits/ 64 <1000000000>;
168 opp-microvolt = <900000>;
169 /* Consumer only */
170 opp-supported-hw = <0xe>, <0x3>;
dbde7ec3 171 clock-latency-ns = <150000>;
db4cfe2f 172 opp-suspend;
dbde7ec3
FE		 173 };
174
8cfd813c
LS		 175 opp-1300000000 {
176 opp-hz = /bits/ 64 <1300000000>;
dbde7ec3 177 opp-microvolt = <1000000>;
9eced3a2 178 opp-supported-hw = <0xc>, <0x4>;
12629c5c 179 clock-latency-ns = <150000>;
db4cfe2f 180 opp-suspend;
12629c5c
LC		 181 };
182
183 opp-1500000000 {
184 opp-hz = /bits/ 64 <1500000000>;
185 opp-microvolt = <1000000>;
9eced3a2 186 opp-supported-hw = <0x8>, <0x3>;
dbde7ec3 187 clock-latency-ns = <150000>;
db4cfe2f 188 opp-suspend;
dbde7ec3
FE		 189 };
190 };
191
b3f6a5f2
CC		 192 pmu {
193 compatible = "arm,cortex-a53-pmu";
194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-parent = <&gic>;
b3f6a5f2
CC		 196 };
197
748f908c
LS		 198 psci {
199 compatible = "arm,psci-1.0";
200 method = "smc";
201 };
202
cddbea8d 203 thermal-zones {
c5486819 204 cpu_thermal: cpu-thermal {
cddbea8d
FE		 205 polling-delay-passive = <250>;
206 polling-delay = <2000>;
207 thermal-sensors = <&tmu 0>;
208
209 trips {
210 cpu_alert: cpu-alert {
211 temperature = <80000>;
212 hysteresis = <2000>;
213 type = "passive";
214 };
215
216 cpu-crit {
217 temperature = <90000>;
218 hysteresis = <2000>;
219 type = "critical";
220 };
221 };
222
223 cooling-maps {
224 map0 {
225 trip = <&cpu_alert>;
226 cooling-device =
227 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
228 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
229 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
230 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
231 };
232 };
233 };
234
235 gpu-thermal {
236 polling-delay-passive = <250>;
237 polling-delay = <2000>;
238 thermal-sensors = <&tmu 1>;
239
240 trips {
9404f2ea
GG		 241 gpu_alert: gpu-alert {
242 temperature = <80000>;
243 hysteresis = <2000>;
244 type = "passive";
245 };
246
cddbea8d
FE		 247 gpu-crit {
248 temperature = <90000>;
249 hysteresis = <2000>;
250 type = "critical";
251 };
252 };
9404f2ea
GG		 253
254 cooling-maps {
255 map0 {
256 trip = <&gpu_alert>;
257 cooling-device =
258 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
259 };
260 };
cddbea8d
FE		 261 };
262
263 vpu-thermal {
264 polling-delay-passive = <250>;
265 polling-delay = <2000>;
266 thermal-sensors = <&tmu 2>;
267
268 trips {
269 vpu-crit {
270 temperature = <90000>;
271 hysteresis = <2000>;
272 type = "critical";
273 };
274 };
275 };
276 };
277
748f908c
LS		 278 timer {
279 compatible = "arm,armv8-timer";
280 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
281 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
282 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
283 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
284 interrupt-parent = <&gic>;
285 arm,no-tick-in-suspend;
286 };
287
288 soc@0 {
ce58459d 289 compatible = "fsl,imx8mq-soc", "simple-bus";
748f908c
LS		 290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges = <0x0 0x0 0x0 0x3e000000>;
ca04fed4 293 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
cbff2379
AG		 294 nvmem-cells = <&imx8mq_uid>;
295 nvmem-cell-names = "soc_unique_id";
748f908c
LS		 296
297 bus@30000000 { /* AIPS1 */
dc3efc6f 298 compatible = "fsl,aips-bus", "simple-bus";
921a6845 299 reg = <0x30000000 0x400000>;
748f908c
LS		 300 #address-cells = <1>;
301 #size-cells = <1>;
302 ranges = <0x30000000 0x30000000 0x400000>;
303
fcb1991c
LS		 304 sai1: sai@30010000 {
305 #sound-dai-cells = <0>;
306 compatible = "fsl,imx8mq-sai";
307 reg = <0x30010000 0x10000>;
308 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
310 <&clk IMX8MQ_CLK_SAI1_ROOT>,
311 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
312 clock-names = "bus", "mclk1", "mclk2", "mclk3";
313 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
314 dma-names = "rx", "tx";
315 status = "disabled";
316 };
317
318 sai6: sai@30030000 {
319 #sound-dai-cells = <0>;
320 compatible = "fsl,imx8mq-sai";
321 reg = <0x30030000 0x10000>;
322 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
324 <&clk IMX8MQ_CLK_SAI6_ROOT>,
325 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
326 clock-names = "bus", "mclk1", "mclk2", "mclk3";
327 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
328 dma-names = "rx", "tx";
329 status = "disabled";
330 };
331
332 sai5: sai@30040000 {
333 #sound-dai-cells = <0>;
334 compatible = "fsl,imx8mq-sai";
335 reg = <0x30040000 0x10000>;
336 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
338 <&clk IMX8MQ_CLK_SAI5_ROOT>,
339 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
340 clock-names = "bus", "mclk1", "mclk2", "mclk3";
341 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
342 dma-names = "rx", "tx";
343 status = "disabled";
344 };
345
346 sai4: sai@30050000 {
347 #sound-dai-cells = <0>;
348 compatible = "fsl,imx8mq-sai";
349 reg = <0x30050000 0x10000>;
350 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
352 <&clk IMX8MQ_CLK_SAI4_ROOT>,
353 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
354 clock-names = "bus", "mclk1", "mclk2", "mclk3";
355 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
356 dma-names = "rx", "tx";
357 status = "disabled";
358 };
359
748f908c
LS		 360 gpio1: gpio@30200000 {
361 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
362 reg = <0x30200000 0x10000>;
363 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
580b064d 365 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
748f908c
LS		 366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
26c2f55a 370 gpio-ranges = <&iomuxc 0 10 30>;
748f908c
LS		 371 };
372
373 gpio2: gpio@30210000 {
374 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
375 reg = <0x30210000 0x10000>;
376 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
580b064d 378 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
748f908c
LS		 379 gpio-controller;
380 #gpio-cells = <2>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
26c2f55a 383 gpio-ranges = <&iomuxc 0 40 21>;
748f908c
LS		 384 };
385
386 gpio3: gpio@30220000 {
387 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
388 reg = <0x30220000 0x10000>;
389 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
580b064d 391 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
748f908c
LS		 392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
26c2f55a 396 gpio-ranges = <&iomuxc 0 61 26>;
748f908c
LS		 397 };
398
399 gpio4: gpio@30230000 {
400 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
401 reg = <0x30230000 0x10000>;
402 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
580b064d 404 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
748f908c
LS		 405 gpio-controller;
406 #gpio-cells = <2>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
26c2f55a 409 gpio-ranges = <&iomuxc 0 87 32>;
748f908c
LS		 410 };
411
412 gpio5: gpio@30240000 {
413 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
414 reg = <0x30240000 0x10000>;
415 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
580b064d 417 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
748f908c
LS		 418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
26c2f55a 422 gpio-ranges = <&iomuxc 0 119 30>;
748f908c
LS		 423 };
424
e464fd2b
AAP		 425 tmu: tmu@30260000 {
426 compatible = "fsl,imx8mq-tmu";
427 reg = <0x30260000 0x10000>;
1f2f98f2 428 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
150736b8 429 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
e464fd2b
AAP		 430 little-endian;
431 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
432 fsl,tmu-calibration = <0x00000000 0x00000023
433 0x00000001 0x00000029
434 0x00000002 0x0000002f
435 0x00000003 0x00000035
436 0x00000004 0x0000003d
437 0x00000005 0x00000043
438 0x00000006 0x0000004b
439 0x00000007 0x00000051
440 0x00000008 0x00000057
441 0x00000009 0x0000005f
442 0x0000000a 0x00000067
443 0x0000000b 0x0000006f
444
445 0x00010000 0x0000001b
446 0x00010001 0x00000023
447 0x00010002 0x0000002b
448 0x00010003 0x00000033
449 0x00010004 0x0000003b
450 0x00010005 0x00000043
451 0x00010006 0x0000004b
452 0x00010007 0x00000055
453 0x00010008 0x0000005d
454 0x00010009 0x00000067
455 0x0001000a 0x00000070
456
457 0x00020000 0x00000017
458 0x00020001 0x00000023
459 0x00020002 0x0000002d
460 0x00020003 0x00000037
461 0x00020004 0x00000041
462 0x00020005 0x0000004b
463 0x00020006 0x00000057
464 0x00020007 0x00000063
465 0x00020008 0x0000006f
466
467 0x00030000 0x00000015
468 0x00030001 0x00000021
469 0x00030002 0x0000002d
470 0x00030003 0x00000039
471 0x00030004 0x00000045
472 0x00030005 0x00000053
473 0x00030006 0x0000005f
474 0x00030007 0x00000071>;
475 #thermal-sensor-cells = <1>;
476 };
477
a2b91efd
LS		 478 wdog1: watchdog@30280000 {
479 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
480 reg = <0x30280000 0x10000>;
481 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
483 status = "disabled";
484 };
485
486 wdog2: watchdog@30290000 {
487 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
488 reg = <0x30290000 0x10000>;
489 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
491 status = "disabled";
492 };
493
494 wdog3: watchdog@302a0000 {
495 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
496 reg = <0x302a0000 0x10000>;
497 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
499 status = "disabled";
500 };
501
1474d48b
DB		 502 sdma2: sdma@302c0000 {
503 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
504 reg = <0x302c0000 0x10000>;
505 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
507 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
508 clock-names = "ipg", "ahb";
509 #dma-cells = <3>;
510 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
511 };
512
1987ddfc
GG		 513 lcdif: lcd-controller@30320000 {
514 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
515 reg = <0x30320000 0x10000>;
516 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
518 clock-names = "pix";
519 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
520 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
521 <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
522 <&clk IMX8MQ_VIDEO_PLL1>;
523 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
524 <&clk IMX8MQ_VIDEO_PLL1>,
525 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
526 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
527 status = "disabled";
d0081bd0
GG		 528
529 port@0 {
530 lcdif_mipi_dsi: endpoint {
531 remote-endpoint = <&mipi_dsi_lcdif_in>;
532 };
533 };
1987ddfc
GG		 534 };
535
c18696de 536 iomuxc: pinctrl@30330000 {
748f908c
LS		 537 compatible = "fsl,imx8mq-iomuxc";
538 reg = <0x30330000 0x10000>;
539 };
540
541 iomuxc_gpr: syscon@30340000 {
21570180
GG		 542 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
543 "syscon", "simple-mfd";
748f908c 544 reg = <0x30340000 0x10000>;
21570180
GG		 545
546 mux: mux-controller {
547 compatible = "mmio-mux";
548 #mux-control-cells = <1>;
549 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
550 };
748f908c
LS		 551 };
552
12fa1078 553 ocotp: efuse@30350000 {
9e113b2e
CC		 554 compatible = "fsl,imx8mq-ocotp", "syscon";
555 reg = <0x30350000 0x10000>;
556 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
557 #address-cells = <1>;
558 #size-cells = <1>;
12629c5c 559
cbff2379
AG		 560 imx8mq_uid: soc-uid@410 {
561 reg = <0x4 0x8>;
562 };
563
12629c5c
LC		 564 cpu_speed_grade: speed-grade@10 {
565 reg = <0x10 4>;
566 };
066438ae
JZ		 567
568 fec_mac_address: mac-address@90 {
569 reg = <0x90 6>;
570 };
9e113b2e
CC		 571 };
572
748f908c
LS		 573 anatop: syscon@30360000 {
574 compatible = "fsl,imx8mq-anatop", "syscon";
575 reg = <0x30360000 0x10000>;
576 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
577 };
578
3ea95c31
AV		 579 snvs: snvs@30370000 {
580 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
581 reg = <0x30370000 0x10000>;
582
583 snvs_rtc: snvs-rtc-lp{
584 compatible = "fsl,sec-v4.0-mon-rtc-lp";
585 regmap =<&snvs>;
586 offset = <0x34>;
587 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
881b54c7
AH		 589 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
590 clock-names = "snvs-rtc";
3ea95c31
AV		 591 };
592
a01194d7
AAP		 593 snvs_pwrkey: snvs-powerkey {
594 compatible = "fsl,sec-v4.0-pwrkey";
595 regmap = <&snvs>;
596 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
edd91ba6
AD		 597 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
598 clock-names = "snvs-pwrkey";
a01194d7
AAP		 599 linux,keycode = <KEY_POWER>;
600 wakeup-source;
601 status = "disabled";
602 };
3ea95c31
AV		 603 };
604
748f908c
LS		 605 clk: clock-controller@30380000 {
606 compatible = "fsl,imx8mq-ccm";
607 reg = <0x30380000 0x10000>;
608 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
610 #clock-cells = <1>;
611 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
612 <&clk_ext1>, <&clk_ext2>,
613 <&clk_ext3>, <&clk_ext4>;
614 clock-names = "ckil", "osc_25m", "osc_27m",
615 "clk_ext1", "clk_ext2",
616 "clk_ext3", "clk_ext4";
9e6337e6
PF		 617 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
618 <&clk IMX8MQ_CLK_A53_CORE>,
71fa01d3
SW		 619 <&clk IMX8MQ_CLK_NOC>,
620 <&clk IMX8MQ_CLK_AUDIO_AHB>,
621 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
622 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
623 <&clk IMX8MQ_AUDIO_PLL1>,
624 <&clk IMX8MQ_AUDIO_PLL2>;
9e6337e6 625 assigned-clock-rates = <0>, <0>,
71fa01d3
SW		 626 <800000000>,
627 <0>,
628 <0>,
629 <0>,
630 <786432000>,
631 <722534400>;
9e6337e6 632 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
71fa01d3
SW		 633 <&clk IMX8MQ_ARM_PLL_OUT>,
634 <0>,
635 <&clk IMX8MQ_SYS2_PLL_500M>,
636 <&clk IMX8MQ_AUDIO_PLL1>,
637 <&clk IMX8MQ_AUDIO_PLL2>;
748f908c 638 };
d3a2d72b 639
d62a250e
AS		 640 src: reset-controller@30390000 {
641 compatible = "fsl,imx8mq-src", "syscon";
642 reg = <0x30390000 0x10000>;
d0955f66 643 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
d62a250e
AS		 644 #reset-cells = <1>;
645 };
646
fdbcc04d
LS		 647 gpc: gpc@303a0000 {
648 compatible = "fsl,imx8mq-gpc";
649 reg = <0x303a0000 0x10000>;
791619f6 650 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
c412123f
LS		 651 interrupt-parent = <&gic>;
652 interrupt-controller;
653 #interrupt-cells = <3>;
fdbcc04d
LS		 654
655 pgc {
656 #address-cells = <1>;
657 #size-cells = <0>;
658
659 pgc_mipi: power-domain@0 {
660 #power-domain-cells = <0>;
661 reg = <IMX8M_POWER_DOMAIN_MIPI>;
662 };
663
de2a538b
AS		 664 /*
665 * As per comment in ATF source code:
666 *
667 * PCIE1 and PCIE2 share the
668 * same reset signal, if we
669 * power down PCIE2, PCIE1
670 * will be held in reset too.
671 *
672 * So instead of creating two
673 * separate power domains for
674 * PCIE1 and PCIE2 we create a
675 * link between both and use
676 * it as a shared PCIE power
677 * domain.
678 */
679 pgc_pcie: power-domain@1 {
fdbcc04d
LS		 680 #power-domain-cells = <0>;
681 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
de2a538b 682 power-domains = <&pgc_pcie2>;
fdbcc04d
LS		 683 };
684
685 pgc_otg1: power-domain@2 {
686 #power-domain-cells = <0>;
687 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
688 };
689
690 pgc_otg2: power-domain@3 {
691 #power-domain-cells = <0>;
692 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
693 };
694
695 pgc_ddr1: power-domain@4 {
696 #power-domain-cells = <0>;
697 reg = <IMX8M_POWER_DOMAIN_DDR1>;
698 };
699
700 pgc_gpu: power-domain@5 {
701 #power-domain-cells = <0>;
702 reg = <IMX8M_POWER_DOMAIN_GPU>;
703 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
704 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
705 <&clk IMX8MQ_CLK_GPU_AXI>,
706 <&clk IMX8MQ_CLK_GPU_AHB>;
707 };
708
709 pgc_vpu: power-domain@6 {
710 #power-domain-cells = <0>;
711 reg = <IMX8M_POWER_DOMAIN_VPU>;
36cebead 712 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
fdbcc04d
LS		 713 };
714
715 pgc_disp: power-domain@7 {
716 #power-domain-cells = <0>;
717 reg = <IMX8M_POWER_DOMAIN_DISP>;
718 };
719
720 pgc_mipi_csi1: power-domain@8 {
721 #power-domain-cells = <0>;
722 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
723 };
724
725 pgc_mipi_csi2: power-domain@9 {
726 #power-domain-cells = <0>;
727 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
728 };
729
730 pgc_pcie2: power-domain@a {
731 #power-domain-cells = <0>;
732 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
733 };
734 };
735 };
748f908c
LS		 736 };
737
738 bus@30400000 { /* AIPS2 */
dc3efc6f 739 compatible = "fsl,aips-bus", "simple-bus";
921a6845 740 reg = <0x30400000 0x400000>;
748f908c
LS		 741 #address-cells = <1>;
742 #size-cells = <1>;
743 ranges = <0x30400000 0x30400000 0x400000>;
a0e046e6
GG		 744
745 pwm1: pwm@30660000 {
746 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
747 reg = <0x30660000 0x10000>;
748 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
750 <&clk IMX8MQ_CLK_PWM1_ROOT>;
751 clock-names = "ipg", "per";
752 #pwm-cells = <2>;
d3a2d72b
BS		 753 status = "disabled";
754 };
755
a0e046e6
GG		 756 pwm2: pwm@30670000 {
757 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
758 reg = <0x30670000 0x10000>;
759 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
761 <&clk IMX8MQ_CLK_PWM2_ROOT>;
762 clock-names = "ipg", "per";
763 #pwm-cells = <2>;
d3a2d72b
BS		 764 status = "disabled";
765 };
766
a0e046e6
GG		 767 pwm3: pwm@30680000 {
768 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
769 reg = <0x30680000 0x10000>;
770 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
772 <&clk IMX8MQ_CLK_PWM3_ROOT>;
773 clock-names = "ipg", "per";
774 #pwm-cells = <2>;
d3a2d72b
BS		 775 status = "disabled";
776 };
748f908c 777
a0e046e6
GG		 778 pwm4: pwm@30690000 {
779 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
780 reg = <0x30690000 0x10000>;
781 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
783 <&clk IMX8MQ_CLK_PWM4_ROOT>;
784 clock-names = "ipg", "per";
785 #pwm-cells = <2>;
786 status = "disabled";
787 };
24e8a5db
AH		 788
789 system_counter: timer@306a0000 {
790 compatible = "nxp,sysctr-timer";
791 reg = <0x306a0000 0x20000>;
792 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&osc_25m>;
794 clock-names = "per";
795 };
748f908c
LS		 796 };
797
798 bus@30800000 { /* AIPS3 */
dc3efc6f 799 compatible = "fsl,aips-bus", "simple-bus";
921a6845 800 reg = <0x30800000 0x400000>;
748f908c
LS		 801 #address-cells = <1>;
802 #size-cells = <1>;
39f1622b
CC		 803 ranges = <0x30800000 0x30800000 0x400000>,
804 <0x08000000 0x08000000 0x10000000>;
748f908c 805
08a1a2e2
SW		 806 spdif1: spdif@30810000 {
807 compatible = "fsl,imx35-spdif";
808 reg = <0x30810000 0x10000>;
809 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
811 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
812 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
813 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
814 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
815 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
816 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
817 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
818 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
819 <&clk IMX8MQ_CLK_DUMMY>; /* spba */
820 clock-names = "core", "rxtx0",
821 "rxtx1", "rxtx2",
822 "rxtx3", "rxtx4",
823 "rxtx5", "rxtx6",
824 "rxtx7", "spba";
825 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
826 dma-names = "rx", "tx";
827 status = "disabled";
828 };
829
85761f45
FE		 830 ecspi1: spi@30820000 {
831 #address-cells = <1>;
832 #size-cells = <0>;
833 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
834 reg = <0x30820000 0x10000>;
835 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
837 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
838 clock-names = "ipg", "per";
8b6b1754
FE		 839 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
840 dma-names = "rx", "tx";
85761f45
FE		 841 status = "disabled";
842 };
843
844 ecspi2: spi@30830000 {
845 #address-cells = <1>;
846 #size-cells = <0>;
847 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
848 reg = <0x30830000 0x10000>;
849 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
851 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
852 clock-names = "ipg", "per";
8b6b1754
FE		 853 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
854 dma-names = "rx", "tx";
85761f45
FE		 855 status = "disabled";
856 };
857
858 ecspi3: spi@30840000 {
859 #address-cells = <1>;
860 #size-cells = <0>;
861 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
862 reg = <0x30840000 0x10000>;
863 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
865 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
866 clock-names = "ipg", "per";
8b6b1754
FE		 867 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
868 dma-names = "rx", "tx";
85761f45
FE		 869 status = "disabled";
870 };
748f908c
LS		 871
872 uart1: serial@30860000 {
873 compatible = "fsl,imx8mq-uart",
874 "fsl,imx6q-uart";
875 reg = <0x30860000 0x10000>;
876 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
878 <&clk IMX8MQ_CLK_UART1_ROOT>;
879 clock-names = "ipg", "per";
880 status = "disabled";
881 };
882
883 uart3: serial@30880000 {
884 compatible = "fsl,imx8mq-uart",
885 "fsl,imx6q-uart";
886 reg = <0x30880000 0x10000>;
887 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
889 <&clk IMX8MQ_CLK_UART3_ROOT>;
890 clock-names = "ipg", "per";
891 status = "disabled";
892 };
893
894 uart2: serial@30890000 {
895 compatible = "fsl,imx8mq-uart",
896 "fsl,imx6q-uart";
897 reg = <0x30890000 0x10000>;
898 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
900 <&clk IMX8MQ_CLK_UART2_ROOT>;
901 clock-names = "ipg", "per";
902 status = "disabled";
903 };
904
08a1a2e2
SW		 905 spdif2: spdif@308a0000 {
906 compatible = "fsl,imx35-spdif";
907 reg = <0x308a0000 0x10000>;
908 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
910 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
911 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
912 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
913 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
914 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
915 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
916 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
917 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
918 <&clk IMX8MQ_CLK_DUMMY>; /* spba */
919 clock-names = "core", "rxtx0",
920 "rxtx1", "rxtx2",
921 "rxtx3", "rxtx4",
922 "rxtx5", "rxtx6",
923 "rxtx7", "spba";
924 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
925 dma-names = "rx", "tx";
926 status = "disabled";
927 };
928
8c61538d
DB		 929 sai2: sai@308b0000 {
930 #sound-dai-cells = <0>;
8d014847 931 compatible = "fsl,imx8mq-sai";
8c61538d
DB		 932 reg = <0x308b0000 0x10000>;
933 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
935 <&clk IMX8MQ_CLK_SAI2_ROOT>,
936 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
937 clock-names = "bus", "mclk1", "mclk2", "mclk3";
938 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
939 dma-names = "rx", "tx";
940 status = "disabled";
941 };
942
fcb1991c
LS		 943 sai3: sai@308c0000 {
944 #sound-dai-cells = <0>;
945 compatible = "fsl,imx8mq-sai";
946 reg = <0x308c0000 0x10000>;
947 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
949 <&clk IMX8MQ_CLK_SAI3_ROOT>,
950 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
951 clock-names = "bus", "mclk1", "mclk2", "mclk3";
952 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
953 dma-names = "rx", "tx";
954 status = "disabled";
955 };
956
007b3cf0
AS		 957 crypto: crypto@30900000 {
958 compatible = "fsl,sec-v4.0";
959 #address-cells = <1>;
960 #size-cells = <1>;
961 reg = <0x30900000 0x40000>;
962 ranges = <0 0x30900000 0x40000>;
963 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&clk IMX8MQ_CLK_AHB>,
965 <&clk IMX8MQ_CLK_IPG_ROOT>;
966 clock-names = "aclk", "ipg";
967
968 sec_jr0: jr@1000 {
969 compatible = "fsl,sec-v4.0-job-ring";
970 reg = <0x1000 0x1000>;
971 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
972 };
973
974 sec_jr1: jr@2000 {
975 compatible = "fsl,sec-v4.0-job-ring";
976 reg = <0x2000 0x1000>;
977 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
978 };
979
980 sec_jr2: jr@3000 {
981 compatible = "fsl,sec-v4.0-job-ring";
982 reg = <0x3000 0x1000>;
983 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
984 };
985 };
986
d0081bd0
GG		 987 mipi_dsi: mipi-dsi@30a00000 {
988 compatible = "fsl,imx8mq-nwl-dsi";
989 reg = <0x30a00000 0x300>;
990 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
991 <&clk IMX8MQ_CLK_DSI_AHB>,
992 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
993 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
994 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
995 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
996 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
997 <&clk IMX8MQ_CLK_DSI_CORE>,
998 <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
999 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1000 <&clk IMX8MQ_SYS1_PLL_266M>;
1001 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1002 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1003 mux-controls = <&mux 0>;
1004 power-domains = <&pgc_mipi>;
1005 phys = <&dphy>;
1006 phy-names = "dphy";
1007 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
1008 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
1009 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
1010 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
1011 reset-names = "byte", "dpi", "esc", "pclk";
1012 status = "disabled";
1013
1014 ports {
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017
1018 port@0 {
1019 reg = <0>;
1020 #address-cells = <1>;
1021 #size-cells = <0>;
1022 mipi_dsi_lcdif_in: endpoint@0 {
1023 reg = <0>;
1024 remote-endpoint = <&lcdif_mipi_dsi>;
1025 };
1026 };
1027 };
1028 };
1029
a99b26b1
GG		 1030 dphy: dphy@30a00300 {
1031 compatible = "fsl,imx8mq-mipi-dphy";
1032 reg = <0x30a00300 0x100>;
1033 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
1034 clock-names = "phy_ref";
62270eeb
GG		 1035 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1036 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
1037 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1038 <&clk IMX8MQ_VIDEO_PLL1>;
1039 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1040 <&clk IMX8MQ_VIDEO_PLL1>,
1041 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
1042 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
a99b26b1
GG		 1043 #phy-cells = <0>;
1044 power-domains = <&pgc_mipi>;
1045 status = "disabled";
1046 };
1047
748f908c
LS		 1048 i2c1: i2c@30a20000 {
1049 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1050 reg = <0x30a20000 0x10000>;
1051 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055 status = "disabled";
1056 };
1057
1058 i2c2: i2c@30a30000 {
1059 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1060 reg = <0x30a30000 0x10000>;
1061 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 status = "disabled";
1066 };
1067
1068 i2c3: i2c@30a40000 {
1069 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1070 reg = <0x30a40000 0x10000>;
1071 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1075 status = "disabled";
1076 };
1077
1078 i2c4: i2c@30a50000 {
1079 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1080 reg = <0x30a50000 0x10000>;
1081 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 status = "disabled";
1086 };
1087
1088 uart4: serial@30a60000 {
1089 compatible = "fsl,imx8mq-uart",
1090 "fsl,imx6q-uart";
1091 reg = <0x30a60000 0x10000>;
1092 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
1094 <&clk IMX8MQ_CLK_UART4_ROOT>;
1095 clock-names = "ipg", "per";
1096 status = "disabled";
1097 };
1098
bcadd5f6
MK		 1099 mipi_csi1: csi@30a70000 {
1100 compatible = "fsl,imx8mq-mipi-csi2";
1101 reg = <0x30a70000 0x1000>;
1102 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1103 <&clk IMX8MQ_CLK_CSI1_ESC>,
1104 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
1105 clock-names = "core", "esc", "ui";
1106 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1107 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
1108 <&clk IMX8MQ_CLK_CSI1_ESC>;
1109 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1110 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1111 <&clk IMX8MQ_SYS2_PLL_1000M>,
1112 <&clk IMX8MQ_SYS1_PLL_800M>;
1113 power-domains = <&pgc_mipi_csi1>;
1114 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
1115 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
1116 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
1117 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1118 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
1119 interconnect-names = "dram";
1120 status = "disabled";
1121
1122 ports {
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125
1126 port@0 {
1127 reg = <0>;
1128
1129 csi1_mipi_ep: endpoint {
1130 remote-endpoint = <&csi1_ep>;
1131 };
1132 };
1133 };
1134 };
1135
1136 csi1: csi@30a90000 {
1137 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1138 reg = <0x30a90000 0x10000>;
1139 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
1141 clock-names = "mclk";
1142 status = "disabled";
1143
1144 port {
1145 csi1_ep: endpoint {
1146 remote-endpoint = <&csi1_mipi_ep>;
1147 };
1148 };
1149 };
1150
1151 mipi_csi2: csi@30b60000 {
1152 compatible = "fsl,imx8mq-mipi-csi2";
1153 reg = <0x30b60000 0x1000>;
1154 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1155 <&clk IMX8MQ_CLK_CSI2_ESC>,
1156 <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
1157 clock-names = "core", "esc", "ui";
1158 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1159 <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
1160 <&clk IMX8MQ_CLK_CSI2_ESC>;
1161 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1162 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1163 <&clk IMX8MQ_SYS2_PLL_1000M>,
1164 <&clk IMX8MQ_SYS1_PLL_800M>;
1165 power-domains = <&pgc_mipi_csi2>;
1166 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
1167 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
1168 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
1169 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1170 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
1171 interconnect-names = "dram";
1172 status = "disabled";
1173
1174 ports {
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177
1178 port@0 {
1179 reg = <0>;
1180
1181 csi2_mipi_ep: endpoint {
1182 remote-endpoint = <&csi2_ep>;
1183 };
1184 };
1185 };
1186 };
1187
1188 csi2: csi@30b80000 {
1189 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1190 reg = <0x30b80000 0x10000>;
1191 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1192 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
1193 clock-names = "mclk";
1194 status = "disabled";
1195
1196 port {
1197 csi2_ep: endpoint {
1198 remote-endpoint = <&csi2_mipi_ep>;
1199 };
1200 };
1201 };
1202
bbfc59be
PF		 1203 mu: mailbox@30aa0000 {
1204 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1205 reg = <0x30aa0000 0x10000>;
1206 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
1208 #mbox-cells = <2>;
1209 };
1210
748f908c
LS		 1211 usdhc1: mmc@30b40000 {
1212 compatible = "fsl,imx8mq-usdhc",
1213 "fsl,imx7d-usdhc";
1214 reg = <0x30b40000 0x10000>;
1215 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
b0759297 1216 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
748f908c
LS		 1217 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1218 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
1219 clock-names = "ipg", "ahb", "per";
1220 fsl,tuning-start-tap = <20>;
1221 fsl,tuning-step = <2>;
1222 bus-width = <4>;
1223 status = "disabled";
1224 };
1225
1226 usdhc2: mmc@30b50000 {
1227 compatible = "fsl,imx8mq-usdhc",
1228 "fsl,imx7d-usdhc";
1229 reg = <0x30b50000 0x10000>;
1230 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
b0759297 1231 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
748f908c
LS		 1232 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1233 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
1234 clock-names = "ipg", "ahb", "per";
1235 fsl,tuning-start-tap = <20>;
1236 fsl,tuning-step = <2>;
1237 bus-width = <4>;
1238 status = "disabled";
1239 };
1240
39f1622b
CC		 1241 qspi0: spi@30bb0000 {
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1244 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1245 reg = <0x30bb0000 0x10000>,
1246 <0x08000000 0x10000000>;
1247 reg-names = "QuadSPI", "QuadSPI-memory";
1248 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1250 <&clk IMX8MQ_CLK_QSPI_ROOT>;
1251 clock-names = "qspi_en", "qspi";
1252 status = "disabled";
1253 };
1254
1474d48b 1255 sdma1: sdma@30bd0000 {
b6c846b9 1256 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1474d48b
DB		 1257 reg = <0x30bd0000 0x10000>;
1258 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1259 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
7240d7d4 1260 <&clk IMX8MQ_CLK_AHB>;
1474d48b
DB		 1261 clock-names = "ipg", "ahb";
1262 #dma-cells = <3>;
1263 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1264 };
1265
748f908c
LS		 1266 fec1: ethernet@30be0000 {
1267 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1268 reg = <0x30be0000 0x10000>;
1269 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 1271 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
748f908c
LS		 1273 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1274 <&clk IMX8MQ_CLK_ENET1_ROOT>,
1275 <&clk IMX8MQ_CLK_ENET_TIMER>,
1276 <&clk IMX8MQ_CLK_ENET_REF>,
1277 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1278 clock-names = "ipg", "ahb", "ptp",
1279 "enet_clk_ref", "enet_out";
6c17f2d6
JZ		 1280 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1281 <&clk IMX8MQ_CLK_ENET_TIMER>,
1282 <&clk IMX8MQ_CLK_ENET_REF>,
1283 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1284 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1285 <&clk IMX8MQ_SYS2_PLL_100M>,
1286 <&clk IMX8MQ_SYS2_PLL_125M>,
1287 <&clk IMX8MQ_SYS2_PLL_50M>;
1288 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
748f908c
LS		 1289 fsl,num-tx-queues = <3>;
1290 fsl,num-rx-queues = <3>;
066438ae
JZ		 1291 nvmem-cells = <&fec_mac_address>;
1292 nvmem-cell-names = "mac-address";
1293 nvmem_macaddr_swap;
afe99354 1294 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
748f908c
LS		 1295 status = "disabled";
1296 };
1297 };
1298
f18e6d57
LC		 1299 noc: interconnect@32700000 {
1300 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1301 reg = <0x32700000 0x100000>;
1302 clocks = <&clk IMX8MQ_CLK_NOC>;
1303 fsl,ddrc = <&ddrc>;
20cf8d98 1304 #interconnect-cells = <1>;
f18e6d57
LC		 1305 operating-points-v2 = <&noc_opp_table>;
1306
1307 noc_opp_table: opp-table {
1308 compatible = "operating-points-v2";
1309
1310 opp-133M {
1311 opp-hz = /bits/ 64 <133333333>;
1312 };
1313
1314 opp-400M {
1315 opp-hz = /bits/ 64 <400000000>;
1316 };
1317
1318 opp-800M {
1319 opp-hz = /bits/ 64 <800000000>;
1320 };
1321 };
1322 };
1323
4af3cfe4 1324 bus@32c00000 { /* AIPS4 */
dc3efc6f 1325 compatible = "fsl,aips-bus", "simple-bus";
921a6845 1326 reg = <0x32c00000 0x400000>;
4af3cfe4
GG		 1327 #address-cells = <1>;
1328 #size-cells = <1>;
1329 ranges = <0x32c00000 0x32c00000 0x400000>;
1330
1331 irqsteer: interrupt-controller@32e2d000 {
1332 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1333 reg = <0x32e2d000 0x1000>;
1334 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1336 clock-names = "ipg";
1337 fsl,channel = <0>;
1338 fsl,num-irqs = <64>;
1339 interrupt-controller;
1340 #interrupt-cells = <1>;
1341 };
1342 };
1343
45d2c84e
LS		 1344 gpu: gpu@38000000 {
1345 compatible = "vivante,gc";
1346 reg = <0x38000000 0x40000>;
1347 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1348 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1349 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1350 <&clk IMX8MQ_CLK_GPU_AXI>,
1351 <&clk IMX8MQ_CLK_GPU_AHB>;
1352 clock-names = "core", "shader", "bus", "reg";
9404f2ea 1353 #cooling-cells = <2>;
45d2c84e
LS		 1354 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1355 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1356 <&clk IMX8MQ_CLK_GPU_AXI>,
ade5a57e
LS		 1357 <&clk IMX8MQ_CLK_GPU_AHB>,
1358 <&clk IMX8MQ_GPU_PLL_BYPASS>;
45d2c84e
LS		 1359 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1360 <&clk IMX8MQ_GPU_PLL_OUT>,
1361 <&clk IMX8MQ_GPU_PLL_OUT>,
ade5a57e
LS		 1362 <&clk IMX8MQ_GPU_PLL_OUT>,
1363 <&clk IMX8MQ_GPU_PLL>;
45d2c84e 1364 assigned-clock-rates = <800000000>, <800000000>,
ade5a57e 1365 <800000000>, <800000000>, <0>;
45d2c84e
LS		 1366 power-domains = <&pgc_gpu>;
1367 };
1368
ad37549c
LS		 1369 usb_dwc3_0: usb@38100000 {
1370 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1371 reg = <0x38100000 0x10000>;
74bd5951 1372 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
ad37549c 1373 <&clk IMX8MQ_CLK_USB_CORE_REF>,
74bd5951 1374 <&clk IMX8MQ_CLK_32K>;
ad37549c
LS		 1375 clock-names = "bus_early", "ref", "suspend";
1376 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1377 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1378 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1379 <&clk IMX8MQ_SYS1_PLL_100M>;
1380 assigned-clock-rates = <500000000>, <100000000>;
1381 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1382 phys = <&usb3_phy0>, <&usb3_phy0>;
1383 phy-names = "usb2-phy", "usb3-phy";
1384 power-domains = <&pgc_otg1>;
1385 usb3-resume-missing-cas;
1386 status = "disabled";
1387 };
1388
1389 usb3_phy0: usb-phy@381f0040 {
1390 compatible = "fsl,imx8mq-usb-phy";
1391 reg = <0x381f0040 0x40>;
1392 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1393 clock-names = "phy";
1394 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1395 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1396 assigned-clock-rates = <100000000>;
1397 #phy-cells = <0>;
1398 status = "disabled";
1399 };
1400
1401 usb_dwc3_1: usb@38200000 {
1402 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1403 reg = <0x38200000 0x10000>;
74bd5951 1404 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
ad37549c 1405 <&clk IMX8MQ_CLK_USB_CORE_REF>,
74bd5951 1406 <&clk IMX8MQ_CLK_32K>;
ad37549c
LS		 1407 clock-names = "bus_early", "ref", "suspend";
1408 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1409 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1410 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1411 <&clk IMX8MQ_SYS1_PLL_100M>;
1412 assigned-clock-rates = <500000000>, <100000000>;
1413 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1414 phys = <&usb3_phy1>, <&usb3_phy1>;
1415 phy-names = "usb2-phy", "usb3-phy";
1416 power-domains = <&pgc_otg2>;
1417 usb3-resume-missing-cas;
1418 status = "disabled";
1419 };
1420
1421 usb3_phy1: usb-phy@382f0040 {
1422 compatible = "fsl,imx8mq-usb-phy";
1423 reg = <0x382f0040 0x40>;
1424 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1425 clock-names = "phy";
1426 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1427 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1428 assigned-clock-rates = <100000000>;
1429 #phy-cells = <0>;
1430 status = "disabled";
1431 };
1432
36cebead
PZ		 1433 vpu: video-codec@38300000 {
1434 compatible = "nxp,imx8mq-vpu";
1435 reg = <0x38300000 0x10000>,
1436 <0x38310000 0x10000>,
1437 <0x38320000 0x10000>;
1438 reg-names = "g1", "g2", "ctrl";
1439 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1441 interrupt-names = "g1", "g2";
1442 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1443 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
1444 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
1445 clock-names = "g1", "g2", "bus";
1446 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
1447 <&clk IMX8MQ_CLK_VPU_G2>,
1448 <&clk IMX8MQ_CLK_VPU_BUS>,
1449 <&clk IMX8MQ_VPU_PLL_BYPASS>;
1450 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
1451 <&clk IMX8MQ_VPU_PLL_OUT>,
1452 <&clk IMX8MQ_SYS1_PLL_800M>,
1453 <&clk IMX8MQ_VPU_PLL>;
1454 assigned-clock-rates = <600000000>, <600000000>,
1455 <800000000>, <0>;
1456 power-domains = <&pgc_vpu>;
1457 };
1458
fc26e600
AS		 1459 pcie0: pcie@33800000 {
1460 compatible = "fsl,imx8mq-pcie";
1461 reg = <0x33800000 0x400000>,
1462 <0x1ff00000 0x80000>;
1463 reg-names = "dbi", "config";
1464 #address-cells = <3>;
1465 #size-cells = <2>;
1466 device_type = "pci";
1467 bus-range = <0x00 0xff>;
c179ee1e
RZ		 1468 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1469 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
fc26e600 1470 num-lanes = <1>;
fc26e600
AS		 1471 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1472 interrupt-names = "msi";
1473 #interrupt-cells = <1>;
1474 interrupt-map-mask = <0 0 0 0x7>;
1475 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1476 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1477 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1478 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1479 fsl,max-link-speed = <2>;
c0b70f05 1480 linux,pci-domain = <0>;
fc26e600
AS		 1481 power-domains = <&pgc_pcie>;
1482 resets = <&src IMX8MQ_RESET_PCIEPHY>,
1483 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1484 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1485 reset-names = "pciephy", "apps", "turnoff";
15a5261e
LS		 1486 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1487 <&clk IMX8MQ_CLK_PCIE1_PHY>,
1488 <&clk IMX8MQ_CLK_PCIE1_AUX>;
1489 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1490 <&clk IMX8MQ_SYS2_PLL_100M>,
1491 <&clk IMX8MQ_SYS1_PLL_80M>;
1492 assigned-clock-rates = <250000000>, <100000000>,
1493 <10000000>;
fc26e600
AS		 1494 status = "disabled";
1495 };
1496
1497 pcie1: pcie@33c00000 {
1498 compatible = "fsl,imx8mq-pcie";
1499 reg = <0x33c00000 0x400000>,
1500 <0x27f00000 0x80000>;
1501 reg-names = "dbi", "config";
1502 #address-cells = <3>;
1503 #size-cells = <2>;
1504 device_type = "pci";
c179ee1e
RZ		 1505 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
1506 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
fc26e600 1507 num-lanes = <1>;
fc26e600
AS		 1508 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1509 interrupt-names = "msi";
1510 #interrupt-cells = <1>;
1511 interrupt-map-mask = <0 0 0 0x7>;
1512 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1513 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1514 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1515 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1516 fsl,max-link-speed = <2>;
c0b70f05 1517 linux,pci-domain = <1>;
fc26e600
AS		 1518 power-domains = <&pgc_pcie>;
1519 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1520 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1521 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1522 reset-names = "pciephy", "apps", "turnoff";
15a5261e
LS		 1523 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1524 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1525 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1526 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1527 <&clk IMX8MQ_SYS2_PLL_100M>,
1528 <&clk IMX8MQ_SYS1_PLL_80M>;
1529 assigned-clock-rates = <250000000>, <100000000>,
1530 <10000000>;
fc26e600
AS		 1531 status = "disabled";
1532 };
1533
748f908c
LS		 1534 gic: interrupt-controller@38800000 {
1535 compatible = "arm,gic-v3";
1536 reg = <0x38800000 0x10000>, /* GIC Dist */
1537 <0x38880000 0xc0000>, /* GICR */
1538 <0x31000000 0x2000>, /* GICC */
1539 <0x31010000 0x2000>, /* GICV */
1540 <0x31020000 0x2000>; /* GICH */
1541 #interrupt-cells = <3>;
1542 interrupt-controller;
1543 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1544 interrupt-parent = <&gic>;
1545 };
1efe85c9 1546
0376f6ec
LC		 1547 ddrc: memory-controller@3d400000 {
1548 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1549 reg = <0x3d400000 0x400000>;
1550 clock-names = "core", "pll", "alt", "apb";
1551 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1552 <&clk IMX8MQ_DRAM_PLL_OUT>,
1553 <&clk IMX8MQ_CLK_DRAM_ALT>,
1554 <&clk IMX8MQ_CLK_DRAM_APB>;
1555 };
1556
1efe85c9
LC		 1557 ddr-pmu@3d800000 {
1558 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1559 reg = <0x3d800000 0x400000>;
1560 interrupt-parent = <&gic>;
1561 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1562 };
748f908c
LS		 1563 };
1564};
Linux 6.x block layer and io_uring tree(s)