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usb: dwc3: core: add gfladj_refclk_lpm_sel quirk
[linux-block.git] / arch / arm64 / boot / dts / freescale / imx8mp.dtsi
CommitLineData
6d9b8d20
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mp-clock.h>
fc0f0512 7#include <dt-bindings/power/imx8mp-power.h>
6d9b8d20
AH		 8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
30cdd62d 11#include <dt-bindings/thermal/thermal.h>
6d9b8d20
AH		 12
13#include "imx8mp-pinfunc.h"
14
15/ {
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &fec;
ec4d1196 22 ethernet1 = &eqos;
6d9b8d20
AH		 23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
ac4af2b1
PF		 28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 i2c4 = &i2c5;
33 i2c5 = &i2c6;
6d9b8d20
AH		 34 mmc0 = &usdhc1;
35 mmc1 = &usdhc2;
36 mmc2 = &usdhc3;
37 serial0 = &uart1;
38 serial1 = &uart2;
39 serial2 = &uart3;
40 serial3 = &uart4;
6914d1ba 41 spi0 = &flexspi;
6d9b8d20
AH		 42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 A53_0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a53";
51 reg = <0x0>;
52 clock-latency = <61036>;
53 clocks = <&clk IMX8MP_CLK_ARM>;
54 enable-method = "psci";
cb551b5e
PF		 55 i-cache-size = <0x8000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <256>;
58 d-cache-size = <0x8000>;
59 d-cache-line-size = <64>;
60 d-cache-sets = <128>;
6d9b8d20 61 next-level-cache = <&A53_L2>;
9ad9773e
MV		 62 nvmem-cells = <&cpu_speed_grade>;
63 nvmem-cell-names = "speed_grade";
21a14c68 64 operating-points-v2 = <&a53_opp_table>;
30cdd62d 65 #cooling-cells = <2>;
6d9b8d20
AH		 66 };
67
68 A53_1: cpu@1 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a53";
71 reg = <0x1>;
72 clock-latency = <61036>;
73 clocks = <&clk IMX8MP_CLK_ARM>;
74 enable-method = "psci";
cb551b5e
PF		 75 i-cache-size = <0x8000>;
76 i-cache-line-size = <64>;
77 i-cache-sets = <256>;
78 d-cache-size = <0x8000>;
79 d-cache-line-size = <64>;
80 d-cache-sets = <128>;
6d9b8d20 81 next-level-cache = <&A53_L2>;
21a14c68 82 operating-points-v2 = <&a53_opp_table>;
30cdd62d 83 #cooling-cells = <2>;
6d9b8d20
AH		 84 };
85
86 A53_2: cpu@2 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a53";
89 reg = <0x2>;
90 clock-latency = <61036>;
91 clocks = <&clk IMX8MP_CLK_ARM>;
92 enable-method = "psci";
cb551b5e
PF		 93 i-cache-size = <0x8000>;
94 i-cache-line-size = <64>;
95 i-cache-sets = <256>;
96 d-cache-size = <0x8000>;
97 d-cache-line-size = <64>;
98 d-cache-sets = <128>;
6d9b8d20 99 next-level-cache = <&A53_L2>;
21a14c68 100 operating-points-v2 = <&a53_opp_table>;
30cdd62d 101 #cooling-cells = <2>;
6d9b8d20
AH		 102 };
103
104 A53_3: cpu@3 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a53";
107 reg = <0x3>;
108 clock-latency = <61036>;
109 clocks = <&clk IMX8MP_CLK_ARM>;
110 enable-method = "psci";
cb551b5e
PF		 111 i-cache-size = <0x8000>;
112 i-cache-line-size = <64>;
113 i-cache-sets = <256>;
114 d-cache-size = <0x8000>;
115 d-cache-line-size = <64>;
116 d-cache-sets = <128>;
6d9b8d20 117 next-level-cache = <&A53_L2>;
21a14c68 118 operating-points-v2 = <&a53_opp_table>;
30cdd62d 119 #cooling-cells = <2>;
6d9b8d20
AH		 120 };
121
122 A53_L2: l2-cache0 {
123 compatible = "cache";
cb551b5e
PF		 124 cache-level = <2>;
125 cache-size = <0x80000>;
126 cache-line-size = <64>;
127 cache-sets = <512>;
6d9b8d20
AH		 128 };
129 };
130
21a14c68
MV		 131 a53_opp_table: opp-table {
132 compatible = "operating-points-v2";
133 opp-shared;
134
135 opp-1200000000 {
136 opp-hz = /bits/ 64 <1200000000>;
137 opp-microvolt = <850000>;
138 opp-supported-hw = <0x8a0>, <0x7>;
139 clock-latency-ns = <150000>;
140 opp-suspend;
141 };
142
143 opp-1600000000 {
144 opp-hz = /bits/ 64 <1600000000>;
145 opp-microvolt = <950000>;
146 opp-supported-hw = <0xa0>, <0x7>;
147 clock-latency-ns = <150000>;
148 opp-suspend;
149 };
150
151 opp-1800000000 {
152 opp-hz = /bits/ 64 <1800000000>;
153 opp-microvolt = <1000000>;
154 opp-supported-hw = <0x20>, <0x3>;
155 clock-latency-ns = <150000>;
156 opp-suspend;
157 };
158 };
159
6d9b8d20
AH		 160 osc_32k: clock-osc-32k {
161 compatible = "fixed-clock";
162 #clock-cells = <0>;
163 clock-frequency = <32768>;
164 clock-output-names = "osc_32k";
165 };
166
167 osc_24m: clock-osc-24m {
168 compatible = "fixed-clock";
169 #clock-cells = <0>;
170 clock-frequency = <24000000>;
171 clock-output-names = "osc_24m";
172 };
173
174 clk_ext1: clock-ext1 {
175 compatible = "fixed-clock";
176 #clock-cells = <0>;
177 clock-frequency = <133000000>;
178 clock-output-names = "clk_ext1";
179 };
180
181 clk_ext2: clock-ext2 {
182 compatible = "fixed-clock";
183 #clock-cells = <0>;
184 clock-frequency = <133000000>;
185 clock-output-names = "clk_ext2";
186 };
187
188 clk_ext3: clock-ext3 {
189 compatible = "fixed-clock";
190 #clock-cells = <0>;
191 clock-frequency = <133000000>;
192 clock-output-names = "clk_ext3";
193 };
194
195 clk_ext4: clock-ext4 {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
33597c62 198 clock-frequency = <133000000>;
6d9b8d20
AH		 199 clock-output-names = "clk_ext4";
200 };
201
bc3ab388
DB		 202 reserved-memory {
203 #address-cells = <2>;
204 #size-cells = <2>;
205 ranges;
206
207 dsp_reserved: dsp@92400000 {
208 reg = <0 0x92400000 0 0x2000000>;
209 no-map;
210 };
211 };
212
0f109a31
JB		 213 pmu {
214 compatible = "arm,cortex-a53-pmu";
215 interrupts = <GIC_PPI 7
216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0f109a31
JB		 217 };
218
6d9b8d20
AH		 219 psci {
220 compatible = "arm,psci-1.0";
221 method = "smc";
222 };
223
30cdd62d
AH		 224 thermal-zones {
225 cpu-thermal {
226 polling-delay-passive = <250>;
227 polling-delay = <2000>;
228 thermal-sensors = <&tmu 0>;
229 trips {
230 cpu_alert0: trip0 {
231 temperature = <85000>;
232 hysteresis = <2000>;
233 type = "passive";
234 };
235
236 cpu_crit0: trip1 {
237 temperature = <95000>;
238 hysteresis = <2000>;
239 type = "critical";
240 };
241 };
242
243 cooling-maps {
244 map0 {
245 trip = <&cpu_alert0>;
246 cooling-device =
247 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
248 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
249 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
251 };
252 };
253 };
254
255 soc-thermal {
256 polling-delay-passive = <250>;
257 polling-delay = <2000>;
258 thermal-sensors = <&tmu 1>;
259 trips {
260 soc_alert0: trip0 {
261 temperature = <85000>;
262 hysteresis = <2000>;
263 type = "passive";
264 };
265
266 soc_crit0: trip1 {
267 temperature = <95000>;
268 hysteresis = <2000>;
269 type = "critical";
270 };
271 };
272
273 cooling-maps {
274 map0 {
275 trip = <&soc_alert0>;
276 cooling-device =
277 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
278 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
279 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
280 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
281 };
282 };
283 };
284 };
285
6d9b8d20
AH		 286 timer {
287 compatible = "arm,armv8-timer";
061883e6
KK		 288 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
289 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
290 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
291 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6d9b8d20
AH		 292 clock-frequency = <8000000>;
293 arm,no-tick-in-suspend;
294 };
295
fcdef92b 296 soc: soc@0 {
ce58459d 297 compatible = "fsl,imx8mp-soc", "simple-bus";
6d9b8d20
AH		 298 #address-cells = <1>;
299 #size-cells = <1>;
300 ranges = <0x0 0x0 0x0 0x3e000000>;
cbff2379
AG		 301 nvmem-cells = <&imx8mp_uid>;
302 nvmem-cell-names = "soc_unique_id";
6d9b8d20
AH		 303
304 aips1: bus@30000000 {
dc3efc6f 305 compatible = "fsl,aips-bus", "simple-bus";
921a6845 306 reg = <0x30000000 0x400000>;
6d9b8d20
AH		 307 #address-cells = <1>;
308 #size-cells = <1>;
309 ranges;
310
311 gpio1: gpio@30200000 {
312 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
313 reg = <0x30200000 0x10000>;
314 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 gpio-ranges = <&iomuxc 0 5 30>;
322 };
323
324 gpio2: gpio@30210000 {
325 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
326 reg = <0x30210000 0x10000>;
327 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 gpio-ranges = <&iomuxc 0 35 21>;
335 };
336
337 gpio3: gpio@30220000 {
338 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
339 reg = <0x30220000 0x10000>;
340 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
b764eb65 347 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
6d9b8d20
AH		 348 };
349
350 gpio4: gpio@30230000 {
351 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
352 reg = <0x30230000 0x10000>;
353 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
356 gpio-controller;
357 #gpio-cells = <2>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 gpio-ranges = <&iomuxc 0 82 32>;
361 };
362
363 gpio5: gpio@30240000 {
364 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
365 reg = <0x30240000 0x10000>;
366 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
369 gpio-controller;
370 #gpio-cells = <2>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 gpio-ranges = <&iomuxc 0 114 30>;
374 };
375
30cdd62d
AH		 376 tmu: tmu@30260000 {
377 compatible = "fsl,imx8mp-tmu";
378 reg = <0x30260000 0x10000>;
379 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
380 #thermal-sensor-cells = <1>;
381 };
382
6d9b8d20
AH		 383 wdog1: watchdog@30280000 {
384 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
385 reg = <0x30280000 0x10000>;
386 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
388 status = "disabled";
389 };
390
36133cb5
PF		 391 wdog2: watchdog@30290000 {
392 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
393 reg = <0x30290000 0x10000>;
394 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
396 status = "disabled";
397 };
398
399 wdog3: watchdog@302a0000 {
400 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
401 reg = <0x302a0000 0x10000>;
402 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
404 status = "disabled";
405 };
406
6d9b8d20
AH		 407 iomuxc: pinctrl@30330000 {
408 compatible = "fsl,imx8mp-iomuxc";
409 reg = <0x30330000 0x10000>;
410 };
411
412 gpr: iomuxc-gpr@30340000 {
413 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
414 reg = <0x30340000 0x10000>;
415 };
416
12fa1078 417 ocotp: efuse@30350000 {
f2fe45d5 418 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
6d9b8d20
AH		 419 reg = <0x30350000 0x10000>;
420 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
421 /* For nvmem subnodes */
422 #address-cells = <1>;
423 #size-cells = <1>;
424
cbff2379
AG		 425 imx8mp_uid: unique-id@420 {
426 reg = <0x8 0x8>;
427 };
428
6d9b8d20
AH		 429 cpu_speed_grade: speed-grade@10 {
430 reg = <0x10 4>;
431 };
066438ae
JZ		 432
433 eth_mac1: mac-address@90 {
434 reg = <0x90 6>;
435 };
44d0dfee
JZ		 436
437 eth_mac2: mac-address@96 {
438 reg = <0x96 6>;
439 };
6d9b8d20
AH		 440 };
441
442 anatop: anatop@30360000 {
443 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
444 "syscon";
445 reg = <0x30360000 0x10000>;
446 };
447
448 snvs: snvs@30370000 {
449 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
450 reg = <0x30370000 0x10000>;
451
452 snvs_rtc: snvs-rtc-lp {
453 compatible = "fsl,sec-v4.0-mon-rtc-lp";
454 regmap =<&snvs>;
455 offset = <0x34>;
456 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
459 clock-names = "snvs-rtc";
460 };
461
462 snvs_pwrkey: snvs-powerkey {
463 compatible = "fsl,sec-v4.0-pwrkey";
464 regmap = <&snvs>;
465 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
6c389f29
AH		 466 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
467 clock-names = "snvs-pwrkey";
6d9b8d20
AH		 468 linux,keycode = <KEY_POWER>;
469 wakeup-source;
470 status = "disabled";
471 };
472 };
473
474 clk: clock-controller@30380000 {
475 compatible = "fsl,imx8mp-ccm";
476 reg = <0x30380000 0x10000>;
477 #clock-cells = <1>;
478 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
479 <&clk_ext3>, <&clk_ext4>;
480 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
481 "clk_ext3", "clk_ext4";
9e6337e6
PF		 482 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
483 <&clk IMX8MP_CLK_A53_CORE>,
484 <&clk IMX8MP_CLK_NOC>,
6d9b8d20
AH		 485 <&clk IMX8MP_CLK_NOC_IO>,
486 <&clk IMX8MP_CLK_GIC>,
487 <&clk IMX8MP_CLK_AUDIO_AHB>,
488 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
6d9b8d20
AH		 489 <&clk IMX8MP_AUDIO_PLL1>,
490 <&clk IMX8MP_AUDIO_PLL2>;
9e6337e6
PF		 491 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
492 <&clk IMX8MP_ARM_PLL_OUT>,
493 <&clk IMX8MP_SYS_PLL2_1000M>,
6d9b8d20
AH		 494 <&clk IMX8MP_SYS_PLL1_800M>,
495 <&clk IMX8MP_SYS_PLL2_500M>,
496 <&clk IMX8MP_SYS_PLL1_800M>,
497 <&clk IMX8MP_SYS_PLL1_800M>;
9e6337e6
PF		 498 assigned-clock-rates = <0>, <0>,
499 <1000000000>,
6d9b8d20
AH		 500 <800000000>,
501 <500000000>,
502 <400000000>,
503 <800000000>,
6d9b8d20
AH		 504 <393216000>,
505 <361267200>;
506 };
455ae0c3
AH		 507
508 src: reset-controller@30390000 {
509 compatible = "fsl,imx8mp-src", "syscon";
510 reg = <0x30390000 0x10000>;
1641b234 511 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
455ae0c3
AH		 512 #reset-cells = <1>;
513 };
fc0f0512
LS		 514
515 gpc: gpc@303a0000 {
516 compatible = "fsl,imx8mp-gpc";
517 reg = <0x303a0000 0x1000>;
518 interrupt-parent = <&gic>;
519 interrupt-controller;
520 #interrupt-cells = <3>;
521
522 pgc {
523 #address-cells = <1>;
524 #size-cells = <0>;
525
9d89189d
LP		 526 pgc_mipi_phy1: power-domain@0 {
527 #power-domain-cells = <0>;
528 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
529 };
530
2ae42e0c
LS		 531 pgc_pcie_phy: power-domain@1 {
532 #power-domain-cells = <0>;
533 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
534 };
535
536 pgc_usb1_phy: power-domain@2 {
537 #power-domain-cells = <0>;
538 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
539 };
540
541 pgc_usb2_phy: power-domain@3 {
542 #power-domain-cells = <0>;
543 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
544 };
545
fc0f0512
LS		 546 pgc_gpu2d: power-domain@6 {
547 #power-domain-cells = <0>;
548 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
549 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
550 power-domains = <&pgc_gpumix>;
551 };
552
553 pgc_gpumix: power-domain@7 {
554 #power-domain-cells = <0>;
555 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
556 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
557 <&clk IMX8MP_CLK_GPU_AHB>;
558 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
559 <&clk IMX8MP_CLK_GPU_AHB>;
560 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
561 <&clk IMX8MP_SYS_PLL1_800M>;
562 assigned-clock-rates = <800000000>, <400000000>;
563 };
564
565 pgc_gpu3d: power-domain@9 {
566 #power-domain-cells = <0>;
567 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
568 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
569 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
570 power-domains = <&pgc_gpumix>;
571 };
2ae42e0c 572
9d89189d
LP		 573 pgc_mediamix: power-domain@10 {
574 #power-domain-cells = <0>;
575 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
576 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
577 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
578 };
579
580 pgc_mipi_phy2: power-domain@16 {
581 #power-domain-cells = <0>;
582 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
583 };
584
2ae42e0c
LS		 585 pgc_hsiomix: power-domains@17 {
586 #power-domain-cells = <0>;
587 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
588 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
589 <&clk IMX8MP_CLK_HSIO_ROOT>;
590 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
591 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
592 assigned-clock-rates = <500000000>;
593 };
9d89189d
LP		 594
595 pgc_ispdwp: power-domain@18 {
596 #power-domain-cells = <0>;
597 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
3fdd4ef4 598 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
9d89189d 599 };
fc0f0512
LS		 600 };
601 };
6d9b8d20
AH		 602 };
603
604 aips2: bus@30400000 {
dc3efc6f 605 compatible = "fsl,aips-bus", "simple-bus";
921a6845 606 reg = <0x30400000 0x400000>;
6d9b8d20
AH		 607 #address-cells = <1>;
608 #size-cells = <1>;
609 ranges;
610
611 pwm1: pwm@30660000 {
612 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
613 reg = <0x30660000 0x10000>;
614 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
616 <&clk IMX8MP_CLK_PWM1_ROOT>;
617 clock-names = "ipg", "per";
d80b9c84 618 #pwm-cells = <3>;
6d9b8d20
AH		 619 status = "disabled";
620 };
621
622 pwm2: pwm@30670000 {
623 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
624 reg = <0x30670000 0x10000>;
625 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
627 <&clk IMX8MP_CLK_PWM2_ROOT>;
628 clock-names = "ipg", "per";
d80b9c84 629 #pwm-cells = <3>;
6d9b8d20
AH		 630 status = "disabled";
631 };
632
633 pwm3: pwm@30680000 {
634 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
635 reg = <0x30680000 0x10000>;
636 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
638 <&clk IMX8MP_CLK_PWM3_ROOT>;
639 clock-names = "ipg", "per";
d80b9c84 640 #pwm-cells = <3>;
6d9b8d20
AH		 641 status = "disabled";
642 };
643
644 pwm4: pwm@30690000 {
645 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
646 reg = <0x30690000 0x10000>;
647 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
649 <&clk IMX8MP_CLK_PWM4_ROOT>;
650 clock-names = "ipg", "per";
d80b9c84 651 #pwm-cells = <3>;
6d9b8d20
AH		 652 status = "disabled";
653 };
fae58b1a
AH		 654
655 system_counter: timer@306a0000 {
656 compatible = "nxp,sysctr-timer";
657 reg = <0x306a0000 0x20000>;
658 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&osc_24m>;
660 clock-names = "per";
661 };
6d9b8d20
AH		 662 };
663
664 aips3: bus@30800000 {
dc3efc6f 665 compatible = "fsl,aips-bus", "simple-bus";
921a6845 666 reg = <0x30800000 0x400000>;
6d9b8d20
AH		 667 #address-cells = <1>;
668 #size-cells = <1>;
669 ranges;
670
671 ecspi1: spi@30820000 {
672 #address-cells = <1>;
673 #size-cells = <0>;
674 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
675 reg = <0x30820000 0x10000>;
676 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
678 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
679 clock-names = "ipg", "per";
680 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
681 dma-names = "rx", "tx";
682 status = "disabled";
683 };
684
685 ecspi2: spi@30830000 {
686 #address-cells = <1>;
687 #size-cells = <0>;
688 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
689 reg = <0x30830000 0x10000>;
690 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
692 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
693 clock-names = "ipg", "per";
694 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
695 dma-names = "rx", "tx";
696 status = "disabled";
697 };
698
699 ecspi3: spi@30840000 {
700 #address-cells = <1>;
701 #size-cells = <0>;
702 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
703 reg = <0x30840000 0x10000>;
704 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
706 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
707 clock-names = "ipg", "per";
708 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
709 dma-names = "rx", "tx";
710 status = "disabled";
711 };
712
713 uart1: serial@30860000 {
714 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
715 reg = <0x30860000 0x10000>;
716 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
718 <&clk IMX8MP_CLK_UART1_ROOT>;
719 clock-names = "ipg", "per";
720 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
721 dma-names = "rx", "tx";
722 status = "disabled";
723 };
724
725 uart3: serial@30880000 {
726 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
727 reg = <0x30880000 0x10000>;
728 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
730 <&clk IMX8MP_CLK_UART3_ROOT>;
731 clock-names = "ipg", "per";
732 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
733 dma-names = "rx", "tx";
734 status = "disabled";
735 };
736
737 uart2: serial@30890000 {
738 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
739 reg = <0x30890000 0x10000>;
740 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
742 <&clk IMX8MP_CLK_UART2_ROOT>;
743 clock-names = "ipg", "per";
a00f1fa6
MZ		 744 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
745 dma-names = "rx", "tx";
6d9b8d20
AH		 746 status = "disabled";
747 };
748
3a7d56b3 749 flexcan1: can@308c0000 {
f5d156c7 750 compatible = "fsl,imx8mp-flexcan";
3a7d56b3
JZ		 751 reg = <0x308c0000 0x10000>;
752 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
754 <&clk IMX8MP_CLK_CAN1_ROOT>;
755 clock-names = "ipg", "per";
756 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
757 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
758 assigned-clock-rates = <40000000>;
759 fsl,clk-source = /bits/ 8 <0>;
760 fsl,stop-mode = <&gpr 0x10 4>;
761 status = "disabled";
762 };
763
764 flexcan2: can@308d0000 {
f5d156c7 765 compatible = "fsl,imx8mp-flexcan";
3a7d56b3
JZ		 766 reg = <0x308d0000 0x10000>;
767 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
769 <&clk IMX8MP_CLK_CAN2_ROOT>;
770 clock-names = "ipg", "per";
771 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
772 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
773 assigned-clock-rates = <40000000>;
774 fsl,clk-source = /bits/ 8 <0>;
775 fsl,stop-mode = <&gpr 0x10 5>;
776 status = "disabled";
777 };
778
d3a719e3
HG		 779 crypto: crypto@30900000 {
780 compatible = "fsl,sec-v4.0";
781 #address-cells = <1>;
782 #size-cells = <1>;
783 reg = <0x30900000 0x40000>;
784 ranges = <0 0x30900000 0x40000>;
785 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clk IMX8MP_CLK_AHB>,
787 <&clk IMX8MP_CLK_IPG_ROOT>;
788 clock-names = "aclk", "ipg";
789
790 sec_jr0: jr@1000 {
791 compatible = "fsl,sec-v4.0-job-ring";
792 reg = <0x1000 0x1000>;
793 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
dc9c1ceb 794 status = "disabled";
d3a719e3
HG		 795 };
796
797 sec_jr1: jr@2000 {
798 compatible = "fsl,sec-v4.0-job-ring";
799 reg = <0x2000 0x1000>;
800 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
801 };
802
803 sec_jr2: jr@3000 {
804 compatible = "fsl,sec-v4.0-job-ring";
805 reg = <0x3000 0x1000>;
806 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
807 };
808 };
809
6d9b8d20
AH		 810 i2c1: i2c@30a20000 {
811 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
812 #address-cells = <1>;
813 #size-cells = <0>;
814 reg = <0x30a20000 0x10000>;
815 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
817 status = "disabled";
818 };
819
820 i2c2: i2c@30a30000 {
821 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
822 #address-cells = <1>;
823 #size-cells = <0>;
824 reg = <0x30a30000 0x10000>;
825 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
827 status = "disabled";
828 };
829
830 i2c3: i2c@30a40000 {
831 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
832 #address-cells = <1>;
833 #size-cells = <0>;
834 reg = <0x30a40000 0x10000>;
835 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
837 status = "disabled";
838 };
839
840 i2c4: i2c@30a50000 {
841 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
842 #address-cells = <1>;
843 #size-cells = <0>;
844 reg = <0x30a50000 0x10000>;
845 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
847 status = "disabled";
848 };
849
850 uart4: serial@30a60000 {
851 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
852 reg = <0x30a60000 0x10000>;
853 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
855 <&clk IMX8MP_CLK_UART4_ROOT>;
856 clock-names = "ipg", "per";
857 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
858 dma-names = "rx", "tx";
859 status = "disabled";
860 };
861
bbfc59be
PF		 862 mu: mailbox@30aa0000 {
863 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
864 reg = <0x30aa0000 0x10000>;
865 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
867 #mbox-cells = <2>;
868 };
869
bc3ab388
DB		 870 mu2: mailbox@30e60000 {
871 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
872 reg = <0x30e60000 0x10000>;
873 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
874 #mbox-cells = <2>;
875 status = "disabled";
876 };
877
6d9b8d20
AH		 878 i2c5: i2c@30ad0000 {
879 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
880 #address-cells = <1>;
881 #size-cells = <0>;
882 reg = <0x30ad0000 0x10000>;
883 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
885 status = "disabled";
886 };
887
888 i2c6: i2c@30ae0000 {
889 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
890 #address-cells = <1>;
891 #size-cells = <0>;
892 reg = <0x30ae0000 0x10000>;
893 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
895 status = "disabled";
896 };
897
898 usdhc1: mmc@30b40000 {
746a7241 899 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 900 reg = <0x30b40000 0x10000>;
901 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&clk IMX8MP_CLK_DUMMY>,
903 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
904 <&clk IMX8MP_CLK_USDHC1_ROOT>;
905 clock-names = "ipg", "ahb", "per";
906 fsl,tuning-start-tap = <20>;
33597c62 907 fsl,tuning-step = <2>;
6d9b8d20
AH		 908 bus-width = <4>;
909 status = "disabled";
910 };
911
912 usdhc2: mmc@30b50000 {
746a7241 913 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 914 reg = <0x30b50000 0x10000>;
915 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&clk IMX8MP_CLK_DUMMY>,
917 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
918 <&clk IMX8MP_CLK_USDHC2_ROOT>;
919 clock-names = "ipg", "ahb", "per";
920 fsl,tuning-start-tap = <20>;
33597c62 921 fsl,tuning-step = <2>;
6d9b8d20
AH		 922 bus-width = <4>;
923 status = "disabled";
924 };
925
926 usdhc3: mmc@30b60000 {
746a7241 927 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 928 reg = <0x30b60000 0x10000>;
929 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&clk IMX8MP_CLK_DUMMY>,
931 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
932 <&clk IMX8MP_CLK_USDHC3_ROOT>;
933 clock-names = "ipg", "ahb", "per";
934 fsl,tuning-start-tap = <20>;
33597c62 935 fsl,tuning-step = <2>;
6d9b8d20
AH		 936 bus-width = <4>;
937 status = "disabled";
938 };
939
6914d1ba
HS		 940 flexspi: spi@30bb0000 {
941 compatible = "nxp,imx8mp-fspi";
942 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
943 reg-names = "fspi_base", "fspi_mmap";
944 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
946 <&clk IMX8MP_CLK_QSPI_ROOT>;
d7cd7446 947 clock-names = "fspi_en", "fspi";
6914d1ba
HS		 948 assigned-clock-rates = <80000000>;
949 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
950 #address-cells = <1>;
951 #size-cells = <0>;
952 status = "disabled";
953 };
954
6d9b8d20
AH		 955 sdma1: dma-controller@30bd0000 {
956 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
957 reg = <0x30bd0000 0x10000>;
958 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
66138621 960 <&clk IMX8MP_CLK_AHB>;
6d9b8d20
AH		 961 clock-names = "ipg", "ahb";
962 #dma-cells = <3>;
963 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
964 };
965
966 fec: ethernet@30be0000 {
f9654d26 967 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
6d9b8d20
AH		 968 reg = <0x30be0000 0x10000>;
969 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 971 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6d9b8d20
AH		 973 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
974 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
975 <&clk IMX8MP_CLK_ENET_TIMER>,
976 <&clk IMX8MP_CLK_ENET_REF>,
977 <&clk IMX8MP_CLK_ENET_PHY_REF>;
978 clock-names = "ipg", "ahb", "ptp",
979 "enet_clk_ref", "enet_out";
980 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
981 <&clk IMX8MP_CLK_ENET_TIMER>,
982 <&clk IMX8MP_CLK_ENET_REF>,
70eacf42 983 <&clk IMX8MP_CLK_ENET_PHY_REF>;
6d9b8d20
AH		 984 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
985 <&clk IMX8MP_SYS_PLL2_100M>,
70eacf42
JZ		 986 <&clk IMX8MP_SYS_PLL2_125M>,
987 <&clk IMX8MP_SYS_PLL2_50M>;
988 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
6d9b8d20
AH		 989 fsl,num-tx-queues = <3>;
990 fsl,num-rx-queues = <3>;
066438ae
JZ		 991 nvmem-cells = <&eth_mac1>;
992 nvmem-cell-names = "mac-address";
afe99354 993 fsl,stop-mode = <&gpr 0x10 3>;
6d9b8d20
AH		 994 status = "disabled";
995 };
ec4d1196
MV		 996
997 eqos: ethernet@30bf0000 {
998 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
999 reg = <0x30bf0000 0x10000>;
77e5253d
JZ		 1000 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1002 interrupt-names = "macirq", "eth_wake_irq";
ec4d1196
MV		 1003 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1004 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1005 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1006 <&clk IMX8MP_CLK_ENET_QOS>;
1007 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1008 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1009 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1010 <&clk IMX8MP_CLK_ENET_QOS>;
1011 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1012 <&clk IMX8MP_SYS_PLL2_100M>,
1013 <&clk IMX8MP_SYS_PLL2_125M>;
1014 assigned-clock-rates = <0>, <100000000>, <125000000>;
44d0dfee
JZ		 1015 nvmem-cells = <&eth_mac2>;
1016 nvmem-cell-names = "mac-address";
ec4d1196
MV		 1017 intf_mode = <&gpr 0x4>;
1018 status = "disabled";
1019 };
6d9b8d20
AH		 1020 };
1021
d4ac6028
PF		 1022 noc: interconnect@32700000 {
1023 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1024 reg = <0x32700000 0x100000>;
1025 clocks = <&clk IMX8MP_CLK_NOC>;
1026 #interconnect-cells = <1>;
1027 operating-points-v2 = <&noc_opp_table>;
1028
1029 noc_opp_table: opp-table {
1030 compatible = "operating-points-v2";
1031
1032 opp-200M {
1033 opp-hz = /bits/ 64 <200000000>;
1034 };
1035
1036 opp-1000M {
1037 opp-hz = /bits/ 64 <1000000000>;
1038 };
1039 };
1040 };
1041
2ae42e0c
LS		 1042 aips4: bus@32c00000 {
1043 compatible = "fsl,aips-bus", "simple-bus";
1044 reg = <0x32c00000 0x400000>;
1045 #address-cells = <1>;
1046 #size-cells = <1>;
1047 ranges;
1048
29f440a7
PE		 1049 media_blk_ctrl: blk-ctrl@32ec0000 {
1050 compatible = "fsl,imx8mp-media-blk-ctrl",
1051 "syscon";
1052 reg = <0x32ec0000 0x10000>;
1053 power-domains = <&pgc_mediamix>,
1054 <&pgc_mipi_phy1>,
1055 <&pgc_mipi_phy1>,
1056 <&pgc_mediamix>,
1057 <&pgc_mediamix>,
1058 <&pgc_mipi_phy2>,
1059 <&pgc_mediamix>,
1060 <&pgc_ispdwp>,
1061 <&pgc_ispdwp>,
1062 <&pgc_mipi_phy2>;
1063 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1064 "lcdif1", "isi", "mipi-csi2",
1065 "lcdif2", "isp", "dwe",
1066 "mipi-dsi2";
1067 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1068 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1069 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1070 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1071 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1072 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1073 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1074 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1075 clock-names = "apb", "axi", "cam1", "cam2",
1076 "disp1", "disp2", "isp", "phy";
1077
1078 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1079 <&clk IMX8MP_CLK_MEDIA_APB>;
1080 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1081 <&clk IMX8MP_SYS_PLL1_800M>;
1082 assigned-clock-rates = <500000000>, <200000000>;
1083
1084 #power-domain-cells = <1>;
1085 };
1086
2ae42e0c
LS		 1087 hsio_blk_ctrl: blk-ctrl@32f10000 {
1088 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1089 reg = <0x32f10000 0x24>;
1090 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1091 <&clk IMX8MP_CLK_PCIE_ROOT>;
1092 clock-names = "usb", "pcie";
1093 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1094 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1095 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1096 power-domain-names = "bus", "usb", "usb-phy1",
1097 "usb-phy2", "pcie", "pcie-phy";
1098 #power-domain-cells = <1>;
1099 };
1100 };
1101
4bdb1192
LS		 1102 gpu3d: gpu@38000000 {
1103 compatible = "vivante,gc";
1104 reg = <0x38000000 0x8000>;
1105 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1107 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1108 <&clk IMX8MP_CLK_GPU_ROOT>,
1109 <&clk IMX8MP_CLK_GPU_AHB>;
1110 clock-names = "core", "shader", "bus", "reg";
1111 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1112 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1113 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1114 <&clk IMX8MP_SYS_PLL1_800M>;
1115 assigned-clock-rates = <800000000>, <800000000>;
1116 power-domains = <&pgc_gpu3d>;
1117 };
1118
1119 gpu2d: gpu@38008000 {
1120 compatible = "vivante,gc";
1121 reg = <0x38008000 0x8000>;
1122 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1123 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1124 <&clk IMX8MP_CLK_GPU_ROOT>,
1125 <&clk IMX8MP_CLK_GPU_AHB>;
1126 clock-names = "core", "bus", "reg";
1127 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1128 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1129 assigned-clock-rates = <800000000>;
1130 power-domains = <&pgc_gpu2d>;
1131 };
1132
6d9b8d20
AH		 1133 gic: interrupt-controller@38800000 {
1134 compatible = "arm,gic-v3";
1135 reg = <0x38800000 0x10000>,
1136 <0x38880000 0xc0000>;
1137 #interrupt-cells = <3>;
1138 interrupt-controller;
1139 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1140 interrupt-parent = <&gic>;
1141 };
b39cb21f 1142
68b7cf5d
SS		 1143 edacmc: memory-controller@3d400000 {
1144 compatible = "snps,ddrc-3.80a";
1145 reg = <0x3d400000 0x400000>;
1146 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1147 };
1148
b39cb21f
JZ		 1149 ddr-pmu@3d800000 {
1150 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1151 reg = <0x3d800000 0x400000>;
1152 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1153 };
fb8587a2
LJ		 1154
1155 usb3_phy0: usb-phy@381f0040 {
1156 compatible = "fsl,imx8mp-usb-phy";
1157 reg = <0x381f0040 0x40>;
1158 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1159 clock-names = "phy";
1160 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1161 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2ae42e0c 1162 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
fb8587a2
LJ		 1163 #phy-cells = <0>;
1164 status = "disabled";
1165 };
1166
1167 usb3_0: usb@32f10100 {
1168 compatible = "fsl,imx8mp-dwc3";
290918c7
AS		 1169 reg = <0x32f10100 0x8>,
1170 <0x381f0000 0x20>;
fb8587a2
LJ		 1171 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1172 <&clk IMX8MP_CLK_USB_ROOT>;
1173 clock-names = "hsio", "suspend";
1174 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2ae42e0c 1175 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
fb8587a2
LJ		 1176 #address-cells = <1>;
1177 #size-cells = <1>;
1178 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1179 ranges;
1180 status = "disabled";
1181
d1689cd3 1182 usb_dwc3_0: usb@38100000 {
fb8587a2
LJ		 1183 compatible = "snps,dwc3";
1184 reg = <0x38100000 0x10000>;
1185 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1186 <&clk IMX8MP_CLK_USB_CORE_REF>,
1187 <&clk IMX8MP_CLK_USB_ROOT>;
1188 clock-names = "bus_early", "ref", "suspend";
fb8587a2
LJ		 1189 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1190 phys = <&usb3_phy0>, <&usb3_phy0>;
1191 phy-names = "usb2-phy", "usb3-phy";
1192 snps,dis-u2-freeclk-exists-quirk;
1193 };
1194
1195 };
1196
1197 usb3_phy1: usb-phy@382f0040 {
1198 compatible = "fsl,imx8mp-usb-phy";
1199 reg = <0x382f0040 0x40>;
1200 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1201 clock-names = "phy";
1202 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1203 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2ae42e0c 1204 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
fb8587a2 1205 #phy-cells = <0>;
b2d67d7b 1206 status = "disabled";
fb8587a2
LJ		 1207 };
1208
1209 usb3_1: usb@32f10108 {
1210 compatible = "fsl,imx8mp-dwc3";
290918c7
AS		 1211 reg = <0x32f10108 0x8>,
1212 <0x382f0000 0x20>;
fb8587a2
LJ		 1213 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1214 <&clk IMX8MP_CLK_USB_ROOT>;
1215 clock-names = "hsio", "suspend";
1216 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2ae42e0c 1217 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
fb8587a2
LJ		 1218 #address-cells = <1>;
1219 #size-cells = <1>;
1220 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1221 ranges;
1222 status = "disabled";
1223
d1689cd3 1224 usb_dwc3_1: usb@38200000 {
fb8587a2
LJ		 1225 compatible = "snps,dwc3";
1226 reg = <0x38200000 0x10000>;
1227 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1228 <&clk IMX8MP_CLK_USB_CORE_REF>,
1229 <&clk IMX8MP_CLK_USB_ROOT>;
1230 clock-names = "bus_early", "ref", "suspend";
fb8587a2
LJ		 1231 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1232 phys = <&usb3_phy1>, <&usb3_phy1>;
1233 phy-names = "usb2-phy", "usb3-phy";
1234 snps,dis-u2-freeclk-exists-quirk;
1235 };
1236 };
bc3ab388
DB		 1237
1238 dsp: dsp@3b6e8000 {
1239 compatible = "fsl,imx8mp-dsp";
1240 reg = <0x3b6e8000 0x88000>;
1241 mbox-names = "txdb0", "txdb1",
1242 "rxdb0", "rxdb1";
1243 mboxes = <&mu2 2 0>, <&mu2 2 1>,
1244 <&mu2 3 0>, <&mu2 3 1>;
1245 memory-region = <&dsp_reserved>;
1246 status = "disabled";
1247 };
6d9b8d20
AH		 1248 };
1249};
Linux 6.x block layer and io_uring tree(s)