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arm64: dts: imx8ulp: no executable source file permission
[linux-block.git] / arch / arm64 / boot / dts / freescale / imx8mp.dtsi
CommitLineData
6d9b8d20
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mp-clock.h>
fc0f0512 7#include <dt-bindings/power/imx8mp-power.h>
6d9b8d20
AH		 8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
3175c706 10#include <dt-bindings/interconnect/fsl,imx8mp.h>
6d9b8d20 11#include <dt-bindings/interrupt-controller/arm-gic.h>
30cdd62d 12#include <dt-bindings/thermal/thermal.h>
6d9b8d20
AH		 13
14#include "imx8mp-pinfunc.h"
15
16/ {
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 ethernet0 = &fec;
ec4d1196 23 ethernet1 = &eqos;
6d9b8d20
AH		 24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
ac4af2b1
PF		 29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
32 i2c3 = &i2c4;
33 i2c4 = &i2c5;
34 i2c5 = &i2c6;
6d9b8d20
AH		 35 mmc0 = &usdhc1;
36 mmc1 = &usdhc2;
37 mmc2 = &usdhc3;
38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
6914d1ba 42 spi0 = &flexspi;
6d9b8d20
AH		 43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 A53_0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a53";
52 reg = <0x0>;
53 clock-latency = <61036>;
54 clocks = <&clk IMX8MP_CLK_ARM>;
55 enable-method = "psci";
cb551b5e
PF		 56 i-cache-size = <0x8000>;
57 i-cache-line-size = <64>;
58 i-cache-sets = <256>;
59 d-cache-size = <0x8000>;
60 d-cache-line-size = <64>;
61 d-cache-sets = <128>;
6d9b8d20 62 next-level-cache = <&A53_L2>;
9ad9773e
MV		 63 nvmem-cells = <&cpu_speed_grade>;
64 nvmem-cell-names = "speed_grade";
21a14c68 65 operating-points-v2 = <&a53_opp_table>;
30cdd62d 66 #cooling-cells = <2>;
6d9b8d20
AH		 67 };
68
69 A53_1: cpu@1 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a53";
72 reg = <0x1>;
73 clock-latency = <61036>;
74 clocks = <&clk IMX8MP_CLK_ARM>;
75 enable-method = "psci";
cb551b5e
PF		 76 i-cache-size = <0x8000>;
77 i-cache-line-size = <64>;
78 i-cache-sets = <256>;
79 d-cache-size = <0x8000>;
80 d-cache-line-size = <64>;
81 d-cache-sets = <128>;
6d9b8d20 82 next-level-cache = <&A53_L2>;
21a14c68 83 operating-points-v2 = <&a53_opp_table>;
30cdd62d 84 #cooling-cells = <2>;
6d9b8d20
AH		 85 };
86
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
91 clock-latency = <61036>;
92 clocks = <&clk IMX8MP_CLK_ARM>;
93 enable-method = "psci";
cb551b5e
PF		 94 i-cache-size = <0x8000>;
95 i-cache-line-size = <64>;
96 i-cache-sets = <256>;
97 d-cache-size = <0x8000>;
98 d-cache-line-size = <64>;
99 d-cache-sets = <128>;
6d9b8d20 100 next-level-cache = <&A53_L2>;
21a14c68 101 operating-points-v2 = <&a53_opp_table>;
30cdd62d 102 #cooling-cells = <2>;
6d9b8d20
AH		 103 };
104
105 A53_3: cpu@3 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a53";
108 reg = <0x3>;
109 clock-latency = <61036>;
110 clocks = <&clk IMX8MP_CLK_ARM>;
111 enable-method = "psci";
cb551b5e
PF		 112 i-cache-size = <0x8000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <128>;
6d9b8d20 118 next-level-cache = <&A53_L2>;
21a14c68 119 operating-points-v2 = <&a53_opp_table>;
30cdd62d 120 #cooling-cells = <2>;
6d9b8d20
AH		 121 };
122
123 A53_L2: l2-cache0 {
124 compatible = "cache";
cb551b5e
PF		 125 cache-level = <2>;
126 cache-size = <0x80000>;
127 cache-line-size = <64>;
128 cache-sets = <512>;
6d9b8d20
AH		 129 };
130 };
131
21a14c68
MV		 132 a53_opp_table: opp-table {
133 compatible = "operating-points-v2";
134 opp-shared;
135
136 opp-1200000000 {
137 opp-hz = /bits/ 64 <1200000000>;
138 opp-microvolt = <850000>;
139 opp-supported-hw = <0x8a0>, <0x7>;
140 clock-latency-ns = <150000>;
141 opp-suspend;
142 };
143
144 opp-1600000000 {
145 opp-hz = /bits/ 64 <1600000000>;
146 opp-microvolt = <950000>;
147 opp-supported-hw = <0xa0>, <0x7>;
148 clock-latency-ns = <150000>;
149 opp-suspend;
150 };
151
152 opp-1800000000 {
153 opp-hz = /bits/ 64 <1800000000>;
154 opp-microvolt = <1000000>;
155 opp-supported-hw = <0x20>, <0x3>;
156 clock-latency-ns = <150000>;
157 opp-suspend;
158 };
159 };
160
6d9b8d20
AH		 161 osc_32k: clock-osc-32k {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <32768>;
165 clock-output-names = "osc_32k";
166 };
167
168 osc_24m: clock-osc-24m {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <24000000>;
172 clock-output-names = "osc_24m";
173 };
174
175 clk_ext1: clock-ext1 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext1";
180 };
181
182 clk_ext2: clock-ext2 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency = <133000000>;
186 clock-output-names = "clk_ext2";
187 };
188
189 clk_ext3: clock-ext3 {
190 compatible = "fixed-clock";
191 #clock-cells = <0>;
192 clock-frequency = <133000000>;
193 clock-output-names = "clk_ext3";
194 };
195
196 clk_ext4: clock-ext4 {
197 compatible = "fixed-clock";
198 #clock-cells = <0>;
33597c62 199 clock-frequency = <133000000>;
6d9b8d20
AH		 200 clock-output-names = "clk_ext4";
201 };
202
bc3ab388
DB		 203 reserved-memory {
204 #address-cells = <2>;
205 #size-cells = <2>;
206 ranges;
207
208 dsp_reserved: dsp@92400000 {
209 reg = <0 0x92400000 0 0x2000000>;
210 no-map;
211 };
212 };
213
0f109a31
JB		 214 pmu {
215 compatible = "arm,cortex-a53-pmu";
216 interrupts = <GIC_PPI 7
217 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0f109a31
JB		 218 };
219
6d9b8d20
AH		 220 psci {
221 compatible = "arm,psci-1.0";
222 method = "smc";
223 };
224
30cdd62d
AH		 225 thermal-zones {
226 cpu-thermal {
227 polling-delay-passive = <250>;
228 polling-delay = <2000>;
229 thermal-sensors = <&tmu 0>;
230 trips {
231 cpu_alert0: trip0 {
232 temperature = <85000>;
233 hysteresis = <2000>;
234 type = "passive";
235 };
236
237 cpu_crit0: trip1 {
238 temperature = <95000>;
239 hysteresis = <2000>;
240 type = "critical";
241 };
242 };
243
244 cooling-maps {
245 map0 {
246 trip = <&cpu_alert0>;
247 cooling-device =
248 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
249 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
252 };
253 };
254 };
255
256 soc-thermal {
257 polling-delay-passive = <250>;
258 polling-delay = <2000>;
259 thermal-sensors = <&tmu 1>;
260 trips {
261 soc_alert0: trip0 {
262 temperature = <85000>;
263 hysteresis = <2000>;
264 type = "passive";
265 };
266
267 soc_crit0: trip1 {
268 temperature = <95000>;
269 hysteresis = <2000>;
270 type = "critical";
271 };
272 };
273
274 cooling-maps {
275 map0 {
276 trip = <&soc_alert0>;
277 cooling-device =
278 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
279 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
280 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
281 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
282 };
283 };
284 };
285 };
286
6d9b8d20
AH		 287 timer {
288 compatible = "arm,armv8-timer";
061883e6
KK		 289 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
290 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
291 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
292 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6d9b8d20
AH		 293 clock-frequency = <8000000>;
294 arm,no-tick-in-suspend;
295 };
296
fcdef92b 297 soc: soc@0 {
ce58459d 298 compatible = "fsl,imx8mp-soc", "simple-bus";
6d9b8d20
AH		 299 #address-cells = <1>;
300 #size-cells = <1>;
301 ranges = <0x0 0x0 0x0 0x3e000000>;
cbff2379
AG		 302 nvmem-cells = <&imx8mp_uid>;
303 nvmem-cell-names = "soc_unique_id";
6d9b8d20
AH		 304
305 aips1: bus@30000000 {
dc3efc6f 306 compatible = "fsl,aips-bus", "simple-bus";
921a6845 307 reg = <0x30000000 0x400000>;
6d9b8d20
AH		 308 #address-cells = <1>;
309 #size-cells = <1>;
310 ranges;
311
312 gpio1: gpio@30200000 {
313 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
314 reg = <0x30200000 0x10000>;
315 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 gpio-ranges = <&iomuxc 0 5 30>;
323 };
324
325 gpio2: gpio@30210000 {
326 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
327 reg = <0x30210000 0x10000>;
328 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
335 gpio-ranges = <&iomuxc 0 35 21>;
336 };
337
338 gpio3: gpio@30220000 {
339 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
340 reg = <0x30220000 0x10000>;
341 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
b764eb65 348 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
6d9b8d20
AH		 349 };
350
351 gpio4: gpio@30230000 {
352 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
353 reg = <0x30230000 0x10000>;
354 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
357 gpio-controller;
358 #gpio-cells = <2>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
361 gpio-ranges = <&iomuxc 0 82 32>;
362 };
363
364 gpio5: gpio@30240000 {
365 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
366 reg = <0x30240000 0x10000>;
367 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 gpio-ranges = <&iomuxc 0 114 30>;
375 };
376
30cdd62d
AH		 377 tmu: tmu@30260000 {
378 compatible = "fsl,imx8mp-tmu";
379 reg = <0x30260000 0x10000>;
380 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
381 #thermal-sensor-cells = <1>;
382 };
383
6d9b8d20
AH		 384 wdog1: watchdog@30280000 {
385 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
386 reg = <0x30280000 0x10000>;
387 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
389 status = "disabled";
390 };
391
36133cb5
PF		 392 wdog2: watchdog@30290000 {
393 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
394 reg = <0x30290000 0x10000>;
395 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
397 status = "disabled";
398 };
399
400 wdog3: watchdog@302a0000 {
401 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
402 reg = <0x302a0000 0x10000>;
403 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
405 status = "disabled";
406 };
407
6d9b8d20
AH		 408 iomuxc: pinctrl@30330000 {
409 compatible = "fsl,imx8mp-iomuxc";
410 reg = <0x30330000 0x10000>;
411 };
412
413 gpr: iomuxc-gpr@30340000 {
414 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
415 reg = <0x30340000 0x10000>;
416 };
417
12fa1078 418 ocotp: efuse@30350000 {
f2fe45d5 419 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
6d9b8d20
AH		 420 reg = <0x30350000 0x10000>;
421 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
422 /* For nvmem subnodes */
423 #address-cells = <1>;
424 #size-cells = <1>;
425
cbff2379
AG		 426 imx8mp_uid: unique-id@420 {
427 reg = <0x8 0x8>;
428 };
429
6d9b8d20
AH		 430 cpu_speed_grade: speed-grade@10 {
431 reg = <0x10 4>;
432 };
066438ae
JZ		 433
434 eth_mac1: mac-address@90 {
435 reg = <0x90 6>;
436 };
44d0dfee
JZ		 437
438 eth_mac2: mac-address@96 {
439 reg = <0x96 6>;
440 };
6d9b8d20
AH		 441 };
442
443 anatop: anatop@30360000 {
444 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
445 "syscon";
446 reg = <0x30360000 0x10000>;
447 };
448
449 snvs: snvs@30370000 {
450 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
451 reg = <0x30370000 0x10000>;
452
453 snvs_rtc: snvs-rtc-lp {
454 compatible = "fsl,sec-v4.0-mon-rtc-lp";
455 regmap =<&snvs>;
456 offset = <0x34>;
457 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
460 clock-names = "snvs-rtc";
461 };
462
463 snvs_pwrkey: snvs-powerkey {
464 compatible = "fsl,sec-v4.0-pwrkey";
465 regmap = <&snvs>;
466 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
6c389f29
AH		 467 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
468 clock-names = "snvs-pwrkey";
6d9b8d20
AH		 469 linux,keycode = <KEY_POWER>;
470 wakeup-source;
471 status = "disabled";
472 };
4dcb6c0f
MV		 473
474 snvs_lpgpr: snvs-lpgpr {
475 compatible = "fsl,imx8mp-snvs-lpgpr",
476 "fsl,imx7d-snvs-lpgpr";
477 };
6d9b8d20
AH		 478 };
479
480 clk: clock-controller@30380000 {
481 compatible = "fsl,imx8mp-ccm";
482 reg = <0x30380000 0x10000>;
483 #clock-cells = <1>;
484 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
485 <&clk_ext3>, <&clk_ext4>;
486 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
487 "clk_ext3", "clk_ext4";
9e6337e6
PF		 488 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
489 <&clk IMX8MP_CLK_A53_CORE>,
490 <&clk IMX8MP_CLK_NOC>,
6d9b8d20
AH		 491 <&clk IMX8MP_CLK_NOC_IO>,
492 <&clk IMX8MP_CLK_GIC>,
493 <&clk IMX8MP_CLK_AUDIO_AHB>,
494 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
6d9b8d20
AH		 495 <&clk IMX8MP_AUDIO_PLL1>,
496 <&clk IMX8MP_AUDIO_PLL2>;
9e6337e6
PF		 497 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
498 <&clk IMX8MP_ARM_PLL_OUT>,
499 <&clk IMX8MP_SYS_PLL2_1000M>,
6d9b8d20
AH		 500 <&clk IMX8MP_SYS_PLL1_800M>,
501 <&clk IMX8MP_SYS_PLL2_500M>,
502 <&clk IMX8MP_SYS_PLL1_800M>,
503 <&clk IMX8MP_SYS_PLL1_800M>;
9e6337e6
PF		 504 assigned-clock-rates = <0>, <0>,
505 <1000000000>,
6d9b8d20
AH		 506 <800000000>,
507 <500000000>,
508 <400000000>,
509 <800000000>,
6d9b8d20
AH		 510 <393216000>,
511 <361267200>;
512 };
455ae0c3
AH		 513
514 src: reset-controller@30390000 {
515 compatible = "fsl,imx8mp-src", "syscon";
516 reg = <0x30390000 0x10000>;
1641b234 517 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
455ae0c3
AH		 518 #reset-cells = <1>;
519 };
fc0f0512
LS		 520
521 gpc: gpc@303a0000 {
522 compatible = "fsl,imx8mp-gpc";
523 reg = <0x303a0000 0x1000>;
524 interrupt-parent = <&gic>;
525 interrupt-controller;
526 #interrupt-cells = <3>;
527
528 pgc {
529 #address-cells = <1>;
530 #size-cells = <0>;
531
9d89189d
LP		 532 pgc_mipi_phy1: power-domain@0 {
533 #power-domain-cells = <0>;
534 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
535 };
536
2ae42e0c
LS		 537 pgc_pcie_phy: power-domain@1 {
538 #power-domain-cells = <0>;
539 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
540 };
541
542 pgc_usb1_phy: power-domain@2 {
543 #power-domain-cells = <0>;
544 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
545 };
546
547 pgc_usb2_phy: power-domain@3 {
548 #power-domain-cells = <0>;
549 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
550 };
551
fc0f0512
LS		 552 pgc_gpu2d: power-domain@6 {
553 #power-domain-cells = <0>;
554 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
555 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
556 power-domains = <&pgc_gpumix>;
557 };
558
559 pgc_gpumix: power-domain@7 {
560 #power-domain-cells = <0>;
561 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
562 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
563 <&clk IMX8MP_CLK_GPU_AHB>;
564 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
565 <&clk IMX8MP_CLK_GPU_AHB>;
566 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
567 <&clk IMX8MP_SYS_PLL1_800M>;
568 assigned-clock-rates = <800000000>, <400000000>;
569 };
570
571 pgc_gpu3d: power-domain@9 {
572 #power-domain-cells = <0>;
573 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
574 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
575 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
576 power-domains = <&pgc_gpumix>;
577 };
2ae42e0c 578
9d89189d
LP		 579 pgc_mediamix: power-domain@10 {
580 #power-domain-cells = <0>;
581 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
582 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
583 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
584 };
585
586 pgc_mipi_phy2: power-domain@16 {
587 #power-domain-cells = <0>;
588 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
589 };
590
2ae42e0c
LS		 591 pgc_hsiomix: power-domains@17 {
592 #power-domain-cells = <0>;
593 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
594 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
595 <&clk IMX8MP_CLK_HSIO_ROOT>;
596 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
597 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
598 assigned-clock-rates = <500000000>;
599 };
9d89189d
LP		 600
601 pgc_ispdwp: power-domain@18 {
602 #power-domain-cells = <0>;
603 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
3fdd4ef4 604 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
9d89189d 605 };
df680992
PF		 606
607 pgc_vpumix: power-domain@19 {
608 #power-domain-cells = <0>;
609 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
610 clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
611 };
612
613 pgc_vpu_g1: power-domain@20 {
614 #power-domain-cells = <0>;
615 power-domains = <&pgc_vpumix>;
616 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
617 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
618 };
619
620 pgc_vpu_g2: power-domain@21 {
621 #power-domain-cells = <0>;
622 power-domains = <&pgc_vpumix>;
623 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
624 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
625 };
626
627 pgc_vpu_vc8000e: power-domain@22 {
628 #power-domain-cells = <0>;
629 power-domains = <&pgc_vpumix>;
630 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
631 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
632 };
fc0f0512
LS		 633 };
634 };
6d9b8d20
AH		 635 };
636
637 aips2: bus@30400000 {
dc3efc6f 638 compatible = "fsl,aips-bus", "simple-bus";
921a6845 639 reg = <0x30400000 0x400000>;
6d9b8d20
AH		 640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges;
643
644 pwm1: pwm@30660000 {
645 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
646 reg = <0x30660000 0x10000>;
647 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
649 <&clk IMX8MP_CLK_PWM1_ROOT>;
650 clock-names = "ipg", "per";
d80b9c84 651 #pwm-cells = <3>;
6d9b8d20
AH		 652 status = "disabled";
653 };
654
655 pwm2: pwm@30670000 {
656 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
657 reg = <0x30670000 0x10000>;
658 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
660 <&clk IMX8MP_CLK_PWM2_ROOT>;
661 clock-names = "ipg", "per";
d80b9c84 662 #pwm-cells = <3>;
6d9b8d20
AH		 663 status = "disabled";
664 };
665
666 pwm3: pwm@30680000 {
667 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
668 reg = <0x30680000 0x10000>;
669 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
671 <&clk IMX8MP_CLK_PWM3_ROOT>;
672 clock-names = "ipg", "per";
d80b9c84 673 #pwm-cells = <3>;
6d9b8d20
AH		 674 status = "disabled";
675 };
676
677 pwm4: pwm@30690000 {
678 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
679 reg = <0x30690000 0x10000>;
680 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
682 <&clk IMX8MP_CLK_PWM4_ROOT>;
683 clock-names = "ipg", "per";
d80b9c84 684 #pwm-cells = <3>;
6d9b8d20
AH		 685 status = "disabled";
686 };
fae58b1a
AH		 687
688 system_counter: timer@306a0000 {
689 compatible = "nxp,sysctr-timer";
690 reg = <0x306a0000 0x20000>;
691 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&osc_24m>;
693 clock-names = "per";
694 };
6d9b8d20
AH		 695 };
696
697 aips3: bus@30800000 {
dc3efc6f 698 compatible = "fsl,aips-bus", "simple-bus";
921a6845 699 reg = <0x30800000 0x400000>;
6d9b8d20
AH		 700 #address-cells = <1>;
701 #size-cells = <1>;
702 ranges;
703
704 ecspi1: spi@30820000 {
705 #address-cells = <1>;
706 #size-cells = <0>;
707 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
708 reg = <0x30820000 0x10000>;
709 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
711 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
712 clock-names = "ipg", "per";
713 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
714 dma-names = "rx", "tx";
715 status = "disabled";
716 };
717
718 ecspi2: spi@30830000 {
719 #address-cells = <1>;
720 #size-cells = <0>;
721 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
722 reg = <0x30830000 0x10000>;
723 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
725 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
726 clock-names = "ipg", "per";
727 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
728 dma-names = "rx", "tx";
729 status = "disabled";
730 };
731
732 ecspi3: spi@30840000 {
733 #address-cells = <1>;
734 #size-cells = <0>;
735 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
736 reg = <0x30840000 0x10000>;
737 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
739 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
740 clock-names = "ipg", "per";
741 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
742 dma-names = "rx", "tx";
743 status = "disabled";
744 };
745
746 uart1: serial@30860000 {
747 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
748 reg = <0x30860000 0x10000>;
749 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
751 <&clk IMX8MP_CLK_UART1_ROOT>;
752 clock-names = "ipg", "per";
753 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
754 dma-names = "rx", "tx";
755 status = "disabled";
756 };
757
758 uart3: serial@30880000 {
759 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
760 reg = <0x30880000 0x10000>;
761 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
763 <&clk IMX8MP_CLK_UART3_ROOT>;
764 clock-names = "ipg", "per";
765 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
766 dma-names = "rx", "tx";
767 status = "disabled";
768 };
769
770 uart2: serial@30890000 {
771 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
772 reg = <0x30890000 0x10000>;
773 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
775 <&clk IMX8MP_CLK_UART2_ROOT>;
776 clock-names = "ipg", "per";
a00f1fa6
MZ		 777 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
778 dma-names = "rx", "tx";
6d9b8d20
AH		 779 status = "disabled";
780 };
781
3a7d56b3 782 flexcan1: can@308c0000 {
f5d156c7 783 compatible = "fsl,imx8mp-flexcan";
3a7d56b3
JZ		 784 reg = <0x308c0000 0x10000>;
785 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
787 <&clk IMX8MP_CLK_CAN1_ROOT>;
788 clock-names = "ipg", "per";
789 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
790 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
791 assigned-clock-rates = <40000000>;
792 fsl,clk-source = /bits/ 8 <0>;
793 fsl,stop-mode = <&gpr 0x10 4>;
794 status = "disabled";
795 };
796
797 flexcan2: can@308d0000 {
f5d156c7 798 compatible = "fsl,imx8mp-flexcan";
3a7d56b3
JZ		 799 reg = <0x308d0000 0x10000>;
800 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
802 <&clk IMX8MP_CLK_CAN2_ROOT>;
803 clock-names = "ipg", "per";
804 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
805 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
806 assigned-clock-rates = <40000000>;
807 fsl,clk-source = /bits/ 8 <0>;
808 fsl,stop-mode = <&gpr 0x10 5>;
809 status = "disabled";
810 };
811
d3a719e3
HG		 812 crypto: crypto@30900000 {
813 compatible = "fsl,sec-v4.0";
814 #address-cells = <1>;
815 #size-cells = <1>;
816 reg = <0x30900000 0x40000>;
817 ranges = <0 0x30900000 0x40000>;
818 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clk IMX8MP_CLK_AHB>,
820 <&clk IMX8MP_CLK_IPG_ROOT>;
821 clock-names = "aclk", "ipg";
822
823 sec_jr0: jr@1000 {
824 compatible = "fsl,sec-v4.0-job-ring";
825 reg = <0x1000 0x1000>;
826 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
dc9c1ceb 827 status = "disabled";
d3a719e3
HG		 828 };
829
830 sec_jr1: jr@2000 {
831 compatible = "fsl,sec-v4.0-job-ring";
832 reg = <0x2000 0x1000>;
833 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
834 };
835
836 sec_jr2: jr@3000 {
837 compatible = "fsl,sec-v4.0-job-ring";
838 reg = <0x3000 0x1000>;
839 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
840 };
841 };
842
6d9b8d20
AH		 843 i2c1: i2c@30a20000 {
844 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
845 #address-cells = <1>;
846 #size-cells = <0>;
847 reg = <0x30a20000 0x10000>;
848 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
850 status = "disabled";
851 };
852
853 i2c2: i2c@30a30000 {
854 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
855 #address-cells = <1>;
856 #size-cells = <0>;
857 reg = <0x30a30000 0x10000>;
858 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
860 status = "disabled";
861 };
862
863 i2c3: i2c@30a40000 {
864 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
865 #address-cells = <1>;
866 #size-cells = <0>;
867 reg = <0x30a40000 0x10000>;
868 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
870 status = "disabled";
871 };
872
873 i2c4: i2c@30a50000 {
874 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
875 #address-cells = <1>;
876 #size-cells = <0>;
877 reg = <0x30a50000 0x10000>;
878 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
880 status = "disabled";
881 };
882
883 uart4: serial@30a60000 {
884 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
885 reg = <0x30a60000 0x10000>;
886 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
888 <&clk IMX8MP_CLK_UART4_ROOT>;
889 clock-names = "ipg", "per";
890 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
891 dma-names = "rx", "tx";
892 status = "disabled";
893 };
894
bbfc59be
PF		 895 mu: mailbox@30aa0000 {
896 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
897 reg = <0x30aa0000 0x10000>;
898 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
900 #mbox-cells = <2>;
901 };
902
bc3ab388
DB		 903 mu2: mailbox@30e60000 {
904 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
905 reg = <0x30e60000 0x10000>;
906 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
907 #mbox-cells = <2>;
908 status = "disabled";
909 };
910
6d9b8d20
AH		 911 i2c5: i2c@30ad0000 {
912 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
913 #address-cells = <1>;
914 #size-cells = <0>;
915 reg = <0x30ad0000 0x10000>;
916 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
918 status = "disabled";
919 };
920
921 i2c6: i2c@30ae0000 {
922 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
923 #address-cells = <1>;
924 #size-cells = <0>;
925 reg = <0x30ae0000 0x10000>;
926 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
928 status = "disabled";
929 };
930
931 usdhc1: mmc@30b40000 {
746a7241 932 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 933 reg = <0x30b40000 0x10000>;
934 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&clk IMX8MP_CLK_DUMMY>,
936 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
937 <&clk IMX8MP_CLK_USDHC1_ROOT>;
938 clock-names = "ipg", "ahb", "per";
939 fsl,tuning-start-tap = <20>;
33597c62 940 fsl,tuning-step = <2>;
6d9b8d20
AH		 941 bus-width = <4>;
942 status = "disabled";
943 };
944
945 usdhc2: mmc@30b50000 {
746a7241 946 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 947 reg = <0x30b50000 0x10000>;
948 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&clk IMX8MP_CLK_DUMMY>,
950 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
951 <&clk IMX8MP_CLK_USDHC2_ROOT>;
952 clock-names = "ipg", "ahb", "per";
953 fsl,tuning-start-tap = <20>;
33597c62 954 fsl,tuning-step = <2>;
6d9b8d20
AH		 955 bus-width = <4>;
956 status = "disabled";
957 };
958
959 usdhc3: mmc@30b60000 {
746a7241 960 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 961 reg = <0x30b60000 0x10000>;
962 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clk IMX8MP_CLK_DUMMY>,
964 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
965 <&clk IMX8MP_CLK_USDHC3_ROOT>;
966 clock-names = "ipg", "ahb", "per";
967 fsl,tuning-start-tap = <20>;
33597c62 968 fsl,tuning-step = <2>;
6d9b8d20
AH		 969 bus-width = <4>;
970 status = "disabled";
971 };
972
6914d1ba
HS		 973 flexspi: spi@30bb0000 {
974 compatible = "nxp,imx8mp-fspi";
975 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
976 reg-names = "fspi_base", "fspi_mmap";
977 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
979 <&clk IMX8MP_CLK_QSPI_ROOT>;
d7cd7446 980 clock-names = "fspi_en", "fspi";
6914d1ba
HS		 981 assigned-clock-rates = <80000000>;
982 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
983 #address-cells = <1>;
984 #size-cells = <0>;
985 status = "disabled";
986 };
987
6d9b8d20
AH		 988 sdma1: dma-controller@30bd0000 {
989 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
990 reg = <0x30bd0000 0x10000>;
991 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
66138621 993 <&clk IMX8MP_CLK_AHB>;
6d9b8d20
AH		 994 clock-names = "ipg", "ahb";
995 #dma-cells = <3>;
996 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
997 };
998
999 fec: ethernet@30be0000 {
f9654d26 1000 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
6d9b8d20
AH		 1001 reg = <0x30be0000 0x10000>;
1002 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 1004 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6d9b8d20
AH		 1006 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1007 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1008 <&clk IMX8MP_CLK_ENET_TIMER>,
1009 <&clk IMX8MP_CLK_ENET_REF>,
1010 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1011 clock-names = "ipg", "ahb", "ptp",
1012 "enet_clk_ref", "enet_out";
1013 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1014 <&clk IMX8MP_CLK_ENET_TIMER>,
1015 <&clk IMX8MP_CLK_ENET_REF>,
70eacf42 1016 <&clk IMX8MP_CLK_ENET_PHY_REF>;
6d9b8d20
AH		 1017 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1018 <&clk IMX8MP_SYS_PLL2_100M>,
70eacf42
JZ		 1019 <&clk IMX8MP_SYS_PLL2_125M>,
1020 <&clk IMX8MP_SYS_PLL2_50M>;
1021 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
6d9b8d20
AH		 1022 fsl,num-tx-queues = <3>;
1023 fsl,num-rx-queues = <3>;
066438ae
JZ		 1024 nvmem-cells = <&eth_mac1>;
1025 nvmem-cell-names = "mac-address";
afe99354 1026 fsl,stop-mode = <&gpr 0x10 3>;
6d9b8d20
AH		 1027 status = "disabled";
1028 };
ec4d1196
MV		 1029
1030 eqos: ethernet@30bf0000 {
1031 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1032 reg = <0x30bf0000 0x10000>;
77e5253d
JZ		 1033 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1035 interrupt-names = "macirq", "eth_wake_irq";
ec4d1196
MV		 1036 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1037 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1038 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1039 <&clk IMX8MP_CLK_ENET_QOS>;
1040 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1041 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1042 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1043 <&clk IMX8MP_CLK_ENET_QOS>;
1044 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1045 <&clk IMX8MP_SYS_PLL2_100M>,
1046 <&clk IMX8MP_SYS_PLL2_125M>;
1047 assigned-clock-rates = <0>, <100000000>, <125000000>;
44d0dfee
JZ		 1048 nvmem-cells = <&eth_mac2>;
1049 nvmem-cell-names = "mac-address";
ec4d1196
MV		 1050 intf_mode = <&gpr 0x4>;
1051 status = "disabled";
1052 };
6d9b8d20
AH		 1053 };
1054
d4ac6028
PF		 1055 noc: interconnect@32700000 {
1056 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1057 reg = <0x32700000 0x100000>;
1058 clocks = <&clk IMX8MP_CLK_NOC>;
1059 #interconnect-cells = <1>;
1060 operating-points-v2 = <&noc_opp_table>;
1061
1062 noc_opp_table: opp-table {
1063 compatible = "operating-points-v2";
1064
1065 opp-200M {
1066 opp-hz = /bits/ 64 <200000000>;
1067 };
1068
1069 opp-1000M {
1070 opp-hz = /bits/ 64 <1000000000>;
1071 };
1072 };
1073 };
1074
2ae42e0c
LS		 1075 aips4: bus@32c00000 {
1076 compatible = "fsl,aips-bus", "simple-bus";
1077 reg = <0x32c00000 0x400000>;
1078 #address-cells = <1>;
1079 #size-cells = <1>;
1080 ranges;
1081
29f440a7
PE		 1082 media_blk_ctrl: blk-ctrl@32ec0000 {
1083 compatible = "fsl,imx8mp-media-blk-ctrl",
1084 "syscon";
1085 reg = <0x32ec0000 0x10000>;
1086 power-domains = <&pgc_mediamix>,
1087 <&pgc_mipi_phy1>,
1088 <&pgc_mipi_phy1>,
1089 <&pgc_mediamix>,
1090 <&pgc_mediamix>,
1091 <&pgc_mipi_phy2>,
1092 <&pgc_mediamix>,
1093 <&pgc_ispdwp>,
1094 <&pgc_ispdwp>,
1095 <&pgc_mipi_phy2>;
1096 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1097 "lcdif1", "isi", "mipi-csi2",
1098 "lcdif2", "isp", "dwe",
1099 "mipi-dsi2";
3175c706
PF		 1100 interconnects =
1101 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1102 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1103 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1104 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1105 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1106 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1107 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1108 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1109 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1110 "isi1", "isi2", "isp0", "isp1",
1111 "dwe";
29f440a7
PE		 1112 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1113 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1114 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1115 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1116 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1117 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1118 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1119 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1120 clock-names = "apb", "axi", "cam1", "cam2",
1121 "disp1", "disp2", "isp", "phy";
1122
1123 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1124 <&clk IMX8MP_CLK_MEDIA_APB>;
1125 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1126 <&clk IMX8MP_SYS_PLL1_800M>;
1127 assigned-clock-rates = <500000000>, <200000000>;
1128
1129 #power-domain-cells = <1>;
1130 };
1131
2ae42e0c
LS		 1132 hsio_blk_ctrl: blk-ctrl@32f10000 {
1133 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1134 reg = <0x32f10000 0x24>;
1135 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1136 <&clk IMX8MP_CLK_PCIE_ROOT>;
1137 clock-names = "usb", "pcie";
1138 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1139 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1140 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1141 power-domain-names = "bus", "usb", "usb-phy1",
1142 "usb-phy2", "pcie", "pcie-phy";
31da63e1
PF		 1143 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
1144 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
1145 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
1146 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
1147 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
2ae42e0c
LS		 1148 #power-domain-cells = <1>;
1149 };
1150 };
1151
4bdb1192
LS		 1152 gpu3d: gpu@38000000 {
1153 compatible = "vivante,gc";
1154 reg = <0x38000000 0x8000>;
1155 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1157 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1158 <&clk IMX8MP_CLK_GPU_ROOT>,
1159 <&clk IMX8MP_CLK_GPU_AHB>;
1160 clock-names = "core", "shader", "bus", "reg";
1161 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1162 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1163 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1164 <&clk IMX8MP_SYS_PLL1_800M>;
1165 assigned-clock-rates = <800000000>, <800000000>;
1166 power-domains = <&pgc_gpu3d>;
1167 };
1168
1169 gpu2d: gpu@38008000 {
1170 compatible = "vivante,gc";
1171 reg = <0x38008000 0x8000>;
1172 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1173 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1174 <&clk IMX8MP_CLK_GPU_ROOT>,
1175 <&clk IMX8MP_CLK_GPU_AHB>;
1176 clock-names = "core", "bus", "reg";
1177 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1178 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1179 assigned-clock-rates = <800000000>;
1180 power-domains = <&pgc_gpu2d>;
1181 };
1182
a763d0cf
PF		 1183 vpumix_blk_ctrl: blk-ctrl@38330000 {
1184 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1185 reg = <0x38330000 0x100>;
1186 #power-domain-cells = <1>;
1187 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1188 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
1189 power-domain-names = "bus", "g1", "g2", "vc8000e";
1190 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
1191 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
1192 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
1193 clock-names = "g1", "g2", "vc8000e";
1194 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
1195 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
1196 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
1197 interconnect-names = "g1", "g2", "vc8000e";
1198 };
1199
6d9b8d20
AH		 1200 gic: interrupt-controller@38800000 {
1201 compatible = "arm,gic-v3";
1202 reg = <0x38800000 0x10000>,
1203 <0x38880000 0xc0000>;
1204 #interrupt-cells = <3>;
1205 interrupt-controller;
1206 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1207 interrupt-parent = <&gic>;
1208 };
b39cb21f 1209
68b7cf5d
SS		 1210 edacmc: memory-controller@3d400000 {
1211 compatible = "snps,ddrc-3.80a";
1212 reg = <0x3d400000 0x400000>;
1213 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1214 };
1215
b39cb21f
JZ		 1216 ddr-pmu@3d800000 {
1217 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1218 reg = <0x3d800000 0x400000>;
1219 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1220 };
fb8587a2
LJ		 1221
1222 usb3_phy0: usb-phy@381f0040 {
1223 compatible = "fsl,imx8mp-usb-phy";
1224 reg = <0x381f0040 0x40>;
1225 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1226 clock-names = "phy";
1227 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1228 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2ae42e0c 1229 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
fb8587a2
LJ		 1230 #phy-cells = <0>;
1231 status = "disabled";
1232 };
1233
1234 usb3_0: usb@32f10100 {
1235 compatible = "fsl,imx8mp-dwc3";
290918c7
AS		 1236 reg = <0x32f10100 0x8>,
1237 <0x381f0000 0x20>;
fb8587a2
LJ		 1238 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1239 <&clk IMX8MP_CLK_USB_ROOT>;
1240 clock-names = "hsio", "suspend";
1241 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2ae42e0c 1242 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
fb8587a2
LJ		 1243 #address-cells = <1>;
1244 #size-cells = <1>;
1245 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1246 ranges;
1247 status = "disabled";
1248
d1689cd3 1249 usb_dwc3_0: usb@38100000 {
fb8587a2
LJ		 1250 compatible = "snps,dwc3";
1251 reg = <0x38100000 0x10000>;
1252 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1253 <&clk IMX8MP_CLK_USB_CORE_REF>,
1254 <&clk IMX8MP_CLK_USB_ROOT>;
1255 clock-names = "bus_early", "ref", "suspend";
fb8587a2
LJ		 1256 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1257 phys = <&usb3_phy0>, <&usb3_phy0>;
1258 phy-names = "usb2-phy", "usb3-phy";
1259 snps,dis-u2-freeclk-exists-quirk;
1260 };
1261
1262 };
1263
1264 usb3_phy1: usb-phy@382f0040 {
1265 compatible = "fsl,imx8mp-usb-phy";
1266 reg = <0x382f0040 0x40>;
1267 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1268 clock-names = "phy";
1269 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1270 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2ae42e0c 1271 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
fb8587a2 1272 #phy-cells = <0>;
b2d67d7b 1273 status = "disabled";
fb8587a2
LJ		 1274 };
1275
1276 usb3_1: usb@32f10108 {
1277 compatible = "fsl,imx8mp-dwc3";
290918c7
AS		 1278 reg = <0x32f10108 0x8>,
1279 <0x382f0000 0x20>;
fb8587a2
LJ		 1280 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1281 <&clk IMX8MP_CLK_USB_ROOT>;
1282 clock-names = "hsio", "suspend";
1283 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2ae42e0c 1284 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
fb8587a2
LJ		 1285 #address-cells = <1>;
1286 #size-cells = <1>;
1287 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1288 ranges;
1289 status = "disabled";
1290
d1689cd3 1291 usb_dwc3_1: usb@38200000 {
fb8587a2
LJ		 1292 compatible = "snps,dwc3";
1293 reg = <0x38200000 0x10000>;
1294 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1295 <&clk IMX8MP_CLK_USB_CORE_REF>,
1296 <&clk IMX8MP_CLK_USB_ROOT>;
1297 clock-names = "bus_early", "ref", "suspend";
fb8587a2
LJ		 1298 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1299 phys = <&usb3_phy1>, <&usb3_phy1>;
1300 phy-names = "usb2-phy", "usb3-phy";
1301 snps,dis-u2-freeclk-exists-quirk;
1302 };
1303 };
bc3ab388
DB		 1304
1305 dsp: dsp@3b6e8000 {
1306 compatible = "fsl,imx8mp-dsp";
1307 reg = <0x3b6e8000 0x88000>;
1308 mbox-names = "txdb0", "txdb1",
1309 "rxdb0", "rxdb1";
1310 mboxes = <&mu2 2 0>, <&mu2 2 1>,
1311 <&mu2 3 0>, <&mu2 3 1>;
1312 memory-region = <&dsp_reserved>;
1313 status = "disabled";
1314 };
6d9b8d20
AH		 1315 };
1316};
Linux 6.x block layer and io_uring tree(s)