[linux-block.git] / arch / arm64 / boot / dts / freescale / imx8mp.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "imx8mp-pinfunc.h"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MP_CLK_ARM>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
		};

		A53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MP_CLK_ARM>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
		};

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MP_CLK_ARM>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MP_CLK_ARM>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
		};
	};

	osc_32k: clock-osc-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency= <133000000>;
		clock-output-names = "clk_ext4";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <8000000>;
		arm,no-tick-in-suspend;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x3e000000>;

		aips1: bus@30000000 {
			compatible = "simple-bus";
			reg = <0x30000000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gpio1: gpio@30200000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 5 30>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 35 21>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 82 32>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 114 30>;
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
				status = "disabled";
			};

			iomuxc: pinctrl@30330000 {
				compatible = "fsl,imx8mp-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			gpr: iomuxc-gpr@30340000 {
				compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
				reg = <0x30340000 0x10000>;
			};

			ocotp: ocotp-ctrl@30350000 {
				compatible = "fsl,imx8mp-ocotp", "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
				/* For nvmem subnodes */
				#address-cells = <1>;
				#size-cells = <1>;

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};
			};

			anatop: anatop@30360000 {
				compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
					     "syscon";
				reg = <0x30360000 0x10000>;
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
				reg = <0x30370000 0x10000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap =<&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
					clock-names = "snvs-rtc";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};
			};

			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mp-ccm";
				reg = <0x30380000 0x10000>;
				#clock-cells = <1>;
				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
					 <&clk_ext3>, <&clk_ext4>;
				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
					      "clk_ext3", "clk_ext4";
				assigned-clocks = <&clk IMX8MP_CLK_NOC>,
						  <&clk IMX8MP_CLK_NOC_IO>,
						  <&clk IMX8MP_CLK_GIC>,
						  <&clk IMX8MP_CLK_AUDIO_AHB>,
						  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
						  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
						  <&clk IMX8MP_AUDIO_PLL1>,
						  <&clk IMX8MP_AUDIO_PLL2>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
							 <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_SYS_PLL2_500M>,
							 <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_SYS_PLL1_800M>;
				assigned-clock-rates = <1000000000>,
						       <800000000>,
						       <500000000>,
						       <400000000>,
						       <800000000>,
						       <400000000>,
						       <393216000>,
						       <361267200>;
			};
		};

		aips2: bus@30400000 {
			compatible = "simple-bus";
			reg = <0x30400000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pwm1: pwm@30660000 {
				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
				reg = <0x30660000 0x10000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
					 <&clk IMX8MP_CLK_PWM1_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm2: pwm@30670000 {
				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
				reg = <0x30670000 0x10000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
					 <&clk IMX8MP_CLK_PWM2_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm3: pwm@30680000 {
				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
				reg = <0x30680000 0x10000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
					 <&clk IMX8MP_CLK_PWM3_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm4: pwm@30690000 {
				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
				reg = <0x30690000 0x10000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
					 <&clk IMX8MP_CLK_PWM4_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};
		};

		aips3: bus@30800000 {
			compatible = "simple-bus";
			reg = <0x30800000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			ecspi1: spi@30820000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
				reg = <0x30820000 0x10000>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
					 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi2: spi@30830000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
				reg = <0x30830000 0x10000>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
					 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi3: spi@30840000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
				reg = <0x30840000 0x10000>;
				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
					 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart1: serial@30860000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30860000 0x10000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
					 <&clk IMX8MP_CLK_UART1_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart3: serial@30880000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30880000 0x10000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
					 <&clk IMX8MP_CLK_UART3_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart2: serial@30890000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30890000 0x10000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
					 <&clk IMX8MP_CLK_UART2_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c1: i2c@30a20000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
					 <&clk IMX8MP_CLK_UART4_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			i2c5: i2c@30ad0000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30ad0000 0x10000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
				status = "disabled";
			};

			i2c6: i2c@30ae0000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30ae0000 0x10000>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
				status = "disabled";
			};

			usdhc1: mmc@30b40000 {
				compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_DUMMY>,
					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MP_CLK_USDHC1_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@30b50000 {
				compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_DUMMY>,
					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MP_CLK_USDHC2_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@30b60000 {
				compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_DUMMY>,
					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MP_CLK_USDHC3_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			sdma1: dma-controller@30bd0000 {
				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
				reg = <0x30bd0000 0x10000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
					 <&clk IMX8MP_CLK_SDMA1_ROOT>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			fec: ethernet@30be0000 {
				compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec";
				reg = <0x30be0000 0x10000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
					 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
					 <&clk IMX8MP_CLK_ENET_TIMER>,
					 <&clk IMX8MP_CLK_ENET_REF>,
					 <&clk IMX8MP_CLK_ENET_PHY_REF>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
						  <&clk IMX8MP_CLK_ENET_TIMER>,
						  <&clk IMX8MP_CLK_ENET_REF>,
						  <&clk IMX8MP_CLK_ENET_TIMER>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
							 <&clk IMX8MP_SYS_PLL2_100M>,
							 <&clk IMX8MP_SYS_PLL2_125M>;
				assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				status = "disabled";
			};
		};

		gic: interrupt-controller@38800000 {
			compatible = "arm,gic-v3";
			reg = <0x38800000 0x10000>,
			      <0x38880000 0xc0000>;
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
		};
	};
};
Commit	Line	Data
6d9b8d20 AH	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright 2019 NXP
	4	*/
	5
	6	#include <dt-bindings/clock/imx8mp-clock.h>
	7	#include <dt-bindings/gpio/gpio.h>
	8	#include <dt-bindings/input/input.h>
	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
	10
	11	#include "imx8mp-pinfunc.h"
	12
	13	/ {
	14	interrupt-parent = <&gic>;
	15	#address-cells = <2>;
	16	#size-cells = <2>;
	17
	18	aliases {
	19	ethernet0 = &fec;
	20	gpio0 = &gpio1;
	21	gpio1 = &gpio2;
	22	gpio2 = &gpio3;
	23	gpio3 = &gpio4;
	24	gpio4 = &gpio5;
	25	mmc0 = &usdhc1;
	26	mmc1 = &usdhc2;
	27	mmc2 = &usdhc3;
	28	serial0 = &uart1;
	29	serial1 = &uart2;
	30	serial2 = &uart3;
	31	serial3 = &uart4;
	32	};
	33
	34	cpus {
	35	#address-cells = <1>;
	36	#size-cells = <0>;
	37
	38	A53_0: cpu@0 {
	39	device_type = "cpu";
	40	compatible = "arm,cortex-a53";
	41	reg = <0x0>;
	42	clock-latency = <61036>;
	43	clocks = <&clk IMX8MP_CLK_ARM>;
	44	enable-method = "psci";
	45	next-level-cache = <&A53_L2>;
	46	};
	47
	48	A53_1: cpu@1 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a53";
	51	reg = <0x1>;
	52	clock-latency = <61036>;
	53	clocks = <&clk IMX8MP_CLK_ARM>;
	54	enable-method = "psci";
	55	next-level-cache = <&A53_L2>;
	56	};
	57
	58	A53_2: cpu@2 {
	59	device_type = "cpu";
	60	compatible = "arm,cortex-a53";
	61	reg = <0x2>;
	62	clock-latency = <61036>;
	63	clocks = <&clk IMX8MP_CLK_ARM>;
	64	enable-method = "psci";
65	next-level-cache = <&A53_L2>;
66	};
67
68	A53_3: cpu@3 {
69	device_type = "cpu";
70	compatible = "arm,cortex-a53";
71	reg = <0x3>;
72	clock-latency = <61036>;
73	clocks = <&clk IMX8MP_CLK_ARM>;
74	enable-method = "psci";
75	next-level-cache = <&A53_L2>;
76	};
77
78	A53_L2: l2-cache0 {
79	compatible = "cache";
80	};
81	};
82
83	osc_32k: clock-osc-32k {
84	compatible = "fixed-clock";
85	#clock-cells = <0>;
86	clock-frequency = <32768>;
87	clock-output-names = "osc_32k";
88	};
89
90	osc_24m: clock-osc-24m {
91	compatible = "fixed-clock";
92	#clock-cells = <0>;
93	clock-frequency = <24000000>;
94	clock-output-names = "osc_24m";
95	};
96
97	clk_ext1: clock-ext1 {
98	compatible = "fixed-clock";
99	#clock-cells = <0>;
100	clock-frequency = <133000000>;
101	clock-output-names = "clk_ext1";
102	};
103
104	clk_ext2: clock-ext2 {
105	compatible = "fixed-clock";
106	#clock-cells = <0>;
107	clock-frequency = <133000000>;
108	clock-output-names = "clk_ext2";
109	};
110
111	clk_ext3: clock-ext3 {
112	compatible = "fixed-clock";
113	#clock-cells = <0>;
114	clock-frequency = <133000000>;
115	clock-output-names = "clk_ext3";
116	};
117
118	clk_ext4: clock-ext4 {
119	compatible = "fixed-clock";
120	#clock-cells = <0>;
121	clock-frequency= <133000000>;
122	clock-output-names = "clk_ext4";
123	};
124
125	psci {
126	compatible = "arm,psci-1.0";
127	method = "smc";
128	};
129
130	timer {
131	compatible = "arm,armv8-timer";
132	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
133	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
134	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
135	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
136	clock-frequency = <8000000>;
137	arm,no-tick-in-suspend;
138	};
139
140	soc@0 {
141	compatible = "simple-bus";
142	#address-cells = <1>;
143	#size-cells = <1>;
144	ranges = <0x0 0x0 0x0 0x3e000000>;
145
146	aips1: bus@30000000 {
147	compatible = "simple-bus";
148	reg = <0x30000000 0x400000>;
149	#address-cells = <1>;
150	#size-cells = <1>;
151	ranges;
152
153	gpio1: gpio@30200000 {
154	compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
155	reg = <0x30200000 0x10000>;
156	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
157	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
158	clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
159	gpio-controller;
160	#gpio-cells = <2>;
161	interrupt-controller;
162	#interrupt-cells = <2>;
163	gpio-ranges = <&iomuxc 0 5 30>;
164	};
165
166	gpio2: gpio@30210000 {
167	compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
168	reg = <0x30210000 0x10000>;
169	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
170	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
171	clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
172	gpio-controller;
173	#gpio-cells = <2>;
174	interrupt-controller;
175	#interrupt-cells = <2>;
176	gpio-ranges = <&iomuxc 0 35 21>;
177	};
178
179	gpio3: gpio@30220000 {
180	compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
181	reg = <0x30220000 0x10000>;
182	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
183	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
184	clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
185	gpio-controller;
186	#gpio-cells = <2>;
187	interrupt-controller;
188	#interrupt-cells = <2>;
189	gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
190	};
191
192	gpio4: gpio@30230000 {
193	compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
194	reg = <0x30230000 0x10000>;
195	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
196	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
197	clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
198	gpio-controller;
199	#gpio-cells = <2>;
200	interrupt-controller;
201	#interrupt-cells = <2>;
202	gpio-ranges = <&iomuxc 0 82 32>;
203	};
204
205	gpio5: gpio@30240000 {
206	compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
207	reg = <0x30240000 0x10000>;
208	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
209	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
210	clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
211	gpio-controller;
212	#gpio-cells = <2>;
213	interrupt-controller;
214	#interrupt-cells = <2>;
215	gpio-ranges = <&iomuxc 0 114 30>;
216	};
217
218	wdog1: watchdog@30280000 {
219	compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
220	reg = <0x30280000 0x10000>;
221	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
222	clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
223	status = "disabled";
224	};
225
226	iomuxc: pinctrl@30330000 {
227	compatible = "fsl,imx8mp-iomuxc";
228	reg = <0x30330000 0x10000>;
229	};
230
231	gpr: iomuxc-gpr@30340000 {
232	compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
233	reg = <0x30340000 0x10000>;
234	};
235
236	ocotp: ocotp-ctrl@30350000 {
237	compatible = "fsl,imx8mp-ocotp", "syscon";
238	reg = <0x30350000 0x10000>;
239	clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
240	/* For nvmem subnodes */
241	#address-cells = <1>;
242	#size-cells = <1>;
243
244	cpu_speed_grade: speed-grade@10 {
245	reg = <0x10 4>;
246	};
247	};
248
249	anatop: anatop@30360000 {
250	compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
251	"syscon";
252	reg = <0x30360000 0x10000>;
253	};
254
255	snvs: snvs@30370000 {
256	compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
257	reg = <0x30370000 0x10000>;
258
259	snvs_rtc: snvs-rtc-lp {
260	compatible = "fsl,sec-v4.0-mon-rtc-lp";
261	regmap =<&snvs>;
262	offset = <0x34>;
263	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
264	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
265	clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
266	clock-names = "snvs-rtc";
267	};
268
269	snvs_pwrkey: snvs-powerkey {
270	compatible = "fsl,sec-v4.0-pwrkey";
271	regmap = <&snvs>;
272	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
273	linux,keycode = <KEY_POWER>;
274	wakeup-source;
275	status = "disabled";
276	};
277	};
278
279	clk: clock-controller@30380000 {
280	compatible = "fsl,imx8mp-ccm";
281	reg = <0x30380000 0x10000>;
282	#clock-cells = <1>;
283	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
284	<&clk_ext3>, <&clk_ext4>;
285	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
286	"clk_ext3", "clk_ext4";
287	assigned-clocks = <&clk IMX8MP_CLK_NOC>,
288	<&clk IMX8MP_CLK_NOC_IO>,
289	<&clk IMX8MP_CLK_GIC>,
290	<&clk IMX8MP_CLK_AUDIO_AHB>,
291	<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
292	<&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
293	<&clk IMX8MP_AUDIO_PLL1>,
294	<&clk IMX8MP_AUDIO_PLL2>;
295	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
296	<&clk IMX8MP_SYS_PLL1_800M>,
297	<&clk IMX8MP_SYS_PLL2_500M>,
298	<&clk IMX8MP_SYS_PLL1_800M>,
299	<&clk IMX8MP_SYS_PLL1_800M>;
300	assigned-clock-rates = <1000000000>,
301	<800000000>,
302	<500000000>,
303	<400000000>,
304	<800000000>,
305	<400000000>,
306	<393216000>,
307	<361267200>;
308	};
309	};
310
311	aips2: bus@30400000 {
312	compatible = "simple-bus";
313	reg = <0x30400000 0x400000>;
314	#address-cells = <1>;
315	#size-cells = <1>;
316	ranges;
317
318	pwm1: pwm@30660000 {
319	compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
320	reg = <0x30660000 0x10000>;
321	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
322	clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
323	<&clk IMX8MP_CLK_PWM1_ROOT>;
324	clock-names = "ipg", "per";
325	#pwm-cells = <2>;
326	status = "disabled";
327	};
328
329	pwm2: pwm@30670000 {
330	compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
331	reg = <0x30670000 0x10000>;
332	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
333	clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
334	<&clk IMX8MP_CLK_PWM2_ROOT>;
335	clock-names = "ipg", "per";
336	#pwm-cells = <2>;
337	status = "disabled";
338	};
339
340	pwm3: pwm@30680000 {
341	compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
342	reg = <0x30680000 0x10000>;
343	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
344	clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
345	<&clk IMX8MP_CLK_PWM3_ROOT>;
346	clock-names = "ipg", "per";
347	#pwm-cells = <2>;
348	status = "disabled";
349	};
350
351	pwm4: pwm@30690000 {
352	compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
353	reg = <0x30690000 0x10000>;
354	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
355	clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
356	<&clk IMX8MP_CLK_PWM4_ROOT>;
357	clock-names = "ipg", "per";
358	#pwm-cells = <2>;
359	status = "disabled";
360	};
361	};
362
363	aips3: bus@30800000 {
364	compatible = "simple-bus";
365	reg = <0x30800000 0x400000>;
366	#address-cells = <1>;
367	#size-cells = <1>;
368	ranges;
369
370	ecspi1: spi@30820000 {
371	#address-cells = <1>;
372	#size-cells = <0>;
373	compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
374	reg = <0x30820000 0x10000>;
375	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
376	clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
377	<&clk IMX8MP_CLK_ECSPI1_ROOT>;
378	clock-names = "ipg", "per";
379	dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
380	dma-names = "rx", "tx";
381	status = "disabled";
382	};
383
384	ecspi2: spi@30830000 {
385	#address-cells = <1>;
386	#size-cells = <0>;
387	compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
388	reg = <0x30830000 0x10000>;
389	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
390	clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
391	<&clk IMX8MP_CLK_ECSPI2_ROOT>;
392	clock-names = "ipg", "per";
393	dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
394	dma-names = "rx", "tx";
395	status = "disabled";
396	};
397
398	ecspi3: spi@30840000 {
399	#address-cells = <1>;
400	#size-cells = <0>;
401	compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
402	reg = <0x30840000 0x10000>;
403	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
404	clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
405	<&clk IMX8MP_CLK_ECSPI3_ROOT>;
406	clock-names = "ipg", "per";
407	dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
408	dma-names = "rx", "tx";
409	status = "disabled";
410	};
411
412	uart1: serial@30860000 {
413	compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
414	reg = <0x30860000 0x10000>;
415	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
416	clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
417	<&clk IMX8MP_CLK_UART1_ROOT>;
418	clock-names = "ipg", "per";
419	dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
420	dma-names = "rx", "tx";
421	status = "disabled";
422	};
423
424	uart3: serial@30880000 {
425	compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
426	reg = <0x30880000 0x10000>;
427	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
428	clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
429	<&clk IMX8MP_CLK_UART3_ROOT>;
430	clock-names = "ipg", "per";
431	dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
432	dma-names = "rx", "tx";
433	status = "disabled";
434	};
435
436	uart2: serial@30890000 {
437	compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
438	reg = <0x30890000 0x10000>;
439	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
440	clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
441	<&clk IMX8MP_CLK_UART2_ROOT>;
442	clock-names = "ipg", "per";
443	status = "disabled";
444	};
445
446	i2c1: i2c@30a20000 {
447	compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
448	#address-cells = <1>;
449	#size-cells = <0>;
450	reg = <0x30a20000 0x10000>;
451	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
452	clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
453	status = "disabled";
454	};
455
456	i2c2: i2c@30a30000 {
457	compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
458	#address-cells = <1>;
459	#size-cells = <0>;
460	reg = <0x30a30000 0x10000>;
461	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
462	clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
463	status = "disabled";
464	};
465
466	i2c3: i2c@30a40000 {
467	compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
468	#address-cells = <1>;
469	#size-cells = <0>;
470	reg = <0x30a40000 0x10000>;
471	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
472	clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
473	status = "disabled";
474	};
475
476	i2c4: i2c@30a50000 {
477	compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
478	#address-cells = <1>;
479	#size-cells = <0>;
480	reg = <0x30a50000 0x10000>;
481	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
482	clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
483	status = "disabled";
484	};
485
486	uart4: serial@30a60000 {
487	compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
488	reg = <0x30a60000 0x10000>;
489	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
490	clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
491	<&clk IMX8MP_CLK_UART4_ROOT>;
492	clock-names = "ipg", "per";
493	dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
494	dma-names = "rx", "tx";
495	status = "disabled";
496	};
497
498	i2c5: i2c@30ad0000 {
499	compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
500	#address-cells = <1>;
501	#size-cells = <0>;
502	reg = <0x30ad0000 0x10000>;
503	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
504	clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
505	status = "disabled";
506	};
507
508	i2c6: i2c@30ae0000 {
509	compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
510	#address-cells = <1>;
511	#size-cells = <0>;
512	reg = <0x30ae0000 0x10000>;
513	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
514	clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
515	status = "disabled";
516	};
517
518	usdhc1: mmc@30b40000 {
519	compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
520	reg = <0x30b40000 0x10000>;
521	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
522	clocks = <&clk IMX8MP_CLK_DUMMY>,
523	<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
524	<&clk IMX8MP_CLK_USDHC1_ROOT>;
525	clock-names = "ipg", "ahb", "per";
526	fsl,tuning-start-tap = <20>;
527	fsl,tuning-step= <2>;
528	bus-width = <4>;
529	status = "disabled";
530	};
531
532	usdhc2: mmc@30b50000 {
533	compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
534	reg = <0x30b50000 0x10000>;
535	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
536	clocks = <&clk IMX8MP_CLK_DUMMY>,
537	<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
538	<&clk IMX8MP_CLK_USDHC2_ROOT>;
539	clock-names = "ipg", "ahb", "per";
540	fsl,tuning-start-tap = <20>;
541	fsl,tuning-step= <2>;
542	bus-width = <4>;
543	status = "disabled";
544	};
545
546	usdhc3: mmc@30b60000 {
547	compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
548	reg = <0x30b60000 0x10000>;
549	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
550	clocks = <&clk IMX8MP_CLK_DUMMY>,
551	<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
552	<&clk IMX8MP_CLK_USDHC3_ROOT>;
553	clock-names = "ipg", "ahb", "per";
554	fsl,tuning-start-tap = <20>;
555	fsl,tuning-step= <2>;
556	bus-width = <4>;
557	status = "disabled";
558	};
559
560	sdma1: dma-controller@30bd0000 {
561	compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
562	reg = <0x30bd0000 0x10000>;
563	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
564	clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
565	<&clk IMX8MP_CLK_SDMA1_ROOT>;
566	clock-names = "ipg", "ahb";
567	#dma-cells = <3>;
568	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
569	};
570
571	fec: ethernet@30be0000 {
572	compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec";
573	reg = <0x30be0000 0x10000>;
574	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
575	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
576	<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
577	clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
578	<&clk IMX8MP_CLK_SIM_ENET_ROOT>,
579	<&clk IMX8MP_CLK_ENET_TIMER>,
580	<&clk IMX8MP_CLK_ENET_REF>,
581	<&clk IMX8MP_CLK_ENET_PHY_REF>;
582	clock-names = "ipg", "ahb", "ptp",
583	"enet_clk_ref", "enet_out";
584	assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
585	<&clk IMX8MP_CLK_ENET_TIMER>,
586	<&clk IMX8MP_CLK_ENET_REF>,
587	<&clk IMX8MP_CLK_ENET_TIMER>;
588	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
589	<&clk IMX8MP_SYS_PLL2_100M>,
590	<&clk IMX8MP_SYS_PLL2_125M>;
591	assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
592	fsl,num-tx-queues = <3>;
593	fsl,num-rx-queues = <3>;
594	status = "disabled";
595	};
596	};
597
598	gic: interrupt-controller@38800000 {
599	compatible = "arm,gic-v3";
600	reg = <0x38800000 0x10000>,
601	<0x38880000 0xc0000>;
602	#interrupt-cells = <3>;
603	interrupt-controller;
604	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
605	interrupt-parent = <&gic>;
606	};
607	};
608	};