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arm64: dts: imx8m: Document the fuse address calculation
[linux-block.git] / arch / arm64 / boot / dts / freescale / imx8mp.dtsi
CommitLineData
6d9b8d20
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mp-clock.h>
fc0f0512 7#include <dt-bindings/power/imx8mp-power.h>
9e65987b 8#include <dt-bindings/reset/imx8mp-reset.h>
6d9b8d20
AH		 9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
3175c706 11#include <dt-bindings/interconnect/fsl,imx8mp.h>
6d9b8d20 12#include <dt-bindings/interrupt-controller/arm-gic.h>
30cdd62d 13#include <dt-bindings/thermal/thermal.h>
6d9b8d20
AH		 14
15#include "imx8mp-pinfunc.h"
16
17/ {
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 ethernet0 = &fec;
ec4d1196 24 ethernet1 = &eqos;
6d9b8d20
AH		 25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
ac4af2b1
PF		 30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 i2c3 = &i2c4;
34 i2c4 = &i2c5;
35 i2c5 = &i2c6;
6d9b8d20
AH		 36 mmc0 = &usdhc1;
37 mmc1 = &usdhc2;
38 mmc2 = &usdhc3;
39 serial0 = &uart1;
40 serial1 = &uart2;
41 serial2 = &uart3;
42 serial3 = &uart4;
6914d1ba 43 spi0 = &flexspi;
6d9b8d20
AH		 44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 A53_0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a53";
53 reg = <0x0>;
54 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci";
cb551b5e
PF		 57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
6d9b8d20 63 next-level-cache = <&A53_L2>;
9ad9773e
MV		 64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "speed_grade";
21a14c68 66 operating-points-v2 = <&a53_opp_table>;
30cdd62d 67 #cooling-cells = <2>;
6d9b8d20
AH		 68 };
69
70 A53_1: cpu@1 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a53";
73 reg = <0x1>;
74 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci";
cb551b5e
PF		 77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
79 i-cache-sets = <256>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
82 d-cache-sets = <128>;
6d9b8d20 83 next-level-cache = <&A53_L2>;
21a14c68 84 operating-points-v2 = <&a53_opp_table>;
30cdd62d 85 #cooling-cells = <2>;
6d9b8d20
AH		 86 };
87
88 A53_2: cpu@2 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a53";
91 reg = <0x2>;
92 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci";
cb551b5e
PF		 95 i-cache-size = <0x8000>;
96 i-cache-line-size = <64>;
97 i-cache-sets = <256>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>;
6d9b8d20 101 next-level-cache = <&A53_L2>;
21a14c68 102 operating-points-v2 = <&a53_opp_table>;
30cdd62d 103 #cooling-cells = <2>;
6d9b8d20
AH		 104 };
105
106 A53_3: cpu@3 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a53";
109 reg = <0x3>;
110 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci";
cb551b5e
PF		 113 i-cache-size = <0x8000>;
114 i-cache-line-size = <64>;
115 i-cache-sets = <256>;
116 d-cache-size = <0x8000>;
117 d-cache-line-size = <64>;
118 d-cache-sets = <128>;
6d9b8d20 119 next-level-cache = <&A53_L2>;
21a14c68 120 operating-points-v2 = <&a53_opp_table>;
30cdd62d 121 #cooling-cells = <2>;
6d9b8d20
AH		 122 };
123
124 A53_L2: l2-cache0 {
125 compatible = "cache";
3b450831 126 cache-unified;
cb551b5e
PF		 127 cache-level = <2>;
128 cache-size = <0x80000>;
129 cache-line-size = <64>;
130 cache-sets = <512>;
6d9b8d20
AH		 131 };
132 };
133
21a14c68
MV		 134 a53_opp_table: opp-table {
135 compatible = "operating-points-v2";
136 opp-shared;
137
138 opp-1200000000 {
139 opp-hz = /bits/ 64 <1200000000>;
140 opp-microvolt = <850000>;
141 opp-supported-hw = <0x8a0>, <0x7>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
144 };
145
146 opp-1600000000 {
147 opp-hz = /bits/ 64 <1600000000>;
148 opp-microvolt = <950000>;
149 opp-supported-hw = <0xa0>, <0x7>;
150 clock-latency-ns = <150000>;
151 opp-suspend;
152 };
153
154 opp-1800000000 {
155 opp-hz = /bits/ 64 <1800000000>;
156 opp-microvolt = <1000000>;
157 opp-supported-hw = <0x20>, <0x3>;
158 clock-latency-ns = <150000>;
159 opp-suspend;
160 };
161 };
162
6d9b8d20
AH		 163 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <32768>;
167 clock-output-names = "osc_32k";
168 };
169
170 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m";
175 };
176
177 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1";
182 };
183
184 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2";
189 };
190
191 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3";
196 };
197
198 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
33597c62 201 clock-frequency = <133000000>;
6d9b8d20
AH		 202 clock-output-names = "clk_ext4";
203 };
204
bc3ab388
DB		 205 reserved-memory {
206 #address-cells = <2>;
207 #size-cells = <2>;
208 ranges;
209
210 dsp_reserved: dsp@92400000 {
211 reg = <0 0x92400000 0 0x2000000>;
212 no-map;
213 };
214 };
215
0f109a31
JB		 216 pmu {
217 compatible = "arm,cortex-a53-pmu";
218 interrupts = <GIC_PPI 7
219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0f109a31
JB		 220 };
221
6d9b8d20
AH		 222 psci {
223 compatible = "arm,psci-1.0";
224 method = "smc";
225 };
226
30cdd62d
AH		 227 thermal-zones {
228 cpu-thermal {
229 polling-delay-passive = <250>;
230 polling-delay = <2000>;
231 thermal-sensors = <&tmu 0>;
232 trips {
233 cpu_alert0: trip0 {
234 temperature = <85000>;
235 hysteresis = <2000>;
236 type = "passive";
237 };
238
239 cpu_crit0: trip1 {
240 temperature = <95000>;
241 hysteresis = <2000>;
242 type = "critical";
243 };
244 };
245
246 cooling-maps {
247 map0 {
248 trip = <&cpu_alert0>;
249 cooling-device =
250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
254 };
255 };
256 };
257
258 soc-thermal {
259 polling-delay-passive = <250>;
260 polling-delay = <2000>;
261 thermal-sensors = <&tmu 1>;
262 trips {
263 soc_alert0: trip0 {
264 temperature = <85000>;
265 hysteresis = <2000>;
266 type = "passive";
267 };
268
269 soc_crit0: trip1 {
270 temperature = <95000>;
271 hysteresis = <2000>;
272 type = "critical";
273 };
274 };
275
276 cooling-maps {
277 map0 {
278 trip = <&soc_alert0>;
279 cooling-device =
280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
284 };
285 };
286 };
287 };
288
6d9b8d20
AH		 289 timer {
290 compatible = "arm,armv8-timer";
061883e6
KK		 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6d9b8d20
AH		 295 clock-frequency = <8000000>;
296 arm,no-tick-in-suspend;
297 };
298
fcdef92b 299 soc: soc@0 {
ce58459d 300 compatible = "fsl,imx8mp-soc", "simple-bus";
6d9b8d20
AH		 301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges = <0x0 0x0 0x0 0x3e000000>;
cbff2379
AG		 304 nvmem-cells = <&imx8mp_uid>;
305 nvmem-cell-names = "soc_unique_id";
6d9b8d20
AH		 306
307 aips1: bus@30000000 {
dc3efc6f 308 compatible = "fsl,aips-bus", "simple-bus";
921a6845 309 reg = <0x30000000 0x400000>;
6d9b8d20
AH		 310 #address-cells = <1>;
311 #size-cells = <1>;
312 ranges;
313
314 gpio1: gpio@30200000 {
315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
316 reg = <0x30200000 0x10000>;
317 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 gpio-ranges = <&iomuxc 0 5 30>;
325 };
326
327 gpio2: gpio@30210000 {
328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
329 reg = <0x30210000 0x10000>;
330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 gpio-ranges = <&iomuxc 0 35 21>;
338 };
339
340 gpio3: gpio@30220000 {
341 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
342 reg = <0x30220000 0x10000>;
343 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
b764eb65 350 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
6d9b8d20
AH		 351 };
352
353 gpio4: gpio@30230000 {
354 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
355 reg = <0x30230000 0x10000>;
356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
359 gpio-controller;
360 #gpio-cells = <2>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 gpio-ranges = <&iomuxc 0 82 32>;
364 };
365
366 gpio5: gpio@30240000 {
367 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
368 reg = <0x30240000 0x10000>;
369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 gpio-ranges = <&iomuxc 0 114 30>;
377 };
378
30cdd62d
AH		 379 tmu: tmu@30260000 {
380 compatible = "fsl,imx8mp-tmu";
381 reg = <0x30260000 0x10000>;
382 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
383 #thermal-sensor-cells = <1>;
384 };
385
6d9b8d20
AH		 386 wdog1: watchdog@30280000 {
387 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
388 reg = <0x30280000 0x10000>;
389 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
391 status = "disabled";
392 };
393
36133cb5
PF		 394 wdog2: watchdog@30290000 {
395 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
396 reg = <0x30290000 0x10000>;
397 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
399 status = "disabled";
400 };
401
402 wdog3: watchdog@302a0000 {
403 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
404 reg = <0x302a0000 0x10000>;
405 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
407 status = "disabled";
408 };
409
6d9b8d20
AH		 410 iomuxc: pinctrl@30330000 {
411 compatible = "fsl,imx8mp-iomuxc";
412 reg = <0x30330000 0x10000>;
413 };
414
415 gpr: iomuxc-gpr@30340000 {
416 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
417 reg = <0x30340000 0x10000>;
418 };
419
12fa1078 420 ocotp: efuse@30350000 {
f2fe45d5 421 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
6d9b8d20
AH		 422 reg = <0x30350000 0x10000>;
423 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
424 /* For nvmem subnodes */
425 #address-cells = <1>;
426 #size-cells = <1>;
427
5b81a87d
MV		 428 /*
429 * The register address below maps to the MX8M
430 * Fusemap Description Table entries this way.
431 * Assuming
432 * reg = <ADDR SIZE>;
433 * then
434 * Fuse Address = (ADDR * 4) + 0x400
435 * Note that if SIZE is greater than 4, then
436 * each subsequent fuse is located at offset
437 * +0x10 in Fusemap Description Table (e.g.
438 * reg = <0x8 0x8> describes fuses 0x420 and
439 * 0x430).
440 */
441 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
cbff2379
AG		 442 reg = <0x8 0x8>;
443 };
444
5b81a87d 445 cpu_speed_grade: speed-grade@10 { /* 0x440 */
6d9b8d20
AH		 446 reg = <0x10 4>;
447 };
066438ae 448
5b81a87d 449 eth_mac1: mac-address@90 { /* 0x640 */
066438ae
JZ		 450 reg = <0x90 6>;
451 };
44d0dfee 452
5b81a87d 453 eth_mac2: mac-address@96 { /* 0x658 */
44d0dfee
JZ		 454 reg = <0x96 6>;
455 };
6d9b8d20
AH		 456 };
457
f98c2dfe
PF		 458 anatop: clock-controller@30360000 {
459 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
6d9b8d20 460 reg = <0x30360000 0x10000>;
f98c2dfe 461 #clock-cells = <1>;
6d9b8d20
AH		 462 };
463
464 snvs: snvs@30370000 {
465 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
466 reg = <0x30370000 0x10000>;
467
468 snvs_rtc: snvs-rtc-lp {
469 compatible = "fsl,sec-v4.0-mon-rtc-lp";
470 regmap =<&snvs>;
471 offset = <0x34>;
472 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
475 clock-names = "snvs-rtc";
476 };
477
478 snvs_pwrkey: snvs-powerkey {
479 compatible = "fsl,sec-v4.0-pwrkey";
480 regmap = <&snvs>;
481 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
6c389f29
AH		 482 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
483 clock-names = "snvs-pwrkey";
6d9b8d20
AH		 484 linux,keycode = <KEY_POWER>;
485 wakeup-source;
486 status = "disabled";
487 };
4dcb6c0f
MV		 488
489 snvs_lpgpr: snvs-lpgpr {
490 compatible = "fsl,imx8mp-snvs-lpgpr",
491 "fsl,imx7d-snvs-lpgpr";
492 };
6d9b8d20
AH		 493 };
494
495 clk: clock-controller@30380000 {
496 compatible = "fsl,imx8mp-ccm";
497 reg = <0x30380000 0x10000>;
498 #clock-cells = <1>;
499 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
500 <&clk_ext3>, <&clk_ext4>;
501 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
502 "clk_ext3", "clk_ext4";
9e6337e6
PF		 503 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
504 <&clk IMX8MP_CLK_A53_CORE>,
505 <&clk IMX8MP_CLK_NOC>,
6d9b8d20
AH		 506 <&clk IMX8MP_CLK_NOC_IO>,
507 <&clk IMX8MP_CLK_GIC>,
508 <&clk IMX8MP_CLK_AUDIO_AHB>,
509 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
6d9b8d20
AH		 510 <&clk IMX8MP_AUDIO_PLL1>,
511 <&clk IMX8MP_AUDIO_PLL2>;
9e6337e6
PF		 512 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
513 <&clk IMX8MP_ARM_PLL_OUT>,
514 <&clk IMX8MP_SYS_PLL2_1000M>,
6d9b8d20
AH		 515 <&clk IMX8MP_SYS_PLL1_800M>,
516 <&clk IMX8MP_SYS_PLL2_500M>,
517 <&clk IMX8MP_SYS_PLL1_800M>,
518 <&clk IMX8MP_SYS_PLL1_800M>;
9e6337e6
PF		 519 assigned-clock-rates = <0>, <0>,
520 <1000000000>,
6d9b8d20
AH		 521 <800000000>,
522 <500000000>,
523 <400000000>,
524 <800000000>,
6d9b8d20
AH		 525 <393216000>,
526 <361267200>;
527 };
455ae0c3
AH		 528
529 src: reset-controller@30390000 {
530 compatible = "fsl,imx8mp-src", "syscon";
531 reg = <0x30390000 0x10000>;
1641b234 532 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
455ae0c3
AH		 533 #reset-cells = <1>;
534 };
fc0f0512
LS		 535
536 gpc: gpc@303a0000 {
537 compatible = "fsl,imx8mp-gpc";
538 reg = <0x303a0000 0x1000>;
539 interrupt-parent = <&gic>;
540 interrupt-controller;
541 #interrupt-cells = <3>;
542
543 pgc {
544 #address-cells = <1>;
545 #size-cells = <0>;
546
9d89189d
LP		 547 pgc_mipi_phy1: power-domain@0 {
548 #power-domain-cells = <0>;
549 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
550 };
551
2ae42e0c
LS		 552 pgc_pcie_phy: power-domain@1 {
553 #power-domain-cells = <0>;
554 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
555 };
556
557 pgc_usb1_phy: power-domain@2 {
558 #power-domain-cells = <0>;
559 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
560 };
561
562 pgc_usb2_phy: power-domain@3 {
563 #power-domain-cells = <0>;
564 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
565 };
566
fc0f0512
LS		 567 pgc_gpu2d: power-domain@6 {
568 #power-domain-cells = <0>;
569 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
570 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
571 power-domains = <&pgc_gpumix>;
572 };
573
574 pgc_gpumix: power-domain@7 {
575 #power-domain-cells = <0>;
576 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
577 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
578 <&clk IMX8MP_CLK_GPU_AHB>;
579 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
580 <&clk IMX8MP_CLK_GPU_AHB>;
581 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
582 <&clk IMX8MP_SYS_PLL1_800M>;
583 assigned-clock-rates = <800000000>, <400000000>;
584 };
585
586 pgc_gpu3d: power-domain@9 {
587 #power-domain-cells = <0>;
588 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
589 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
590 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
591 power-domains = <&pgc_gpumix>;
592 };
2ae42e0c 593
9d89189d
LP		 594 pgc_mediamix: power-domain@10 {
595 #power-domain-cells = <0>;
596 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
597 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
598 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
599 };
600
601 pgc_mipi_phy2: power-domain@16 {
602 #power-domain-cells = <0>;
603 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
604 };
605
2ae42e0c
LS		 606 pgc_hsiomix: power-domains@17 {
607 #power-domain-cells = <0>;
608 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
609 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
610 <&clk IMX8MP_CLK_HSIO_ROOT>;
611 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
612 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
613 assigned-clock-rates = <500000000>;
614 };
9d89189d
LP		 615
616 pgc_ispdwp: power-domain@18 {
617 #power-domain-cells = <0>;
618 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
3fdd4ef4 619 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
9d89189d 620 };
df680992
PF		 621
622 pgc_vpumix: power-domain@19 {
623 #power-domain-cells = <0>;
624 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
625 clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
626 };
627
628 pgc_vpu_g1: power-domain@20 {
629 #power-domain-cells = <0>;
630 power-domains = <&pgc_vpumix>;
631 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
632 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
633 };
634
635 pgc_vpu_g2: power-domain@21 {
636 #power-domain-cells = <0>;
637 power-domains = <&pgc_vpumix>;
638 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
639 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
640 };
641
642 pgc_vpu_vc8000e: power-domain@22 {
643 #power-domain-cells = <0>;
644 power-domains = <&pgc_vpumix>;
645 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
646 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
647 };
834464c8
PF		 648
649 pgc_mlmix: power-domain@24 {
650 #power-domain-cells = <0>;
651 reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
652 clocks = <&clk IMX8MP_CLK_ML_AXI>,
653 <&clk IMX8MP_CLK_ML_AHB>,
654 <&clk IMX8MP_CLK_NPU_ROOT>;
655 };
fc0f0512
LS		 656 };
657 };
6d9b8d20
AH		 658 };
659
660 aips2: bus@30400000 {
dc3efc6f 661 compatible = "fsl,aips-bus", "simple-bus";
921a6845 662 reg = <0x30400000 0x400000>;
6d9b8d20
AH		 663 #address-cells = <1>;
664 #size-cells = <1>;
665 ranges;
666
667 pwm1: pwm@30660000 {
668 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
669 reg = <0x30660000 0x10000>;
670 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
672 <&clk IMX8MP_CLK_PWM1_ROOT>;
673 clock-names = "ipg", "per";
d80b9c84 674 #pwm-cells = <3>;
6d9b8d20
AH		 675 status = "disabled";
676 };
677
678 pwm2: pwm@30670000 {
679 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
680 reg = <0x30670000 0x10000>;
681 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
683 <&clk IMX8MP_CLK_PWM2_ROOT>;
684 clock-names = "ipg", "per";
d80b9c84 685 #pwm-cells = <3>;
6d9b8d20
AH		 686 status = "disabled";
687 };
688
689 pwm3: pwm@30680000 {
690 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
691 reg = <0x30680000 0x10000>;
692 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
694 <&clk IMX8MP_CLK_PWM3_ROOT>;
695 clock-names = "ipg", "per";
d80b9c84 696 #pwm-cells = <3>;
6d9b8d20
AH		 697 status = "disabled";
698 };
699
700 pwm4: pwm@30690000 {
701 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
702 reg = <0x30690000 0x10000>;
703 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
705 <&clk IMX8MP_CLK_PWM4_ROOT>;
706 clock-names = "ipg", "per";
d80b9c84 707 #pwm-cells = <3>;
6d9b8d20
AH		 708 status = "disabled";
709 };
fae58b1a
AH		 710
711 system_counter: timer@306a0000 {
712 compatible = "nxp,sysctr-timer";
713 reg = <0x306a0000 0x20000>;
714 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&osc_24m>;
716 clock-names = "per";
717 };
6d9b8d20
AH		 718 };
719
720 aips3: bus@30800000 {
dc3efc6f 721 compatible = "fsl,aips-bus", "simple-bus";
921a6845 722 reg = <0x30800000 0x400000>;
6d9b8d20
AH		 723 #address-cells = <1>;
724 #size-cells = <1>;
725 ranges;
726
727 ecspi1: spi@30820000 {
728 #address-cells = <1>;
729 #size-cells = <0>;
48d74376 730 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
6d9b8d20
AH		 731 reg = <0x30820000 0x10000>;
732 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
734 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
735 clock-names = "ipg", "per";
48d74376
PF		 736 assigned-clock-rates = <80000000>;
737 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
738 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
6d9b8d20
AH		 739 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
740 dma-names = "rx", "tx";
741 status = "disabled";
742 };
743
744 ecspi2: spi@30830000 {
745 #address-cells = <1>;
746 #size-cells = <0>;
48d74376 747 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
6d9b8d20
AH		 748 reg = <0x30830000 0x10000>;
749 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
751 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
752 clock-names = "ipg", "per";
48d74376
PF		 753 assigned-clock-rates = <80000000>;
754 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
755 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
6d9b8d20
AH		 756 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
757 dma-names = "rx", "tx";
758 status = "disabled";
759 };
760
761 ecspi3: spi@30840000 {
762 #address-cells = <1>;
763 #size-cells = <0>;
48d74376 764 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
6d9b8d20
AH		 765 reg = <0x30840000 0x10000>;
766 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
768 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
769 clock-names = "ipg", "per";
48d74376
PF		 770 assigned-clock-rates = <80000000>;
771 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
772 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
6d9b8d20
AH		 773 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
774 dma-names = "rx", "tx";
775 status = "disabled";
776 };
777
778 uart1: serial@30860000 {
779 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
780 reg = <0x30860000 0x10000>;
781 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
783 <&clk IMX8MP_CLK_UART1_ROOT>;
784 clock-names = "ipg", "per";
785 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
786 dma-names = "rx", "tx";
787 status = "disabled";
788 };
789
790 uart3: serial@30880000 {
791 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
792 reg = <0x30880000 0x10000>;
793 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
795 <&clk IMX8MP_CLK_UART3_ROOT>;
796 clock-names = "ipg", "per";
797 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
798 dma-names = "rx", "tx";
799 status = "disabled";
800 };
801
802 uart2: serial@30890000 {
803 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
804 reg = <0x30890000 0x10000>;
805 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
807 <&clk IMX8MP_CLK_UART2_ROOT>;
808 clock-names = "ipg", "per";
a00f1fa6
MZ		 809 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
810 dma-names = "rx", "tx";
6d9b8d20
AH		 811 status = "disabled";
812 };
813
3a7d56b3 814 flexcan1: can@308c0000 {
f5d156c7 815 compatible = "fsl,imx8mp-flexcan";
3a7d56b3
JZ		 816 reg = <0x308c0000 0x10000>;
817 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
819 <&clk IMX8MP_CLK_CAN1_ROOT>;
820 clock-names = "ipg", "per";
821 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
822 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
823 assigned-clock-rates = <40000000>;
824 fsl,clk-source = /bits/ 8 <0>;
825 fsl,stop-mode = <&gpr 0x10 4>;
826 status = "disabled";
827 };
828
829 flexcan2: can@308d0000 {
f5d156c7 830 compatible = "fsl,imx8mp-flexcan";
3a7d56b3
JZ		 831 reg = <0x308d0000 0x10000>;
832 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
834 <&clk IMX8MP_CLK_CAN2_ROOT>;
835 clock-names = "ipg", "per";
836 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
837 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
838 assigned-clock-rates = <40000000>;
839 fsl,clk-source = /bits/ 8 <0>;
840 fsl,stop-mode = <&gpr 0x10 5>;
841 status = "disabled";
842 };
843
d3a719e3
HG		 844 crypto: crypto@30900000 {
845 compatible = "fsl,sec-v4.0";
846 #address-cells = <1>;
847 #size-cells = <1>;
848 reg = <0x30900000 0x40000>;
849 ranges = <0 0x30900000 0x40000>;
850 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clk IMX8MP_CLK_AHB>,
852 <&clk IMX8MP_CLK_IPG_ROOT>;
853 clock-names = "aclk", "ipg";
854
855 sec_jr0: jr@1000 {
856 compatible = "fsl,sec-v4.0-job-ring";
857 reg = <0x1000 0x1000>;
858 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
dc9c1ceb 859 status = "disabled";
d3a719e3
HG		 860 };
861
862 sec_jr1: jr@2000 {
863 compatible = "fsl,sec-v4.0-job-ring";
864 reg = <0x2000 0x1000>;
865 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
866 };
867
868 sec_jr2: jr@3000 {
869 compatible = "fsl,sec-v4.0-job-ring";
870 reg = <0x3000 0x1000>;
871 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
872 };
873 };
874
6d9b8d20
AH		 875 i2c1: i2c@30a20000 {
876 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
877 #address-cells = <1>;
878 #size-cells = <0>;
879 reg = <0x30a20000 0x10000>;
880 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
882 status = "disabled";
883 };
884
885 i2c2: i2c@30a30000 {
886 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
887 #address-cells = <1>;
888 #size-cells = <0>;
889 reg = <0x30a30000 0x10000>;
890 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
892 status = "disabled";
893 };
894
895 i2c3: i2c@30a40000 {
896 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
897 #address-cells = <1>;
898 #size-cells = <0>;
899 reg = <0x30a40000 0x10000>;
900 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
902 status = "disabled";
903 };
904
905 i2c4: i2c@30a50000 {
906 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
907 #address-cells = <1>;
908 #size-cells = <0>;
909 reg = <0x30a50000 0x10000>;
910 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
912 status = "disabled";
913 };
914
915 uart4: serial@30a60000 {
916 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
917 reg = <0x30a60000 0x10000>;
918 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
920 <&clk IMX8MP_CLK_UART4_ROOT>;
921 clock-names = "ipg", "per";
922 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
923 dma-names = "rx", "tx";
924 status = "disabled";
925 };
926
bbfc59be
PF		 927 mu: mailbox@30aa0000 {
928 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
929 reg = <0x30aa0000 0x10000>;
930 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
932 #mbox-cells = <2>;
933 };
934
bc3ab388
DB		 935 mu2: mailbox@30e60000 {
936 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
937 reg = <0x30e60000 0x10000>;
938 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
939 #mbox-cells = <2>;
940 status = "disabled";
941 };
942
6d9b8d20
AH		 943 i2c5: i2c@30ad0000 {
944 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
945 #address-cells = <1>;
946 #size-cells = <0>;
947 reg = <0x30ad0000 0x10000>;
948 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
950 status = "disabled";
951 };
952
953 i2c6: i2c@30ae0000 {
954 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
955 #address-cells = <1>;
956 #size-cells = <0>;
957 reg = <0x30ae0000 0x10000>;
958 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
960 status = "disabled";
961 };
962
963 usdhc1: mmc@30b40000 {
746a7241 964 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 965 reg = <0x30b40000 0x10000>;
966 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&clk IMX8MP_CLK_DUMMY>,
968 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
969 <&clk IMX8MP_CLK_USDHC1_ROOT>;
970 clock-names = "ipg", "ahb", "per";
971 fsl,tuning-start-tap = <20>;
33597c62 972 fsl,tuning-step = <2>;
6d9b8d20
AH		 973 bus-width = <4>;
974 status = "disabled";
975 };
976
977 usdhc2: mmc@30b50000 {
746a7241 978 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 979 reg = <0x30b50000 0x10000>;
980 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&clk IMX8MP_CLK_DUMMY>,
982 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
983 <&clk IMX8MP_CLK_USDHC2_ROOT>;
984 clock-names = "ipg", "ahb", "per";
985 fsl,tuning-start-tap = <20>;
33597c62 986 fsl,tuning-step = <2>;
6d9b8d20
AH		 987 bus-width = <4>;
988 status = "disabled";
989 };
990
991 usdhc3: mmc@30b60000 {
746a7241 992 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
6d9b8d20
AH		 993 reg = <0x30b60000 0x10000>;
994 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&clk IMX8MP_CLK_DUMMY>,
996 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
997 <&clk IMX8MP_CLK_USDHC3_ROOT>;
998 clock-names = "ipg", "ahb", "per";
999 fsl,tuning-start-tap = <20>;
33597c62 1000 fsl,tuning-step = <2>;
6d9b8d20
AH		 1001 bus-width = <4>;
1002 status = "disabled";
1003 };
1004
6914d1ba
HS		 1005 flexspi: spi@30bb0000 {
1006 compatible = "nxp,imx8mp-fspi";
1007 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1008 reg-names = "fspi_base", "fspi_mmap";
1009 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1011 <&clk IMX8MP_CLK_QSPI_ROOT>;
d7cd7446 1012 clock-names = "fspi_en", "fspi";
6914d1ba
HS		 1013 assigned-clock-rates = <80000000>;
1014 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 status = "disabled";
1018 };
1019
6d9b8d20
AH		 1020 sdma1: dma-controller@30bd0000 {
1021 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1022 reg = <0x30bd0000 0x10000>;
1023 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
66138621 1025 <&clk IMX8MP_CLK_AHB>;
6d9b8d20
AH		 1026 clock-names = "ipg", "ahb";
1027 #dma-cells = <3>;
1028 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1029 };
1030
1031 fec: ethernet@30be0000 {
f9654d26 1032 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
6d9b8d20
AH		 1033 reg = <0x30be0000 0x10000>;
1034 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 1036 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6d9b8d20
AH		 1038 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1039 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1040 <&clk IMX8MP_CLK_ENET_TIMER>,
1041 <&clk IMX8MP_CLK_ENET_REF>,
1042 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1043 clock-names = "ipg", "ahb", "ptp",
1044 "enet_clk_ref", "enet_out";
1045 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1046 <&clk IMX8MP_CLK_ENET_TIMER>,
1047 <&clk IMX8MP_CLK_ENET_REF>,
70eacf42 1048 <&clk IMX8MP_CLK_ENET_PHY_REF>;
6d9b8d20
AH		 1049 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1050 <&clk IMX8MP_SYS_PLL2_100M>,
70eacf42
JZ		 1051 <&clk IMX8MP_SYS_PLL2_125M>,
1052 <&clk IMX8MP_SYS_PLL2_50M>;
1053 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
6d9b8d20
AH		 1054 fsl,num-tx-queues = <3>;
1055 fsl,num-rx-queues = <3>;
066438ae
JZ		 1056 nvmem-cells = <&eth_mac1>;
1057 nvmem-cell-names = "mac-address";
afe99354 1058 fsl,stop-mode = <&gpr 0x10 3>;
6d9b8d20
AH		 1059 status = "disabled";
1060 };
ec4d1196
MV		 1061
1062 eqos: ethernet@30bf0000 {
1063 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1064 reg = <0x30bf0000 0x10000>;
77e5253d
JZ		 1065 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1067 interrupt-names = "macirq", "eth_wake_irq";
ec4d1196
MV		 1068 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1069 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1070 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1071 <&clk IMX8MP_CLK_ENET_QOS>;
1072 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1073 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1074 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1075 <&clk IMX8MP_CLK_ENET_QOS>;
1076 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1077 <&clk IMX8MP_SYS_PLL2_100M>,
1078 <&clk IMX8MP_SYS_PLL2_125M>;
1079 assigned-clock-rates = <0>, <100000000>, <125000000>;
44d0dfee
JZ		 1080 nvmem-cells = <&eth_mac2>;
1081 nvmem-cell-names = "mac-address";
ec4d1196
MV		 1082 intf_mode = <&gpr 0x4>;
1083 status = "disabled";
1084 };
6d9b8d20
AH		 1085 };
1086
d4ac6028
PF		 1087 noc: interconnect@32700000 {
1088 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1089 reg = <0x32700000 0x100000>;
1090 clocks = <&clk IMX8MP_CLK_NOC>;
1091 #interconnect-cells = <1>;
1092 operating-points-v2 = <&noc_opp_table>;
1093
1094 noc_opp_table: opp-table {
1095 compatible = "operating-points-v2";
1096
0c068a36 1097 opp-200000000 {
d4ac6028
PF		 1098 opp-hz = /bits/ 64 <200000000>;
1099 };
1100
0c068a36 1101 opp-1000000000 {
d4ac6028
PF		 1102 opp-hz = /bits/ 64 <1000000000>;
1103 };
1104 };
1105 };
1106
2ae42e0c
LS		 1107 aips4: bus@32c00000 {
1108 compatible = "fsl,aips-bus", "simple-bus";
1109 reg = <0x32c00000 0x400000>;
1110 #address-cells = <1>;
1111 #size-cells = <1>;
1112 ranges;
1113
29f440a7
PE		 1114 media_blk_ctrl: blk-ctrl@32ec0000 {
1115 compatible = "fsl,imx8mp-media-blk-ctrl",
1116 "syscon";
1117 reg = <0x32ec0000 0x10000>;
1118 power-domains = <&pgc_mediamix>,
1119 <&pgc_mipi_phy1>,
1120 <&pgc_mipi_phy1>,
1121 <&pgc_mediamix>,
1122 <&pgc_mediamix>,
1123 <&pgc_mipi_phy2>,
1124 <&pgc_mediamix>,
1125 <&pgc_ispdwp>,
1126 <&pgc_ispdwp>,
1127 <&pgc_mipi_phy2>;
1128 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1129 "lcdif1", "isi", "mipi-csi2",
1130 "lcdif2", "isp", "dwe",
1131 "mipi-dsi2";
3175c706
PF		 1132 interconnects =
1133 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1134 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1135 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1136 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1137 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1138 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1139 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1140 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1141 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1142 "isi1", "isi2", "isp0", "isp1",
1143 "dwe";
29f440a7
PE		 1144 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1145 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1146 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1147 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1148 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1149 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1150 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1151 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1152 clock-names = "apb", "axi", "cam1", "cam2",
1153 "disp1", "disp2", "isp", "phy";
1154
1155 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1156 <&clk IMX8MP_CLK_MEDIA_APB>;
1157 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1158 <&clk IMX8MP_SYS_PLL1_800M>;
1159 assigned-clock-rates = <500000000>, <200000000>;
1160
1161 #power-domain-cells = <1>;
1162 };
1163
9e65987b
RZ		 1164 pcie_phy: pcie-phy@32f00000 {
1165 compatible = "fsl,imx8mp-pcie-phy";
1166 reg = <0x32f00000 0x10000>;
1167 resets = <&src IMX8MP_RESET_PCIEPHY>,
1168 <&src IMX8MP_RESET_PCIEPHY_PERST>;
1169 reset-names = "pciephy", "perst";
1170 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1171 #phy-cells = <0>;
1172 status = "disabled";
1173 };
1174
2ae42e0c
LS		 1175 hsio_blk_ctrl: blk-ctrl@32f10000 {
1176 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1177 reg = <0x32f10000 0x24>;
1178 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1179 <&clk IMX8MP_CLK_PCIE_ROOT>;
1180 clock-names = "usb", "pcie";
1181 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1182 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1183 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1184 power-domain-names = "bus", "usb", "usb-phy1",
1185 "usb-phy2", "pcie", "pcie-phy";
31da63e1
PF		 1186 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
1187 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
1188 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
1189 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
1190 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
2ae42e0c
LS		 1191 #power-domain-cells = <1>;
1192 };
1193 };
1194
9e65987b
RZ		 1195 pcie: pcie@33800000 {
1196 compatible = "fsl,imx8mp-pcie";
1197 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1198 reg-names = "dbi", "config";
1199 #address-cells = <3>;
1200 #size-cells = <2>;
1201 device_type = "pci";
1202 bus-range = <0x00 0xff>;
1203 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1204 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1205 num-lanes = <1>;
1206 num-viewport = <4>;
1207 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1208 interrupt-names = "msi";
1209 #interrupt-cells = <1>;
1210 interrupt-map-mask = <0 0 0 0x7>;
1211 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1212 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1213 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1214 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1215 fsl,max-link-speed = <3>;
1216 linux,pci-domain = <0>;
1217 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1218 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1219 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1220 reset-names = "apps", "turnoff";
1221 phys = <&pcie_phy>;
1222 phy-names = "pcie-phy";
1223 status = "disabled";
1224 };
1225
4bdb1192
LS		 1226 gpu3d: gpu@38000000 {
1227 compatible = "vivante,gc";
1228 reg = <0x38000000 0x8000>;
1229 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1231 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1232 <&clk IMX8MP_CLK_GPU_ROOT>,
1233 <&clk IMX8MP_CLK_GPU_AHB>;
1234 clock-names = "core", "shader", "bus", "reg";
1235 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1236 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1237 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1238 <&clk IMX8MP_SYS_PLL1_800M>;
1239 assigned-clock-rates = <800000000>, <800000000>;
1240 power-domains = <&pgc_gpu3d>;
1241 };
1242
1243 gpu2d: gpu@38008000 {
1244 compatible = "vivante,gc";
1245 reg = <0x38008000 0x8000>;
1246 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1248 <&clk IMX8MP_CLK_GPU_ROOT>,
1249 <&clk IMX8MP_CLK_GPU_AHB>;
1250 clock-names = "core", "bus", "reg";
1251 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1252 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1253 assigned-clock-rates = <800000000>;
1254 power-domains = <&pgc_gpu2d>;
1255 };
1256
a763d0cf
PF		 1257 vpumix_blk_ctrl: blk-ctrl@38330000 {
1258 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1259 reg = <0x38330000 0x100>;
1260 #power-domain-cells = <1>;
1261 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1262 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
1263 power-domain-names = "bus", "g1", "g2", "vc8000e";
1264 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
1265 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
1266 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
1267 clock-names = "g1", "g2", "vc8000e";
1268 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
1269 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
1270 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
1271 interconnect-names = "g1", "g2", "vc8000e";
1272 };
1273
6d9b8d20
AH		 1274 gic: interrupt-controller@38800000 {
1275 compatible = "arm,gic-v3";
1276 reg = <0x38800000 0x10000>,
1277 <0x38880000 0xc0000>;
1278 #interrupt-cells = <3>;
1279 interrupt-controller;
1280 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1281 interrupt-parent = <&gic>;
1282 };
b39cb21f 1283
68b7cf5d
SS		 1284 edacmc: memory-controller@3d400000 {
1285 compatible = "snps,ddrc-3.80a";
1286 reg = <0x3d400000 0x400000>;
1287 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1288 };
1289
b39cb21f
JZ		 1290 ddr-pmu@3d800000 {
1291 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1292 reg = <0x3d800000 0x400000>;
1293 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1294 };
fb8587a2
LJ		 1295
1296 usb3_phy0: usb-phy@381f0040 {
1297 compatible = "fsl,imx8mp-usb-phy";
1298 reg = <0x381f0040 0x40>;
1299 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1300 clock-names = "phy";
1301 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1302 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2ae42e0c 1303 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
fb8587a2
LJ		 1304 #phy-cells = <0>;
1305 status = "disabled";
1306 };
1307
1308 usb3_0: usb@32f10100 {
1309 compatible = "fsl,imx8mp-dwc3";
290918c7
AS		 1310 reg = <0x32f10100 0x8>,
1311 <0x381f0000 0x20>;
fb8587a2
LJ		 1312 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1313 <&clk IMX8MP_CLK_USB_ROOT>;
1314 clock-names = "hsio", "suspend";
1315 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2ae42e0c 1316 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
fb8587a2
LJ		 1317 #address-cells = <1>;
1318 #size-cells = <1>;
1319 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1320 ranges;
1321 status = "disabled";
1322
d1689cd3 1323 usb_dwc3_0: usb@38100000 {
fb8587a2
LJ		 1324 compatible = "snps,dwc3";
1325 reg = <0x38100000 0x10000>;
1326 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1327 <&clk IMX8MP_CLK_USB_CORE_REF>,
1328 <&clk IMX8MP_CLK_USB_ROOT>;
1329 clock-names = "bus_early", "ref", "suspend";
fb8587a2
LJ		 1330 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1331 phys = <&usb3_phy0>, <&usb3_phy0>;
1332 phy-names = "usb2-phy", "usb3-phy";
5c3d5ecf 1333 snps,gfladj-refclk-lpm-sel-quirk;
fb8587a2
LJ		 1334 };
1335
1336 };
1337
1338 usb3_phy1: usb-phy@382f0040 {
1339 compatible = "fsl,imx8mp-usb-phy";
1340 reg = <0x382f0040 0x40>;
1341 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1342 clock-names = "phy";
1343 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1344 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2ae42e0c 1345 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
fb8587a2 1346 #phy-cells = <0>;
b2d67d7b 1347 status = "disabled";
fb8587a2
LJ		 1348 };
1349
1350 usb3_1: usb@32f10108 {
1351 compatible = "fsl,imx8mp-dwc3";
290918c7
AS		 1352 reg = <0x32f10108 0x8>,
1353 <0x382f0000 0x20>;
fb8587a2
LJ		 1354 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1355 <&clk IMX8MP_CLK_USB_ROOT>;
1356 clock-names = "hsio", "suspend";
1357 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2ae42e0c 1358 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
fb8587a2
LJ		 1359 #address-cells = <1>;
1360 #size-cells = <1>;
1361 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1362 ranges;
1363 status = "disabled";
1364
d1689cd3 1365 usb_dwc3_1: usb@38200000 {
fb8587a2
LJ		 1366 compatible = "snps,dwc3";
1367 reg = <0x38200000 0x10000>;
1368 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1369 <&clk IMX8MP_CLK_USB_CORE_REF>,
1370 <&clk IMX8MP_CLK_USB_ROOT>;
1371 clock-names = "bus_early", "ref", "suspend";
fb8587a2
LJ		 1372 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1373 phys = <&usb3_phy1>, <&usb3_phy1>;
1374 phy-names = "usb2-phy", "usb3-phy";
5c3d5ecf 1375 snps,gfladj-refclk-lpm-sel-quirk;
fb8587a2
LJ		 1376 };
1377 };
bc3ab388
DB		 1378
1379 dsp: dsp@3b6e8000 {
1380 compatible = "fsl,imx8mp-dsp";
1381 reg = <0x3b6e8000 0x88000>;
1382 mbox-names = "txdb0", "txdb1",
1383 "rxdb0", "rxdb1";
1384 mboxes = <&mu2 2 0>, <&mu2 2 1>,
1385 <&mu2 3 0>, <&mu2 3 1>;
1386 memory-region = <&dsp_reserved>;
1387 status = "disabled";
1388 };
6d9b8d20
AH		 1389 };
1390};
Linux 6.x block layer and io_uring tree(s)