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arm64: dts: imx8m: add mac address for FEC
[linux-block.git] / arch / arm64 / boot / dts / freescale / imx8mp.dtsi
CommitLineData
6d9b8d20
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mp-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
30cdd62d 10#include <dt-bindings/thermal/thermal.h>
6d9b8d20
AH		 11
12#include "imx8mp-pinfunc.h"
13
14/ {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
ac4af2b1
PF		 26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 i2c4 = &i2c5;
31 i2c5 = &i2c6;
6d9b8d20
AH		 32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 A53_0: cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53";
48 reg = <0x0>;
49 clock-latency = <61036>;
50 clocks = <&clk IMX8MP_CLK_ARM>;
51 enable-method = "psci";
52 next-level-cache = <&A53_L2>;
30cdd62d 53 #cooling-cells = <2>;
6d9b8d20
AH		 54 };
55
56 A53_1: cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a53";
59 reg = <0x1>;
60 clock-latency = <61036>;
61 clocks = <&clk IMX8MP_CLK_ARM>;
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
30cdd62d 64 #cooling-cells = <2>;
6d9b8d20
AH		 65 };
66
67 A53_2: cpu@2 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a53";
70 reg = <0x2>;
71 clock-latency = <61036>;
72 clocks = <&clk IMX8MP_CLK_ARM>;
73 enable-method = "psci";
74 next-level-cache = <&A53_L2>;
30cdd62d 75 #cooling-cells = <2>;
6d9b8d20
AH		 76 };
77
78 A53_3: cpu@3 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a53";
81 reg = <0x3>;
82 clock-latency = <61036>;
83 clocks = <&clk IMX8MP_CLK_ARM>;
84 enable-method = "psci";
85 next-level-cache = <&A53_L2>;
30cdd62d 86 #cooling-cells = <2>;
6d9b8d20
AH		 87 };
88
89 A53_L2: l2-cache0 {
90 compatible = "cache";
91 };
92 };
93
94 osc_32k: clock-osc-32k {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <32768>;
98 clock-output-names = "osc_32k";
99 };
100
101 osc_24m: clock-osc-24m {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <24000000>;
105 clock-output-names = "osc_24m";
106 };
107
108 clk_ext1: clock-ext1 {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <133000000>;
112 clock-output-names = "clk_ext1";
113 };
114
115 clk_ext2: clock-ext2 {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <133000000>;
119 clock-output-names = "clk_ext2";
120 };
121
122 clk_ext3: clock-ext3 {
123 compatible = "fixed-clock";
124 #clock-cells = <0>;
125 clock-frequency = <133000000>;
126 clock-output-names = "clk_ext3";
127 };
128
129 clk_ext4: clock-ext4 {
130 compatible = "fixed-clock";
131 #clock-cells = <0>;
132 clock-frequency= <133000000>;
133 clock-output-names = "clk_ext4";
134 };
135
0f109a31
JB		 136 pmu {
137 compatible = "arm,cortex-a53-pmu";
138 interrupts = <GIC_PPI 7
139 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
140 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
141 };
142
6d9b8d20
AH		 143 psci {
144 compatible = "arm,psci-1.0";
145 method = "smc";
146 };
147
30cdd62d
AH		 148 thermal-zones {
149 cpu-thermal {
150 polling-delay-passive = <250>;
151 polling-delay = <2000>;
152 thermal-sensors = <&tmu 0>;
153 trips {
154 cpu_alert0: trip0 {
155 temperature = <85000>;
156 hysteresis = <2000>;
157 type = "passive";
158 };
159
160 cpu_crit0: trip1 {
161 temperature = <95000>;
162 hysteresis = <2000>;
163 type = "critical";
164 };
165 };
166
167 cooling-maps {
168 map0 {
169 trip = <&cpu_alert0>;
170 cooling-device =
171 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
172 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
173 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
174 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
175 };
176 };
177 };
178
179 soc-thermal {
180 polling-delay-passive = <250>;
181 polling-delay = <2000>;
182 thermal-sensors = <&tmu 1>;
183 trips {
184 soc_alert0: trip0 {
185 temperature = <85000>;
186 hysteresis = <2000>;
187 type = "passive";
188 };
189
190 soc_crit0: trip1 {
191 temperature = <95000>;
192 hysteresis = <2000>;
193 type = "critical";
194 };
195 };
196
197 cooling-maps {
198 map0 {
199 trip = <&soc_alert0>;
200 cooling-device =
201 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
202 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
203 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
204 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
205 };
206 };
207 };
208 };
209
6d9b8d20
AH		 210 timer {
211 compatible = "arm,armv8-timer";
061883e6
KK		 212 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
213 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
214 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
215 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
6d9b8d20
AH		 216 clock-frequency = <8000000>;
217 arm,no-tick-in-suspend;
218 };
219
220 soc@0 {
ce58459d 221 compatible = "fsl,imx8mp-soc", "simple-bus";
6d9b8d20
AH		 222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0x0 0x0 0x0 0x3e000000>;
cbff2379
AG		 225 nvmem-cells = <&imx8mp_uid>;
226 nvmem-cell-names = "soc_unique_id";
6d9b8d20
AH		 227
228 aips1: bus@30000000 {
dc3efc6f 229 compatible = "fsl,aips-bus", "simple-bus";
921a6845 230 reg = <0x30000000 0x400000>;
6d9b8d20
AH		 231 #address-cells = <1>;
232 #size-cells = <1>;
233 ranges;
234
235 gpio1: gpio@30200000 {
236 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
237 reg = <0x30200000 0x10000>;
238 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
241 gpio-controller;
242 #gpio-cells = <2>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
245 gpio-ranges = <&iomuxc 0 5 30>;
246 };
247
248 gpio2: gpio@30210000 {
249 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
250 reg = <0x30210000 0x10000>;
251 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
254 gpio-controller;
255 #gpio-cells = <2>;
256 interrupt-controller;
257 #interrupt-cells = <2>;
258 gpio-ranges = <&iomuxc 0 35 21>;
259 };
260
261 gpio3: gpio@30220000 {
262 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
263 reg = <0x30220000 0x10000>;
264 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
267 gpio-controller;
268 #gpio-cells = <2>;
269 interrupt-controller;
270 #interrupt-cells = <2>;
271 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
272 };
273
274 gpio4: gpio@30230000 {
275 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
276 reg = <0x30230000 0x10000>;
277 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
280 gpio-controller;
281 #gpio-cells = <2>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
284 gpio-ranges = <&iomuxc 0 82 32>;
285 };
286
287 gpio5: gpio@30240000 {
288 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
289 reg = <0x30240000 0x10000>;
290 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
293 gpio-controller;
294 #gpio-cells = <2>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 gpio-ranges = <&iomuxc 0 114 30>;
298 };
299
30cdd62d
AH		 300 tmu: tmu@30260000 {
301 compatible = "fsl,imx8mp-tmu";
302 reg = <0x30260000 0x10000>;
303 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
304 #thermal-sensor-cells = <1>;
305 };
306
6d9b8d20
AH		 307 wdog1: watchdog@30280000 {
308 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
309 reg = <0x30280000 0x10000>;
310 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
312 status = "disabled";
313 };
314
315 iomuxc: pinctrl@30330000 {
316 compatible = "fsl,imx8mp-iomuxc";
317 reg = <0x30330000 0x10000>;
318 };
319
320 gpr: iomuxc-gpr@30340000 {
321 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
322 reg = <0x30340000 0x10000>;
323 };
324
12fa1078 325 ocotp: efuse@30350000 {
f2fe45d5 326 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
6d9b8d20
AH		 327 reg = <0x30350000 0x10000>;
328 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
329 /* For nvmem subnodes */
330 #address-cells = <1>;
331 #size-cells = <1>;
332
cbff2379
AG		 333 imx8mp_uid: unique-id@420 {
334 reg = <0x8 0x8>;
335 };
336
6d9b8d20
AH		 337 cpu_speed_grade: speed-grade@10 {
338 reg = <0x10 4>;
339 };
066438ae
JZ		 340
341 eth_mac1: mac-address@90 {
342 reg = <0x90 6>;
343 };
6d9b8d20
AH		 344 };
345
346 anatop: anatop@30360000 {
347 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
348 "syscon";
349 reg = <0x30360000 0x10000>;
350 };
351
352 snvs: snvs@30370000 {
353 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
354 reg = <0x30370000 0x10000>;
355
356 snvs_rtc: snvs-rtc-lp {
357 compatible = "fsl,sec-v4.0-mon-rtc-lp";
358 regmap =<&snvs>;
359 offset = <0x34>;
360 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
363 clock-names = "snvs-rtc";
364 };
365
366 snvs_pwrkey: snvs-powerkey {
367 compatible = "fsl,sec-v4.0-pwrkey";
368 regmap = <&snvs>;
369 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
6c389f29
AH		 370 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
371 clock-names = "snvs-pwrkey";
6d9b8d20
AH		 372 linux,keycode = <KEY_POWER>;
373 wakeup-source;
374 status = "disabled";
375 };
376 };
377
378 clk: clock-controller@30380000 {
379 compatible = "fsl,imx8mp-ccm";
380 reg = <0x30380000 0x10000>;
381 #clock-cells = <1>;
382 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
383 <&clk_ext3>, <&clk_ext4>;
384 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
385 "clk_ext3", "clk_ext4";
9e6337e6
PF		 386 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
387 <&clk IMX8MP_CLK_A53_CORE>,
388 <&clk IMX8MP_CLK_NOC>,
6d9b8d20
AH		 389 <&clk IMX8MP_CLK_NOC_IO>,
390 <&clk IMX8MP_CLK_GIC>,
391 <&clk IMX8MP_CLK_AUDIO_AHB>,
392 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
393 <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
394 <&clk IMX8MP_AUDIO_PLL1>,
395 <&clk IMX8MP_AUDIO_PLL2>;
9e6337e6
PF		 396 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
397 <&clk IMX8MP_ARM_PLL_OUT>,
398 <&clk IMX8MP_SYS_PLL2_1000M>,
6d9b8d20
AH		 399 <&clk IMX8MP_SYS_PLL1_800M>,
400 <&clk IMX8MP_SYS_PLL2_500M>,
401 <&clk IMX8MP_SYS_PLL1_800M>,
402 <&clk IMX8MP_SYS_PLL1_800M>;
9e6337e6
PF		 403 assigned-clock-rates = <0>, <0>,
404 <1000000000>,
6d9b8d20
AH		 405 <800000000>,
406 <500000000>,
407 <400000000>,
408 <800000000>,
409 <400000000>,
410 <393216000>,
411 <361267200>;
412 };
455ae0c3
AH		 413
414 src: reset-controller@30390000 {
415 compatible = "fsl,imx8mp-src", "syscon";
416 reg = <0x30390000 0x10000>;
1641b234 417 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
455ae0c3
AH		 418 #reset-cells = <1>;
419 };
6d9b8d20
AH		 420 };
421
422 aips2: bus@30400000 {
dc3efc6f 423 compatible = "fsl,aips-bus", "simple-bus";
921a6845 424 reg = <0x30400000 0x400000>;
6d9b8d20
AH		 425 #address-cells = <1>;
426 #size-cells = <1>;
427 ranges;
428
429 pwm1: pwm@30660000 {
430 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
431 reg = <0x30660000 0x10000>;
432 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
434 <&clk IMX8MP_CLK_PWM1_ROOT>;
435 clock-names = "ipg", "per";
436 #pwm-cells = <2>;
437 status = "disabled";
438 };
439
440 pwm2: pwm@30670000 {
441 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
442 reg = <0x30670000 0x10000>;
443 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
445 <&clk IMX8MP_CLK_PWM2_ROOT>;
446 clock-names = "ipg", "per";
447 #pwm-cells = <2>;
448 status = "disabled";
449 };
450
451 pwm3: pwm@30680000 {
452 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
453 reg = <0x30680000 0x10000>;
454 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
456 <&clk IMX8MP_CLK_PWM3_ROOT>;
457 clock-names = "ipg", "per";
458 #pwm-cells = <2>;
459 status = "disabled";
460 };
461
462 pwm4: pwm@30690000 {
463 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
464 reg = <0x30690000 0x10000>;
465 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
467 <&clk IMX8MP_CLK_PWM4_ROOT>;
468 clock-names = "ipg", "per";
469 #pwm-cells = <2>;
470 status = "disabled";
471 };
fae58b1a
AH		 472
473 system_counter: timer@306a0000 {
474 compatible = "nxp,sysctr-timer";
475 reg = <0x306a0000 0x20000>;
476 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&osc_24m>;
478 clock-names = "per";
479 };
6d9b8d20
AH		 480 };
481
482 aips3: bus@30800000 {
dc3efc6f 483 compatible = "fsl,aips-bus", "simple-bus";
921a6845 484 reg = <0x30800000 0x400000>;
6d9b8d20
AH		 485 #address-cells = <1>;
486 #size-cells = <1>;
487 ranges;
488
489 ecspi1: spi@30820000 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
493 reg = <0x30820000 0x10000>;
494 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
496 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
497 clock-names = "ipg", "per";
498 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
499 dma-names = "rx", "tx";
500 status = "disabled";
501 };
502
503 ecspi2: spi@30830000 {
504 #address-cells = <1>;
505 #size-cells = <0>;
506 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
507 reg = <0x30830000 0x10000>;
508 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
510 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
511 clock-names = "ipg", "per";
512 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
513 dma-names = "rx", "tx";
514 status = "disabled";
515 };
516
517 ecspi3: spi@30840000 {
518 #address-cells = <1>;
519 #size-cells = <0>;
520 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
521 reg = <0x30840000 0x10000>;
522 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
524 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
525 clock-names = "ipg", "per";
526 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
527 dma-names = "rx", "tx";
528 status = "disabled";
529 };
530
531 uart1: serial@30860000 {
532 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
533 reg = <0x30860000 0x10000>;
534 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
536 <&clk IMX8MP_CLK_UART1_ROOT>;
537 clock-names = "ipg", "per";
538 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
539 dma-names = "rx", "tx";
540 status = "disabled";
541 };
542
543 uart3: serial@30880000 {
544 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
545 reg = <0x30880000 0x10000>;
546 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
548 <&clk IMX8MP_CLK_UART3_ROOT>;
549 clock-names = "ipg", "per";
550 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
551 dma-names = "rx", "tx";
552 status = "disabled";
553 };
554
555 uart2: serial@30890000 {
556 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
557 reg = <0x30890000 0x10000>;
558 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
560 <&clk IMX8MP_CLK_UART2_ROOT>;
561 clock-names = "ipg", "per";
562 status = "disabled";
563 };
564
3a7d56b3
JZ		 565 flexcan1: can@308c0000 {
566 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
567 reg = <0x308c0000 0x10000>;
568 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
570 <&clk IMX8MP_CLK_CAN1_ROOT>;
571 clock-names = "ipg", "per";
572 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
573 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
574 assigned-clock-rates = <40000000>;
575 fsl,clk-source = /bits/ 8 <0>;
576 fsl,stop-mode = <&gpr 0x10 4>;
577 status = "disabled";
578 };
579
580 flexcan2: can@308d0000 {
581 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
582 reg = <0x308d0000 0x10000>;
583 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
585 <&clk IMX8MP_CLK_CAN2_ROOT>;
586 clock-names = "ipg", "per";
587 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
588 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
589 assigned-clock-rates = <40000000>;
590 fsl,clk-source = /bits/ 8 <0>;
591 fsl,stop-mode = <&gpr 0x10 5>;
592 status = "disabled";
593 };
594
d3a719e3
HG		 595 crypto: crypto@30900000 {
596 compatible = "fsl,sec-v4.0";
597 #address-cells = <1>;
598 #size-cells = <1>;
599 reg = <0x30900000 0x40000>;
600 ranges = <0 0x30900000 0x40000>;
601 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk IMX8MP_CLK_AHB>,
603 <&clk IMX8MP_CLK_IPG_ROOT>;
604 clock-names = "aclk", "ipg";
605
606 sec_jr0: jr@1000 {
607 compatible = "fsl,sec-v4.0-job-ring";
608 reg = <0x1000 0x1000>;
609 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
610 };
611
612 sec_jr1: jr@2000 {
613 compatible = "fsl,sec-v4.0-job-ring";
614 reg = <0x2000 0x1000>;
615 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
616 };
617
618 sec_jr2: jr@3000 {
619 compatible = "fsl,sec-v4.0-job-ring";
620 reg = <0x3000 0x1000>;
621 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
622 };
623 };
624
6d9b8d20
AH		 625 i2c1: i2c@30a20000 {
626 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 reg = <0x30a20000 0x10000>;
630 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
632 status = "disabled";
633 };
634
635 i2c2: i2c@30a30000 {
636 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
637 #address-cells = <1>;
638 #size-cells = <0>;
639 reg = <0x30a30000 0x10000>;
640 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
642 status = "disabled";
643 };
644
645 i2c3: i2c@30a40000 {
646 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
647 #address-cells = <1>;
648 #size-cells = <0>;
649 reg = <0x30a40000 0x10000>;
650 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
652 status = "disabled";
653 };
654
655 i2c4: i2c@30a50000 {
656 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
657 #address-cells = <1>;
658 #size-cells = <0>;
659 reg = <0x30a50000 0x10000>;
660 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
662 status = "disabled";
663 };
664
665 uart4: serial@30a60000 {
666 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
667 reg = <0x30a60000 0x10000>;
668 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
670 <&clk IMX8MP_CLK_UART4_ROOT>;
671 clock-names = "ipg", "per";
672 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
673 dma-names = "rx", "tx";
674 status = "disabled";
675 };
676
bbfc59be
PF		 677 mu: mailbox@30aa0000 {
678 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
679 reg = <0x30aa0000 0x10000>;
680 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
682 #mbox-cells = <2>;
683 };
684
6d9b8d20
AH		 685 i2c5: i2c@30ad0000 {
686 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
687 #address-cells = <1>;
688 #size-cells = <0>;
689 reg = <0x30ad0000 0x10000>;
690 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
692 status = "disabled";
693 };
694
695 i2c6: i2c@30ae0000 {
696 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
697 #address-cells = <1>;
698 #size-cells = <0>;
699 reg = <0x30ae0000 0x10000>;
700 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
702 status = "disabled";
703 };
704
705 usdhc1: mmc@30b40000 {
706 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
707 reg = <0x30b40000 0x10000>;
708 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&clk IMX8MP_CLK_DUMMY>,
710 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
711 <&clk IMX8MP_CLK_USDHC1_ROOT>;
712 clock-names = "ipg", "ahb", "per";
713 fsl,tuning-start-tap = <20>;
714 fsl,tuning-step= <2>;
715 bus-width = <4>;
716 status = "disabled";
717 };
718
719 usdhc2: mmc@30b50000 {
720 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
721 reg = <0x30b50000 0x10000>;
722 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&clk IMX8MP_CLK_DUMMY>,
724 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
725 <&clk IMX8MP_CLK_USDHC2_ROOT>;
726 clock-names = "ipg", "ahb", "per";
727 fsl,tuning-start-tap = <20>;
728 fsl,tuning-step= <2>;
729 bus-width = <4>;
730 status = "disabled";
731 };
732
733 usdhc3: mmc@30b60000 {
734 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
735 reg = <0x30b60000 0x10000>;
736 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clk IMX8MP_CLK_DUMMY>,
738 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
739 <&clk IMX8MP_CLK_USDHC3_ROOT>;
740 clock-names = "ipg", "ahb", "per";
741 fsl,tuning-start-tap = <20>;
742 fsl,tuning-step= <2>;
743 bus-width = <4>;
744 status = "disabled";
745 };
746
747 sdma1: dma-controller@30bd0000 {
748 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
749 reg = <0x30bd0000 0x10000>;
750 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
66138621 752 <&clk IMX8MP_CLK_AHB>;
6d9b8d20
AH		 753 clock-names = "ipg", "ahb";
754 #dma-cells = <3>;
755 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
756 };
757
758 fec: ethernet@30be0000 {
f9654d26 759 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
6d9b8d20
AH		 760 reg = <0x30be0000 0x10000>;
761 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
d3762a47
FE		 763 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6d9b8d20
AH		 765 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
766 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
767 <&clk IMX8MP_CLK_ENET_TIMER>,
768 <&clk IMX8MP_CLK_ENET_REF>,
769 <&clk IMX8MP_CLK_ENET_PHY_REF>;
770 clock-names = "ipg", "ahb", "ptp",
771 "enet_clk_ref", "enet_out";
772 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
773 <&clk IMX8MP_CLK_ENET_TIMER>,
774 <&clk IMX8MP_CLK_ENET_REF>,
70eacf42 775 <&clk IMX8MP_CLK_ENET_PHY_REF>;
6d9b8d20
AH		 776 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
777 <&clk IMX8MP_SYS_PLL2_100M>,
70eacf42
JZ		 778 <&clk IMX8MP_SYS_PLL2_125M>,
779 <&clk IMX8MP_SYS_PLL2_50M>;
780 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
6d9b8d20
AH		 781 fsl,num-tx-queues = <3>;
782 fsl,num-rx-queues = <3>;
066438ae
JZ		 783 nvmem-cells = <&eth_mac1>;
784 nvmem-cell-names = "mac-address";
785 nvmem_macaddr_swap;
6d9b8d20
AH		 786 status = "disabled";
787 };
788 };
789
790 gic: interrupt-controller@38800000 {
791 compatible = "arm,gic-v3";
792 reg = <0x38800000 0x10000>,
793 <0x38880000 0xc0000>;
794 #interrupt-cells = <3>;
795 interrupt-controller;
796 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
797 interrupt-parent = <&gic>;
798 };
b39cb21f
JZ		 799
800 ddr-pmu@3d800000 {
801 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
802 reg = <0x3d800000 0x400000>;
803 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
804 };
6d9b8d20
AH		 805 };
806};
Linux 6.x block layer and io_uring tree(s)