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arm64: dts: imx8mp-evk: correct vbus pad settings
[linux-block.git] / arch / arm64 / boot / dts / freescale / imx8mp-evk.dts
CommitLineData
9e847693
AH		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9
10/ {
11 model = "NXP i.MX8MPlus EVK board";
12 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
13
14 chosen {
15 stdout-path = &uart2;
16 };
17
50d336b1
AH		 18 gpio-leds {
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_gpio_led>;
22
23 status {
24 label = "yellow:status";
25 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
26 default-state = "on";
27 };
28 };
29
9e847693
AH		 30 memory@40000000 {
31 device_type = "memory";
32 reg = <0x0 0x40000000 0 0xc0000000>,
33 <0x1 0x00000000 0 0xc0000000>;
34 };
35
3a7d56b3
JZ		 36 reg_can1_stby: regulator-can1-stby {
37 compatible = "regulator-fixed";
38 regulator-name = "can1-stby";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_flexcan1_reg>;
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
44 enable-active-high;
45 };
46
47 reg_can2_stby: regulator-can2-stby {
48 compatible = "regulator-fixed";
49 regulator-name = "can2-stby";
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_flexcan2_reg>;
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
54 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
55 enable-active-high;
56 };
57
9e847693
AH		 58 reg_usdhc2_vmmc: regulator-usdhc2 {
59 compatible = "regulator-fixed";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
62 regulator-name = "VSD_3V3";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 };
68};
69
3a7d56b3
JZ		 70&flexcan1 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_flexcan1>;
73 xceiver-supply = <&reg_can1_stby>;
74 status = "okay";
75};
76
77&flexcan2 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_flexcan2>;
80 xceiver-supply = <&reg_can2_stby>;
81 status = "disabled";/* can2 pin conflict with pdm */
82};
83
dc6d5dc8
JZ		 84&eqos {
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_eqos>;
87 phy-mode = "rgmii-id";
88 phy-handle = <&ethphy0>;
0bc3e333
XY		 89 snps,force_thresh_dma_mode;
90 snps,mtl-tx-config = <&mtl_tx_setup>;
91 snps,mtl-rx-config = <&mtl_rx_setup>;
dc6d5dc8
JZ		 92 status = "okay";
93
94 mdio {
95 compatible = "snps,dwmac-mdio";
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 ethphy0: ethernet-phy@1 {
100 compatible = "ethernet-phy-ieee802.3-c22";
101 reg = <1>;
102 eee-broken-1000t;
e0aa402b
JZ		 103 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
104 reset-assert-us = <10000>;
105 reset-deassert-us = <80000>;
311ad460 106 realtek,clkout-disable;
dc6d5dc8
JZ		 107 };
108 };
0bc3e333
XY		 109
110 mtl_tx_setup: tx-queues-config {
111 snps,tx-queues-to-use = <5>;
112 snps,tx-sched-sp;
113
114 queue0 {
115 snps,dcb-algorithm;
116 snps,priority = <0x1>;
117 };
118
119 queue1 {
120 snps,dcb-algorithm;
121 snps,priority = <0x2>;
122 };
123
124 queue2 {
125 snps,dcb-algorithm;
126 snps,priority = <0x4>;
127 };
128
129 queue3 {
130 snps,dcb-algorithm;
131 snps,priority = <0x8>;
132 };
133
134 queue4 {
135 snps,dcb-algorithm;
136 snps,priority = <0xf0>;
137 };
138 };
139
140 mtl_rx_setup: rx-queues-config {
141 snps,rx-queues-to-use = <5>;
142 snps,rx-sched-sp;
143
144 queue0 {
145 snps,dcb-algorithm;
146 snps,priority = <0x1>;
147 snps,map-to-dma-channel = <0>;
148 };
149
150 queue1 {
151 snps,dcb-algorithm;
152 snps,priority = <0x2>;
153 snps,map-to-dma-channel = <1>;
154 };
155
156 queue2 {
157 snps,dcb-algorithm;
158 snps,priority = <0x4>;
159 snps,map-to-dma-channel = <2>;
160 };
161
162 queue3 {
163 snps,dcb-algorithm;
164 snps,priority = <0x8>;
165 snps,map-to-dma-channel = <3>;
166 };
167
168 queue4 {
169 snps,dcb-algorithm;
170 snps,priority = <0xf0>;
171 snps,map-to-dma-channel = <4>;
172 };
173 };
dc6d5dc8
JZ		 174};
175
9e847693
AH		 176&fec {
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_fec>;
179 phy-mode = "rgmii-id";
180 phy-handle = <&ethphy1>;
181 fsl,magic-packet;
182 status = "okay";
183
184 mdio {
185 #address-cells = <1>;
186 #size-cells = <0>;
187
188 ethphy1: ethernet-phy@1 {
189 compatible = "ethernet-phy-ieee802.3-c22";
190 reg = <1>;
191 eee-broken-1000t;
192 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
798a1807
FE		 193 reset-assert-us = <10000>;
194 reset-deassert-us = <80000>;
311ad460 195 realtek,clkout-disable;
9e847693
AH		 196 };
197 };
198};
199
5497bc2a
UKK		 200&i2c1 {
201 clock-frequency = <400000>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_i2c1>;
204 status = "okay";
205
206 pmic@25 {
207 compatible = "nxp,pca9450c";
208 reg = <0x25>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_pmic>;
211 interrupt-parent = <&gpio1>;
212 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
213
214 regulators {
215 BUCK1 {
216 regulator-name = "BUCK1";
217 regulator-min-microvolt = <720000>;
218 regulator-max-microvolt = <1000000>;
219 regulator-boot-on;
220 regulator-always-on;
221 regulator-ramp-delay = <3125>;
222 };
223
224 BUCK2 {
225 regulator-name = "BUCK2";
226 regulator-min-microvolt = <720000>;
227 regulator-max-microvolt = <1025000>;
228 regulator-boot-on;
229 regulator-always-on;
230 regulator-ramp-delay = <3125>;
231 nxp,dvs-run-voltage = <950000>;
232 nxp,dvs-standby-voltage = <850000>;
233 };
234
235 BUCK4 {
236 regulator-name = "BUCK4";
237 regulator-min-microvolt = <3000000>;
238 regulator-max-microvolt = <3600000>;
239 regulator-boot-on;
240 regulator-always-on;
241 };
242
243 BUCK5 {
244 regulator-name = "BUCK5";
245 regulator-min-microvolt = <1650000>;
246 regulator-max-microvolt = <1950000>;
247 regulator-boot-on;
248 regulator-always-on;
249 };
250
251 BUCK6 {
252 regulator-name = "BUCK6";
253 regulator-min-microvolt = <1045000>;
254 regulator-max-microvolt = <1155000>;
255 regulator-boot-on;
256 regulator-always-on;
257 };
258
259 LDO1 {
260 regulator-name = "LDO1";
261 regulator-min-microvolt = <1650000>;
262 regulator-max-microvolt = <1950000>;
263 regulator-boot-on;
264 regulator-always-on;
265 };
266
267 LDO3 {
268 regulator-name = "LDO3";
269 regulator-min-microvolt = <1710000>;
270 regulator-max-microvolt = <1890000>;
271 regulator-boot-on;
272 regulator-always-on;
273 };
274
275 LDO5 {
276 regulator-name = "LDO5";
277 regulator-min-microvolt = <1800000>;
278 regulator-max-microvolt = <3300000>;
279 regulator-boot-on;
280 regulator-always-on;
281 };
282 };
283 };
284};
285
5e4a67ff
AH		 286&i2c3 {
287 clock-frequency = <400000>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c3>;
290 status = "okay";
2dfb4b13
AH		 291
292 pca6416: gpio@20 {
293 compatible = "ti,tca6416";
294 reg = <0x20>;
295 gpio-controller;
296 #gpio-cells = <2>;
9fb35e0d
HV		 297 interrupt-controller;
298 #interrupt-cells = <2>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_pca6416_int>;
301 interrupt-parent = <&gpio1>;
302 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
6bb691f2
HV		 303 gpio-line-names = "EXT_PWREN1",
304 "EXT_PWREN2",
305 "CAN1/I2C5_SEL",
306 "PDM/CAN2_SEL",
307 "FAN_EN",
308 "PWR_MEAS_IO1",
309 "PWR_MEAS_IO2",
310 "EXP_P0_7",
311 "EXP_P1_0",
312 "EXP_P1_1",
313 "EXP_P1_2",
314 "EXP_P1_3",
315 "EXP_P1_4",
316 "EXP_P1_5",
317 "EXP_P1_6",
318 "EXP_P1_7";
2dfb4b13 319 };
5e4a67ff
AH		 320};
321
8134822d
HV		 322/* I2C on expansion connector J22. */
323&i2c5 {
324 clock-frequency = <100000>; /* Lower clock speed for external bus. */
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_i2c5>;
327 status = "disabled"; /* can1 pins conflict with i2c5 */
328
329 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
330 * LOW: CAN1 (default, pull-down)
331 * HIGH: I2C5
332 * You need to set it to high to enable I2C5 (for example, add gpio-hog
333 * in pca6416 node).
334 */
335};
336
9e847693
AH		 337&snvs_pwrkey {
338 status = "okay";
339};
340
341&uart2 {
342 /* console */
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_uart2>;
345 status = "okay";
346};
347
43da4f92
LJ		 348&usb3_phy1 {
349 status = "okay";
350};
351
352&usb3_1 {
353 status = "okay";
354};
355
356&usb_dwc3_1 {
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_usb1_vbus>;
359 dr_mode = "host";
360 status = "okay";
361};
362
9e847693
AH		 363&usdhc2 {
364 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
365 assigned-clock-rates = <400000000>;
366 pinctrl-names = "default", "state_100mhz", "state_200mhz";
367 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
368 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
369 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
370 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
371 vmmc-supply = <&reg_usdhc2_vmmc>;
372 bus-width = <4>;
373 status = "okay";
374};
375
376&usdhc3 {
377 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
378 assigned-clock-rates = <400000000>;
379 pinctrl-names = "default", "state_100mhz", "state_200mhz";
380 pinctrl-0 = <&pinctrl_usdhc3>;
381 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
382 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
383 bus-width = <8>;
384 non-removable;
385 status = "okay";
386};
387
388&wdog1 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_wdog>;
391 fsl,ext-reset-output;
392 status = "okay";
393};
394
395&iomuxc {
dc6d5dc8
JZ		 396 pinctrl_eqos: eqosgrp {
397 fsl,pins = <
398 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
399 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
400 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
401 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
402 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
403 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
404 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
405 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
406 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
407 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
408 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
409 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
410 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
411 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
412 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
413 >;
414 };
415
9e847693
AH		 416 pinctrl_fec: fecgrp {
417 fsl,pins = <
418 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
419 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
420 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
421 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
422 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
423 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
424 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
425 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
426 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
427 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
428 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
429 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
430 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
431 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
432 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
433 >;
434 };
435
3a7d56b3
JZ		 436 pinctrl_flexcan1: flexcan1grp {
437 fsl,pins = <
438 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
439 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
440 >;
441 };
442
443 pinctrl_flexcan2: flexcan2grp {
444 fsl,pins = <
445 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
446 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
447 >;
448 };
449
450 pinctrl_flexcan1_reg: flexcan1reggrp {
451 fsl,pins = <
452 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
453 >;
454 };
455
456 pinctrl_flexcan2_reg: flexcan2reggrp {
457 fsl,pins = <
458 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
459 >;
460 };
461
50d336b1
AH		 462 pinctrl_gpio_led: gpioledgrp {
463 fsl,pins = <
b838582a 464 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
50d336b1
AH		 465 >;
466 };
467
5497bc2a
UKK		 468 pinctrl_i2c1: i2c1grp {
469 fsl,pins = <
470 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
471 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
472 >;
473 };
474
5e4a67ff
AH		 475 pinctrl_i2c3: i2c3grp {
476 fsl,pins = <
477 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
478 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
479 >;
480 };
481
8134822d
HV		 482 pinctrl_i2c5: i2c5grp {
483 fsl,pins = <
484 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
485 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
486 >;
487 };
488
5497bc2a
UKK		 489 pinctrl_pmic: pmicgrp {
490 fsl,pins = <
491 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
492 >;
493 };
494
9fb35e0d
HV		 495 pinctrl_pca6416_int: pca6416_int_grp {
496 fsl,pins = <
497 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
498 >;
499 };
500
7124b34f 501 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
9e847693 502 fsl,pins = <
01785f1f 503 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
9e847693
AH		 504 >;
505 };
506
507 pinctrl_uart2: uart2grp {
508 fsl,pins = <
2d4fb72b
SS		 509 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
510 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
9e847693
AH		 511 >;
512 };
513
43da4f92
LJ		 514 pinctrl_usb1_vbus: usb1grp {
515 fsl,pins = <
e2c00820 516 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
43da4f92
LJ		 517 >;
518 };
519
9e847693
AH		 520 pinctrl_usdhc2: usdhc2grp {
521 fsl,pins = <
522 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
523 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
524 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
525 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
526 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
527 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
01785f1f 528 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
9e847693
AH		 529 >;
530 };
531
7124b34f 532 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
9e847693
AH		 533 fsl,pins = <
534 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
535 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
536 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
537 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
538 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
539 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
01785f1f 540 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
9e847693
AH		 541 >;
542 };
543
7124b34f 544 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
9e847693
AH		 545 fsl,pins = <
546 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
547 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
548 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
549 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
550 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
551 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
01785f1f 552 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
9e847693
AH		 553 >;
554 };
555
7124b34f 556 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
9e847693
AH		 557 fsl,pins = <
558 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
559 >;
560 };
561
562 pinctrl_usdhc3: usdhc3grp {
563 fsl,pins = <
564 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
565 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
566 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
567 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
568 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
569 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
570 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
571 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
572 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
573 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
574 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
575 >;
576 };
577
7124b34f 578 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
9e847693
AH		 579 fsl,pins = <
580 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
581 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
582 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
583 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
584 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
585 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
586 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
587 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
588 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
589 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
590 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
591 >;
592 };
593
7124b34f 594 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
9e847693
AH		 595 fsl,pins = <
596 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
597 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
598 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
599 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
600 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
601 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
602 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
603 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
604 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
605 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
606 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
607 >;
608 };
609
610 pinctrl_wdog: wdoggrp {
611 fsl,pins = <
fa15cec9 612 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
9e847693
AH		 613 >;
614 };
615};
Linux 6.x block layer and io_uring tree(s)